EP0366361A3 - Hierarchical multiple bus computer system - Google Patents

Hierarchical multiple bus computer system Download PDF

Info

Publication number
EP0366361A3
EP0366361A3 EP19890310774 EP89310774A EP0366361A3 EP 0366361 A3 EP0366361 A3 EP 0366361A3 EP 19890310774 EP19890310774 EP 19890310774 EP 89310774 A EP89310774 A EP 89310774A EP 0366361 A3 EP0366361 A3 EP 0366361A3
Authority
EP
European Patent Office
Prior art keywords
bus
processor
shared
master
slave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19890310774
Other languages
German (de)
French (fr)
Other versions
EP0366361A2 (en
EP0366361B1 (en
Inventor
Paul T. Schweizer
Michael L. Carroll
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR Corp
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp, NCR International Inc filed Critical NCR Corp
Publication of EP0366361A2 publication Critical patent/EP0366361A2/en
Publication of EP0366361A3 publication Critical patent/EP0366361A3/en
Application granted granted Critical
Publication of EP0366361B1 publication Critical patent/EP0366361B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

A modular and hierarchical multiple bus computer system architecture includes a master bus (1) and a slave bus (4) which are substantially identical, communication being effected through a combination of an interface controller (12) and a shared dual port RAM (14) responsive to a shared RAM controller (13). Thus processor engine modules including a bus, a processor, an interface controller, a shared dual port RAM, and a shared RAM controller are horizontally and/or vertically integrated at multiple levels without major restructuring of the composite system control operations by having each slave processor engine module interface as a peripheral upon the bus of its master. The modularity of the architecture allows the use of standard peripherals and platform processor engines to expand memory or increase functionality without burdening the master bus processor engine. Each slave bus processor engine is fully functional as an independent processor with mastery over its own bus. The architecture is particularly efficient in extended data base, fault tolerant data base or multi-communication system adapter interface functions.
EP89310774A 1988-10-24 1989-10-19 Hierarchical multiple bus computer system Expired - Lifetime EP0366361B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US261537 1988-10-24
US07/261,537 US4912633A (en) 1988-10-24 1988-10-24 Hierarchical multiple bus computer architecture

Publications (3)

Publication Number Publication Date
EP0366361A2 EP0366361A2 (en) 1990-05-02
EP0366361A3 true EP0366361A3 (en) 1991-03-20
EP0366361B1 EP0366361B1 (en) 1997-01-08

Family

ID=22993763

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89310774A Expired - Lifetime EP0366361B1 (en) 1988-10-24 1989-10-19 Hierarchical multiple bus computer system

Country Status (5)

Country Link
US (1) US4912633A (en)
EP (1) EP0366361B1 (en)
JP (1) JPH02127759A (en)
KR (1) KR920008458B1 (en)
DE (1) DE68927626T2 (en)

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JP3524110B2 (en) * 1992-11-06 2004-05-10 株式会社ルネサステクノロジ Microcomputer system
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US5621901A (en) * 1994-10-31 1997-04-15 Intel Corporation Method and apparatus for serial bus elements of an hierarchical serial bus assembly to electrically represent data and control states to each other
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US5615404A (en) * 1994-10-31 1997-03-25 Intel Corporation System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals
US5623610A (en) * 1994-10-31 1997-04-22 Intel Corporation System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset
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US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
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Also Published As

Publication number Publication date
EP0366361A2 (en) 1990-05-02
EP0366361B1 (en) 1997-01-08
US4912633A (en) 1990-03-27
DE68927626T2 (en) 1997-09-04
KR900006866A (en) 1990-05-09
DE68927626D1 (en) 1997-02-20
JPH02127759A (en) 1990-05-16
KR920008458B1 (en) 1992-09-30

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