KR900002542A - 데이타 출력용 버퍼회로 - Google Patents

데이타 출력용 버퍼회로 Download PDF

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Publication number
KR900002542A
KR900002542A KR1019880008952A KR880008952A KR900002542A KR 900002542 A KR900002542 A KR 900002542A KR 1019880008952 A KR1019880008952 A KR 1019880008952A KR 880008952 A KR880008952 A KR 880008952A KR 900002542 A KR900002542 A KR 900002542A
Authority
KR
South Korea
Prior art keywords
pull
buffer circuit
transistor
data output
channel
Prior art date
Application number
KR1019880008952A
Other languages
English (en)
Other versions
KR910004735B1 (ko
Inventor
김건수
임형규
이형곤
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019880008952A priority Critical patent/KR910004735B1/ko
Priority to DE3910466A priority patent/DE3910466C2/de
Priority to JP1083847A priority patent/JPH02161692A/ja
Priority to US07/332,005 priority patent/US4972100A/en
Priority to GB8907333A priority patent/GB2221587B/en
Priority to NL8900795A priority patent/NL190742C/xx
Priority to FR8905106A priority patent/FR2634311B1/fr
Publication of KR900002542A publication Critical patent/KR900002542A/ko
Application granted granted Critical
Publication of KR910004735B1 publication Critical patent/KR910004735B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음.

Description

데이타 출력용 버퍼회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 3 도는 본 발명에서 공핍형 트랜지스터를 사용한 데이타 출력용 버퍼회로,
제 4 도는 각 데이타 출력용 버퍼회로에서 드라이버 구동 소자들의 전류대 전압 특성도,
제 5 도는 각 데이타 출력용 버퍼회로에서 전원에 따른 접지전 잡음비교도이다.

Claims (3)

  1. 풀다운 트랜지스터 및 풀업 트랜지스터가 CMOS 인버터와 연결된 버퍼회로에 있어서, 상기 CMOS 인버터를 구성한 NMOS 트랜지스터 및 PMOS 트랜지스터 사이에 공핍형 트랜지스터를 구성시켜 출력 드라이버의 구동속도가 제어되게한 데이타 출력용 버퍼회로.
  2. 제 1 항에 있어서, 출력측 드라이버에 P 채널인 풀업 트랜지스터(Mpu3)를 사용하고 N 채널인 풀다운트랜지스터(MpD3)를 사용하는 데이타 출력용 버퍼회로.
  3. 제 1 항 또는 제 2 항에 있어서, 출력측 드라이버에 구성되는 풀업 및 풀다운트랜지스터(MpU4)(MpD4)를 모두 N 채널형을 사용하는 데이타 출력용 버퍼회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880008952A 1988-07-10 1988-07-18 데이타 출력용 버퍼회로 KR910004735B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019880008952A KR910004735B1 (ko) 1988-07-18 1988-07-18 데이타 출력용 버퍼회로
DE3910466A DE3910466C2 (de) 1988-07-18 1989-03-31 Ausgangspufferschaltung für einen byte-weiten Speicher
JP1083847A JPH02161692A (ja) 1988-07-18 1989-03-31 バイト―ワイドメモリのデータ出力バッファ回路
US07/332,005 US4972100A (en) 1988-07-10 1989-03-31 Data output buffer circuit for byte-wide memory
GB8907333A GB2221587B (en) 1988-07-18 1989-03-31 Data output buffer circuit for byte-wide memory
NL8900795A NL190742C (nl) 1988-07-18 1989-03-31 Uitgangsbufferschakeling voor een byte-breed geheugen.
FR8905106A FR2634311B1 (fr) 1988-07-18 1989-04-18 Circuit tampon de sortie de donnees pour une memoire d'octets

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880008952A KR910004735B1 (ko) 1988-07-18 1988-07-18 데이타 출력용 버퍼회로

Publications (2)

Publication Number Publication Date
KR900002542A true KR900002542A (ko) 1990-02-28
KR910004735B1 KR910004735B1 (ko) 1991-07-10

Family

ID=19276180

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880008952A KR910004735B1 (ko) 1988-07-10 1988-07-18 데이타 출력용 버퍼회로

Country Status (7)

Country Link
US (1) US4972100A (ko)
JP (1) JPH02161692A (ko)
KR (1) KR910004735B1 (ko)
DE (1) DE3910466C2 (ko)
FR (1) FR2634311B1 (ko)
GB (1) GB2221587B (ko)
NL (1) NL190742C (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100300052B1 (ko) * 1998-09-19 2001-09-06 김영환 출력버퍼회로
KR100670672B1 (ko) * 2004-11-02 2007-01-17 주식회사 하이닉스반도체 반도체메모리소자

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JPH03185921A (ja) * 1989-12-14 1991-08-13 Toshiba Corp 半導体集積回路
JP2567153B2 (ja) * 1991-01-14 1996-12-25 株式会社東芝 Ｃｍｏｓ出力バッファ回路
JP3079515B2 (ja) * 1991-01-29 2000-08-21 株式会社東芝 ゲ−トアレイ装置及び入力回路及び出力回路及び降圧回路
US5120999A (en) * 1991-02-08 1992-06-09 Texas Instruments Incorporated Output-buffer noise-control circuit
KR930008656B1 (ko) * 1991-07-19 1993-09-11 삼성전자 주식회사 노이즈가 억제되는 데이타 출력 버퍼
JPH05243939A (ja) * 1991-11-20 1993-09-21 Nec Corp 半導体集積回路装置
EP0586207B1 (en) * 1992-08-31 1997-03-26 STMicroelectronics, Inc. Integrated circuit output driver
US5300828A (en) * 1992-08-31 1994-04-05 Sgs-Thomson Microelectronics, Inc. Slew rate limited output buffer with bypass circuitry
JP2968653B2 (ja) * 1992-09-03 1999-10-25 日本電気株式会社 出力回路
US5300837A (en) * 1992-09-17 1994-04-05 At&T Bell Laboratories Delay compensation technique for buffers
US5576640A (en) * 1992-09-25 1996-11-19 At&T Global Information Solutions Company CMOS driver for fast single-ended bus
US5477166A (en) * 1993-04-22 1995-12-19 Benchmarq Microelectronics Programmable output device with integrated circuit
US5367206A (en) * 1993-06-17 1994-11-22 Advanced Micro Devices, Inc. Output buffer circuit for a low voltage EPROM
US5682116A (en) * 1994-06-07 1997-10-28 International Business Machines Corporation Off chip driver having slew rate control and differential voltage protection circuitry
JP3537500B2 (ja) * 1994-08-16 2004-06-14 バー−ブラウン・コーポレーション インバータ装置
JPH0977184A (ja) * 1995-09-19 1997-03-25 Sato Sangyo Kk 粒体排出装置付袋を内側に嵌装したコンテナ
KR100206604B1 (ko) * 1996-06-29 1999-07-01 김영환 반도체 메모리 장치
WO1998008224A1 (fr) * 1996-08-16 1998-02-26 Mitsubishi Denki Kabushiki Kaisha Dispositif de circuit integre a semi-conducteurs
JPH1125678A (ja) 1997-06-27 1999-01-29 Samsung Electron Co Ltd 出力ドライバ及び半導体メモリ装置
US5949259A (en) * 1997-11-19 1999-09-07 Atmel Corporation Zero-delay slew-rate controlled output buffer
US6362665B1 (en) * 1999-11-19 2002-03-26 Intersil Americas Inc. Backwards drivable MOS output driver
US6570405B1 (en) * 2001-12-20 2003-05-27 Integrated Device Technology, Inc. Integrated output driver circuits having current sourcing and current sinking characteristics that inhibit power bounce and ground bounce
US6894529B1 (en) 2003-07-09 2005-05-17 Integrated Device Technology, Inc. Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control
US6967501B1 (en) 2003-12-18 2005-11-22 Integrated Device Technology, Inc. Impedance-matched output driver circuits having enhanced predriver control
CN101814842A (zh) * 2009-02-24 2010-08-25 飞思卡尔半导体公司 具有可调整驱动电流的高频电源开关电路
US8456939B2 (en) * 2009-12-11 2013-06-04 Arm Limited Voltage regulation circuitry
KR101326777B1 (ko) * 2012-04-12 2013-11-08 한국조폐공사 다층 보안 용지
US10879899B2 (en) * 2017-08-15 2020-12-29 Realtek Semiconductor Corp. Clock buffer and method thereof

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JPS5268304A (en) * 1975-12-05 1977-06-07 Fujitsu Ltd Transistor circuit
US4274014A (en) * 1978-12-01 1981-06-16 Rca Corporation Switched current source for current limiting complementary symmetry inverter
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KR890004212B1 (en) * 1983-07-08 1989-10-27 Fujitsu Ltd Complementary logic circuit
JPS60115092A (ja) * 1983-11-28 1985-06-21 Nec Corp 半導体記憶回路
JPS61267413A (ja) * 1985-05-22 1986-11-27 Fujitsu Ltd 入力バツフア回路
JPS62159917A (ja) * 1986-01-08 1987-07-15 Toshiba Corp 集積回路におけるインバ−タ回路
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100300052B1 (ko) * 1998-09-19 2001-09-06 김영환 출력버퍼회로
KR100670672B1 (ko) * 2004-11-02 2007-01-17 주식회사 하이닉스반도체 반도체메모리소자

Also Published As

Publication number Publication date
DE3910466C2 (de) 1993-10-21
JPH02161692A (ja) 1990-06-21
FR2634311B1 (fr) 1993-02-05
NL190742B (nl) 1994-02-16
GB2221587A (en) 1990-02-07
NL8900795A (nl) 1990-02-16
NL190742C (nl) 1994-07-18
DE3910466A1 (de) 1990-01-25
US4972100A (en) 1990-11-20
JPH0529995B2 (ko) 1993-05-06
FR2634311A1 (fr) 1990-01-19
GB8907333D0 (en) 1989-05-17
GB2221587B (en) 1992-04-15
KR910004735B1 (ko) 1991-07-10

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