KR880700460A - 실리콘 집적회로 및 그 제조 공정 - Google Patents

실리콘 집적회로 및 그 제조 공정

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Publication number
KR880700460A
KR880700460A KR1019860700526A KR860700526A KR880700460A KR 880700460 A KR880700460 A KR 880700460A KR 1019860700526 A KR1019860700526 A KR 1019860700526A KR 860700526 A KR860700526 A KR 860700526A KR 880700460 A KR880700460 A KR 880700460A
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layer
distance
less
top surface
silicon dioxide
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KR1019860700526A
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English (en)
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KR960000378B1 (ko
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충 창 츄안
캉 대원
캄거 애비드
칼 파릴로 루이스
Original Assignee
마이클 와이.엡스타인
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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Publication of KR880700460A publication Critical patent/KR880700460A/ko
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Publication of KR960000378B1 publication Critical patent/KR960000378B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/3143Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

내용 없음

Description

실리콘 집적회로 및 그 제조 공정
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 내지 제 3 도는 본 발명의 한 실시예에 따르는 회로를 여러가지로 계속 제조하는 단계동안, MOS 트랜지스터를 포함 하는 집적회로의 한 부분에 대한 횡단면도를 예시.

Claims (7)

  1. 상부 표면 밑 하부 표면을 갖는 질화물 실리콘 이산화물층을 포함하는 집적 회로에 있어서, 층의 상부 표면에의 질소비는 0.13보다 크며, 상기 층에서 질소비는 상기 표면으로 부터 약 30옹스트롬 또는 그이하의 제 1 거리에서 약 0.13밑의 값으로 내려가고, 상기 상부 표면으로부터 약 두배의 제 1 거리 혹은 그 이하의 제 2 거리에서 약 0.05이하 값으로 내려가는 것을 특징으로 하는 실리콘 집적회로.
  2. 제 1 항에 있어서, 상기 층의 질소비는 상기 층의 상부 표면으로부터 제 2 거리에 위치한 상부 단부와 상기 층의 하부 표면으로 부터 약 20옹스트롬 또는 그이하의 제 3 거리에 위치한 하부 단부의 중간 영역 전체에서 0.05 이하로 머무른다는 것을 특징으로 하는 실리콘 집적회로.
  3. 제 2 항에 있어서, 질소비는 상기 층의 하부 표면에서 중간 영역의 하부 단부에 연장된 상기 층의 하부 영역에서는 더이상 0.15를 못 올라간다는 것을 특징으로 하는 실리콘 집적 회로.
  4. 제 1 항에 있어서, 질화물 실리콘 이산화물 층의 두께가 대략 50 내지 400옹스트롬의 범위내인 것을 특징으로 하는 실리콘 집적 회로.
  5. 상부 표면 및 하부 표면을 갖는 질화물 실리콘 이산화물 층을 형성하도록 실리콘 이산화물 층을 질화하는 것을 포함하는 집적 회로 제조 과정에 있어서, 상기 층의 주 표면이 질소를 포함하는 주변에 노출되는 동안 최소한 약 섭씨 1200도의 온도로 증가되게 하도록 실리콘 이산화물 층을 고속 열 어니일링 하는 단계와, 그것에 의하여 질화물 실리콘 이산화물 층에서 질소비는 상부 표면에 약 0.13을 웃도는 값에서 상기 상부 표면으로 부터 약 30옹스트롬 또는 그이하의 제 1 거리에서 약 0.13 이하 값으로 내려가고, 또 상기 상부 표면으로부터 약 60옹스트롬 또는 그 이하의 제 2 거리에 약 0.05 이값으로 내려가는 것을 특징으로 하는 실리콘 집적 회로 제조 공정.
  6. 제 5 항에 있어서, 주변이 암모니아인 것을 특징으로 하는 실리콘 집적회로 제조 공정.
  7. 제 6 항에 있어서, 반도체 본체 및 상승된 온도상에 위치한 실리콘 이산화물 층이 최소한 약 섭씨 1250도인 것을 특징으로 하는 실리콘 집적 회로 제조 공정.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860700526A 1984-12-05 1985-11-13 실리콘 집적회로 및 그 제조 공정 KR960000378B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US678569 1984-12-05
US678,569 1984-12-05
US06/678,569 US4623912A (en) 1984-12-05 1984-12-05 Nitrided silicon dioxide layers for semiconductor integrated circuits
PCT/US1985/002243 WO1986003621A1 (en) 1984-12-05 1985-11-13 Nitrided silicon dioxide layers for semiconductor integrated circuits

Publications (2)

Publication Number Publication Date
KR880700460A true KR880700460A (ko) 1988-03-15
KR960000378B1 KR960000378B1 (ko) 1996-01-05

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Country Status (9)

Country Link
US (1) US4623912A (ko)
EP (1) EP0205613B1 (ko)
JP (1) JP2568527B2 (ko)
KR (1) KR960000378B1 (ko)
CA (1) CA1260364A (ko)
DE (1) DE3578656D1 (ko)
ES (1) ES8801968A1 (ko)
IE (1) IE57207B1 (ko)
WO (1) WO1986003621A1 (ko)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4882649A (en) * 1988-03-29 1989-11-21 Texas Instruments Incorporated Nitride/oxide/nitride capacitor dielectric
JPH0793298B2 (ja) * 1988-10-11 1995-10-09 日本電気株式会社 半導体装置の形成方法
US5874766A (en) * 1988-12-20 1999-02-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device having an oxynitride film
JPH02288235A (ja) * 1989-04-27 1990-11-28 Fujitsu Ltd 半導設装置の製造方法
US5242848A (en) * 1990-01-22 1993-09-07 Silicon Storage Technology, Inc. Self-aligned method of making a split gate single transistor non-volatile electrically alterable semiconductor memory device
US5572054A (en) * 1990-01-22 1996-11-05 Silicon Storage Technology, Inc. Method of operating a single transistor non-volatile electrically alterable semiconductor memory device
JP2907344B2 (ja) * 1990-06-27 1999-06-21 株式会社東芝 半導体装置およびその製造方法
US5254489A (en) * 1990-10-18 1993-10-19 Nec Corporation Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation
KR940011483B1 (ko) * 1990-11-28 1994-12-19 가부시끼가이샤 도시바 반도체 디바이스를 제조하기 위한 방법 및 이 방법에 의해 제조되는 반도체 디바이스
JP2652108B2 (ja) * 1991-09-05 1997-09-10 三菱電機株式会社 電界効果トランジスタおよびその製造方法
US5250456A (en) * 1991-09-13 1993-10-05 Sgs-Thomson Microelectronics, Inc. Method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby
US5449941A (en) * 1991-10-29 1995-09-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
US5726087A (en) * 1992-04-30 1998-03-10 Motorola, Inc. Method of formation of semiconductor gate dielectric
US6791131B1 (en) * 1993-04-02 2004-09-14 Micron Technology, Inc. Method for forming a storage cell capacitor compatible with high dielectric constant materials
US6531730B2 (en) * 1993-08-10 2003-03-11 Micron Technology, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US5392189A (en) * 1993-04-02 1995-02-21 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
TW264575B (ko) * 1993-10-29 1995-12-01 Handotai Energy Kenkyusho Kk
US5397720A (en) * 1994-01-07 1995-03-14 The Regents Of The University Of Texas System Method of making MOS transistor having improved oxynitride dielectric
US5629221A (en) * 1995-11-24 1997-05-13 National Science Council Of Republic Of China Process for suppressing boron penetration in BF2 + -implanted P+ -poly-Si gate using inductively-coupled nitrogen plasma
US5808335A (en) * 1996-06-13 1998-09-15 Vanguard International Semiconductor Corporation Reduced mask DRAM process
US5969397A (en) * 1996-11-26 1999-10-19 Texas Instruments Incorporated Low defect density composite dielectric
US6331468B1 (en) * 1998-05-11 2001-12-18 Lsi Logic Corporation Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers
US6177363B1 (en) 1998-09-29 2001-01-23 Lucent Technologies Inc. Method for forming a nitride layer suitable for use in advanced gate dielectric materials
US6380055B2 (en) 1998-10-22 2002-04-30 Advanced Micro Devices, Inc. Dopant diffusion-retarding barrier region formed within polysilicon gate layer
US6087236A (en) * 1998-11-24 2000-07-11 Intel Corporation Integrated circuit with multiple gate dielectric structures
US6303520B1 (en) 1998-12-15 2001-10-16 Mattson Technology, Inc. Silicon oxynitride film
JP3350478B2 (ja) * 1999-04-21 2002-11-25 宮城沖電気株式会社 半導体素子の製造方法
US6323143B1 (en) * 2000-03-24 2001-11-27 Taiwan Semiconductor Manufacturing Company Method for making silicon nitride-oxide ultra-thin gate insulating layers for submicrometer field effect transistors
US6559007B1 (en) * 2000-04-06 2003-05-06 Micron Technology, Inc. Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide
DE50006609D1 (de) 2000-08-28 2004-07-01 Medela Ag Baar Brusthaubeneinsatz
US6544908B1 (en) * 2000-08-30 2003-04-08 Micron Technology, Inc. Ammonia gas passivation on nitride encapsulated devices
JP2004538650A (ja) * 2001-08-10 2004-12-24 スピネカ セミコンダクター, インコーポレイテッド 基板とのショットキーコンタクトを形成する高誘電率ゲート絶縁層、ソースおよびドレインを有するトランジスタ
US6878415B2 (en) * 2002-04-15 2005-04-12 Varian Semiconductor Equipment Associates, Inc. Methods for chemical formation of thin film layers using short-time thermal processes
US6780720B2 (en) 2002-07-01 2004-08-24 International Business Machines Corporation Method for fabricating a nitrided silicon-oxide gate dielectric
KR20110057645A (ko) * 2009-11-24 2011-06-01 삼성전자주식회사 절연막 형성 방법 및 이를 포함하는 트랜지스터 형성 방법
KR101562020B1 (ko) * 2010-02-22 2015-10-21 삼성전자주식회사 반도체 소자 및 그 제조 방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0006706B2 (en) * 1978-06-14 1993-03-17 Fujitsu Limited Process for producing a semiconductor device having an insulating layer of silicon dioxide covered by a film of silicon oxynitride

Also Published As

Publication number Publication date
EP0205613A1 (en) 1986-12-30
EP0205613B1 (en) 1990-07-11
IE57207B1 (en) 1992-06-03
ES549560A0 (es) 1988-03-16
JPS62501184A (ja) 1987-05-07
CA1260364A (en) 1989-09-26
WO1986003621A1 (en) 1986-06-19
US4623912A (en) 1986-11-18
JP2568527B2 (ja) 1997-01-08
IE853050L (en) 1986-06-05
ES8801968A1 (es) 1988-03-16
DE3578656D1 (de) 1990-08-16
KR960000378B1 (ko) 1996-01-05

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