KR870002645A - 반도체장치의 제조방법 - Google Patents
반도체장치의 제조방법 Download PDFInfo
- Publication number
- KR870002645A KR870002645A KR1019860005855A KR860005855A KR870002645A KR 870002645 A KR870002645 A KR 870002645A KR 1019860005855 A KR1019860005855 A KR 1019860005855A KR 860005855 A KR860005855 A KR 860005855A KR 870002645 A KR870002645 A KR 870002645A
- Authority
- KR
- South Korea
- Prior art keywords
- melting point
- high melting
- point metal
- gas
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims 6
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims 7
- 230000008018 melting Effects 0.000 claims 7
- 239000007789 gas Substances 0.000 claims 6
- 238000000034 method Methods 0.000 claims 6
- 239000002184 metal Substances 0.000 claims 4
- 229910001512 metal fluoride Inorganic materials 0.000 claims 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 2
- 239000011261 inert gas Substances 0.000 claims 2
- 150000002736 metal compounds Chemical class 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1(c)도는 본 발명의 1실시예의 제작공정도.
제2(c)도는 다른 실시예의 제작공정도.
제4도는 W의 포화막 두께와 퇴적온도의 관계를 나타낸 측정데이터.
* 도면의 주요부분에 대한 부호의 설명
11 : P형 Si기판 12 : n+gid 확산층(전극 배선층)
13 : 산화막 14 : 접속구
15, 17 : W막 16 : Al 배선
Claims (3)
- 확산층 또는 전극 배선층(12)중 최소한 한쪽이 형성된 반도체기판(11)에 절연막(13)을 형성하는 공정과, 상기 절연막(13)에 상기 확산층 또는 전극배선층(12)에 대한 접속구(14)를 형성하는 공정, 상기 접속구(14)내에 선택기상성장법에 의해 고융점금속막(15)을 매립하는 공정, 매립된 고융점금속막(15)에 접속되는 배선(16)을 형성하는 공정을 구비한 반도체장치의 제조방법에 있어서, 상기 고융점금속막(15)의 선택기상성장공정은 최소한 성장초기의 조건으로서 기판온도 500∼600℃, 반응로 내의 압력 0.01∼1torr, 고융점 금속화합물 가스분압 0.001∼0.5torr로 설정된 것을 특징으로 하는 반도체 장치의 제조방법.
- 제1항에 있어서, 고융점 금속화합물가스가 불활성가스 또는 수소가스에 의해 희석된 고융점금속 불화물가스인 것을 특징으로 하는 반도체 장치의 제조방법.
- 제1항에 있어서, 고융점금속막(15)의 선택기상 성장공정은 금속불화물 가스와 불활성가스를 이용한 초기조건을 만족시키는 제1의 성장공정과, 이것에 있따라 금속불화물가스와 수소가스를 이용한 제2의 성장공정으로 된 것을 특징으로 하는 반도체 장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60170764A JPS6231116A (ja) | 1985-08-02 | 1985-08-02 | 半導体装置の製造方法 |
JP60-170764 | 1985-08-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR870002645A true KR870002645A (ko) | 1987-04-06 |
KR900001654B1 KR900001654B1 (ko) | 1990-03-17 |
Family
ID=15910942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860005855A KR900001654B1 (ko) | 1985-08-02 | 1986-07-19 | 반도체장치의 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5071789A (ko) |
JP (1) | JPS6231116A (ko) |
KR (1) | KR900001654B1 (ko) |
DE (1) | DE3625860A1 (ko) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5643310A (en) * | 1979-09-19 | 1981-04-22 | Sumitomo Naugatuck Co Ltd | Production of copolymer latex |
EP0319214A1 (en) * | 1987-12-04 | 1989-06-07 | AT&T Corp. | Method for making semiconductor integrated circuits using selective tungsten deposition |
FR2624304B1 (fr) * | 1987-12-04 | 1990-05-04 | Philips Nv | Procede pour etablir une structure d'interconnexion electrique sur un dispositif semiconducteur au silicium |
US5055423A (en) * | 1987-12-28 | 1991-10-08 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
EP0326956A3 (en) * | 1988-02-02 | 1991-03-13 | National Semiconductor Corporation | Method for connecting devices on an integrated circuit substrate to a metallization layer |
FR2630587A1 (fr) * | 1988-04-22 | 1989-10-27 | Philips Nv | Procede pour etablir des contacts electriques de petites dimensions sur un dispositif semiconducteur |
JPH01298765A (ja) * | 1988-05-27 | 1989-12-01 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5202287A (en) * | 1989-01-06 | 1993-04-13 | International Business Machines Corporation | Method for a two step selective deposition of refractory metals utilizing SiH4 reduction and H2 reduction |
US5110760A (en) * | 1990-09-28 | 1992-05-05 | The United States Of America As Represented By The Secretary Of The Navy | Method of nanometer lithography |
KR950012918B1 (ko) * | 1991-10-21 | 1995-10-23 | 현대전자산업주식회사 | 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법 |
US5227336A (en) * | 1991-12-27 | 1993-07-13 | Small Power Communication Systems Research Laboratories Co., Ltd. | Tungsten chemical vapor deposition method |
JP3326698B2 (ja) * | 1993-03-19 | 2002-09-24 | 富士通株式会社 | 集積回路装置の製造方法 |
DE4417966A1 (de) * | 1994-05-21 | 1995-11-23 | Fraunhofer Ges Forschung | Verfahren zur modularen Kontaktierung mehrlagiger Halbleiterbauelemente |
US5484747A (en) * | 1995-05-25 | 1996-01-16 | United Microelectronics Corporation | Selective metal wiring and plug process |
JPH0922896A (ja) * | 1995-07-07 | 1997-01-21 | Toshiba Corp | 金属膜の選択的形成方法 |
JPH09139429A (ja) * | 1995-11-10 | 1997-05-27 | Nippon Steel Corp | 半導体装置の製造方法 |
JPH1064848A (ja) * | 1996-08-13 | 1998-03-06 | Toshiba Corp | 半導体装置の製造装置および製造方法 |
US8722417B2 (en) * | 2003-04-28 | 2014-05-13 | Invoy Technologies, L.L.C. | Thermoelectric sensor for analytes in a fluid and related method |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS543480A (en) * | 1977-06-09 | 1979-01-11 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS5948952B2 (ja) * | 1981-03-23 | 1984-11-29 | 富士通株式会社 | 金属薄膜の形成方法 |
JPS5928360A (ja) * | 1982-08-10 | 1984-02-15 | Nec Corp | 半導体装置の製造方法 |
JPS5961446A (ja) * | 1982-09-30 | 1984-04-07 | Toshiba Corp | 超電導回転子の電磁ダンパ−シ−ルドおよびその製造方法 |
JPS5984576A (ja) * | 1982-11-08 | 1984-05-16 | Nec Corp | 半導体装置の製造方法 |
JPS5963745A (ja) * | 1983-06-06 | 1984-04-11 | Nec Corp | 半導体装置 |
JPS6050920A (ja) * | 1983-08-30 | 1985-03-22 | Toshiba Corp | 半導体装置の製造方法 |
JPS60138940A (ja) * | 1983-12-27 | 1985-07-23 | Toshiba Corp | 半導体装置の製造方法 |
JPS60186038A (ja) * | 1984-03-05 | 1985-09-21 | Fujitsu Ltd | 半導体装置 |
JPS60229350A (ja) * | 1984-04-27 | 1985-11-14 | Toshiba Corp | 半導体装置の製造方法 |
JPS615580A (ja) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | 半導体装置の製造方法 |
-
1985
- 1985-08-02 JP JP60170764A patent/JPS6231116A/ja active Pending
-
1986
- 1986-07-19 KR KR1019860005855A patent/KR900001654B1/ko not_active IP Right Cessation
- 1986-07-31 DE DE19863625860 patent/DE3625860A1/de not_active Ceased
-
1990
- 1990-06-12 US US07/536,933 patent/US5071789A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6231116A (ja) | 1987-02-10 |
KR900001654B1 (ko) | 1990-03-17 |
US5071789A (en) | 1991-12-10 |
DE3625860A1 (de) | 1987-02-12 |
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G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
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FPAY | Annual fee payment |
Payment date: 19930311 Year of fee payment: 4 |
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LAPS | Lapse due to unpaid annual fee |