KR850005152A - 반 도 체 장 치 - Google Patents

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KR850005152A
KR850005152A KR1019840007370A KR840007370A KR850005152A KR 850005152 A KR850005152 A KR 850005152A KR 1019840007370 A KR1019840007370 A KR 1019840007370A KR 840007370 A KR840007370 A KR 840007370A KR 850005152 A KR850005152 A KR 850005152A
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side wall
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semiconductor device
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KR1019840007370A
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KR930007518B1 (ko
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마사오 야마구지 (외 1)
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미쓰다 가쓰시게
가부시기 가이샤 히다찌새이사꾸쇼
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음

Description

반 도 체 장 치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 리이드 프레임에 칩을 부착한 상태를 도시한 리이드 프레임의 사시도,
제2도는 제1도에 도시되는, 리이드 프레임을 레진몰드 할 때의 상태를 도시한 단면도,
제3도는 레진몰드 공정이 끝났을 때의 트랜지스터의 외형을 도시한 사시도,
제6도는 제5도에 도시되는 절연형 트랜지스터의 구성 부분인 리이드프레임의 외형을 도시한 사시도.

Claims (6)

  1. 다음 사항으로 되는 반도체 장치, (1) 전기 도전성과 열전도성이 좋은 물질로 되는 햇더; (2) 상기 햇더의 1주면 위에 고정된 칩; (3) 전기 전도성이 좋은 물질로 되는 다수개의 리이드; (4) 상기 칩과 상기 리이드를 전기적으로 접속하는 와이어; (5) 상기 햇더, 상기 칩, 상기 리이드의 일부, 상기 와이어를 덮고, 제1주면과, 제1주면에 대량하는 제2주면과, 상기 제1주면과, 제2주면과의 사이에 존재하는 다수개의 측벽을 가진 봉지체; 그리고, (6) 상기 햇더에 그 한쪽 끝이 연접하고, 또한 그 다른 쪽 끝이, 상기 봉지체에서 노출하는 햇더 지지체에 있어서, 상기 햇더 지지체의 다른 쪽 끝은 상기 봉지체의 측벽보다도 봉지에 내측에서 종단하고 있다.
  2. 다음 사항으로 되는 반도체 장치, (1) 전기 전도성과 열전도성이 좋은 물질로 되는 햇더(5); (2) 상기 햇더의 1주면위에 고정된 칩(14); (3) 전기 도전성이 좋은 물질로 되는 다수개의 리이드(2a,2b,2c); (4) 상기 칩과 상기 리이드를 전기적으로 접속하는 와이어(15); (5) 상기 햇더, 상기 칩, 상기 리이드의 일부, 상기 와이어를 덮고, 또한 제1주면(1a)와, 상기 제1주면에 대향하는 제2주면(1b)와, 상기 제1주면과, 제2주면에 걸치는 제1측벽(1c)와, 상기 제1측벽에 대향하고, 상기 제1 및 제2의 주면에 걸치는 제2측벽(1d)와, 상기 제1주면 및 제2주면과, 상기 제1측벽 및 제2측벽에 걸치는 제3측벽(1e)와, 상기 제3측벽에 대향하며, 상기 제1 및 제2의 주면과 상기 제1 및 제2의 측벽에 걸치는 제4측벽(1f)와, 상기 제2측벽(1d)와, 제4측벽(1f)에 걸쳐서 마련된 제1의 스텝포오션(26a)와, 상기 제2측벽(1d)과 제3측벽(1e)에, 걸쳐서 마련된 제2의 스템포오션(26b)을 가진 봉지체(1) 그리고, (6) 상기 햇더에, 그 한쪽끝이 연접하고 또한 그 다른쪽끝이 상기 봉지체에서 노출하는 2개의 햇더 지지체(6a,6b)에 있어서 상기 제1의 스텝포오션(26a)에는, 제1의 홈(28a)이 마련되어 있으며, 상기 제2의 스텝포오션(26b)에는, 제2의 홈(28b)가 마련되어 있고, 그리고, 상기 햇더 지지체(6a)의 다른쪽 끝은 상기 제1의 홈내의, 상기 제4측벽(1f)보다도 내측에 있어서, 종단하고 있으며, 상기 햇더 지지체(6b)의 다른쪽 끝은, 상기 제2의 홈내의, 상기 제3측벽(1e)보다도, 내측에, 종단하고 있다.
  3. 특허청구의 범위 제1항에 따르는 반도체 장치에 있어서, 봉지체는 레진으로 된다.
  4. 다음 사항으로 되는 반도체 장치, (1) 전기 도전성과 열 전도성이 좋은 물질로 되는 햇더(5'); (2) 상기 햇더의 1주면위에 고정된 칩(14'); (3) 전기 도전성이 좋은 물질로 되는 다수개의 리이드(2a',2b',2c'); (4) 상기 칩과 상기 리이드를 전기적으로 접속하는 와이어(15'); (5) 상기 햇더, 상기 칩, 상기 리이드의 일부, 상기 와이어를 덮고, 또한 제1주면(1a')와, 상기 제1주면 대향하는 제2주면(1b')와, 제1스텝포오션(1g')와, 제2스텝포오션(1h')와, 상기 제1주면(1a')와, 상기 제2주면(1b')와, 제2스텝포오션(1g')와, 제2스텝포오션(1h')에 걸치는 제1벽측 (1e')와, 상기 제1측벽에 대향하고, 상기 제1주면과, 제2주면과, 제1스텝포오션과, 제2스텝포오션에 걸치는 제2측벽(1f')와, 상기 제1주면(1a')와, 제2주면(1b')와, 제1측벽(1e')와, 제2측벽(1f')에 걸치는 제3측벽(1c')와 상기 제3측벽(1c')에 대향하고 제1주면(1a')와, 제2스텝포오션(1h')와, 제1측벽(1e')와 제2측벽(1f')에 걸치는 제4측벽(1d')와를 가진 봉지체(1').
    (6) 상기 햇더에 그 한쪽 끝이 연접하고 또한, 그 다른 쪽 끝이 상기 봉지체에서 노출하는 햇더 지지체 (6a',6b')에 있어서, 상기 제2스텝포오션(1h')에는, 홈(28a',28b')가 마련되어 있으며, 상기 햇더 지지체(6a',6b')의 다른 쪽 끝은 상기 홈(28a',28b')내의 상기 제4측벽(1d') 보다도 내측에 있어서, 종단하고 있다.
  5. 특허청구의 범위 제3항에 따르는 반도체 장치에 있어서, 봉지체는 레진으로 된다.
  6. 특허청구의 범위 제13항에 따르는 반도체 장치에 있어서, 상기 봉지체에는 제1스텝포오션(1g')에서, 제1주면에 달하는 개공이 마련되어 있다.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840007370A 1983-12-16 1984-11-24 반도체장치 KR930007518B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58236154A JPS60128646A (ja) 1983-12-16 1983-12-16 絶縁型パワートランジスタの製造方法
JP58-236154 1983-12-16

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KR850005152A true KR850005152A (ko) 1985-08-21
KR930007518B1 KR930007518B1 (ko) 1993-08-12

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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60172346U (ja) * 1984-04-23 1985-11-15 新電元工業株式会社 樹脂密封型半導体装置
JPS61207040U (ko) * 1985-06-17 1986-12-27
JPS62180957U (ko) * 1986-05-06 1987-11-17
JPH079917B2 (ja) * 1987-05-11 1995-02-01 サンケン電気株式会社 樹脂封止型半導体装置の製造方法
JPH0824156B2 (ja) * 1987-05-25 1996-03-06 サンケン電気株式会社 樹脂封止型半導体装置の製造方法
JPH0744194B2 (ja) * 1989-02-17 1995-05-15 サンケン電気株式会社 樹脂封止形半導体装置の製造方法
US5028741A (en) * 1990-05-24 1991-07-02 Motorola, Inc. High frequency, power semiconductor device
JP3598579B2 (ja) * 1995-04-17 2004-12-08 株式会社デンソー 電磁弁ブロック
US20040113240A1 (en) 2002-10-11 2004-06-17 Wolfgang Hauser An electronic component with a leadframe
JP4953205B2 (ja) * 2007-05-01 2012-06-13 三菱電機株式会社 半導体装置
US11602055B2 (en) 2018-09-04 2023-03-07 Apple Inc. Overmolded components having sub-flush residuals

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS615818Y2 (ko) * 1979-06-07 1986-02-21
US4451973A (en) * 1981-04-28 1984-06-05 Matsushita Electronics Corporation Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor
JPS57188858A (en) * 1981-05-18 1982-11-19 Matsushita Electronics Corp Plastic molded type semiconductor device
JPS58143538A (ja) * 1982-02-19 1983-08-26 Matsushita Electronics Corp 樹脂封止形半導体装置の製造方法

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KR930007518B1 (ko) 1993-08-12
JPH0527261B2 (ko) 1993-04-20
GB2151845A (en) 1985-07-24
GB8429620D0 (en) 1985-01-03
JPS60128646A (ja) 1985-07-09

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