GB2151845A - A semiconductor memory - Google Patents
A semiconductor memory Download PDFInfo
- Publication number
- GB2151845A GB2151845A GB08429620A GB8429620A GB2151845A GB 2151845 A GB2151845 A GB 2151845A GB 08429620 A GB08429620 A GB 08429620A GB 8429620 A GB8429620 A GB 8429620A GB 2151845 A GB2151845 A GB 2151845A
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- United Kingdom
- Prior art keywords
- header
- resin
- transistor
- guides
- side wall
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01057—Lanthanum [La]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
A lead frame (4) used for producing the power transistor has guides (6a, 6b) supporting a header during a resin-molding step. A V-shaped groove (13) is formed at a cut portion of each guide in such a fashion that it is exposed further inward than the outer wall of a resin package after the resin molding. The V-shaped grooves can provide a power transistor which has a high degree of moistureproofing. Since the cut portions of the guides, that is, the positions of the V-shaped grooves, are further inward than the outer wall of the resin package, a power transistor with a high withstand voltage can be obtained. <IMAGE>
Description
SPECIFICATION
A semiconductor device
This invention relates to semiconductor devices such as insulated power transistors.
The power transistor is known as one of the resin-packaged semiconductor devices (transistors). Power transistors are applied to a variety of appliances in which high voltages and high power levels are required, and are used as driving transistors for driving motors in home appliances, or as output-stage transistors to obtain audio outputs.
Since a power transistor easily generates heat within itself, its characteristics will be affected thereby unless that heat is efficiently radiated from the transistor. A known power transistor has a package shape such that a semiconductor element (called a chip) is fixed to an electrically-conductive header, and the reverse of the header is exposed so that the heat generated in the chip during operation is radiated outward. When packaging the transistor, the transistor is usually screwed onto a metal heat sink plate in order to further improve the heat radiation. In this case, an insulating sheet which is highly conductive of heat is inserted and screwed between the header and the metal heat sink plate, in order to prevent the potential of the header (which is the same as the potential of an electrode formed on the reverse of the chip) from reaching earth potential.
In order to eliminate the trouble of inserting this insulating sheet between the heat sink plate and the header when packaging the transistor, an insulated power transistor with a structure in which the reverse of the header is also molded from resin has been developed recently.
In accordance with this resin package, a separate insulating sheet need not be provided, and packaging can be done easily because the reverse of the header is also resin-molded. The transistor of this structure is referred to as a "full package" in this field. An example of such a transistor is disclosed in "NEC TECHNICAL JOURNAL", Vol. 36, No. 21, 1983, pp. 68-71, published by K.K. Nippon Bunka
Center.
In a transistor of this kind, a semiconductor element (chip) is fixed to the main surface of a heatradiating header. The inner peripheral surface of fitting holes provided in the header are covered with resin as well as both the upper and lower surface of the header.
The resin on the lower surface of the header is made extremely thin to reduce thermal resistance, so that the heat generated in the chip during operation can be efficiently radiated outward. In order to form such a thin resin film on the lower surface of the header, it is necessary to let the resin flow down to the lower surface of the header within the mold, and, to accomplish this object, the header must be supported so that it is floating to a limited extent. Header supports (or "guides") act as this support.
To provide the resin molding, header supports (guides), etc., are inserted between the upper and lower molds, and the resin is then charged thereinto. Thereafter, unwanted portions of a lead frame and the guides are cut off, providing the resin package.
However, we have discovered the following problems.
(a) Since the end portions of thin guides (header supports) continuing from the header project from the periphery of the resin package in such an insulated power transistor, a discharge is likely to occur if such a guide end portion is close to a conductive portion of an electronic component adjacent thereto when the resin package is assembled into an electronic appliance or the like, and hence high-density packaging on a packaging substrate is difficult.
(b) The guides are formed when the resin package is cut off from the frame portion of the lead frame after resin molding. In order to reduce the projecting lengths of the guides, the cutting position is selected to be as close as possible to the outer surface of the resin package. Accordingly a large external force acts upon each guide during the cutting, and there is a high likelihood that cracks will develop in the interface between the resin of the resin package and the guide. If such cracks develop, moisture can enter the package therethrough, so that the moisture-proofness of the resin package drops, and it is thus difficult to provide a highly moisture-proof resin package.
It is an object of the present invention to overcome partially or wholly the above disadvantages and thereby provide an insulated semiconductor device which has a high withstand voltage and which can be packaged close to other conductors.
According to the present invention there is provided a semiconductor device including:
(a) a header consisting of a material which has a high electric conductivity and high heat conductivity;
(b) a chip fixed to one main surface of said header;
(c) a plurality of leads consisting of a material of a high electric conductivity;
(d) wires electrically connecting said chip to said leads;
(e) a molding member covering said header, said chip, parts of said leads, and said wires, and which has a first main plane, a second main plane opposite to said first main plane, and a plurality of said walls between said first and second main planes; and
(f) a header support of which one edge is connected to said header and another edge thereof is exposed from said molding member, the another edge of said header support terminating at a position further inward within said molding member than said side walls of said molding member.
The following advantages can be obtained as a result of the above construction:
(a) The transistor has a structure such that resin with a large insulating effect covers the lower surface and side surface of each guide, and the tip of the guide is recessed more deeply inward than the peripheral surface of the resin package. Accord ingly, mounting plates and the guides can be insulated from one another during the packaging of the transistor, no discharge occurs during the operation of the transistor, and the withstand voltage can be improved.
(b~ When cutting off the guides from the lead frame in the transistor, they are cut off utilizing the
V-shaped grooves provided at the cut portions of the guides. Therefore, no large stress is applied to the guides, and the resin and the guides can be kept in close contact with each other to improve the moistureproofing.
The present invention will now be described in greater detail by way of examples with reference to the accompanying drawings, wherein:
Figure 1 is a perspective view of a lead frame, showing a chip fitted to a lead frame;
Figure 2 is a section showing how the lead frame of Figure 1 is resin-molded;
Figure 3 is a perspective view of a transistor when the resin-molding step is completed;
Figure 4 is a perspective view of the transistor of
Figure 3 after the guides 6 and the unwanted portions of the lead frame have been removed;
Figure 5 is a perspective view of the insulated transistor in accordance with another embodiment of the present invention;
Figure 6 is a perspective view of the lead frame which is a component of the insulated transistor of
Figure 5; and
Figure 7 is a section through the insulated transistor of Figure 5, taken along the line A-A'.
In this specification, the longitudinal direction of the lead is defined as the length, a direction perpendicular to the longitudinal direction of the lead as the width, and a direction perpendicular to the main surface of the lead as the height (or thickness).
Figures 1 to 4 are perspective views and a section showing the method of producing the insulated power transistor in accordance with one embodiment of the present invention.
As shown in Figure 4, the insulated power transistor of this embodiment consists of a rectangular resin package 1 (10 mm wide, 16 mm-17 mm long, and 5 mm thick) and three leads 2a, 2b and 2c (15 mm long and 0.4 mm thick) that project from one end surface of this resin package 1. A mounting hole 3 (3.1 mm in diameter) through which a screw is inserted when packaging the transistor is defined in the resin package 1. This mounting hole 3 is made in insulating resin.
The method of producing (assembling) this transistor will now be described with reference to Figures 1 to 4, to enable an explanation of details of the transistor.
When assembling the transistor, a lead frame 4 such as that shown in Figure 1 is used. This lead frame 4 is formed by patterning a metal sheet which has a good heat-radiating property, such as sheet copper, by a precision press or the like. This metal sheet is an odd-shaped sheet of varying thickness, such that a header 5 of the lead frame 4 is as thick as 1.26 mm, while leads 2a, 2b, and 2c and guides 6a and 6b that extend from both sides of the header 5 are as thin as 0.4 mm. The upper surfaces (main planes) of the leads 2a, 2b, 2c and guides 6a, 6b are on the same level. In other words, the lower surfaces of the guides 6a, 6b and leads 2a, 2b, 2c are positioned higher than the lower surface of the header 5. This difference in height enables the leads 2a, 2b, 2c to project from an intermediate height position of the resin package 1.This arrangement also makes it possible to float the header 5 inside the cavity of a mold, and enable the resin to flow thinly and uniformly over the lower surface of the header 5 when resin molding is carried out, utilizing the leads 2a, 2b, 2c and the guides 6a, 6b, as will be described later.
The specific shape of the lead frame will now be described. The lead frame 4 has a thin frame portion 7 (0.9 mm wide) and three leads 2a, 2b, 2c that extend parallel from one side of the frame portion 7. (The lead 2b is used as a collector lead while leads 2a and 2c are used as an emitter lead and a base lead, respectively.) The three leads 2a, 2b, 2c are connected to one another by a thin dam plate 8 (1.0 mm wide) that extends parallel to the frame portion 7.
This dam plate 8 functions as a reinforcing member when the lead frame 4 is being handled. For this reason, the dam plate 8 is wider than the frame portion 7. The dam plate 8 also functions as a dam which prevents the outflow of the resin towards the leads 2a, 2b, 2c during the resin molding. A recess 22 and a wire connection portion (2.5 mm wide and 1 mm long) are provided at the end of each of the leads 2a and 2c. These recesses 22 are provided so that when the ends of the leads 2a, 2c are positioned inside the resin package 1, the wire connection portions 9 bite into the resin and are not pulled off. The ends of the wire connection portion 9 (the floating ends) are made wide in order to secure a sufficiently wire-bonding area.
The lead 2b in the center continues from the header 5. This header 5 consists of a chip-mounting portion 10 (8 mm wide and between 4 mm to 5 mm long) and a mounting hole portion 12 (6 mm wide and 9 mm long) which is slightly narrower than the chip-mounting portion 10 and is part of the header 5. A through-hole 11 of a diameter of 4 mm is bored at the center of this mounting hole portion 12. The through-hole 11 has a larger diameter than the mounting hole 3 (3.1 mum in diameter) of the resin package 1. The diameters of the through-hole 11 and the mounting hole 3 must be selected as suitable in accordance with the desired withstand voltage, because the resin between them functions as an insulating member between the screw inserted into the mounting hole 3 and the header 5. In this embodiment, the resin is 0.45 mm thick and provides a withstand voltage of 7 KV.
The term "withstand voltage" means the voltage applied immediately before the insulating film consisting of the resin between the metal heat-radiating plate or screw and the header breaks down by the application of a bias voltage between the heatradiating plate and the header.
Two thin guides 6a, 6b (0.4 mm wide) that extend parallel to the dam plate 8 and the frame por tion 7, are provided at the end of the header 5 on the side of the mounting hole portion 12. A Vshaped groove 13 is cut across each guide 6a, 6b at an intermediate portion between its surface on the side of the mounting hole portion 12 and its side surface on the side of the chip-mounting portion 10. The depth of the groove 13 is preferably 0.2 mm when the guides 6a, 6b are 0.4 mm thick. If the grooves 13 have such a depth, the guides 6a, 6b can be easily cut off and, at the same time, the lead frame 4 can ensure sufficient mechanical strength.
When assembling the transistor using the lead frame 4, the chip (semiconductor element) 14 is first mounted onto the chip-mounting portion 10 of the lead frame 4 by a conductive adhesive such as solder, as shown in Figure 1. An npn (or pnp) transistor is formed on this chip 14. The base and emitter electrodes (not shown) of this transistor are in the same main plane, while the collector electrode is on the reverse. Next, the emitter electrode of the chip is electrically connected to the lead 2a (or 2c) by a wire 15, and the base electrode to the lead 2c (or 2a) by wire 15. Similarly, the reverse of the chip 14 is electrically connected to the lead 2b, because it acts as the collector electrode.
Thereafter, the leads 2a, 2b, 2c at the end of the dam plate 8, the header portion, and part of the guides are resin-molded. In this instance, the lead frame 4 is held inverted between a lower mold 16 and an upper mold 17, as shown in Figure 2. With the lead frame 4 held in this position, resin 19 is charged into a cavity 18 of the mold from a gate 23 denoted by the dot-dash line in the drawing, so that the assembly is partially covered with the resin package 1, as shown in Figure 3. The portions of the upper and lower molds 17, 16 corresponding to the mounting hole 3 have no cavities because the mounting hole 3, which has a smaller diameter than the through-hole 11, must be formed at the position of the resin package 1 corresponding to the through-hole 11 of the lead frame 4.
The upper surface portions of the guides 6, in which the grooves 13 are provided, are supported by the lower mold, as shown by the broken line in
Figure 2, so that they are exposed from the package 1 in grooves 28a, 28b that are formed in step portions 26a, 26b provided at the corners of the package 1, as shown in Figure 3. The resin package 1 consists of a first main plane 1a, a second main plane 1b opposite to the first main plane 1a, a first side wall 1c, a second side wall 1d, a third side wall 1e, and a fourth side wall 1f, as well as the step portions 26a and 26b, as shown in Figure 3.
In Figure 2, the upper and lower molds 17 and 16 may be turned upside down. However, when the upper surfaces of the guides 6a and 6b are supported by the lower mold, the suspended length of the guides 6a, 6b is shorter and the height of the header 5 within the cavity is believed to be most stable, as in this embodiment.
In order to obtain the highest heat-radiating property of the transistor during resin molding, the resin provided over the lower surface of the header 5 must be as thin and as uniform as possible, within ranges in which the desired insulating property can be maintained. In this embodiment, the resin thickness is preferably between 0.3 mm to 0.4 mm, and a withstand voltage of between 4.8 KV to 6.4 KV can be obtained in such a case. A contrivance is made for the lead frame 4 in order to form this resin as thinly and uniformly as possible. The contrivance is to finish obliquely a side surface 10a of a header end portion 10b facing the gate 23, as shown in Figure 2.According to this arrangement, the resin charged through the gate 23 first impinges against the oblique side surface, and part of the resin is smoothly charged towards the lower surface of the header 5 before the upper surface of the header is covered by the resin. In consequence, the resin between the header 5 and the lower surface becomes uniform and has a high quality, although it is thin, and a transistor which has a high degree of moistureproofing and a high withstand voltage can be obtained.
Next, as shown in Figure 3, when the guides 6a and 6b project from the side surface of the resin package 1 are pushed upward by only weak forces, denoted by thick arrows, they can be easily separated because of stress concentrations at the grooves 13. The unwanted portions of the lead frame 4, that is, the dam plate 8 and the frame portion 7, are cut off and removed, providing a transistor such as that shown in Figure 4.
Since no large force acts upon the interface between the guides 6a, 6b and the resin, as described above, no cracks or the like occur, and a transistor with a high degree of moistureproofing can be obtained. The upper surfaces of the guides 6a and 6b that remain in the transistor are exposed, but their lower and side surfaces are covered with the insulating resin. Therefore, even when conductors are arranged below and close to the lower surface of the resin package, no discharge occurs between the guides 6a, 6b and the conductors, and a transistor with a high withstand voltage can be obtained. Since the withstand voltage is high and since there are no projecting portions around the periphery of the resin package, the transistor can be packaged to a high packaging density.
Figure 5 is a perspective view of the insulated power transistor in accordance with another embodiment of the present invention.
Figure 6 shows the lead frame used for producing the insulated power transistor of Figure 5, and
Figure 7 is a section through of the insulated power transistor of Figure 5, taken along the line
A-A'.
Hereinafter, this embodiment will be described with reference to Figures 5 to 7, in which the same reference numerals are used to identify components the same as those in the foregoing embodiment.
The resin package will be described first.
The resin package 1 shown in Figures 5 and 7 can be obtained by use of the lead frame 4 shown in
Figure 6. The resin package 1 consists of a first main plane la', a second main plane Ib' a first step portion 1g', a second step portion 1h', a first side wall 1e', a second side wall If, a third side wall Ic' and a fourth side wall 1d'. The height from the first main plane 1a' to the second main plane Ib' of the resin package 1 is 5 mm. The moistureproofing of the transistor will drop, particularly when the tops of the loops of wire 15 are exposed outside the package 1. Therefore, tops 26 of the loops are positioned within the resin.In this embodiment, guides 6a, 6b provided with the grooves 13' extend in the direction of the leads 2a, 2b, 2c, and their ends continue from another frame portion 21, which will be described later.
A mounting hole 3' (3.1 mm in diameter) is provided in the first step portion 1g' of the resin package 1. Since the surface of this transistor with the mounting hole 3' is lower (by 1 mm) than the uppermost surface of the resin package 1, the screw head (5 mm in diameter and between 1 mm to 1.2 mm long) of a screw (having a screw portion of 3 mm diameter) does not project or projects only slightly from the uppermost of the resin package 1 when the screw is fitted. In other words, the height from the lower surface of the resin package to the screw head is substantially the same as the height of the resin package. Therefore, the height of the total package is equal to that of the resin package, and thus when a plurality of transistors are packaged in a multistage arrangment in an electronic appliance, the packaging height can be reduced.
The resin package is 10 mm wide and between 16 to 17 mm long, the second main plane 1b' of the resin package 1 is 10 mm wide and 10 mm long, the first step portion lg' is 10 mm wide and 6 mm long, the diameter of the mounting hole 3' is 3.1 mm, and the distance from the out portions of the guides 6'a, 6'b to the fourth side wall 1d' of the resin package is 0.5 mm. The cut portions are positioned further inward than the periphery of the first main plane 1a' so as to improve the withstand voltage. The distance from the upper surface of the guides 6'a, 6'b to the lower surface of the resin package 1 is 2.5 mm. The leads 2a', 2b', 2c' are about 3 mm high.A layer of resin which is between 300 Fm to 400 iim thick covers the lower surface of the header 5', and provides a withstand voltage of between 4.8 KV to 6.4 KV, as in the embodiment described above. Similarly, a 0.45 mm thick layer of resin 19 covers the side surfaces of the throughhole 11' and the mounting hole 3', and provides a 7 KV withstand voltage.
The process of producing this transistor is the same as that of the foregoing embodiment.
Next, the lead frame will be described.
The lead frame 1 shown in Figure 6 consists of thin (0.4 mm thick) metal sheet. A press is employed to pattern the sheet and form the step portions. Therefore, the production cost of this lead frame is lower than that produced from an oddshaped material, and the production cost of the transistor can be reduced consequently.
The height from the underside of the header 5 to the upper surface of the guide 6 is 2.1 mm, and the height from the underside of the header 5' to the upper surface of the leads 2a', 2b', 2c' is between 2.5 to 2.6 mm. These two differences in height are provided in order to optimize the height of the guides 6', the height of the leads 2a', 2b', 2c' and the resin thickness on the underside of the header 5', with a lead frame of a uniform thickness. The other dimensions are the same as those of the lead frame of the foregoing embodiment, and are therefore omitted.
The width of the header 5' (8 mm) and that of the mounting hole portion 12' (6 mm) are the same as those in the foregoing embodiment.
In the two embodiments described above, the grooves 13' of the lead frame are formed on the chipmounting surface of the header, but the same effect can be obtained by forming the grooves 13' on the underside of the header instead of the chipmounting surface.
The present invention provides the following effects.
(a) In the insulated transistor in accordance with the present invention, the lower and side surfaces of the guide 6 are covered with insulating resin 19.
The ends of guides 6 are deeply recessed into the resin package 1 from its side surfaces, and end up at grooves 28 provided in step portions. As a result, even when this transistor is placed on and fixed to an electrically-conductive plate (not shown), no discharge is likely to occur between them because the insulating resin 19 is interposed between the guides 6, which are at the same potential as the collector potential while the transistor is operating, and the fitting plate, and the peripheral portions of the guides are insulated from the fitting plate. Accordingly, a high insulating property which can sufficiently cope with increases in the withstand voltage of the transistor can be accomplished.
(b) The peripheral surface of each guide 6 is recessed inward from that of the resin package 1, as described in (a) above. Therefore, even when other conductors are arranged so as to come into contact with the peripheral surface of the resin package 1, when packaging the transistor, no discharge is likely to occur between them because sufficient insulator consisting of resin is interposed between the conductors and the peripheral surfaces of the guides. In consequence, high-density packaging in which transistor are packaged close to one another can be accomplished.
(c) In the process of producing the transistor of the present invention, the guides 6 are separated after resin-molding utilizing stress concentration portions (portions of the grooves 13) provided on the guides 6.
As a result, the guides 6 can be separated by even a weak force, and no stress is applied to the guides 6. In consequence, cracks do not develop between the guides 6 and the resin 19 when separating the guides, they can be kept in close contact with each other, and a high degree of moistureproofing can be accomplished for the transistor.
(d) The present invention can provide a transistor which has a high performance due to the effects described in (a) to (c) above.
Claims (7)
1. A semiconductor device including:
(a) a header consisting of a material which has a high electric conductivity and high heat conductivity;
(b) a chip fixed to one main surface of said header;
(c) a plurality of leads consisting of a material of a high electric conductivity;
(d) wires electrically connecting said chip to said leads;
(e) a molding member covering said header, said chip, parts of said leads, and said wires, and which has a first main plane, a second main plane opposite to said first main plane, and a plurality of said walls between said first and second main planes; and
(f) a header support of which one edge is connected to said header and another edge thereof is exposed from said molding member, the another edge of said header support terminating at a position further inward within said molding member than said side walls of said molding member.
2. A semiconductor device according to claim 1, wherein the plurality of said walls of the molding member includes: a first side wall extending between said first and second main planes; a second side wall opposite to said first side wall and extending between said first and second main planes; a third side wall extending between said first and second main planes and between said first and second side walls; a fourth side wall opposite to said third side wall and extending between said first and second main planes and between said first and second side walls; a first step portion formed so as to straddle said second and fourth side walls; and a second step portion formed so as to straddle said second and third side walls.
3. A semiconductor device according to claim 1 or 2 wherein there are two header supports.
4. A semiconductor device according to claim 3, wherein a first groove is provided in said first step portion, a second groove is provided in said second step portion, said other end of one of said header supports terminating at a position further inward than said fourth side wall within said first groove, and said other end of the other of said header supports terminating at a position further inward than said third side wall within said second groove.
5. A semiconductor device according to any one of the preceding claims, wherein said molding member consists of a resin.
6. A semiconductor device according to claim 2, wherein an opening provided in said molding member extends from said first step portion to said first main plane.
7. A semiconductor device constructed substantially as herein described with reference to and as illustrated in Figures 1 to 4 or Figures 5 to 7 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58236154A JPS60128646A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device and lead frame used for manufacturing the same device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8429620D0 GB8429620D0 (en) | 1985-01-03 |
| GB2151845A true GB2151845A (en) | 1985-07-24 |
Family
ID=16996560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08429620A Withdrawn GB2151845A (en) | 1983-12-16 | 1984-11-23 | A semiconductor memory |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS60128646A (en) |
| KR (1) | KR930007518B1 (en) |
| GB (1) | GB2151845A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4115128A1 (en) * | 1990-05-24 | 1991-11-28 | Motorola Inc | SEMICONDUCTOR PERFORMANCE ARRANGEMENT FOR HIGH-FREQUENCY APPLICATIONS |
| US9620391B2 (en) | 2002-10-11 | 2017-04-11 | Micronas Gmbh | Electronic component with a leadframe |
| WO2020050991A1 (en) * | 2018-09-04 | 2020-03-12 | Apple Inc. | Overmolded electronic components on circuit board |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60172346U (en) * | 1984-04-23 | 1985-11-15 | 新電元工業株式会社 | Resin-sealed semiconductor device |
| JPS61207040U (en) * | 1985-06-17 | 1986-12-27 | ||
| JPS62180957U (en) * | 1986-05-06 | 1987-11-17 | ||
| JPH079917B2 (en) * | 1987-05-11 | 1995-02-01 | サンケン電気株式会社 | Method for manufacturing resin-sealed semiconductor device |
| JPH0824156B2 (en) * | 1987-05-25 | 1996-03-06 | サンケン電気株式会社 | Method for manufacturing resin-sealed semiconductor device |
| JPH0744194B2 (en) * | 1989-02-17 | 1995-05-15 | サンケン電気株式会社 | Method for manufacturing resin-sealed semiconductor device |
| JP3598579B2 (en) * | 1995-04-17 | 2004-12-08 | 株式会社デンソー | Solenoid valve block |
| JP4953205B2 (en) * | 2007-05-01 | 2012-06-13 | 三菱電機株式会社 | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0063811A1 (en) * | 1981-04-28 | 1982-11-03 | Matsushita Electronics Corporation | A method for manufacturing a plastic encapsulated semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS615818Y2 (en) * | 1979-06-07 | 1986-02-21 | ||
| JPS57188858A (en) * | 1981-05-18 | 1982-11-19 | Matsushita Electronics Corp | Plastic molded type semiconductor device |
| JPS58143538A (en) * | 1982-02-19 | 1983-08-26 | Matsushita Electronics Corp | Manufacture of resin seal type semiconductor device |
-
1983
- 1983-12-16 JP JP58236154A patent/JPS60128646A/en active Granted
-
1984
- 1984-11-23 GB GB08429620A patent/GB2151845A/en not_active Withdrawn
- 1984-11-24 KR KR1019840007370A patent/KR930007518B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0063811A1 (en) * | 1981-04-28 | 1982-11-03 | Matsushita Electronics Corporation | A method for manufacturing a plastic encapsulated semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4115128A1 (en) * | 1990-05-24 | 1991-11-28 | Motorola Inc | SEMICONDUCTOR PERFORMANCE ARRANGEMENT FOR HIGH-FREQUENCY APPLICATIONS |
| DE4115128C2 (en) * | 1990-05-24 | 1999-09-30 | Motorola Inc | Semiconductor power device for high-frequency applications and methods for forming such a device |
| US9620391B2 (en) | 2002-10-11 | 2017-04-11 | Micronas Gmbh | Electronic component with a leadframe |
| WO2020050991A1 (en) * | 2018-09-04 | 2020-03-12 | Apple Inc. | Overmolded electronic components on circuit board |
| US11602055B2 (en) | 2018-09-04 | 2023-03-07 | Apple Inc. | Overmolded components having sub-flush residuals |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930007518B1 (en) | 1993-08-12 |
| JPH0527261B2 (en) | 1993-04-20 |
| KR850005152A (en) | 1985-08-21 |
| GB8429620D0 (en) | 1985-01-03 |
| JPS60128646A (en) | 1985-07-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |