KR860007729A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

Info

Publication number
KR860007729A
KR860007729A KR1019860000164A KR860000164A KR860007729A KR 860007729 A KR860007729 A KR 860007729A KR 1019860000164 A KR1019860000164 A KR 1019860000164A KR 860000164 A KR860000164 A KR 860000164A KR 860007729 A KR860007729 A KR 860007729A
Authority
KR
South Korea
Prior art keywords
main surface
header
semiconductor chip
thickness
opening part
Prior art date
Application number
KR1019860000164A
Other languages
English (en)
Other versions
KR930010069B1 (ko
Inventor
우수게 에노모도
우스게 에노모도
마사오 야마구지
도모오 사가모도
다가시 나가가와
노브가쯔 다나가
Original Assignee
가부시기가이샤 히다찌세이사꾸쇼
미쓰다 가쓰시게
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시기가이샤 히다찌세이사꾸쇼, 미쓰다 가쓰시게 filed Critical 가부시기가이샤 히다찌세이사꾸쇼
Publication of KR860007729A publication Critical patent/KR860007729A/ko
Application granted granted Critical
Publication of KR930010069B1 publication Critical patent/KR930010069B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명을 적용한 절연형 파우어 트랜지스터의 사시도로 개구부와 홈의 상태를 도시한 도면.
제 2 도 A는 제 1 도의 ⅡA-ⅡA'선의 단면도로 헤더 지지체 12가 패케이지 높이의 대략 중앙에 존재하는 상태를 도시한 도면.
제 2 도는 B는 제 1 도 ⅡB-ⅡB'선의 단면도로 칩과 관통 구멍의 사이에 홈이 존재하는 상태를 도시한 도면.
제 3 도는 제 1 도의 절연형 파우어 트랜지스터에 이용되는 평판상의 리이드 프레임의 사시도.

Claims (7)

  1. 다음 사항을 포함하는 반도체 장치
    (1) 전기 도전성과 열전도성이 좋은 헤더 : 이 헤더는 제 1 주면과 그 제 1 주면에 대향하는 제 2 주면 및 제 1 주면과 제 2 주면의 사이에 다수 개의 측면을 가지며, 또한 상기 제 1 주면에는 반도체칩이 고정되어 있다.
    (2) 상기 헤더의 1측면에 한쪽 끝이 연결되고, 또한 종단부를 가진 헤더 지지체 : 이 헤더 지지체는, 제 1 주면과 이 제 1 주면에 대향한 제 2 주면을 갖는다.
    (3) 전기 도전성과 열도전성이 좋은 다수개의 리이드 : 이 리이드는 상기 반도체칩의 전극에 와이어를 거처서 전기적으로 접속되어 있다.
    (4) 봉지체는 상기 헤더 지지체의 제 1 주면의 일부가 바닥면으로 되는 제 1 개구부와, 상기 헤더 지지체의 제 2 주면의 일부가 바닥면으로 되는 제 2 개구부와, 상기 헤더의 긴쪽 방향과 수직인 방향으로 마련된 홈부를 갖는다.
    이 봉지체는, 상기 헤더, 상기 반도체칩, 상기 헤더지지체의 종단부를 덮으며, 또한 제 1 주면과, 이 제 1 주면에 대향하는 제 2 주면과, 제 1 주면에서 제 2 주면에 걸쳐서 마련된 관통 구멍을 갖는다.
    이 홈 부분은, 상기 관통 구멍과 상기 반도체칩의 사이에 마련되어 있다.
  2. 특허 청구의 범위 제 1 항에 있어서, 봉지체는 수지로 된다.
  3. 특허 청구의 범위 제 1 항에 있어서, 제 1 개구부와 제 2 개구부의 깊이는 근사(近似)하다.
  4. 특허 청구의 범위 제 2 항에 있어서, 홈 부분에 있어서의 헤더의 제 1 주면위의 수지의 두께는, 헤더의 제 2 주면 아래의 수지의 두께에 근사하고 있다.
  5. 특허청구의 범위 제 4 항에 있어서, 헤더의 두께는 리이드의 두께와 동일하다.
  6. 특허청구의 범위 제 2 항 내지 제 5 항의 반도체 장치는 또한 다음 사항을 구비한다.
    (5) 상기 홈 부분을 매입하는 절연층.
  7. 특허청구의 범위 제 6 항의 반도체 장치는 또 다음 사항을 구비한다.
    (6) 제 1 개구부 및 제 2 개구부를 매입하는 절연층.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860000164A 1985-03-13 1986-01-14 반도체 장치 KR930010069B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP60-48309 1985-03-13
JP48309 1985-03-13
JP60048309A JPS61208242A (ja) 1985-03-13 1985-03-13 半導体装置

Publications (2)

Publication Number Publication Date
KR860007729A true KR860007729A (ko) 1986-10-15
KR930010069B1 KR930010069B1 (ko) 1993-10-14

Family

ID=12799814

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860000164A KR930010069B1 (ko) 1985-03-13 1986-01-14 반도체 장치

Country Status (2)

Country Link
JP (1) JPS61208242A (ko)
KR (1) KR930010069B1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0815165B2 (ja) * 1987-09-17 1996-02-14 株式会社東芝 樹脂絶縁型半導体装置の製造方法
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
EP0694966A1 (en) * 1994-07-29 1996-01-31 STMicroelectronics S.r.l. Package for an electronic semiconductor circuit

Also Published As

Publication number Publication date
JPS61208242A (ja) 1986-09-16
KR930010069B1 (ko) 1993-10-14

Similar Documents

Publication Publication Date Title
US4167647A (en) Hybrid microelectronic circuit package
KR920015496A (ko) 반도체장치
KR920001696A (ko) 반도체 다이를 절연시키기 위한 히트 싱크 및 다중 장착 패드 리드 프레임 패키지 및 그 방법
KR950030323A (ko) 반도체 장치와 반도체 장치의 생산방법 및 반도체 모듈
US4994897A (en) Multi-level semiconductor package
US4642419A (en) Four-leaded dual in-line package module for semiconductor devices
EP0837504A3 (en) Partially or completely encapsulated ferroelectric device
KR890013748A (ko) 반도체 장치
KR840006561A (ko) 반도체장치 및 그 조립방법
KR930024145A (ko) 적층된 다중칩 모듈 및 그의 제조방법
US7508060B2 (en) Multi-chip semiconductor connector assemblies
KR880011910A (ko) 수지봉합형 집적회로장치
KR870009613A (ko) 집적회로 칩 마운팅 및 패키징 조립품
KR940012549A (ko) 반도체 펙케지
MY106696A (en) Electrically isolated heatsink for single-in-line package
KR940020539A (ko) 저 인덕턴스 반도체 패키지(Low inductance semiconductor package)
US5231305A (en) Ceramic bonding bridge
KR960039449A (ko) 반도체 패키지, 리드프레임 및 제조방법
KR850005152A (ko) 반 도 체 장 치
KR880002260A (ko) 열적으로 향상된 대규모 집적회로 패키지 및 집적회로 다이의 장착방법
KR860007729A (ko) 반도체 장치
KR880008441A (ko) 고주파 반도체 소자용 세라믹 패키지
KR830009650A (ko) 반도체 장치
JPH0680748B2 (ja) 樹脂封止型半導体装置
KR890003022A (ko) 반도체 장치

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20011004

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee