KR850002688A - 래치-업이 제거된 다수의 역행 우물 고밀도 cmos fet - Google Patents

래치-업이 제거된 다수의 역행 우물 고밀도 cmos fet Download PDF

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KR850002688A
KR850002688A KR1019840005516A KR840005516A KR850002688A KR 850002688 A KR850002688 A KR 850002688A KR 1019840005516 A KR1019840005516 A KR 1019840005516A KR 840005516 A KR840005516 A KR 840005516A KR 850002688 A KR850002688 A KR 850002688A
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well region
substrate
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cmos fet
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KR930004343B1 (ko
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와이. 첸 존
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원본 미기재
휴우즈 에어크라프트 캄파니
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

내용 없음

Description

래치-업이 제거된 다수의 역행 우물 고밀도 CMOS FET
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 기생(parastic) 쌍극성 트랜지스터 쌍 및 중요한 상호 접속부의 회로 구조가 위해 입혀진 것처럼 도시된 본 발명이 양호하게 적용되게 CMOS 장치 구조물의 횡단면도.
제2도는 본 발명의 양호한 이중 역행 우물(retrograde well) 실시예의 소오스(source) 또는 드레인(drain)영역, 우물 영역, 및 기질을 통해 취해진 도우핑(doping) 밀도 분포를 도시한 그래포도.

Claims (10)

  1. 기질(12), 상기 기질(12)의 표면내에 인접하여 있고 다수의 역행 도우핑 밀도 분포를 갖고 있는 우물 영역(14) 및 상기 우물 영역(14) 내에 있고, 상기 기질(12)의 표면에 인접하여 있으며, 상기 우물 영역(14)내의 평균 결함 밀도보다 더 크고 우물 영역 소오스 및 드레인 영역(18,20)의 가장 깊은 부분 및 상기 우물영역(14)의 기저 부분에 각각 관련된 잔여 결함의 밀도를 갖고 있는 소오스 및 드레인 영역(18,20)으로 구성된 것을 특징으로 하는 CMOS FET.
  2. 제1항에 있어서, 상기 CMOS FET의 동작이 영향을 받지 않도록 상기 잔여 결함들이 상기 우물 영역 소오스 및 드레인 영역(18,20) 및 상기 우물 영역(14)의 기저 부분 내에만 존재하는 것을 특징으로 하는 CMOS FET.
  3. 제2항에 있어서, 상기 우물영역(14)의 깊이와 상기 우물영역(14)의 평균도우핑 밀도의 적이 약 1.0×1013cm-2이상이고, 상기 우물영역(14)의 깊이가 약 3.0um 이하인 것을 특징으로 하는 CMOS FET.
  4. 제3항에 있어서, 다수의 역행 도우핑 밀도 분포의 각각의 역행 피이크로 인해 상기 우물영역(14)내에 유도된 전계의 전체전계 세기가 약 800v/㎝ 이상인 것을 특징으로 하는 CMOS FET.
  5. 제4항에 있어서, 상기 우물영역(14)의 상기 다수의 역행 도우핑 밀도 분포가 2개의 역행 피이크를 갖고 있는 것을 특징으로 하는 CMOS FET.
  6. 다수의 역행 불순물 도우핑 분포를 갖고 있는 상기 기질내에 우물영역(14)를 제공하도록 상이한 이식 에너지로 각각 실행되는 다수의 우물 불순물 이온 이식을 상기 기질의 표면내에 실행하는 수단, 상기 우물영역(14)내에 소오스 및 드레인 영역을 제공하도록 소오스 및 드레인 불순물의 이온 이식을 상기 기질(12)의 표면내에 실행하는 수단 및 잔여 결함의 밀도가 소오스 및 드레인 영역(18,20)의 가장 깊은 부분 및 상기 우물 영역(14)의 기저 부분내에 유지되어 관련되도록 상기 우물영역 소오스 및 드레인 영역(18,20)의 불완전 어니얼링 처리를 실행하는 수단을 포함하는 것을 특징으로 하는 CMOS FET 제조 방법.
  7. 제6항에 있어서, 상기 불완전 어니얼링 처리가 약 2 내지 20초동안 약 900°내지 100℃ 사이의 온도로 상기 기질(12)를 가열시키는 수단을 포함하는 것을 특징으로 하는 방법.
  8. 제6항에 있어서, 상기 어니얼링 처리가 약 15 내지 30분 동안 약 800°내지 875℃ 온도로 상기 기질(12)를 가열시키는 수단을 포함하는 것을 특징으로 하는 방법.
  9. 제6항에 있어서, 상기 다수의 우물 불순물 이온 이식이 최소한 2개의 이식, 즉 약 100 내지 200KeV의 이식에너지로 실행되는 알은 이식 및 약 340 내지 500KeV의 이식에너지로 실행되는 비교적 깊은 이식으로 이루어진 것을 특징으로 하는 방법.
  10. 제9항에 있어서, 상기 기질(12)가 실리콘이고, 상기 다수의 우물 불순물 이식이 2개의 이식, 즉 약 1×1013cm-2의 인 이온의 용량을 각각 제공하는 약 120KeV에서 실행되는 제1이식 및 약 340KeV에서 실행되는 제2이식으로 이루어진 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840005516A 1983-09-12 1984-09-08 래치-업이 제거된 다수의 역경사 웰을 갖는 고밀도 cmos fet 및 그 제조방법 KR930004343B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US531546 1983-09-12
US06/531,546 US4633289A (en) 1983-09-12 1983-09-12 Latch-up immune, multiple retrograde well high density CMOS FET
US531,546 1983-09-12

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KR850002688A true KR850002688A (ko) 1985-05-15
KR930004343B1 KR930004343B1 (ko) 1993-05-26

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US (1) US4633289A (ko)
EP (1) EP0157779B1 (ko)
JP (1) JPH0628298B2 (ko)
KR (1) KR930004343B1 (ko)
DE (1) DE3376782D1 (ko)
IL (1) IL72337A (ko)
WO (1) WO1985001391A1 (ko)

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EP0157779A1 (en) 1985-10-16
DE3376782D1 (en) 1988-06-30
JPS60502178A (ja) 1985-12-12
US4633289A (en) 1986-12-30
EP0157779B1 (en) 1988-05-25
KR930004343B1 (ko) 1993-05-26
IL72337A (en) 1988-11-15
JPH0628298B2 (ja) 1994-04-13
WO1985001391A1 (en) 1985-03-28
IL72337A0 (en) 1984-11-30

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