KR890011084A - Hct 반도체 장치의 제조방법 - Google Patents

Hct 반도체 장치의 제조방법 Download PDF

Info

Publication number
KR890011084A
KR890011084A KR1019870015551A KR870015551A KR890011084A KR 890011084 A KR890011084 A KR 890011084A KR 1019870015551 A KR1019870015551 A KR 1019870015551A KR 870015551 A KR870015551 A KR 870015551A KR 890011084 A KR890011084 A KR 890011084A
Authority
KR
South Korea
Prior art keywords
region
forming
substrate
well
mos transistor
Prior art date
Application number
KR1019870015551A
Other languages
English (en)
Other versions
KR900005354B1 (ko
Inventor
홍필영
오태엽
김천중
강상석
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870015551A priority Critical patent/KR900005354B1/ko
Priority to DE3843103A priority patent/DE3843103A1/de
Priority to JP63323827A priority patent/JPH023270A/ja
Priority to FR888817423A priority patent/FR2625609B1/fr
Priority to NL8803213A priority patent/NL8803213A/nl
Priority to US07/292,106 priority patent/US4920066A/en
Priority to GB8900015A priority patent/GB2213321B/en
Publication of KR890011084A publication Critical patent/KR890011084A/ko
Application granted granted Critical
Publication of KR900005354B1 publication Critical patent/KR900005354B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

HCT 반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 씨모오스 인버어터의 회로도.
제2도는 상기 제1도의 a영역의 단면도.

Claims (5)

  1. 반도체 장치의 제조방법에 있어서, 제1도전형의 실리콘 반도체 기판(10)상의 소정 영역에 제2도전형의 웰 영역(15)을 형성하는 제1공정과, 상기 기판(10)상부에 제1산화막 (16)과 질화막을 순차적으로 형성하는 제2공정과, 상기 웰 영역 상부에 제1모오스 트랜지스터의 드레인 및 소오스(29)와 기판의 소정영역에 스톱채널영역(30)을 형성하는 제3공정과, 상기 기판상부의 스톱채널 영역(30)사이에 제2모오스 트랜지스터의 드레인 및 소오스(37)와 상기 웰(15)에 에지영역에 오믹접촉 영역(38)을 형성하는 제4공정과, 기판상부의 질화막을 제거하고 제1 및 제2 모오스 트랜지스터의 게이트 영역의 제1 산화막(16)을 제거한 후 게이트 산화막을 형성하기 위하여 기판전면에 산화막(40)을 형성하는 제5공정과, 상기 제1 및 제2모오스 트랜지스터의 소오스 및 드레인 접속을 위한 접속창(41)(42)을 형성하는 제6공정과, 제1 및 제2모오스 트랜지스터의 각 전극을 형성하기 위하여 제1금속막(44a)(44b)(44c)(44d)(44e)의 패턴을 형성하는 제7공정과, 상기 제1금속막 상부에 제1금속막을 소정부위와 절연시키기 위하여 저온 산화막(46)의 패턴을 형성하는 제8공정과, 상기 저온산화막으로 이격되어 제1금속막과 절연되고 접속창을 통해서 제1금속막과 접속되는 제2금속막(48)의 패턴을 형성하는 제9공정과, 상기 제2금속막(48)상에 보호막층(50)을 형성하는 제10공정을 구비하여 상기 공정의 연속으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법.
  2. 제1항에 있어서, 제2공정 후 제2도전형의 웰의 에지영역(20)과, 상기 웰(15)상부의 제1모오스 트랜지스터가 형성될 영역(18)과, 기판상부의 제2모오스 트랜지스터가 형성될 영역(19)과, 상기 영역(19)둘레에 형성될 스톱채널 영역(21)상부의 질화막(17)을 제거하고 열처리 공정으로 상기 질화막이 노출된 영역에 필드 산화막(23)을 형성함을 특징으로 하는 반도체 장치의 제조방법.
  3. 제1항에 있어서, 제2도전형의 웰(15)은 2×1015-3×1015ions/㎠의 도우즈로 에너지는 40-50KeV로 하여 제2도전형의 이온주입을 한 후 열처리 하여 접합깊이가 5-6㎛로 형성함을 특징으로 하는 반도체 제조방법.
  4. 제1항에 있어서, 제1모오스 트랜지스터의 드레인 및 소오스(29)와 스톱 채널영역(30)은 인 또는 인과 비소이온을 이온 주입하고 열처리하여 소정의 깊이로 형성함을 특징으로 하는 반도체 장치의 제조방법.
  5. 제1항에 있어서, 제2모오스트랜지스터의 드레인 및 소오스(37)와 웰 에지영역의 오믹접촉 영역(38)은 제1도전형의 이온주입을 하고 열처리하여 제1모오스 트랜지스터의 드레인 및 소오스(29)의 접합 깊이보다 깊게 형성함을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870015551A 1987-12-31 1987-12-31 Hct 반도체 장치의 제조방법 KR900005354B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019870015551A KR900005354B1 (ko) 1987-12-31 1987-12-31 Hct 반도체 장치의 제조방법
DE3843103A DE3843103A1 (de) 1987-12-31 1988-12-21 Verfahren zur herstellung eines halbleiterbauelements, insbesondere eines hochgeschwindigkeits-cmos-ttl-halbleiterbauelements
JP63323827A JPH023270A (ja) 1987-12-31 1988-12-23 Ｈｃｔ半導体装置の製造方法
FR888817423A FR2625609B1 (fr) 1987-12-31 1988-12-29 Procede de fabrication d'un dispositif cmos rapide
NL8803213A NL8803213A (nl) 1987-12-31 1988-12-30 Werkwijze voor het vervaardigen van een snelle cmos ttl halfgeleiderinrichting.
US07/292,106 US4920066A (en) 1987-12-31 1988-12-30 Process for fabricating a high-speed CMOS TTL semiconductor device
GB8900015A GB2213321B (en) 1987-12-31 1989-01-03 High-speed cmos ttl semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870015551A KR900005354B1 (ko) 1987-12-31 1987-12-31 Hct 반도체 장치의 제조방법

Publications (2)

Publication Number Publication Date
KR890011084A true KR890011084A (ko) 1989-08-12
KR900005354B1 KR900005354B1 (ko) 1990-07-27

Family

ID=19267824

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870015551A KR900005354B1 (ko) 1987-12-31 1987-12-31 Hct 반도체 장치의 제조방법

Country Status (7)

Country Link
US (1) US4920066A (ko)
JP (1) JPH023270A (ko)
KR (1) KR900005354B1 (ko)
DE (1) DE3843103A1 (ko)
FR (1) FR2625609B1 (ko)
GB (1) GB2213321B (ko)
NL (1) NL8803213A (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3924062C2 (de) * 1989-07-21 1993-11-25 Eurosil Electronic Gmbh EEPROM-Halbleitereinrichtung mit Isolierzonen für Niedervolt-Logikelemente
DE69128876T2 (de) * 1990-11-30 1998-08-06 Sharp Kk Dünnfilm-Halbleitervorrichtung
US5438005A (en) * 1994-04-13 1995-08-01 Winbond Electronics Corp. Deep collection guard ring
US6017785A (en) * 1996-08-15 2000-01-25 Integrated Device Technology, Inc. Method for improving latch-up immunity and interwell isolation in a semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983620A (en) * 1975-05-08 1976-10-05 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
US4152823A (en) * 1975-06-10 1979-05-08 Micro Power Systems High temperature refractory metal contact assembly and multiple layer interconnect structure
JPS5543842A (en) * 1978-09-25 1980-03-27 Hitachi Ltd Manufacture of al gate cmos ic
JPS5565446A (en) * 1978-11-10 1980-05-16 Nec Corp Semiconductor device
US4288910A (en) * 1979-04-16 1981-09-15 Teletype Corporation Method of manufacturing a semiconductor device
DE3133841A1 (de) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
DE3318213A1 (de) * 1983-05-19 1984-11-22 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum herstellen eines integrierten isolierschicht-feldeffekttransistors mit zur gateelektrode selbstausgerichteten kontakten

Also Published As

Publication number Publication date
JPH023270A (ja) 1990-01-08
GB2213321B (en) 1991-03-27
NL8803213A (nl) 1989-07-17
FR2625609A1 (fr) 1989-07-07
FR2625609B1 (fr) 1992-07-03
KR900005354B1 (ko) 1990-07-27
GB8900015D0 (en) 1989-03-01
DE3843103A1 (de) 1989-07-13
GB2213321A (en) 1989-08-09
US4920066A (en) 1990-04-24

Similar Documents

Publication Publication Date Title
KR870000763A (ko) 반도체 장치 및 그 제조방법
KR0137625B1 (ko) 매립 채널형 mos 트랜지스터 및 그 제조방법
KR930000605B1 (ko) 절연 게이트 mosfet의 제조방법
KR960026463A (ko) 모스 전계 효과 트랜지스터(mosfet) 제조 방법
KR980006542A (ko) 반도체소자 제조방법
KR960009229A (ko) 고내압용 모스 트랜지스터 및 그 제조방법
KR890011084A (ko) Hct 반도체 장치의 제조방법
DE3377039D1 (en) Voltage-stable mos transistor for very high density integrated circuits
KR890008980A (ko) 반도체 장치의 제조방법
KR100247810B1 (ko) 모스 트랜지스터 제조방법
JPS62118578A (ja) 半導体装置の製造方法
KR100254618B1 (ko) 반도체소자 및 그 제조방법
KR950015643A (ko) 트랜지스터 구조 및 그 제조방법
KR940016961A (ko) 모스(mos) 트랜지스터 및 그 제조 방법
KR0137996B1 (ko) 엘디디 구조의 모스펫 제조방법
KR910001876A (ko) 반도체 장치 제조방법
KR890017819A (ko) 고속 및 고전압 반도체 소자와 제조방법
KR100265851B1 (ko) 반도체장치의전계효과트랜지스터제조방법
KR930011281A (ko) 반도체장치 및 그 제조방법
JPS6142960A (ja) 半導体装置の製造方法
KR960036015A (ko) Ldd 구조의 모오스 트랜지스터 제조방법
KR890016684A (ko) 바이씨모오스 반도체 장치의 제조방법
KR970072206A (ko) 반도체 소자의 트랜지스터 제조 방법
JPS6449266A (en) Transistor
KR940010387A (ko) 반도체 소자 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070612

Year of fee payment: 18

EXPY Expiration of term