KR20140091575A - Methods and systems for utilizing design data in combination with inspection data - Google Patents

Abstract

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for determining the location of inspection data within a design data space includes aligning data acquired by an inspection system with respect to an alignment site on a wafer with data for a predetermined alignment site. The method also includes determining a position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site within the design data space. The method also includes determining the location of the inspection data acquired for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. In one embodiment, the location of the inspection data is determined by sub-pixel accuracy.

Description

TECHNICAL FIELD [0001] The present invention relates to a method and system for utilizing design data in combination with inspection data,

Priority claim

This application is related to U.S. Provisional Application No. 60 / 737,947, filed November 18, 2005, entitled " Methods and Systems for Utilizing Design Data in Combination with Inspection Data & Combination with Inspection Data "filed on November 18, 2005, which claims priority to U.S. Provisional Patent Application No. 60 / 738,290, which is incorporated herein by reference in its entirety.

The present invention relates to a method and system for using design data in combination with inspection data. Certain embodiments relate to a computer-implemented method for determining the location of inspection data within a design data space and / or determining a location of a design space location on a wafer substantially precisely during an inspection process.

The following description and examples are not intended to be prior art because of their inclusion in this section.

Integrated circuit (IC) designs can be developed using methods or systems such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. The circuit pattern database includes data representing a plurality of layouts for various layers of the IC. The data in the circuit pattern database can be used to determine the layout for a plurality of reticles. The layout of the reticle generally includes a plurality of polygons defining features in one pattern on the reticle. Each reticle may be used to fabricate one of the various layers of the IC. The layer of the IC may comprise, for example, a connection pattern in a semiconductor substrate, a gate insulator pattern, a gate electrode pattern, a contact pattern in the interlayer insulator, and an interconnect pattern on the metallization layer.

As used herein, "design data" generally refers to data derived from the physical design (layout) and complex simulation or simple structure and Boolean manipulation of the IC.

Semiconductor device designs are evidenced by different procedures prior to the manufacture of ICs. For example, a semiconductor device design is checked by software simulation to verify that all features will be printed correctly after lithography in manufacturing. Such checks typically involve steps such as design rule checking (DRC), optical rule checking (ORC), and more complex software based verification approaches including process simulations measured for specific fabs and processes. The output of the physical design demonstration phase can potentially be used to identify a number of critical points (sometimes referred to as "hot spots" in design).

The step of fabricating a semiconductor device, such as logic and memory devices, typically involves processing a substrate, such as a semiconductor wafer, using a plurality of semiconductor fabrication processes to form various features and multiple layers of semiconductor devices . For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle onto an aligned resist on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etch, deposition, and ion implantation. A plurality of semiconductor devices are fabricated into a batch on a single semiconductor wafer and then separated into individual semiconductor devices.

The inspection process is used at various stages during the semiconductor manufacturing process to detect defects on the wafer to promote high yields of the manufacturing process and thus promote high profits. Testing has become an important part of semiconductor device manufacturing such as IC. However, as the size of the semiconductor device is reduced, the inspection becomes more important in the successful manufacture of an acceptable semiconductor device, since small defects can cause the device to fail. For example, as the dimensions of a semiconductor device decrease, even a relatively small defect may cause undesired deformation in the semiconductor device, thus requiring detection of defects of reduced size.

Another important part of manufacturing yield control is to determine the cause of defects on the wafer or reticle so that the cause of the defect is corrected to reduce the number of defects on other wafers or reticles. Often, determining the cause of the defect includes identifying the defect type and other attributes of the defect, such as size, shape, configuration, and the like. Because the inspection typically only includes the steps of detecting defects on the wafer and providing limited information about the defects, such as the location on the wafer or reticle, the number of defects on the wafer or reticle, and sometimes the defect size, Is often used to determine more information about individual defects that can be determined from test results. For example, the defect review tool can be used to revisit detected defects on a wafer or a reticle and inspect the defects in an automated or manual manner.

Defect review typically involves generating additional information about the defect at a high resolution using a high magnification optical system or a scanning electron microscope (SEM). The high resolution data generated by the defect review is more suitable for determining the attributes of the defect, such as profile, roughness, more accurate size information, and the like. Defect analysis can be performed using a system such as an electron dispersive x-ray spectroscopy (EDS) system. Such defect analysis can be performed to determine information such as the composition of the defect. Attributes of defects determined by inspection, review, analysis, or some combination thereof may be used to identify the type of defect (i.e., the defect category) and possibly the root cause of the defect. This information can be used to monitor and modify one or more parameters of one or more semiconductor manufacturing processes to reduce or eliminate defects.

However, as the design rules decrease, the semiconductor manufacturing process can be manipulated close to the limits on the performance capabilities of the process. Also, as the design rule decreases, small defects can affect the electrical parameters of the device, leading to more than one sensitive test. Thus, as design rules decrease, the population of potentially yield-related defects detected by inspection increases dramatically, and the population of Newson's defects detected by inspection also increases dramatically. Thus, more and more defects are detected on the wafer, and the step of calibrating the process to remove all defects may be more difficult and costly. As such, the step of determining which of the defects actually affects the electrical parameters and yield of the device is focused and allowed only on the defect, with the process control method largely ignoring other defects. Also, in small design rules, process induced errors may be systematic in some cases. That is, process induced errors tend to be error in certain design patterns that are often repeated many times within the design. Spatially organized and electrically related defects are important because the elimination of such defects can have a significant overall impact on yield. Whether a defect affects device parameters and yield can often not be determined from the inspection, review, and analysis process described above because these processes can not determine the location of defects in the electrical design.

Some methods and systems for aligning defect information to electrical designs have been developed. For example, the SEM review system can be used to determine more accurate coordinates of a defect location for a sample of a defect, and the defect coordinates reported by the SEM review system can be used to determine the location of a defect in an electrical design. Another method includes aligning the inspection area (e.g., the area of the device pattern formed on the wafer to be inspected) with the physical location of the printed pattern on the wafer. However, at present, the region of interest can be aligned to a pattern printed on the wafer with an accuracy of only 2 [mu] m due to system errors and drawbacks. For example, some BF (bright field) inspection systems have coordinate accuracy of about +/- 1 mu m. In addition, the area of inspection attention in currently used methods is relatively large and includes many non-key features as well as desired key features. In an attempt to maximize the sensitivity of the inspection system to capture spatially-structured design-for-manufacturability (DFM) defects resulting from design and process interdependencies, the system is capable of handling millions of non- It can be overwhelmed by events. For example, these Newswens events need to be filtered from the test results by post-processing of test data. In addition, Newson's event detection limits the ultimately achievable sensitivity of the inspection system for DFM applications. A high percentage of Newson's defect data can overload the runtime data processing capability of the inspection system, degrading throughput and / or causing loss of data.

A substantially highly accurate "context" of the design data is defined by the use of design contexts as part of a defect detection algorithm or method, detection sense tailoring, Newson defect filtering, defect classification, defect grouping, In order to be able to be utilized to perform one or more context-based functions such as defect sampling for review, the method of arranging inspection data in sub-pixel accuracy (the size of the pixel may be as large as the size of the structure being examined) And systems can be beneficial.

Summary of the Invention

The following description of various embodiments of methods and systems is not to be considered as limiting the scope of the appended claims.

One embodiment relates to a computer-implemented method for determining the location of inspection data within a design data space. The method includes aligning the data acquired by the inspection system with data for a given alignment site (e.g., design data) for an alignment site on the wafer. The data for a given alignment site and the data acquired by the inspection system for an alignment site on the wafer are obtained separately. For example, data for a given alignment site is not acquired using a wafer on which an alignment site is printed. The method also includes determining a position of the alignment site on the wafer in the design data based on the position of the predetermined alignment site in the design data space. The step of determining the position of the alignment site on the wafer within the design data space may be performed based on the orientation of the wafer during design layout and / or inspection on the wafer. The method also includes determining the location of the inspection data acquired for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. The location of the inspection data may be stored and used as further described herein. In one embodiment, the location of the inspection data is determined by sub-pixel accuracy.

In another embodiment, the data for a given alignment site may be stored in a data structure such as a graphics data stream (GDS) file, any other standard machine-readable file, any other suitable file known in the art, And includes design data to be stored. A GDSII file is a category of files used to represent design layout data. Other examples of such files include GL1 and OASIS files. Some embodiments are described herein for GDS or GDSII files, but the embodiments are equally applicable to the entire category of files regardless of the data structure configuration, storage format, or storage mechanism. In another embodiment, the data for a given alignment site includes one or more simulated images that indicate how a given alignment site will be printed on the wafer.

In some embodiments, the data for a given alignment site includes one or more attributes of a given alignment site, the data for the alignment site includes one or more attributes of the alignment site, And sorting the above attributes into one or more sorting sites of the sorting site. In one such embodiment, one or more attributes of a given alignment site include the center of a given alignment site, and one or more attributes of the alignment site include the center of the alignment site.

In a further embodiment, the data for a given alignment site is acquired by an inspection system or other image acquisition system and includes data aligned with design data stored in a data structure, such as a GDSII file for the design data. In yet another embodiment, the data for a given alignment site includes at least a portion of a standard reference die image that is aligned to design coordinates within the design data space. The standard reference die image may be a reference image that is acquired, simulated, magnified, or a combination thereof.

In some embodiments, a given alignment site includes at least one alignment feature having one or more properties that are unique in the x and y directions. In another embodiment, a given alignment site includes at least two alignment features. The first of the two alignment features has one or more properties that are unique in the x direction. The second of the two alignment features has one or more properties that are unique in the y direction.

In a further embodiment, the method comprises selecting an alignment site using an inspection system. In such an embodiment, the imaging mode of the inspection system or other image acquisition system used to select a given alignment site is different from the imaging mode of the inspection system used to acquire inspection data. In some embodiments, the step of determining the position of the alignment site is performed prior to the inspection of the wafer, and the step of determining the location of the inspection data is performed during the inspection of the wafer. In another embodiment, the step of determining the location of the inspection data is performed subsequent to the inspection of the wafer. In one such embodiment, the step of determining the location of the inspection data is performed not on the portion of the inspection data that does not correspond to the defect, but on the portion of the inspection data corresponding to the defect detected on the wafer. In this manner, the location of the inspection data within the design data space is determined only for the inspection data (e.g., patch image) acquired at the defective location on the wafer.

In another embodiment, the data for the alignment site is within the swath of the inspection data. In one such embodiment, determining the position of the swath in the design data space based on the position of the alignment site in the design data space, determining the position of the swath of the inspection data in the design data space based on the position of the swath .

In one embodiment, the method includes determining sensitivity to detect defects on other portions of the wafer based on the location of the inspection data in the design data and one or more attributes of the design data in the design data space . In one such embodiment, one or more attributes of the design data may be associated with the design data, other design data, or some combination thereof for the process layer, other process layers, or some combination thereof, Is selected based on one or more attributes of inspection data previously obtained for a wafer, another wafer, or some combination thereof. In such other embodiments, one or more attributes of the design data may include a yield criticality of a previously detected defect at another site, a fault probability of a previously detected defect at the other site, Is selected based on the combination.

Determining a degree of detection for detecting defects on other parts of the wafer based on the location of the inspection data in the design data space and the context map, Lt; RTI ID = 0.0 > 1 < / RTI > In one such embodiment, the step of determining the degree of sensitivity includes determining a degree of sensitivity used in the inspection data to detect defects on other parts of the wafer. In such other embodiments, the step of determining the degree of sensitivity is performed by the inspection system during inspection of the wafer. In such a further embodiment, the step of determining the degree of sensitivity is performed after the acquisition of the inspection data for the wafer is completed.

In a further embodiment, the method further comprises detecting, based on at least one attribute of the inspection data, one or more attributes of the design data in the design data space, the location of the inspection data in the design data space, And determining a degree of freedom. In one such embodiment, one or more attributes of the inspection data include one or more image noise attributes, whether the defect has been detected at another site, or some combination thereof.

In some embodiments, the method may include one or more attributes of schematic data for the design of the device being fabricated on the wafer, one or more attributes of the expected electrical behavior of the physical layout for the device, or some combination thereof The method further comprises changing one or more parameters for detecting defects on the wafer. In another embodiment, the method includes altering one or more parameters for detecting defects on a wafer using inspection data based on one or more parameters of an electrical test process performed on the wafer. In a further embodiment, the method includes modifying one or more parameters of an electrical test process performed on the wafer based on defects detected on the wafer using the inspection data.

In a further embodiment, the method comprises the steps of periodically changing one or more parameters of the inspection process performed by the inspection system, based on the results of one or more of the steps of the method, using a feedback control technique . In another embodiment, the method includes automatically changing one or more parameters of an inspection process performed by the inspection system, based on a result of one or more of the steps of the method, using feedback control techniques. In yet another embodiment, the method includes generating a knowledge base using the results of one or more steps of the method, generating a test process performed by the test system using the knowledge base, .

In another embodiment, the method includes classifying defects detected on other parts of the wafer based on the location of the portion of the inspection data corresponding to the defects in the design data space and the context map, And a value for one or more attributes of the design data over the data space. In one such embodiment, the classification step is performed by the inspection system during inspection of the wafer. In such another embodiment, the classification step is performed after the acquisition of the inspection data for the wafer is completed.

In another embodiment, the inspection data includes data on defects on the wafer. In one such embodiment, the method includes determining a location of a defect in the design data space based on the location of the inspection data in the design data space, determining the location of the defect in the design data space, And determining whether the defect is a nuisance defect based on the attribute. In one such embodiment, determining whether the defect, which is not determined to be a Newson defect, is a systematic or a random defect based on one or more attributes of the design data in the design data space. Determining whether the defect is a spatially systematic defect or a random defect is based on one or more attributes of the design data in the design data space in combination with other information, such as historical fab data or other data corresponding to a hot spot in the design data Can be performed. In one such embodiment, the method may also include determining whether the defect is systematic or random defect based on the location of the inspection data in the design data space and one or more statistically determined attributes of the inspection data. In one embodiment, the inspection data is obtained for a process window qualification (PWQ). In another embodiment, the method includes classifying defects based on the location of inspection data within the design data space and one or more attributes of the design data in the design data space.

In one embodiment, the method includes binning a defect based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. In some embodiments, the method further comprises determining, based on at least one of the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and the reticle inspection data acquired for the reticle onto which the design data is printed , And binning the defect into groups. In a further embodiment, the method includes binning a defect into groups based on the location of the inspection data within the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. In some embodiments, the method includes the steps of: locating inspection data within a design data space; at least one property of design data in a design data space; at least one property of inspection data; And binning the defects into groups based on the one or more attributes. In a further embodiment, the method further comprises the steps of: locating the inspection data in the design data space, one or more properties of the design data in the design data space, one or more properties of the inspection data, Based on one or more attributes of inspection data previously obtained for a wafer, another wafer, or some combination thereof, for design data, other design data, or some combination thereof, As shown in FIG.

As described above, the inspection data may include data on defects on the wafer. In one such embodiment, the method includes selecting at least a portion of the defect for review based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. In such a further embodiment, the method comprises determining a sequence in which the defect is to be reviewed, based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. In yet another such embodiment, the method includes selecting at least a portion of the defects for review, wherein at least a portion of the defects are associated with each of the design data in the design data space having different values of one or more attributes of the design data And at least one defect located within the portion. The defect review sampling may also (or alternatively) be performed based on one or more attributes of the group to which the defect is being binned. Defects may be binned as further described herein, and one or more attributes of the group may be determined based on one or more attributes of the design data or in any other manner described herein.

In another embodiment, the method further comprises the step of determining, based on the location of the inspection data in the design data space and the one or more attributes of the design data in the design data space, And extracting the predetermined attribute. In one such embodiment, one or more attributes of the design data may be associated with the design data, other design data, or some combination thereof for the process layer, other process layers, or some combination thereof, Is selected based on one or more attributes of inspection data previously obtained for a wafer, another wafer, or some combination thereof.

In another embodiment, the method comprises the steps of: acquiring, for at least a portion of the inspection data acquired on another part of the wafer, based on at least one attribute of the inspection data, at least one attribute of the design data in the design data space, And extracting one or more predetermined attributes of the output from the one or more detectors of the system. In one such embodiment, one or more attributes of the inspection data include one or more image noise attributes, one or more defects detected at the other site, or some combination thereof.

In some embodiments, the method includes determining an error probability value for one or more defects detected on the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space do.

In another embodiment, the method includes determining positional coordinates of a defect detected on a wafer in a design data space based on the location of inspection data in a design data space, determining, based on the topographic view of the design data, To the design cell coordinates. In one such embodiment, the method includes determining overlay tolerance to determine a different area around the defect, determining whether the one or more cell types are systematically defective cell types, And performing a defective repeater analysis for one or more cell types using the region to determine one or more locations of at least one systematically defective structure within the type. In one such embodiment, the method is based on one or more attributes, structures, or a portion thereof, of design data for a cell that is systematically located close to a defective cell type, such that spatially systematic defects are systematically located within the defective cell type Lt; / RTI >

In another embodiment, the method includes determining a location of a detected defect on a wafer in a design data space based on the location of inspection data in the design data space, determining a predetermined value for one or more properties of the design data, Determining a value for one or more attributes of the design data corresponding to the location of the defect using the data structure stored as a function of location within the space.

In a further embodiment, the image of the reticle generated by the reticle inspection system is used as design data in the design data space. The reticle is used to print the design data on the wafer. In another embodiment, a simulated image representing how the reticle image is to be printed on the wafer is used as design data in the design data space. In a further embodiment, the method includes generating a context map for design data in the design data space based on the reticle inspection data acquired for the reticle used to print the design data on the wafer.

In one embodiment, the method includes optimizing the wafer inspection process to determine the printability of reticle defects on the wafer using the location of the inspection data within the design data space and the context map. In another embodiment, the method includes detecting defects on the wafer using inspection data and standard reference die for standard reference die based inspection for standard reference die based inspection. In a further embodiment, the method further comprises detecting a defect on the wafer using a noise representation of the wafer noise associated with the standard reference die in the perturbation matrix for inspection data, standard reference die, and standard reference die based inspection .

In a further embodiment, the wafers and additional wafers are processed using wafer level process parameter adjustments, wherein the method further comprises comparing the inspection data for the wafers and the die on the additional wafers to a standard reference standard die, And detecting defects on the substrate.

Each of the above-described steps can be performed based on the near position of the inspection data in the design data space, one or more properties of the design data in the design data space, the history fab data, or other data corresponding to the hot spot in the design data. In some embodiments, the method includes performing statistical process control (SPC) based on the defect, one or more attributes of the group in which the defect is to be binned, or any other result of any of the methods described herein can do. Each embodiment of the above-described method may comprise any other step of any of the methods described herein. Each embodiment of the above-described method may be performed by any of the system embodiments described herein.

Another embodiment is directed to a system configured to determine the location of inspection data within a design data space. The system includes a storage medium containing design data. The system also includes a processor coupled to the storage medium. The processor is configured to align the data acquired by the inspection system with the data for a given alignment site for alignment sites on the wafer. The processor is further configured to determine the position of the alignment site on the wafer within the design data space based on the position of the predetermined alignment site within the design data space. The processor is further configured to determine the location of the inspection data acquired for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer within the design data space. This embodiment of the system may be further configured as described herein.

A further embodiment relates to a system configured to determine the location of inspection data within a design data space. Such a system includes data for an alignment site on a wafer and an inspection system configured to acquire inspection data for the wafer. The system also includes a storage medium containing design data. The system also includes a processor coupled to the inspection system and the storage medium. The processor is configured to align data for an alignment site on the wafer with data for a given alignment site. The processor is configured to determine the position of the alignment site on the wafer within the design data space based on the position of the predetermined alignment site within the design data space. The processor is further configured to determine the location of the inspection data within the design data space based on the position of the alignment site on the wafer within the design data space.

Additional embodiments are configured to determine the location of a design data-based attention area (e.g., an inspection area, a region to be inspected with high sensitivity, or a region to be inspected with low sensitivity) in the inspection space at the time of operation (e.g., during the inspection process) . In addition, the system can be configured to assign the acquired pixels of data substantially accurately to the correct attention area during the inspection process. The size and frequency of the attention area can approach the size and frequency of the design structure on the die. Such a system may be further configured as described herein.

A further embodiment relates to a computer-implemented method of binning detected defects on a wafer. The method includes comparing portions of the design data that are close to the location of the defects in the design data space. The method includes determining based on the comparing step whether design data in the portion is at least similar. The step of determining whether the design data in the portion is at least similar may include rotating and / or reflecting one or more portions. The method also includes grouping the defects into groups such that the portions of the design data that are close to the locations of the defects in each group are at least similar. The method further includes storing the result of the binning step on a storage medium.

In one embodiment, the dimensions of the part are determined by the location of the defect reported by the inspection system used to detect the defect, the coordinate inaccuracy of the inspection system, one or more properties of the design data, defect size errors of the inspection system, Based on at least in part. In other embodiments, the dimensions of at least some of the portions are different.

In one embodiment, the design data in that portion includes design data for one or more design layers. In this manner, the design data used in the methods described herein may include design data for one or more design layers. Using design data for one or more design layers in the methods described herein may be useful when a defect is detected using a BF (bright field) inspection capable of detecting defects on one or more layers, And may depend on what occurred on the previous or subsequent layers of the application. The method described above may include binning some or all of the data of interest into a group having at least similar design data.

In another embodiment, the comparing includes comparing the entire design data within at least a portion of the portion to design data in another portion of the portion. In another embodiment, the step of comparing includes comparing the other area of design data in at least a portion of the portion to design data in another portion of the portion.

In one embodiment, the method includes determining a location of a defect in a design data space by comparing data obtained by the inspection system for alignment sites on the wafer with data for a given alignment site. In another embodiment, the method includes determining a location of a defect in the design data space by comparing data acquired by the inspection system during a defect inspection to a location in the design data determined by review.

Alignment accuracy depends on both the coordinate conversion from design to wafer and the coordinate accuracy of the inspection system. Thus, preferably, the coordinates reported by the inspection system are substantially accurate. Further, the measurement for the alignment site can be performed using the logical check coordinates. (The inspection system outputs the logical wafer coordinates, but a defect review tool such as a scanning electron microscope (SEM) measures the physical wafer coordinates.) Thus, the physical coordinates on the wafer can be compared with the expected wafer layout, Can be corrected by the inspection system to account for differences in scaling and minute rotation. As such, such correction may be applied to the SEM measurement to reduce errors between the two coordinate systems from the reticle to the reticle .

In one embodiment, the binning step includes binning the defect into groups such that the portion of the design data that is close to the location of the defect in each group is at least similar and at least one attribute of the defect in each group is at least similar. In such an embodiment, the one or more attributes include one or more attributes of the test results from which the defect is detected, one or more parameters of the test, or some combination thereof.

In some embodiments, the portion of the design data that is close to the location of the defect includes design data where the defect is located. In another embodiment, the portion of the design data near the location of the defect includes design data around the location of the defect.

In another embodiment, the binning step includes binning the defect into groups such that the portion of the design data that is close to the location of the defect in each group is at least similar and the location of the defect in each group relative to the polygon within that portion is at least similar do.

In a further embodiment, the method includes determining a defect criticality index (DCI) for one or more defects. In another embodiment, the method includes determining at least one attribute of the design data near the location of the defect, one or more attributes of the defect, the location of the defect reported by the inspection system used to detect the defect, the coordinate inaccuracy of the inspection system, Or some combination thereof, determining the probability that one or more defects will cause one or more electrical failures in the device being manufactured for the design data. In one such embodiment, the method also includes determining a DCI for one or more defects based on the probability.

In some embodiments, the method includes identifying one or more hot spots in the design data based on a result of the binning step. In another embodiment, the method includes selecting at least a portion of a defect for review based on a result of the binning step. In a further embodiment, the method includes generating a process for sampling a defect for review based on a result of the binning step. In a further embodiment, the method includes modifying a process for inspecting a wafer based on a result of a binning step. In some embodiments, the method includes modifying a process for inspection of a wafer during an inspection based on inspection results. In another embodiment, the method includes modifying the metrology process for the wafer based on the result of the binning step. In a further embodiment, the method includes modifying the sampling plan for the metrology process for the wafer based on the result of the binning step. In yet another embodiment, the method includes monitoring over time systematic defects, potential systematic defects, or some combination thereof, using the results of the binning step.

In yet another embodiment, a defect is detected by an inspection process, the method comprising: reviewing a location on the wafer where at least one pattern of interest in the design data is printed; Based on the result of the review step, and changing the inspection process to improve one or more defect capture rates.

In some embodiments, the method includes prioritizing one or more POIs in the design data, optimizing one or more processes to be performed on the wafer on which the design data is printed based on the results of the prioritizing step . In another embodiment, the method includes prioritizing one or more POIs in the design data and optimizing at least one of the one or more POIs based on the results of the prioritizing step. In a further embodiment, the method comprises prioritizing one or more POIs in the design data and optimizing the resolution enhancement technology (RET) feature of one or more POIs based on the results of the prioritizing step .

In one embodiment, the defect is detected by optical inspection. In some embodiments, the defects are detected by electron beam inspection. In another embodiment, the defect is detected in a process window qualification (PWQ) method.

In some embodiments, the method includes reviewing at least a portion of the defects in the at least one group to determine whether the defects of the at least one group correspond to Newson defects, and to increase the S / N of the result of the inspection process, And removing one or more groups corresponding to the Newson defect from the result of the detected inspection process. In another embodiment, the method further comprises classifying defects of one or more groups based on review results of at least a portion of the defects in the one or more groups, one or more attributes of the design data, one or more attributes of the defects, . In a further embodiment, the method further comprises determining the root cause of one or more of the defects based on a review result of at least a portion of the defects in the one or more groups, one or more attributes of the design data, one or more attributes of the defects, .

In one embodiment, the method includes determining a root cause of a defect in one or more groups by mapping at least a portion of the defects in the one or more groups to an experimental process window result. In another embodiment, the method includes determining a root cause of a defect of one or more groups by mapping at least a portion of the defects in the one or more groups to a simulated process window result.

In some embodiments, the method includes the steps of modeling the electrical characteristics of a device being manufactured using design data for a defective location, determining the parameter relevance of the defects at the defective location based on the results of the modeling step . In another embodiment, the method includes monitoring a kill probability (KP) value of one or more defects based on one or more attributes of the design data. In a further embodiment, the method further comprises monitoring a KP value for one or more POIs in the design data, and if the portion of the design data near the location of the defect binned in one or more groups corresponds to one or more POIs, Lt; / RTI > to a group of one or more.

In some embodiments, one or more of the steps described herein may be performed by a test system (i.e., "on tool") or a processor that is physically separate but coupled to the inspection system by a transmission medium quot; off tool "). For example, in one embodiment, the computer-implemented method is performed by an inspection system used to detect defects. In an alternative embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect defects.

In another embodiment, the determining includes determining whether a common pattern in design data within the portion is at least similar. In a further embodiment, the determining includes determining if the common attribute of the design data in the portion is at least similar. In a further embodiment, the determining comprises determining whether a common attribute in the feature space of the design data in the portion is at least similar.

In one embodiment, the method includes determining a percentage of a die formed on a wafer affected by a defect of at least one group. In another embodiment, the method further comprises determining one or more POIs in the design data corresponding to the one or more groups, and determining at least one POI in the design data corresponding to the at least one group corresponding to one or more POIs And determining a ratio of the number of defects. In a further embodiment, the method comprises determining at least one POI in the design data corresponding to at least one group and at least one group corresponding to one or more POIs for the number of positions of the one or more POIs in the design data And determining the ratio of the number of binned defects.

In a further embodiment, the method further comprises determining a POI in design data corresponding to at least one group, determining a percentage of die formed on the wafer on which the at least one group of defects is located, And assigning a priority to the POI based on the percentage. In some embodiments, the method includes prioritizing one or more groups with a total number of design instances on a wafer from which defects of one or more groups are detected. In another embodiment, the method includes prioritizing one or more groups with the number of design instances on a reticle used to print design data on a wafer where defects in one or more groups are detected at least once. In a further embodiment, the method comprises comparing the number of positions on the reticle where a defect borne by at least one group is detected and design data printed on a reticle at least similar to a portion of the design data close to the position of the defect, Determining a reticle-based margin for the one or more groups based on the total number of portions.

In one embodiment, the method includes converting the portion of the design data near the location of the defect in the design data space to a bitmap prior to the comparing step. In one such embodiment, the comparing step compares the bitmaps to each other.

Each embodiment of the above-described method may include any of the steps of any of the methods described herein. In addition, each embodiment of the above-described method may be performed by any system described herein.

Another embodiment relates to a method for determining a DCI for a defect detected on a wafer. The method includes determining for a device near the location of the defect in the design data space a probability of changing the one or more electrical attributes of the device on which the defect is being fabricated based on the one or more attributes of the design data . The method also includes determining a DCI for the defect based on a probability that the defect will change the one or more electrical attributes. The method also includes storing the DCI in a storage medium.

In one embodiment, the defect includes a random defect. In another embodiment, the defects include systematic defects. In a further embodiment, the one or more electrical attributes comprise functionality of the device. In a further embodiment, the one or more electrical attributes comprise one or more electrical parameters of the device.

In one embodiment, one or more attributes of the design data include redundancy, a net list, or some combination thereof. In another embodiment, the one or more attributes of the design data include the dimensions of the features in the design data, the density of features in the design data, or some combination thereof.

In one embodiment, determining the probability comprises determining a probability using a correlation between an electrical test result for the design data and one or more attributes of the design data. In another embodiment, the step of determining a probability comprises determining a position of a defect in the design data space, a position of a defect reported by the inspection system used to detect the defect, a coordinate inaccuracy of the inspection system, Defect size error, or some combination thereof, based on one or more attributes of the design data. In one such embodiment, the defect includes random defects.

In some embodiments, determining the probability includes determining a probability based on at least one attribute of the design data, in combination with one or more attributes of the defect. In one such embodiment, the defects include systematic defects.

In one embodiment, the step of determining the DCI comprises determining the DCI for the defect based on the probability, in combination with the category assigned to the defect. In another embodiment, one or more defects in the design data include one or more attributes of design data for one or more design layers of the device.

In one embodiment, the method includes determining the location of inspection data within the design data space, and determining design data that is close to the location of the defect. In another embodiment, the method includes determining design data that is close to the location of the defect by defect alignment. In some embodiments, the method further comprises determining a position of a defect reported by the inspection system used to detect the defect, a coordinate inaccuracy of the inspection system, one or more attributes of the design data, a defect size, And determining design data that is close to the location of the defect based at least in part on some combination thereof.

In one embodiment, the method includes modifying the DCI based on the yield sensitivity of the design data for the defect. In another embodiment, the method includes modifying a process performed on a defect based on a DCI determined for the defect. In a further embodiment, the method includes modifying the process used to detect the defect based on the DCI determined for the defect. In a further embodiment, the method includes generating a process for inspection of additional wafers to be fabricated above, based on DCI for defects.

In one embodiment, the computer-implemented method is performed by an inspection system used to detect defects. In another embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect defects.

Each of the above-described embodiments may include any of the steps of any of the methods described herein. In addition, each embodiment of the above-described method may be performed by any system described herein.

Another embodiment relates to a computer implemented method for determining a memory repair index (MRI) for a memory bank formed on a wafer. The method includes determining a plurality of redundancy rows and a plurality of redundancy rows required to repair a memory bank based on a defect located in the array block region of the bank. The method also includes comparing the number of redundancy columns required to repair the memory bank to the number of redundancy columns available for the memory bank. The method also includes comparing the number of redundancy rows required to repair the memory bank to the amount of redundancy rows available for the memory bank. The method further includes determining an MRI for the memory based on the results of comparing the number of redundant rows and comparing the number of redundant rows. The MRI indicates whether the memory bank is repairable. The method also includes storing the MRI in a storage medium.

In one embodiment, the method further comprises the steps of determining which of the defects located in the array block area can cause the bits in the memory bank to fail, and determining if the bit is faulty based on the location of the defect And determining the location of the failed bit. In one such embodiment, the step of determining the number of redundant rows and the number of redundant rows required to repair the memory bank is performed using the location of the fail bit.

In another embodiment, the method includes modifying one or more parameters of the electrical test process based on the MRI using feedforward control techniques. In a further embodiment, the method further comprises altering one or more parameters of the electrical test process based on the MRI using a feedforward technique so that, if the memory bank is unrepairable, the die on which the memory bank is located is not tested during the electrical test process . In a further embodiment, the method further comprises changing one or more parameters of the repair process based on one or more attributes of the defects located in the array block areas of the memory banks, defects located within the array blocks of the memory banks, .

In one embodiment, the defect includes defects detected in the gates layer of the memory bank. In another embodiment, the defect includes a defect detected in the metal layer of the memory bank.

In some embodiments, the method includes predicting a bit error mode of the defect based on the location of the defect in the memory bank. In another embodiment, the method includes determining a DCI for one or more defects located within the array block area. In one such embodiment, determining the number of redundancy columns required for repair of the memory bank and determining the number of redundancy rows is performed using the DCI for one or more defects.

In one embodiment, comparing the number of redundancy columns is performed separately for each bank of memory dies, and comparing the number of redundancy rows is performed separately for each bank of memory dies. In some embodiments, the method includes determining an amount of available redundant rows and an amount of available redundant rows based on defects located in the redundant rows and redundant rows of the memory banks.

In one embodiment, the method includes determining an MRI for at least one memory bank formed in the die, and predicting the repair yield for the die based on the MRI for the at least one memory bank. In another embodiment, the method includes determining, based on the MRI, whether the amount of available redundancy rows in the memory bank, the amount of available redundancy columns, or some combination thereof is to be evaluated by a memory bank designer.

In some embodiments, the method includes determining an MRI for each memory bank in the at least one die on the wafer, and determining a memory repair yield for the at least one die based on the MRI for each memory bank . In some such embodiments, the method includes performing a wafer placement based on at least one memory repair yield for at least one die on the wafer.

In one embodiment, comparing the number of redundant rows includes determining a fraction of redundant rows required to repair a memory bank, wherein comparing the number of redundant rows includes comparing the fraction of redundant rows required to repair the memory bank Wherein determining the MRI for the memory bank comprises determining the MRI based on the fraction of redundant rows and the fraction of redundant rows. In some such embodiments, the method includes determining an MRI for each memory bank in at least one die on the wafer, and determining a memory repair yield for the one or more die based on the MRI for each memory bank . In a further such embodiment, the method includes determining a memory repair yield for the wafer based on a memory repair yield for each of the one or more dies.

In one embodiment, the MRI also indicates the probability that the memory repair bank can not be repaired. In one such embodiment, the method includes determining an MRI for each memory bank in the at least one die on the wafer, and determining an MRI for the at least one die based on the MRI for each memory bank in the at least one die Wherein the MRI for one or more dies indicates a probability that one or more die will not be able to be repaired. In one such embodiment, the method includes determining a wafer based yield prediction based on a threshold of MRI for at least one die on the wafer.

In one embodiment, the method determines a number of non-repairable defects in a memory bank based on a number of defects located in a decoder region of a memory bank, a number of defects located in a sense amplifier region of a memory bank, or some combination thereof. .

In some embodiments, determining the number of redundancy rows and the number of redundancy rows includes determining a DCI for each defect located in an array block region of a memory bank, comparing the DCI to a predetermined threshold value , Determining the number of redundant rows and the number of redundant rows required to repair all defects having a DCI of a predetermined threshold or more.

In one embodiment, the method includes determining an MRI for an error in a memory bank due to a defect located in an array block area of the memory bank. In another embodiment, the method includes determining an MRI for a memory bank error due to a defect located in the redundant column and redundant rows of the memory bank.

In some embodiments, the method includes generating a stack map of a pseudo memory bank design that represents a spatial correlation between detected defects in a memory bank. In another embodiment, the method includes determining MRI on a die-based basis. In a further embodiment, the method includes determining an index that indicates that the die on the wafer has failed due to a defect located in the array block region.

In one embodiment, the method includes the steps of determining an MRI for a memory bank in a die on a wafer, generating a stack map of the die representing a spatial correlation between two or more memory banks indicated by the MRI as unrepairable . In another embodiment, the method includes determining an MRI for a memory bank in a die on a wafer and using the memory bank to form a memory bank on the wafer indicative of a spatial correlation between two or more memory banks indicated by the MIR as unrepairable And generating a stacked map of the reticles.

In some embodiments, the method includes identifying a memory bank of the die affected by the detected defect in the die, and rating the memory bank based on the effect of the defect on the memory bank . In another embodiment, the method includes determining a percentage of a memory bank formed on a wafer affected by a defect in a non-repairable area of the memory bank. In some embodiments, the method includes generating a stacked wafer map of possible errors in a memory bank formed on the wafer that exhibits spatial correlation between possible errors. In a further embodiment, the method includes determining an MRI for one or more dies formed on a wafer, and rating the one or more dies based on the MRI.

Each embodiment of the above-described method can include any of the steps of any of the methods described herein. Further, each embodiment of the above-described method can be performed by any of the systems described herein.

Another embodiment is directed to another computer-implemented method for binning detected defects on a wafer. The method includes comparing a location of a defect in a design data space to a location of a hot spot in the design data. At least hot spots located close to similar design data are correlated with each other. The method also includes associating a defect with a hot spot having at least a similar location. The method also includes grouping the defects into groups such that defects in each group are associated only with hot spots that are correlated with each other. The method further includes storing the result of the binning step on a storage medium.

In one embodiment, the method comprises identifying locations of POIs in the design data associated with systematic defects to correlate hot spots, correlating POIs with similar patterns in the design data, correlating hot spots And correlating the location of the POI with the location of a similar pattern in the design data.

In some embodiments, the method includes assigning a DBC to one or more groups. In another embodiment, a computer-implemented method is performed by an inspection system used to detect defects on a wafer. In a further embodiment, the method includes monitoring the hot spot using the inspection results of the one or more wafers on which the design data is printed.

In one embodiment, the method includes inspecting a wafer based on a correlation between hot spots. In another embodiment, the method includes monitoring over time systematic defects, potential systematic defects, or some combination thereof based on the results of the binning step. In a further embodiment, the method includes performing a review of the defect based on the result of the binning step. In a further embodiment, the method includes generating a process for selecting a defect for review based on a result of the binning step.

In one embodiment, the method includes identifying systematic defects and potential systematic defects in the design data based on the results of the binning step, and monitoring results of systematic defects over time and the appearance of potential systemic defects . In another embodiment, the method includes generating a process for inspecting a wafer on which design data is printed based on a result of the binning step. In a further embodiment, the design data includes modifying the process for inspecting the wafer printed thereon based on the results of the binning step.

In some embodiments, the method includes determining a percentage of a die formed on a wafer affected by a defect of at least one group. In another embodiment, the method includes determining a DCI for one or more defects. In a further embodiment, the method includes determining a percentage of a die formed on a wafer on which a defect binned into at least one group is located, and assigning a priority to at least one group based on the percentage do.

In one embodiment, the method includes prioritizing one or more groups by the number of total hot spots correlated with the hot spots associated with the defects in the at least one group and the number of defects within the at least one group. In another embodiment, the method includes prioritizing one or more groups by the number of corresponding hot spot locations on the reticle used to print the design data on the wafer at least once the defects in the at least one group are detected do.

In some embodiments, the method further comprises determining, based on the number of positions on the reticle where a defect binned in one or more groups is detected, and the total number of hot spot locations on the reticle correlated to a hot spot associated with a defect in the one or more groups, And determining a reticle-based margin for the one or more groups.

Each embodiment of the above-described method may include any other step of any of the methods described herein. Further, each embodiment of the above-described method can be performed by any of the systems described herein.

Another embodiment is directed to another computer-implemented method for binning detected defects on a wafer. The method includes comparing one or more attributes of design data that are close to the location of a defect in the design data space. The method also includes determining whether at least one attribute of the design data near the location of the defect is at least similar, based on the comparison result. The method also includes grouping the defects into groups such that at least one attribute of the design data near the location of the defects in each group is at least similar. The method further comprises storing the result of the binning step on a storage medium.

In one embodiment, the one or more attributes comprise a pattern density. In another embodiment, the method includes using one or more attributes to determine whether the defect is a random or systematic defect. In a further embodiment, the method includes rating one or more groups using one or more attributes. In a further embodiment, the method includes rating the defects in at least one group using one or more attributes. In some embodiments, the one or more attributes include one or more attributes within the feature space.

In one embodiment, the method includes binning at least one group into a sub-group using one or more attributes. In another embodiment, the method includes analyzing a defect in at least one group using one or more attributes. In a further embodiment, the method includes determining the yield relevance of one or more defects using one or more attributes. In a further embodiment, the method includes determining overall yield relevance using one or more attributes. In yet another embodiment, the method includes assigning a DCI to one or more defects using one or more attributes.

In some embodiments, the method includes separating the design data near the location of the defect into design data in the defect surrounding area and design data in the area where the defect is located. In another embodiment, the method includes identifying a structure in design data for binning or filtering using rules and one or more attributes.

In one embodiment, the method includes determining a location on the wafer on which the review, measurement, test, or some combination thereof will be performed based on the inspection results produced during the detection of the defect and the defect identified as the systematic defect do. In another embodiment, the method further comprises determining a location on the wafer on which the review, measurement, test, or some combination thereof will be performed based on the inspection results produced during the detection of the defects, the defects identified as systematic defects, . In a further embodiment, the method determines the location on the wafer on which the review, measurement, test, or some combination thereof will be performed based on the inspection results produced during the detection of the defect, the defect identified as a systematic defect, and the process window mapping .

In one embodiment, the method includes performing a systematic search using the results of the binning step and the user-assisted review. In another embodiment, the method includes separating defects based on the functional block in which the defect is located, prior to the comparing step, to improve the S / N in the result of the binning step.

In some embodiments, design data is organized into hierarchical cells by design, and the method further comprises, prior to the comparing step, determining a defect based on the hierarchical cell in which the defect is located, in order to improve the S / N in the result of the binning step . In another embodiment, if the design data is organized into hierarchical cells by design and the defects can be located in one or more hierarchical cells, the method may be based on the area of the hierarchical cell, the defect location probability, And correlating the defect to each layer cell based on a probability of being located in each layer cell.

In one embodiment, the defect is detected by an inspection process, the method comprising the steps of: reviewing the location on the wafer where at least one POI in the design data is printed; and determining whether the defect should have been detected at the location of the POI Determining a result based on the result, and modifying the inspection process to improve one or more defect capture rates.

Each embodiment of the above-described method may comprise any other step of any of the methods described herein. Further, each of the embodiments can be performed by any of the systems described herein.

Another embodiment relates to a computer-implemented method for assigning categories to defects detected on a wafer. The method includes comparing a portion of the design data near the location of the defect in the design data space to design data (e.g., a POI design example) corresponding to a different DBC (e.g., different DBC bin specifications). The design data corresponding to the different DBCs and the different DBCs are stored in the data structure. The method also includes determining whether design data in the portion is at least similar to design data corresponding to a different DBC, based on a result of the comparison step. The method also includes assigning a DBC corresponding to at least similar design data to the defects in the design data in the portion. The method also includes storing the result of the allocating step in a storage medium.

In one embodiment, the computer-implemented method is performed by an inspection system used to check for defects. In another embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect defects.

In one embodiment, the method includes monitoring a hot spot in the design data based on a result of the allocating step. In another embodiment, design data corresponding to different DBCs are grouped by identifying defects detected on one or more other wafers based on portions of the design data that are close to the locations of defects detected on one or more other wafers in the design data space do.

In some embodiments, a defect is detected in an inspection process, the method comprising the steps of: reviewing a location on the wafer on which one or more POIs in the design data are printed; determining, based on the review result, , And modifying the inspection process to improve the defect coverage rate.

In one embodiment, the method further comprises determining whether the defect is a Newson defect based on the DBC assigned to the defect, determining whether the defect is a Newson defect from the result of the inspection process in which the defect is detected to increase the S / And removing the defect.

In another embodiment, the method includes determining a KP value for one or more defects. In a further embodiment, the method further comprises the steps of determining whether the DBC assigned to the defect corresponds to a systematic defect visible to the review system, and selecting only the defect visible to the review system for review and sampling the defect for review . In a further embodiment, the method includes determining one or more POIs in the design data by identifying one or more features in the design data indicating a pattern-dependent defect.

In one embodiment, the DBC identifies one or more polygons in the design data where the defect is located or where the defect is located. In another embodiment, the DBC identifies the location of one or more polygons in the design data. In a further embodiment, the data structure includes a library containing examples of design data organized by techniques, processes, or some combination thereof (e.g. POI design examples for DBC bin specifications).

In some embodiments, the method includes separating design data near the location of the defect into design data within the defect perimeter area and design data within the area where the defect is located. In another embodiment, the method includes monitoring over time systematic defects, potential systematic defects, or some combination thereof using the results of the allocating step. In a further embodiment, determining a KP value for one or more DBCs based on one or more attributes of the design data corresponding to the DBC. The KP value may be determined based on one or more attributes of the electrical test data and design data corresponding to the DBC. In a further embodiment, the method includes determining a KP value for one or more defects based on at least one attribute of the design data corresponding to the DBC assigned to the one or more defects. In another embodiment, the method includes monitoring a KP value for one or more DBCs and assigning a KP value for a DBC assigned to the defect to a defect.

In one embodiment, the dimensions of at least some of the portions are different. In another embodiment, the design data in that portion includes design data for one or more design layers. In another embodiment, the method includes determining a location of a defect in a design data space by comparing data obtained by the inspection system with respect to an alignment site on the wafer and data for a predetermined alignment site. In a further embodiment, the method includes determining the location of a defect in the design data by comparing the data acquired by the inspection system during the detection of the defect to a location in the design data determined for review.

In one embodiment, the step of allocating includes at least a step of assigning a DBC corresponding to the design data having at least one property that is at least similar to one or more attributes of the design data in the portion to a defect, do. In one such embodiment, the one or more attributes include one or more attributes of the defect in which the defect was detected, one or more parameters of the check, or some combination thereof.

In one embodiment, the design data near the location of the defect includes design data where the defect is located. In another embodiment, the design data near the location of the defect includes design data around the location of the defect. In a further embodiment, the method includes binning the defects assigned to one or more DBCs into a group such that the locations of defects in each group for the polygons in the portion of the design data near the location of the defect are at least similar.

In one embodiment, the method includes selecting at least a portion of a defect for review based on a result of the assigning step. In another embodiment, the method includes generating a process for sampling a defect for review based on a result of the assigning step. In a further embodiment, the method includes modifying a process for inspecting a wafer based on a result of the assigning step. In some embodiments, the method includes modifying a process for inspection during an inspection based on inspection results. In a further embodiment, the method includes modifying the metrology process for the wafer based on the result of the assigning step. In yet another embodiment, the method includes modifying a sampling plan for a metrology process for a wafer based on a result of the assigning step. The method may also include determining a location on the wafer where measurements, tests, reviews, or some combination thereof are to be performed upon actuation based on the results of the assigning step.

In another embodiment, the method includes optimizing one or more processes to be performed on a wafer to which design data is to be printed, prioritizing one or more DBCs and based on the results of the prioritizing step .

In one embodiment, the method includes determining a root cause of the defect based on the DBC assigned to the defect. In another embodiment, the method includes determining a root cause of at least a portion of a defect by mapping at least a portion of the defect to an experimental process window result. In a further embodiment, the method includes determining a root cause of at least a portion of a defect by mapping at least a portion of the defect to a simulated experimental process window result. In a further embodiment, the method includes determining a root cause corresponding to one or more DBCs and assigning a root cause to the defect based on the root cause corresponding to the DBC assigned to the defect.

In one embodiment, the method includes determining a percentage of die formed on a wafer affected by a defect to which more than one DBC is assigned. In another embodiment, the method includes determining a POI in design data corresponding to at least one DBC and determining a ratio of the number of defects allocated by at least one DBC to the number of locations on the wafer do.

In some embodiments, the method includes determining at least one POI in the design data corresponding to at least one DBC, determining a number of POIs in the design data corresponding to at least one POI in the design data, And determining a ratio. In another embodiment, the method includes determining a POI in design data corresponding to at least one DBC, determining a percentage of a die formed on the wafer on which the at least one DBC is assigned the defect, And assigning a priority to the POI based on the POI.

In one embodiment, the method may include determining one or more DBCs by a number of overall design instances (e.g., POI design examples from a DBC bean specification) on a wafer (e.g., on an inspection area of a wafer) And prioritizing the DBC. In another embodiment, the method further comprises determining the number of design instances on the reticle (e.g., on the reticle's inspection area) used to print the design data on the wafer at least once the defect to which more than one DBC has been assigned, And prioritizing the data.

In another embodiment, the method further comprises the step of determining whether a defect assigned to one or more DBCs is present in a portion of the design data that is close to the number of positions on the reticle (e.g., on the inspection region of the reticle) Based margin for one or more DBCs based on the total number of portions of design data printed on a similar reticle (e.g., a POI design example from a DBC bean specification).

In some embodiments, the method further comprises the steps of: prior to the comparing step, converting a portion of the design data near the location of the defect into a first bitmap, which may be performed as described herein, , And converting the design data corresponding to the DBC into a second bitmap, which can be performed as described herein. In one such embodiment, the comparing comprises comparing the first bitmap and the second bitmap.

Each embodiment of the above-described method may comprise any other step of any of the methods described herein. Further, each embodiment of the above-described method may be performed by any system described herein.

A further embodiment is directed to a method of altering an inspection process for a wafer. The method includes reviewing a location on the wafer on which one or more POIs in the design data are printed. The method also includes determining whether a defect should have been detected at the location of the one or more POIs based on the result of the review step. The method also includes modifying the inspection process to improve one or more defect capture rates for defects located in at least a portion of the one or more POIs.

In one embodiment, the modifying includes modifying the optical mode of the inspection system used to perform the inspection process. In another embodiment, the modifying includes modifying the optical mode of the inspection system used to perform the inspection process based on the result of the determining step. In a further embodiment, the modifying step includes modifying the inspection process to suppress noise in the result of the inspection process. In a further embodiment, the modifying step includes modifying the inspection process to reduce the detection of uninteresting defects. In another embodiment, the altering step includes altering the algorithm used in the inspecting process. In yet another embodiment, the altering step includes altering one or more parameters of the algorithm used in the inspection process.

Each embodiment of the above-described method may include any of the steps of any of the methods described herein. Further, each of the above-described embodiments can be performed by any of the systems described herein.

A further embodiment relates to a system configured to display and analyze design and defect data. The system includes a design layout for a semiconductor device, in-line inspection data obtained for a wafer on which at least a portion of the semiconductor device is formed, and a user interface configured to display electrical test data acquired for the wafer. The user interface can be configured to display modeled data for the semiconductor device and / or error analysis data for the wafer. The system also includes a processor configured to analyze one or more design layouts, inline inspection data, and electrical test data upon receiving an instruction from the user to perform an analysis via the user interface. The processor may be configured to analyze modeled data and / or error analysis data as described above.

In one embodiment, the electrical test data includes logic bitmap data. In another embodiment, the user interface is configured to display at least two overlays of design layout, inline check data, and electrical test data, possibly in combination with any other data described herein. In one such embodiment, the electrical test data includes logic bitmap data. In some embodiments, the processor is configured to determine a defect density in the design data space upon receiving an instruction from the user to perform a defect density determination step through a user interface. In a further embodiment, upon receiving a command to perform a defect sampling step from the user via the user interface, the defect sampling is performed for review. In a further embodiment, upon receiving an instruction from the user to perform the grouping step through the user interface, the defect grouping is configured to group defects based on the similarity of the design layout near the location of the defects in the design data space. Each embodiment of the system described herein may be further configured as described herein.

 A further embodiment relates to a computer-implemented method for determining the root cause of an electrical defect detected on a wafer. The method includes determining the location of an electrical defect in the design data space. The method also includes determining whether the location of the portion of the electrical defect defines a spatial signature corresponding to one or more process conditions. Where the location of the portion of the electrical defect defines a spatial signature corresponding to the one or more process conditions, the method includes identifying the root cause of the portion of the electrical defect as one or more process conditions. In this manner, the method includes performing a spatial signature analysis on the electrical test results. The method includes storing the result of the identifying step on a storage medium. Embodiments of the above-described method may include any of the other steps described herein. Embodiments of the above-described methods may be performed by any of the system embodiments described herein.

Yet another embodiment relates to a computer-implemented method for selecting defects detected on a wafer for review. The method includes identifying one or more regions of the wafer. One or more regions are associated with the location of one or more types of defects (e.g., possibly systematic defects) on the wafer. The method includes selecting defects detected in at least one region for review. The method also includes storing the result of the selection step on a storage medium. Such method embodiments may include any of the other steps described herein. This method embodiment may be performed by any of the system embodiments described herein.

There are a plurality of review use cases in which the method as described above can be used. For example, the above-described method can be used for systematic defect verification from a list of potential systematic defects, which can be performed during the search phase or maintenance of the monitoring phase. Further, the above-described method may also be applied to a known hot spot or location having a local pattern (i. E., Local design data) similar to a known hot spot (which may be identified during search step or recipe setup, Can be used to capture systematic defects. The method can be used for the verification or classification of defects detected at or near a hot spot, which can be performed during monitoring.

The above-described area information is used not only to sample defects from a specific area, but also to sample defects from all areas of the wafer in some intelligent manner and / or to detect or locate a specific type of design- Can be used to correct the extracted main area to a specific area of the high wafer. The primary area extracted from the design data may be for a single device, but the probability of finding the actual inspection defect due to the primary area may be more pronounced in a particular wafer area than in the other areas. In this manner, the method may include the step of supplementing the defect information from the die with the wafer using the area analysis described above. Such an embodiment may use any of the other information described herein.

Yet another embodiment relates to a computer-implemented method for evaluating one or more yield related processes for design data. The method includes identifying a potential error in the design data using a rule check or any suitable step or method described herein. The method also includes determining one or more attributes of the potential error. The method also includes determining if a potential error is detectable based on the one or more attributes. The method includes determining, based on the one or more attributes, which of the plurality of different inspection systems is most suitable for detecting a potential error. The method also includes storing the determination result in a storage medium which of the plurality of different inspection systems is most suitable for detecting a potential error.

In one embodiment, the method comprises selecting one or more parameters of the inspection system determined to be most appropriate. The parameter is selected based on one or more attributes. In this way, the best inspection system type can be estimated or selected based on the properties of the defect of interest. In another embodiment, the method comprises determining the effect of a potential error on the yield of the device produced by the design data. Each of the above-described method embodiments may include any other step of any of the methods described herein. Further, each of the above-described method embodiments may be performed by any of the system embodiments described herein.

A further embodiment relates to a carrier medium comprising program instructions executable on a processor to perform any of the computer-implemented methods described above. Additional embodiments relate to a system configured to perform any of the computer-implemented methods described herein. The system may include a processor configured to execute a computer instruction to perform the one or more computer-implemented methods described herein. In one embodiment, the system may be an independent system. In another embodiment, the system is part of or may be coupled to an inspection system, such as a wafer inspection system. In another embodiment, the system is part of or may be coupled to a defect review system. In another embodiment, the system may be coupled to a fab database. The system may be coupled to an inspection system, a review system, and / or a fab database by a transmission medium such as wire, cable, wireless communication path, and / or network. The transmission medium may include "wired" or "wireless" portions.

A method and system are provided for aligning inspection data to design data with sub-pixel accuracy (the size of the pixel can be as much as the size of the structure being examined).

Additional advantages of the present invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiments and accompanying drawings.
1 is a flow diagram illustrating one embodiment of a computer implemented method for determining the location of inspection data within a design data space.
Figures 2 and 3 are schematic diagrams showing a top view of another embodiment of a given alignment site.
4 is a hierarchy diagram illustrating various embodiments of a computer implemented method for performing inter-wafer comparison.
5 is a schematic diagram illustrating one embodiment of a computer implemented method for performing inter-wafer comparison.
6 is a schematic diagram showing a top view of one embodiment of the inspection data acquired for a wafer surface area separated by an annular ring;
7 is a schematic diagram illustrating a top view of one embodiment of inspection data acquired for a wafer surface area separated by a radial sector;
8 is a schematic diagram illustrating another embodiment of a computer implemented method for performing inter-wafer comparison.
Figure 9 is a schematic diagram illustrating a top view of one embodiment of a die array printed on a wafer.
10 is a schematic diagram showing a top view of one embodiment of inspection data obtained for a printing die on a wafer separated by a frame;
11 is a schematic diagram illustrating another embodiment of a computer implemented method for performing inter-wafer comparison.
12 is a schematic diagram illustrating a scan path on a wafer and a top view of one embodiment of a die array printed on a wafer.
13 is a schematic view showing a top view of a continuous swath of inspection data acquired for a wafer;
14 is a top view of an alignment site selected by a computer implemented method for determining the location of swath N + 1 relative to swath N using data in the swath overlap region, Fig.
14A is a schematic diagram showing a top view of one embodiment of another swath of inspection data acquired for a wafer whose alignment site is relatively far away from the first inspection swath;
Figures 14 (b) - 14 (d) are schematic views showing top views of various embodiments of other swaths of inspection data acquired for a wafer.
Figure 15 is a flow chart illustrating another embodiment of a computer implemented method for determining the location of inspection data within a design data space.
16 is a schematic diagram illustrating a side view of various embodiments of a system configured to determine the location of inspection data within a design data space;
Figure 17 is a schematic diagram illustrating one embodiment of a computer implemented method for binning detected defects on a wafer.
Figure 18 is a schematic diagram illustrating a top view of one embodiment of an array site on a wafer in three different dies, positioned on the wafer in a triangular arrangement.
19 is a schematic diagram illustrating another embodiment of a computer implemented method for binning detected defects on a wafer.
Figure 20 is a schematic diagram illustrating one embodiment of an input to and output from a module configured to perform a computer implemented method for binning detected defects on a wafer in accordance with an embodiment described herein.
Figures 21 and 22 are schematic diagrams illustrating another embodiment of the output of the module of Figure 20;
Figure 23 is a schematic diagram illustrating one embodiment of the input and output of the module of Figure 20;
Figure 24 is a schematic diagram illustrating a top view of one embodiment of the output of the module of Figure 20;
Figure 25 is a schematic diagram illustrating a side view of one embodiment of a system configured to display and analyze defect data and design.
26 is a schematic diagram illustrating a top view of one embodiment of one or more regions on a wafer associated with the location of one or more defect types on the wafer.
Figure 27 is a flow chart illustrating one embodiment of a computer implemented method for evaluating one or more yield related processes for design data.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. The drawings may not be scaled. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. .

As used herein, the term "wafer" generally refers to a substrate formed of a semiconductor or non-semiconductor material. Examples of such semiconductor or non-semiconductor materials include, but are not limited to, monocrystalline silicon, gallium arsenide, and indium phosphide. Such a substrate may be commonly found and / or processed in a semiconductor manufacturing facility.

The wafer may comprise at least one layer formed on the substrate. For example, such a layer may include, but is not limited to, resist, dielectric material, and conductive material. Various other types of such layers are known in the art, and the term wafer as used herein is intended to include wafers that include all types of such layers.

The one or more layers formed on the wafer may be patterned or unpatterned. For example, the wafer may include a plurality of dies each having repeatable pattern features. The formation and treatment of such a layer of material may ultimately result in a finished device. Various other types of devices, such as integrated circuits (ICs), may be formed on a wafer, and the term wafer as disclosed herein is intended to include wafers on which any type of device known in the art is formed .

Although an embodiment has been described herein with respect to a wafer, it should be understood that embodiments may be used for other specimens, such as a reticle, which may be commonly referred to as a mask or a photomask. Various other types of reticles are known in the art, and the terms "reticle", "mask", and "photomask" disclosed herein are intended to encompass all types of reticles known in the art.

The term "design data" as used herein generally refers to data derived from a physical design through the physical design (layout) of the IC and complex simulations or simple boolean operations. In addition, the image of the reticle acquired by the reticle inspection system and / or its derivation can be used as "proxies " or" proxies "of design data. The reticle image or derivative thereof may serve as an alternative to the design layout in any of the embodiments disclosed herein using design data.

For example, in one embodiment, the image of the reticle generated by the reticle inspection system is used as design data in the design data space. The reticle is used to print design data on the wafer. In this way, the image of the reticle generated by the reticle inspection system can be used as an alternative to the design data. The image of the reticle used in this embodiment may comprise any suitable reticle image produced in any suitable manner by any reticle inspection system known in the art. For example, the image of the reticle may be a high magnification optical or electron beam image of the reticle acquired by each of the high magnification optical reticle inspection system or the electron beam based reticle inspection system. Alternatively, the image of the reticle may be an aerial image of a reticle acquired by an aerial imaging reticle inspection system. The image of the reticle may be used as a proxy for design data in any of the embodiments described herein that use design data to perform one or more steps.

In a further embodiment, the method includes generating a context map for design data in a design data space based on the reticle inspection data acquired for the reticle used to print the design data on the wafer. In this manner, the reticle inspection data can be included as input to the creation of the context map. The context map may be configured as described further herein (e.g., the context map may include values for one or more attributes of the design data across the design data space). The reticle inspection data used to generate the context map may include any suitable reticle inspection data known in the art, such as one or more of the reticle images described above. Thus, in this embodiment, the reticle inspection data can be used to determine a value for one or more attributes of the design data printed on the reticle over the reticle, the value being mapped to the design data space to generate the context map mapping. The step of determining a value for one or more attributes of the design data printed on the reticle may be performed as described herein or in any suitable manner. One or more attributes of the design data may include any of the attributes described herein. The mapping of values to one or more attributes from the reticle space to the design data space may be performed as further described herein. Such a context map may be used in any of the embodiments described herein, including using a context map to perform one or more steps. Further, such a context map may be additionally generated based on any other information described herein and / or as described herein.

The image derived from the reticle image can serve as a "proxy" for the design data. For example, a reticle image generated by a reticle inspection system or any other suitable imaging system may be used to generate a simulated image that can be used as a "proxy" for design data, describing how a reticle image can be printed on a wafer . In one embodiment, a simulated image representing how the reticle image is printed on the wafer may be used as design data in the design data space. In this way, a simulation of how the reticle image appears on the wafer surface can serve as a substitute for the design data. The simulated image may be generated in any manner using any suitable method or system known in the art. The simulated image may be used as a proxy for design data in any of the embodiments shown herein that use design data to perform one or more steps.

In the embodiments described herein in which design data is used, at least in part, to perform one or more steps, the design data may comprise any of the design data or design data proxies described above or any combination thereof.

In the drawings, it should be noted that the drawings are not drawn to scale. In particular, the scale of some of the elements in the figures is highly exaggerated to emphasize the features of the elements. It should also be noted that the drawings are not drawn to scale. Elements shown in one or more figures that may be similarly configured are indicated using the same reference numerals.

Figure 1 illustrates one embodiment of a computer implemented method for determining the location of inspection data within a design data space. It should be noted that not all of the steps shown in FIG. 1 are necessary for the implementation of the method. One or more steps may be omitted from or added to the method shown in FIG. 1, and the method may still be practiced within the scope of this embodiment.

In general, the method may include a data preparation step, a recipe setup step (e.g., wafer inspection recipe setup), and a wafer inspection step itself. The method may also include a review and analysis step. The data preparation step may be performed from a data structure such as a design data (e.g., a graphics data stream (GDS) file, a GDSII file, or other standard file or database) that is being fabricated on a wafer or that reflects the physical design layout of the device to be fabricated on the wafer And acquiring or acquiring the acquired information). GDS files, other files, or information from a database may describe the physical design layout pre-decoration (i.e., the optical proximity correction (OPC) feature added to the design and any other Without resolution enhancement technology (RET) features).

The method shown in FIG. 1 generally includes aligning the inspection data stream to design data within sub-pixel accuracy as further described herein. In this manner, the method described herein can be generally referred to as a " align to design "method for inspection (e.g., wafer inspection). The method utilizes design data and optionally context data for wafer inspection. In this manner, the method described herein may also be referred to as a "Context Based Inspection (CBI)" method. Device design and context data can be used to increase wafer inspection sensitivity, dramatically reduce nuisance event detection, increase defect classification accuracy, and improve application to inspection systems such as process window qualification (PWQ) Lt; / RTI > Context data may be used to provide advantages to the defect review process and system as further described herein. Examples of how to use design data and context data are described in U.S. Patent 6,886,153 (Devis) and U.S. Patent Application Publication No. 2005/0004774 (Volk et al.), Filed January 6, 2005, No. 10 / 883,372, filed January 1, 2004, which is hereby incorporated by reference as if fully set forth herein. The methods described herein may include any step in any of the methods described in such patents and patent applications.

The method described herein may include a hot spot search step. The hotspot search can be performed during technology investigation and deployment, product design, RET design, reticle design and manufacture, and product ramp. The hot spot exploration step may include the steps of enhancing the reticle design and identifying hot spots for defect monitoring and classification. The hot spot searching step may also include generating a data structure that includes information about a hot spot, such as a hot spot database. In some embodiments, the hot spot search may be performed using multiple sources. For example, the hotspot search may be performed using a correlation between any of design space hotspot search, wafer space hotspot search, reticle hotspot search, test space hotspot search, and process space hotspot search . In one example, the hotspot search can be performed correlating multiple sources of design, modeling results, search results, metrology results, and test and error analysis (FA) results. Any of the steps described herein may be used in any combination to search hot spots.

In the design space, hotspots can be identified using the results of a design rule check (DRC) to generate a list of critical points in the design data. DRC is typically performed for quality control (QC) of the reticle layout data prior to mask fabrication (pre-mask). Thus, the DRC may not generate hot spots. Instead, the result of the DRC can be used in a design manual that is not part of the DRC rule, or can be used to identify a newly discovered marginal hot spot. Hot spots can also be explored using electron design automation (EDA). In this way, during the hotspot search phase, design rules (DRCs used as marginality checkers) and / or EDA design tools can be used as a source of hotspots. Hot spots can also be explored using computer aided design (TCAD) tools and techniques for proxies. The TCAD tool is commercially available from Synopsis, Inc. of Mountaintown, CA. In addition (or alternatively), design scan analysis software commercially available from KLA-Tencor Corporation of San Jose, Calif., Any pattern search and design context (e.g., function block, design library element , Whether cells, patterns are redundant, pattern density, dummy / fill vs. activity, etc.) can be used as a source of hot spots. In another example, a design data based grouping of defects (with or without pareto analysis) can be used to search and group hot spots, which can be performed as described herein.

In a further example, in the design space, the hotspot searching step includes aligning or superimposing a scanning electron microscope (SEM) image of the design data printed on the wafer onto the design data to identify the actual defect location in the design data space (Which may be performed as described herein), and any pattern search based on design data close to the location of the defects in the design data space may be performed to identify similar hot spots in the design . A repeater analysis performed on the original inspection results for the wafer, which may then be performed as described herein, may be used to identify its design grouping in systematic defects and design data. One advantage of this approach is that the pattern search window used for arbitrary pattern searching and / or systematic defect identification can be adjusted for each defect if the target defect is located substantially precisely in the design data space.

In the wafer space, the hot spots can be divided into a plurality of areas, such as repeater analysis, which can be performed as described further herein, regional / spatial signature analysis of systematic (e.g., process margin) deficiencies, temporary signature analysis of systematic defects , Stacking die (or reticle) results by design overlay to improve signal to noise ratio (S / N) for searching in the reticle / die space, and attributes of defects to prioritize systematic defects or systematic defect groups Can be searched using one or more of the yields (or KP (kill probability)) correlated to the defect space.

In the reticle / die space, hot spots can be added to a design context (e.g., function block) to improve the S / N, such as repeater analysis, defect density mapping, design pattern based grouping analysis, Or by identifying one or more defects that are not of interest from the reticle inspection to search for cold spots in the design.

In a test space, a hot spot can be searched using one or more of a bit failure density for designing a mapping and a logic bitmap density for designing a mapping, (Performed in a wafer space) or a design data based grouping (performed in a reticle / die space) to identify a cold spot. Each of these steps may be performed as further described herein.

In a process space, a hot spot is defined as a PWQ (using a die-die, a standard reference die, or a die-database method) as a source of a hot spot and a DOE of experiment (using a die-die, standard reference die, or die-database method), each of which may be performed as described further herein.

In some embodiments, as shown in step 10 of Figure 1, the method includes selecting a predetermined alignment site in the design data. The predetermined alignment site selection step can be performed using the inspection system. The predetermined alignment site may be selected during setup of the inspection process recipe. A "recipe" is generally defined as a set of instructions for performing processes such as inspection. Recipe setup for wafer inspection, as described herein, may be performed automatically, semi-automatically (e.g., user-assisted), or manually.

In one example, during the setup of the inspection process performed by the inspection system, in addition to the design data, inspection system parameters such as wafer swathing information, inspection system model number, optical mode to be used for inspection, Information about the variable can be used to select a predetermined sorting site. The predetermined alignment site can be selected based on one or more attributes of the wafer to be inspected. The data for a given alignment site (or indicia that refers to this data) and / or its image may be stored in a recipe for the inspection process. For example, information about a given alignment site for a layer on a wafer can be stored as alignment data in an inspection process recipe for a layer on the wafer, and the alignment data is used when the inspection system inspects wafers of this particular device and layer .

Although some embodiments include "wafer scanning steps" for acquiring data and / or images for wafers, such data and / or images may be acquired using any suitable technology and / or system known in the art You should understand that you can. For example, data and / or images for wafers may be obtained by the inspection system described herein, or by another inspection system configured to perform field-by-field image acquisition. In this manner, instead of scanning across the wafer, the inspection system can acquire data and / or images in a stepping fashion. In another example, data and / or images for wafers may be obtained by the inspection system described herein, or by another inspection system configured to perform point-by-point inspection, commonly referred to as an automated process inspection (API).

Several methods can be used to select a given alignment site. In one embodiment, the method includes obtaining design data corresponding to a predetermined alignment site. Data or images for a given alignment site that can be used in the methods described herein may be used for rendering GDS clips (the term "clip" used herein refers to a relatively small portion of the design layout) Contains images generated by inspection systems arranged in clips. The step of simulating (or "rendering") the design data corresponding to a given alignment site can be used to create an image that describes how the design data is printed on the wafer. The method includes performing a cross-correlation of a simulated ("rendered") image with design data or GDS clips, writing the location of the simulated image into a design data space (i.e., . Image simulations that describe how design data corresponding to a given alignment site are to be printed on a wafer, as described above, can be performed using any suitable method, algorithm, or method known in the art, such as PROLITH, commercially available from KLA-Tencor Can be performed using the software.

In addition, after one or more processes have been performed on the wafer, a simulation image may be generated as described above that describes how a given alignment site will be printed on the wafer. One or more processes may include, for example, lithography, combinations of lithography and etch, other lithography processes, and the like. In this manner, the data for a given alignment site used in the methods described herein may include one or more simulated images selected or generated based on one or more processes performed on the wafer prior to inspection. Using different data for a given alignment site for alignment of the acquired inspection data after another process is performed on the wafer may increase the precision of the method described herein.

Selecting a given alignment site may include pre-processing design data (e.g., GDS data) to select a predetermined alignment site that is compatible with the inspection process and system. For example, in some instances, the rendered GDS clips are not affected by the variations (e.g., color variations) caused by the wafer fabrication process because the GDS clips are not affected by the data for a given alignment site in the methods described herein As shown in Fig. However, the image of the given alignment site acquired by the inspection system aligned with respect to the rendered GDS clip "off-line " is not an image of the alignment site on the wafer produced by the inspection system, It is advantageous to use it with the inspection data generated at a later stage of the device fabrication. Thus, in some embodiments, the alignment data used in the method described herein may be applied to a GDS clip and its GDS clips to ensure that a suitable match to the data for the alignment site on the wafer can be found during test run. And may include both aligned images. Alternatively, one or more attributes of a given alignment site in the design data may be determined, such as the center of a given alignment site, and the corresponding center of the image of the alignment site acquired by the inspection system may be scanned Can be determined and used to align.

The number of predetermined alignment sites selected per die may vary greatly. For example, a relatively sparse set of predetermined alignment sites may be selected. Also, a given alignment site can be selected at a predetermined frequency across the die. Because a given alignment site may be included in the die itself, the desired alignment site may be selected to include device features within the die and / or features located within the device region of the die. In this manner, a given alignment site may be selected to include pre-existing features of the design data. Such predetermined alignment sites are advantageous because the design data need not be modified to include alignment features and alignment features do not increase die size.

The method may also include selecting a given alignment site in the design data (in some non-alignment tolerance windows) that can be uniquely identified within the image or data acquired by the inspection system. For example, a given alignment site may be selected to include a distinct alignment feature (i.e., a target) within a given search range uncertainty. In this manner, if a particular positional uncertainty of the position of the alignment site on the wafer is given to the image or data, alignment data and alignment data to identify a relatively strong match of the two alignment sites without any ambiguity, Can be performed.

In one embodiment, a given alignment site includes at least one alignment feature having one or more properties unique in the x and y directions. One embodiment of such a predetermined alignment site is shown in Fig. As shown in FIG. 2, the predetermined alignment site 32 includes the alignment feature 34. The alignment feature 34 has one or more attributes that are unique in the x and y directions. For example, the corners of the alignment feature impart a unique alignment feature in the x and y directions to other features within the die, and approximate the alignment feature. A given alignment site may also include one or more such alignment features that may be similar or differently configured. In this way, the alignment feature may be unique in the x and y directions.

In an alternative embodiment, a given alignment site includes at least two alignment features. The first of the two alignment features has one or more properties that are unique in the x direction. The second of the two alignment features has one or more properties that are unique in the y direction. An embodiment of such a predetermined alignment site is shown in Fig. As shown in FIG. 2, the predetermined alignment site 32 includes alignment features 38. The alignment feature 38 has one or more attributes that are unique in the x direction but do not provide information about alignment in the y direction. For example, the vertical edge of the alignment feature 38 may give a distinctive alignment feature in the x direction for other features in the die, and may approximate the alignment feature. A given alignment site may include one or more such features.

The predetermined alignment site 36 includes the alignment feature 40. The alignment feature 40 has one or more attributes that are specific to the y direction but do not provide alignment information in the x direction. For example, the horizontal edge of the alignment feature 40 may impart a unique alignment feature in the y direction for other features within the die, and may approximate the alignment feature. A given alignment site may also include one or more such features. Also, a given alignment site may include two or more alignment features that are specific to the x and / or y directions. In this manner, a given sorting site may store an absolute (x, y) offset between the "live" image or data (e.g., image or data acquired by the inspection system during inspection) Such as features 38 and 40, that provide sufficient x and y alignment information in combination to determine the alignment feature.

The selection of a given alignment site may be performed manually, automatically, or any combination thereof (i.e., semi-automatic or user-assisted). Whether performed manually, automatically, or both, a given alignment site selection may be performed using design data, optical or electron beam images of the wafer, or both. In a user-assisted selection of a given alignment site, a user may select a computer-aided design (CAD) layout, a live or stored optical or electron beam image of the wafer, or a computer-aided design (CAD) layout to determine one or more predetermined alignment sites that meet the above- You can check both of them.

In automatic or semi-automatic selection of a given alignment site, the method includes scanning the die array on the wafer using the inspection system, processing each frame of the die to identify a unique alignment site (e.g., By algorithm execution). The term "frame" is generally defined herein as data or an image for a portion of a die in a swath of inspection data or images acquired during scanning of the wafer. Processing the frame includes determining an x and y gradient of a feature in the frame and selecting one or more features having a relatively strong gradient in the x and / or y direction for use at a given alignment site do. The method includes performing a cross-correlation of a patch image and a frame comprising such features to determine if only one relatively strong peak of the gradient is within a predetermined search range. In this manner, distinctive alignment features within the pattern search window can be identified and selected for a given alignment site. The method includes connecting to the design data, assigning at least one relatively small region of the design data as at least one image, and performing the steps described above to identify a suitable alignment site. The method includes displaying at least one potential alignment site identified by the method (e.g., an optical or electron beam and a CAD image pair for a potential alignment site), and determining a 1 And allowing the user to select a suitable alignment site.

In another embodiment, the imaging mode of the inspection system or other image acquisition system used to select a given alignment site is different from the imaging mode of the inspection system used to acquire inspection data. In this manner, the method may include using different imaging modes for alignment site selection and wafer inspection. The alignment site selection step may be performed based on various imaging modes that may be used to inspect the wafer. For example, the inspection system may include a light field (BF) mode, a dark field (DF) mode, an edge contrast (KLA-Tencor trademark) mode, various aperture modes, and / May be configured to use one or more same optical imaging modes for inspection. Edge contrast (EC) inspection is generally performed using a circular symmetrical illumination aperture with a complementary imaging aperture. The best imaging mode for inspection of a specific layer on the wafer is an imaging mode that maximizes the defect S / N, and the best imaging mode may vary depending on the layer type. The inspection system can also be configured to inspect the wafer using one or more imaging modes simultaneously or sequentially. Since the alignment site image or data acquisition performed during the wafer inspection uses the best imaging mode for wafer inspection, it is preferred that the alignment site selection use that mode to select the appropriate alignment site and alignment feature.

However, in order to precisely determine the position of a selected predetermined alignment site within the design data space, the optical patch image of a given alignment site (on the wafer) is aligned with the GDSII clip or a simulated image derived from the design data as described above . Obtaining a simulated image with an appropriate quality for the alignment of the optical image and the simulated image may be difficult for all imaging modes. However, the best match of the simulated image and the optical image may be obtained for a particular imaging mode (e.g., BF mode). Thus, the method may also include scanning the wafer using the best imaging mode for inspection to select a suitable alignment site. The method may include revisiting a selected predetermined alignment site on the wafer using an inspection system to obtain an optical patch image using a mode that provides a simulated image or an image that best matches a GDSII clip May also be included.

The image acquired using the best mode to match the simulated image or GDSII clip may be aligned to the simulated image or GDSII clip for the corresponding alignment site in the design data. By using the (x, y) position of the selected alignment site in the design data space determined by aligning the acquired image with the simulated image or GDSII clip using the best mode for the match, such x and y positions are best for inspection Lt; / RTI > may be associated with the acquired patch image using the mode of FIG. If there are some fixed offsets between images collected for the same site in different modes (the test mode and the best mode for matching a simulated image or a GDSII clip), this offset can be determined using an appropriate calibration target May be measured and / or modified at the start (or after) of the test.

In such an embodiment, the method may be used to determine the mapping (i. E., To determine the position of an individual pixel of an optical or electron beam image within the design data space), to the optical < And may include off-line alignment of the simulated image or GDSII clip. For example, after an image of these sites on the wafer is acquired using an imaging mode that can select a predetermined alignment site and provide the best image for matching with the simulated image, design data corresponding to a predetermined alignment site (In any format, such as a polygonal representation), and then applied as a simulated image of the appropriate pixel size using the appropriate transform function. The optical (or electron beam) image and the simulated image may be aligned with one another using any suitable method and / or algorithm known in the art. The step of aligning the optical (or electron beam) image and the simulated image with each other may be performed in such a way that the previous layer structure can be a source of noise in the optical image such that it can be removed from the optical image or otherwise considered to achieve sufficiently precise alignment May be performed using other information (e.g., in the design database) about the design data, such as the previous layer structure.

The result of the process of setting up the inspection recipe may include one or more optical or electron beam patch images representing a given alignment site, respective positions (e.g., x and y coordinates) of a given alignment site within the design data space, And may include any additional information that can be utilized by the inspection system to perform substantially precise alignment during inspection.

As shown in step 12 of Figure 1, the method includes aligning the data acquired by the inspection system with the data for a given alignment site for alignment sites on the wafer. The data for a given alignment site may include any of the data discussed above. For example, data for a given alignment site may include design data stored in a data structure such as a GDSII file or other standard instrument-readable file format. In another embodiment, the data for a given alignment site includes one or more simulated images that describe how a given alignment site will be printed on the wafer. One or more simulated images may be mapped to a design data space as further described herein so that the location of alignment sites on the wafer within the design data space may be further described herein based on the location of certain alignment sites within the design data space Can be determined as follows.

In a further embodiment, the data for a given alignment site includes one or more attributes of a given alignment site, the data for an alignment site on the wafer includes one or more attributes of the alignment site, To at least one attribute of the sorting site. The alignment sites on the wafers used in this embodiment and one or more attributes of a given alignment site may include any of the attributes described herein. For example, in one embodiment, one or more attributes of a given alignment site include the center of a given alignment site, and one or more attributes of the alignment site on the wafer include the center of the alignment site. The alignment sites on the wafer and the center of a given alignment site may be centered on one or more alignment features within the site. In this manner, the method may include matching the alignment site on the wafer with the center of the predetermined alignment site to align the alignment site on the wafer to the predetermined alignment site. As such, the data for a given alignment site may include some feature of a given alignment site, such as a center, that can be aligned to a corresponding feature of the data for the alignment site on the wafer. One or more attributes, such as the alignment site on the wafer and the center of a given alignment site, may be determined in any manner known in the art or as described herein.

In a further embodiment, the data for a given alignment site includes data obtained by inspection systems arranged in design data stored in a data structure such as a GDSII file. The data acquired by the inspection system for a given alignment site may be arranged into a design as described herein. In some embodiments, the data for a given alignment site includes at least a portion of a standard reference die image aligned with the design coordinates in the design data space. The standard reference die image may include any of the standard reference die images described herein, and the standard reference die image may be aligned to the design coordinates as described herein. For example, a standard reference die image may be mapped to a design space and then used for alignment.

The step of aligning the data for the alignment site to the data for a given alignment site may be performed using any suitable alignment and / or alignment algorithm known in the art.

In one embodiment, step 12 may be performed during wafer inspection. This step may also be performed each time the wafer is inspected using the inspection process recipe. For example, it may include an initialization step that can be performed at the start of a plurality of wafer tests and at the start of inspection of each wafer in a lot. During the initialization step, the (x, y or two-dimensional) mapping of a given alignment site and a predetermined alignment site in the design data space can be accessed from the recipe setup result, and the live May be downloaded to an image computer processing node that may be used to perform the alignment of the patch image and the stored alignment patch image. The image computer and processing node may have any suitable configuration known in the art.

During the inspection process, the method may include scanning the wafer using an inspection system to obtain a swath of inspection data. Each swath may be acquired as a pixel stream at some height H (in the y direction) when the inspection system scans across the die in rows or columns on the wafer (in the x direction). Each processing node in the image computer can process a portion of the swath. For example, the swath can be divided into parts or "pages " and each part of the swath can be directed to another processing node. The processing node may be configured to perform defect detection using pixels within the portion of the swath received by the processing node. The method and image computer use the information about the location of the alignment site (e.g., location within each die) on the wafer and the patch image of a given alignment site acquired from the image computer storage media (e.g., downloaded during the initialization step) To align the given alignment site to the live stream data for the alignment site on the wafer.

In some embodiments, a context map (e.g., stored in a data structure such as a database) may be connected and downloaded to the processing node. Such context data may be stored in any suitable format known in the art. Such context data may be stored and / or used in a compact polygonal format rather than an image format. However, the context map can be given to the image so that its context map can be used for defect detection purposes. This grant may be performed once during the initialization or whenever a context map is used during the test. The advantage of the former approach is that granting a context map during initialization reduces the data processing cycles that are performed during the inspection process. However, the disadvantage of this approach is that storing the full image of the context map may require a relatively large amount of memory.

As shown in step 14 of FIG. 1, the method includes determining an alignment position on a wafer within a design data space based on a position of a predetermined alignment site in the design data space. For example, since the (x, y) location of a given alignment site for design data coordinates (i.e., within the design data space) is determined and the data for a given alignment site is aligned with the data for the alignment site, The absolute position of the live pixel coordinates of the alignment site can be determined within the design data space. In another embodiment, the step of determining the position of the alignment site on the wafer within the design data space comprises arranging the raw data stream (e.g., a live image) into data for a given alignment site . ≪ / RTI > The step of determining the position of the alignment site on the wafer within the design data space may be performed before the inspection of the wafer or after the acquisition of inspection data for the wafer.

As shown in step 16 of Figure 1, the method includes determining the location of the inspection data acquired for the wafer by the inspection system in the design data space based on the alignment location on the wafer within the design data space. The inspection data for the location at which the design data is determined may include any data (e.g., image data) acquired for the wafer by the inspection system during the inspection. For example, the location of the inspection data may be determined for some or all of the data acquired by the inspection system during inspection of the wafer. For example, the position of the inspection data can be determined only for the inspection data acquired for the area of interest on the wafer.

In one embodiment, after aligning the position of a new data stream corresponding to an alignment site on the wafer with a reference image of a given alignment site, as described above, the method may include the step of providing a coordinate offset between the inspection data stream and the design data, And measuring within the pixel precision. In addition, the coordinate errors between the live inspection data and the design data are such that a new inspection data image is projected onto a reference image for a given alignment site, such that the alignment site on the wafer is aligned substantially precisely to a predetermined alignment site for all points across the die As shown in FIG. One significant advantage of the methods and systems described herein is that the location of inspection data within the design data space can be determined with sub-pixel accuracy. In this manner, the protection and non-attention regions on the wafer can be determined with a relatively high accuracy of less than 100 nm accuracy, as further described herein.

In another embodiment, the data for a given alignment site can be used to determine a two-dimensional mapping transformation that can be used to map the live image pixel space to the design data space. For example, as described above, the method may include correlating the downloaded predetermined alignment site patch image (obtained during setup of the inspection process) with live image data over a predetermined range, and between the downloaded image and the live image And determining an offset of the first signal. The method further comprises determining the correspondence between the live image pixel location and the design data coordinates using such an offset since the (x, y) location of a given alignment site in the design data space is determined during setup . The method may include determining a two-dimensional function for mapping live pixel coordinate space to a design data space using correspondence between live image pixel locations and design data coordinates.

In such an example, by using the appropriate polynomial fit of the grid of the alignment site for the absolute coordinates in the design data space, any pixels in the inspection data (e.g., the live pixel stream) may be used to map to corresponding locations in the design data space The mapping function can be determined. In a similar manner, any pixel in the inspection data may be mapped to its corresponding location in the context space, as described below. Several other corrections may be used to provide a substantially accurate mapping. For example, the correction can be performed based on the stage correction data and the data provided by the inspection system, such as pixel size in the x direction, obtainable by the runtime alignment (RTA) subsystem of the inspection system . The mapping can be used in die-die inspection mode. The mapping of the live pixel stream as described above may be performed in real time during inspection of the wafer or may be performed after acquisition of inspection data for the wafer. In this way, positioning of the inspection data within the design data space can be performed during inspection of the wafer. Alternatively, the positioning of the inspection data within the design data space may be performed subsequent to inspection of the wafer.

The location of inspection data within the design data space can be stored and used in any manner described herein.

In one embodiment, the method includes detecting inspection data and defects on the wafer using a standard reference die for standard reference die based inspection. In this manner, embodiments of the method described herein may include performing a standard reference die based inspection. In some such embodiments, the method may include applying a mapping of a standard reference die image within a design data space to a live image obtained by a inspection system for a wafer in a standard reference die-die inspection mode. The term "standard reference die" refers to a reference die that, while generally being inspected, does not meet normal adjacent constraints on the "test " die obtained for the die-die inspection. Some commercially available inspection systems are configured to use some version of the standard reference die-die inspection mode. One implementation of the standard reference die-die check mode includes comparing a die to any die in the die array. In other implementations, the standard reference die image may be a stored image. Thus, the stored standard reference die-die inspection mode is similar to the standard reference die-die inspection mode, except that the constraint using the reference die on the wafer is removed. One advantage of this inspection mode is that the stored reference die image can be modified to produce a " substantially defect free "standard reference die image. This inspection mode also enables the use of standard reference die images from other wafers, thereby enabling the simplest implementation of the iPWQ application, as further described herein.

In one embodiment, which may be used in a standard reference die-die inspection mode, the live image acquired for the die being inspected is aligned with and compared to a stored die image obtained from a known good die (standard reference die) on another wafer . Such alignment and comparison can be performed as described herein. In this case, the mapping of the standard reference die pixel to the design data coordinate space can be performed completely offline. For example, an alignment site within a standard reference die may be mapped in the design data space as described above, and a mapped standard reference die pixel may be stored offline during inspection and supplied to the inspection system. In this manner, for the standard reference die-die check mode, positioning of the live inspection data within the design data coordinate space can be performed by aligning the live data to the standard reference die image or to the self-mapped data in the design space.

In another embodiment, for a standard reference die-die check, a known good die on a reference wafer is scanned in a selected pixel size and imaging mode, and the entire known good die image can be stored in a suitable storage medium (e.g., a disk) . During inspection of the wafer, the swath of the appropriate standard reference die image is downloaded to the inspection system image computer, and when each die is scanned, the frame of the target die (i.e., the die being inspected) do. Misalignment between frames can be corrected using interpolation of sub-pixels. The standard reference die image can then be compared to the image of the wafer to detect defects on the wafer (i.e., to detect defective pixels). In this manner, the same image can be used to align the inspection data to the design data space coordinates and for defect detection.

In another embodiment, the method includes aligning alignment data for an alignment site on a wafer in the inspection data stream to a rendered GDS clip for a given alignment site to correct errors in real time. For example, the method may include applying a mapping of rendered GDSII clips in a design data space to data for an alignment site on a wafer for a die-die inspection mode. The method may include correlating the live image data and the downloaded alignment site patch image over a predetermined search range (selected during setup of the inspection process). In another example, aligning the data for the alignment site on the wafer in the inspection data stream to the data for a given alignment site may include aligning the center of one or more features within the alignment site, Or by aligning other attributes.

In one embodiment, for fault locating in the die-and-die checking mode, each scanned die frame is aligned with the data for subsequent die frames in the swath. In this case, the mapping of a given alignment site to an alignment site on the wafer may not be performed off-line because the location of the data for each die in the inspection data stream is subject to a mechanical error source and other error sources of the inspection system . Thus, in this case, the method may include identifying an alignment site within each die during acquisition of inspection data (e.g., using an image computer).

In another embodiment, the defect detection can be performed in the inter-wafer inspection mode. In one such embodiment, data for an alignment site on one wafer can be aligned to data for a given alignment site, and data for an alignment site on such a wafer can be aligned to data for an alignment site on another wafer . Alternatively, the data for the alignment sites on both wafers may be aligned to the data for a given alignment site containing any of the data described herein. In this manner, after the data for the alignment sites on the wafer are aligned to the data for a given alignment site, the inspection data for the wafers can be effectively aligned with each other and can be overlapped or compared for defect detection. In some embodiments, the inter-wafer inspection mode includes using a reference die that is external to the wafer being inspected (i.e., off wafer basis). Implementations of this method include separating the currently used runtime feedback concept so that the inspection system can achieve die-to-die level overlay tolerance (e.g., 0.1 pixel) to achieve the result of proper sensitivity , Never easy.

In one such embodiment, the method includes RTA on an off-wafer reference image of the wafer being inspected. The RTA to off-wafer image is a scanning inspection technique to wafer-to-wafer inspection to detect defects on the patterned wafer from a wafer "self-referencing" approach such as die- Lt; RTI ID = 0.0 > a < / RTI > image alignment approach. For example, the RTA may include electromechanically aligning the acquired live image with the previously acquired image to obtain positioning of the sub-pixel accuracy prior to digitizing the signal generated by the one or more detectors of the inspection system have. Examples of how RTA can be performed in the embodiments described herein are described in U.S. Patent No. 7,061,625 (Hwang et al), which is incorporated herein by reference in its entirety.

One currently available approach, including comparing the wafer image to the off-wafer image, is the die-database inspection mode (NGR) used by Japan's "Nanogeometric Research ". The die-database inspection approach involves "step and repeat" image acquisition and stitching followed by a complex series of edge-based image processing, process simulation, and detection algorithm steps. However, this method can not be used to directly compare the images of other wafers. In particular, the die-to-database inspection mode compares the wafer image and the simulated reference derived from the design layout database. The simulation step of this approach must be deeply calibrated according to the specific manufacturing process used to manufacture the wafer under test. This calibration is a costly and time consuming process. The correction is particularly complicated for multi-step integrated process flows. Also, the "step and repeat" image acquisition inspection process is typically slower than the scanning based inspection process due to the practical limitations of stage inertia, stage vibration, static image acquisition, image stitching,

An alternative die-to-database check mode is a logical extension of the check mode using the "off-wafer" In this case, "database" is the rendered image generated from the design data and the process simulation as described above. Thus, a "standard reference die" generated from the inter-wafer inspection image (possibly a statistical increase that can be performed as described herein) and a "standard reference die" generated from the design data and process modeling Quot ;, the database based inspection can be regarded as a logical extension of the "off-wafer" reference inspection mode. Using standard reference dies generated from design data and process modeling is the most complex wafer inspection mode to implement. While many attempts have been made to implement such an inspection mode, the current performance of an attempted implementation is not suitable due to the computational strength (modeling and detection), image acquisition rate, and image quality challenges of such applications. However, the method described herein is more practical because the conventional absolute reference (e.g., design data) can be used for alignment of inspection data for off-wafer reference and wafer under test.

Thus, the method described herein can be used to enable comparison of wafers to each other, potentially a very useful application. One motivation for defect inspection using wafer-to-wafer comparison is to search for "systematic defect mechanisms" that can result from the interaction of the specific circuit layout with the cumulative tolerances of the wafer fabrication process. This search process may include comparing the wafers to be processed that are printed on but the same device design. The most critical approach is to modularize process parameters in single- or multi-variable experiments (eg, using a systematic DOE approach). In one embodiment, the wafer and additional wafers (e.g., two or more wafers) are processed using wafer level process parameter adjustment, which may be performed as described above or in any other suitable manner. The process parameters may be adjusted so that the measurable physical and / or electrical properties of the resulting wafer approach its acceptable limits. The method may also include detecting defects on the wafer and additional wafers by comparing inspection data for the wafers and additional wafers on the die to a standard reference standard die. Detection of defects on the wafer in this manner can be performed as described further herein. In one such embodiment, the method may include determining whether structural differences between wafers occur, as measured by detection of "defects ". Such an approach can be referred to as an integrated PWQ (iPWQ). In this manner, the method described herein can be used to enable the implementation of iPWQ (e.g., using a standard reference die approach to iPWQ). As such, the PWQ methodology can be extended to include comparison of die on other wafers with conventional standard reference dies and wafer level process parameter adjustments for the purpose of implementing the iPWQ methodology.

In contrast, the search for a lithographic induction "systematic defect mechanism" is based on a method disclosed in U.S. Patent No. 6,902,855 (Peterson et al), which is incorporated herein by reference in its entirety, as well as a method that is commercially available from KLA-Tencor It can be done using PWQ products. The PWQ affects the unique ability of the lithography tool to adjust the lithographic exposure process parameters at the reticle shot level using focus and exposure as variables to determine the design-lithographic interaction. These applications are often used for OPC verification. However, the PWQ is limited to a direct comparison of the die on the printed wafer with the adjusted focus and / or exposure parameters. The impact of other process variables associated with process steps such as etch, deposition, heat treatment, chemical-mechanical polishing (CMP), etc. can not be directly assessed because these parameters can only be adjusted at the wafer level. However, systematic fault mechanisms associated with or caused by these process variables can not be exploited using the methods described herein. In particular, the methods described herein can be used to inspect non-lithographic process adjustments in PWQ type applications by wafer-to-wafer comparison.

In a scanning-based defect detection system, die-to-die image subtraction is performed by "sub-pixel" image alignment to reduce difference image registration noise to enable better detection of defects can do. A defect can be identified by detecting a pixel in a difference image that exceeds one or more thresholds. The scanning-based image acquisition process includes a feedback mechanism, often referred to as RTA. This mechanism precisely aligns the image being acquired with the image often taken from the same wafer prior to the current image. Depending on the configuration of the inspection system, the feedback mechanism may include a combination of a photo-mechanical approach, an electromechanical approach, and an electronic / algorithm approach.

In one embodiment, the method described herein includes an RTA that uses a stored image as a reference based on images acquired for a wafer under test. The stored image may be a "standard reference wafer" or an image of a reference wafer. Each die on a wafer under test can be compared to a corresponding die on a standard reference wafer. While the embodiments described herein are described as including a comparison of images of two wafers or wafers, an embodiment may include comparing any data acquired by inspection of two or more wafers.

Figure 4 illustrates various embodiments of a computer implemented method for performing wafer-to-wafer comparisons. The steps shown in Fig. 4 are not necessary to perform the method. One or more steps may be omitted from the method shown in FIG. 4, and the method may still be practiced within the scope of the present embodiment.

As shown in step 220, the method includes wafer-wafer comparison. In one embodiment, the wafer-to-wafer comparison includes comparing the reference wafer image to a test wafer image, as shown in step 222. For example, the reference wafer image used in the method described herein may be a stored image of the entire reference wafer. A comparison of the reference wafer image and the test wafer image can be performed as described herein. Alternatively, as shown in step 224, the wafer-to-wafer comparison may include comparing the standard reference die image with the image of all the die on the wafer (e.g., a reference or test wafer).

In one embodiment, the method includes detecting a defect on a wafer using a noise representation of wafer noise associated with a standard reference die in a perturbation matrix for inspection data, a standard reference die, and a standard reference die based inspection . In this manner, the method may include using a relatively compact representation of wafer noise associated with a standard reference die in the form of a perturbation matrix. For example, the image of the reference die on the reference wafer may be stored in addition to the perturbation matrix, or other suitable data structure showing how the die pixel changes from die to die on the reference wafer. Storing the image of the reference die in addition to the perturbation matrix instead of the entire reference wafer image allows a more compact representation of the reference wafer to be stored. In this manner, the perturbation matrix may be included in the representation of the reference wafer to reduce the reference wafer image size to a level that can be implemented in a substantial and acceptable manner. As such, the method may include a standard reference die based test that includes using a perturbation matrix representation of the noise signature.

The step of generating the reference wafer image and the corresponding perturbation matrix may comprise a standard reference die based inspection using a standard reference die obtained from the reference wafer (i.e., a type of self referencing). The single standard reference die image on the reference wafer is used to detect not only the baseline image perturbed with the compressed differential data stored for each die on the reference wafer but also the baseline image perturbed during the driving to reduce any effects of RTA performance on the sensitivity. It can be used as an RTA reference. The stored difference data can be reduced through a compression algorithm as well as a constraint on the size of the total attention area per die swath. Upon actuation, the perturbation matrix of the differential image data may be loaded for the entire reference wafer into a swath for each corresponding reference standard die swath to be loaded. The perturbation matrix data volume for the entire wafer may be on the order of about 1 Gb to about 3 Gb, and the data volume for the standard reference die may be on the order of 1 Gb. All other methods described herein, including standard standard die comparison, can use the perturbation matrix as described above.

The perturbation matrix is defined as P ₁ (x, y), D _x (1, 2), D _y (1, 2) Diff _1,2 (x, y); P ₂ (x, y), D _x (2, 3), D _y (2, 3) Diff _2,3 (x, y); ... _{P m-1 (x, y} ), D x (m-1, m), D y (m-1, m) Diff m-1, m (x, y) can be defined by, where P _i a (x, y) is the position (x, y) i and the pixel value of the second _{die, D x (i, i +} 1), D y (i, i + 1) is a die (i + 1) in the (X, y) is the offset at x and y of each of the dies i for i and Diff _{i, i + 1} (x, y) is the offset at x and y for aligning it with the frame of die i. Is the difference gray level of die (i + 1) relative to die (i) at position x, y after being shifted. However, from the error in the interpolated boundary, P ₂ (x, y) is _{P 1 (x, y),} D x (1, 2), D y (1, 2) and _1,2 Diff (x, y) Can be reconstructed. In addition, P _i (x, y) can be reconfigured for any other die by applying these steps sequentially for each die. Of course, this can mix interpolation errors and a gradual blur of the image from the die to the die.

However, if a standard reference die is stored and all interpolation is performed for each die, the above-described migration error accumulation does not occur. Rather, the error is a simple interpolation error associated with reconstructing any die on the wafer from the standard reference die given the offset and differential image. Thus, as shown in step 226, the method may include preserving the differential image of each die with respect to a standard reference die.

Figure 5 illustrates an embodiment of a method for performing a wafer-to-wafer comparison using a differential image as a basis for comparison. For example, the reference wafer 250 may include a plurality of die [(0,0), (0,1), ... (4,2), one of which (e.g., die (2,2)) is designated as a standard reference die. The reference wafer 252 used for the comparison to the test wafer is the difference image [Diff (0,0), Diff (0,1) ...) for each die for the standard reference die image 254 ... Diff (4,2)]. The test wafer 256 can then be compared to the reference wafer 252. For example, as shown in Fig. 5, defect detection for test dies 1 and 3 is performed by adding a standard reference die image 254 and a corresponding difference image Diff (1,3) (1, 3) to produce a difference 258 between the reference die 1, 3 and the reference die 1, 3.

Thus, the differential image between any die (under test) and a standard reference die can be represented in a compact manner. A lossy compression algorithm may be employed to achieve a higher degree of compression. The information that can be lost by such a compression technique depends on the technology itself. For example, as shown in step 228 of FIG. 4, the method may include performing lossy compression for non-critical areas of the differential image and lossless compression for critical areas of the differential image. In this manner, "intelligent" compression techniques can be used such that less critical device areas allow greater loss than more critical areas. Similar compression techniques can be used for reference wafer images. For example, as shown in step 230, the method may include performing lossy compression for non-critical areas of the wafer image and lossless compression for critical areas of the wafer image.

Alternatively, the method may include preserving differential statistics per pixel for a standard reference die, as shown in step 232. For example, as shown in step 234, the method may include storing per-die statistics for each context type. Each die may be separated into one or more context types, which may be performed as further described herein. In one such example, the method may include recording statistics for a difference at each (x, y) position in a standard reference die for a different group of die. As shown in step 236, the context may be a die area. Alternatively, as shown in step 238, the context may be a background type. The differential statistics per pixel may be determined in any suitable manner.

In another example, the wafer may be divided into N radial sectors and / or M annular rings. For example, as shown in FIG. 6, the wafer 260 can be separated into annular rings 1, 2, and 3. Although shown as separating the wafer 260 into three annular rings, it should be understood that the wafer can be separated into any suitable number of annular rings. In addition (or alternatively), the wafer 260 can be separated into wafer sectors A, B, C, D, E, F, G and H, as shown in FIG. It should be appreciated that although the wafer 260 is shown as being divided into eight sectors, the wafer may be separated into any suitable number of sectors. The method includes storing per-pixel statistics for each wafer sector and / or annular ring, as shown in step 240 of FIG. In such an example, for each (N + M) segment, the mean and standard deviation of the difference for the standard reference die image at the (x, y) location may be recorded. The 8 bit mean and the 8 bit standard deviation include storing 2 x (N + M) bytes at each (x, y) location versus bytes per die on the wafer. In this way, if there are 100 dies on the wafer, using 8 sectors and 8 annular rings requires 100 bytes per position (x, y) of 32 bytes per (x, y) position. In a further example, the method includes preserving the wafer sector and / or annotation statistics as described above for each context type, as shown in step 242. [ The context type may be based on the die area, as shown in step 244. Alternatively, the context type may be based on a background type, as shown in step 246. Statistics per Context Type and Context Type can be determined as described herein.

Figure 8 shows how such a technique is performed when statistics are stored for each (x, y) location on a standard reference die on a per ring-ring basis. In particular, Figure 8 illustrates one embodiment of a method for performing wafer-to-wafer comparisons using differential statistics by reference annulus. 8, the reference wafer 262 includes a plurality of die [(0, 0), (0, 1) ... (4,2), one of which (e.g., die (2,2)) is designated as a standard reference die. The reference wafer 264 used for the comparison to the test wafer has an average difference in the pixel (x, y) and a difference in the pixel (x, y) for the standard reference die image 266 for each annulus And is generated by determining the standard deviation. The test wafer 268 (shown in FIG. 8, where the annulus is overlaid on the test wafer) can be compared to the reference wafer 264. For example, to produce a difference 270 between the test die 1, 3 and the standard reference die image 266, the test die 1, 3 is subtracted from the standard reference die image 266. As further shown in Fig. 8, the test dies 1, 3 are located inside annular 1 and annular 2. Thus, at step 272, the difference image 270 is compared to the statistics 274 (e.g., the mean difference +/- k x the standard deviation of the differences) at each (x, y) location in the test die on an annular basis . That is, the difference 270 for the portion of the test die located within the annulus 1 is compared to the statistics for the annulus 1 and the difference 270 for the portion of the test die located within the annulus 2 It is compared with the statistics for annulus (2).

More compact storage of standard reference dies can be realized by storing standard reference die data on a statistical basis (e.g., by dividing the die into frames and frames into different structures (binned contexts), and each frame / For example, as shown in step 248 of Figure 4, the method includes storing per die per frame per contextual statistics for a standard reference die. (0,0), (0,1) ... (M, N)] 276 may be formed on the wafer 278, as shown in FIG. 9 The die 276 can be separated into a frame 280. The die can be separated into a frame 280 and the pixels of each frame can be separated based on the context (Not shown in Fig. 10). The differential statistics for each of the different contexts of each frame can be determined as described herein.

Figure 11 illustrates a method for performing wafer-to-wafer comparisons using differential frame statistics separated by context. 11, reference wafer 282 includes a plurality of die [(0,0), (0,1) ... (4,2), one of which (e.g., die (2,2)) is designated as a standard reference die. The reference 284 used for comparison with the test wafer 286 includes a die 276 separated by a frame 280 and a standard reference die image 288. [ The frame 280 can be configured as described above. The criteria 284 may be generated by determining statistics 290 such as the mean and standard deviation of the differences for each context and each frame within each frame for each die. To detect defects on the test wafer 286, the test wafer is compared to a reference 284. For example, to detect defects in test dies 1,3, test dies 1,3 are subtracted from standard reference die image 288 to produce a difference 292 between the test die and standard reference die image . In step 294, the difference 292 includes statistics 290 for the dies 1, 3 of the reference wafer 282 (e.g., the average of the differences for each frame and context and the standard Deviation).

If the "standard reference die" is not known to be defect free, then a single adjustment can be performed using a "polishing" technique (defect detection can be performed using a single comparison with a truly defect- have). In addition, "polishing" can be performed to reflect the expected image variations across the wafer due to "inherent" or expected process variations. Thus, a standard reference die "polishing" can be performed on all dies on the reference wafer to produce a "defect free" reference wafer.

Table 1 shows the maximum die size of 40 mm x 40 mm, the smallest test pixel size of 90 nm, the number of maximum size dice on 44 wafers, the number of pixels in the maximum size die of 1.975E + 11, the frame size of 512 x 512 pixels, A maximum size of 7.535 + 0.5 frames per die, a byte to store the average difference and standard deviation of the difference of 2 bytes, a pixel per swath of a maximum size die of 0.91 G pixels, a maximum size of 217 swaths per die, and 2048 pixels Assumes a height swath and represents the approximate size of the reference data for various wafer-wafer comparisons as described above. A standard reference die, assuming a 2K height sensor, contains 197 G pixels or 0.91 G pixels per swath. In addition, a differential image for each die on the reference wafer or some compressed form thereof must be stored.

Way Data size (Gbytes) Stored differential image (no compression) 8727.8 Difference image at 0.1% of total pixels 8.7 Per pixel sector based statistics: 8 sectors 3160.5 Per pixel ring-based statistics: 8 annular rings 3160.5 Per pixel sector + ring based statistics: 8 sectors, 8 rings 6321.0 Frame-based statistics: 512 × 512 frames 0.0666 Frame + Context-based Statistics: 8 Context / Frame 0.5327

Table 1 shows that the data size for storing the differential image is much larger than the data size for storing context-based statistics and frames per die. However, storing some difference pixels (e.g., 0.1%) with the largest difference and those in the critical area reduces the data size requirement from 8727.7 gigabytes to 8.7 gigabytes.

The die on the test wafer may be scanned multiple times using a serpentine scan path to generate a plurality of swaths of inspection data. One embodiment of such a span-scan is shown in Fig. As shown in Fig. 12, the test wafer 296 has a die [(0,0), (0,1) ... (4,2)]. The test wafer 296 is scanned by the serpentine scan 298 and the serpentine scan 300. Although FIG. 12 illustrates two types of serpentine scan, it should be understood that the test wafer can be scanned using any suitable number of times. Assuming 217 swars per die and performing the same serpentine scan on all die rows, you can load the compression differentials for all dies against the standard reference die swath, swath 1, swath 2, and so on. In this case, the memory requirement for storing the reference data for the test wafer scan is (197 + 8.7) / 217 = 0.95 G pixels per swath.

One consideration in the implementation of standard reference die-die inspection is the disk input / output (I / O) rate, which may affect throughput. Disk I / O traffic can be reduced by loading each swath of a "standard reference die" at a time. Such loading can be used for serpentine scanning across the entire wafer, with a die level step (a serpentine pattern of vicinal wafer scans) between wafer scans.

Of course, in all of the inspection modes described herein, the inspection can be performed using one image stored on disk versus another image stored on disk, or an image in memory just acquired from the wafer in real time. All of the foregoing data may be stored as further described herein, and all of the storage steps described herein may be performed in any manner described herein.

As described above, the step of determining the position of the inspection data in the design data space can be performed following the inspection of the wafer. In one such embodiment, the step of determining the location of the inspection data in the design data space is performed on the portion of inspection data corresponding to the defect detected on the wafer, rather than the portion of inspection data that does not correspond to the detected data on the wafer . In this way, the mapping transformation from pixel or wafer space to design data space is applied only to the location where the defect is found. That is, the method may include a post-process mapping of the defects detected on the wafer to the design data space. Also, although alignment (e.g., alignment error measurements) may be performed after defect detection is completed in the post-processing step, the alignment sites within each die may be identified during inspection. The mapping is then applied to locate the defects in the design data space.

Regardless of when and how positioning of the inspection data in the design data space is performed, if there is more than one defect on the wafer, the inspection data includes data on defects or defects on the wafer. Thus, the location of one or more defects in the design data space can be determined from the location of the inspection data in the design data space. In addition, the location of one or more defects in the design data space may be advantageously determined to be substantially high (e.g., sub-pixel) precision equal to the location of the inspection data in the design data space.

As described further herein, in some embodiments, inspection data is acquired in swath by scanning the wafer. In such an embodiment, by arranging the alignment sites in each swath to the data for a given alignment site, each swath of the inspection data can be individually aligned in the design data space, which is performed as described above .

In another embodiment, determining the location of the inspection data comprises determining the location of the swath of the inspection data in the design data space based on the location of the alignment site in the design data space, determining the location of the swath in the design data space And determining the location of an additional swath of the inspection data in the design data space based on the location of the swath. In this manner, one swath of the inspection data can be aligned to the design data space as described above (e.g., by aligning the data for a given alignment site and the alignment site on the wafer within the swath of the inspection data ), Additional swaths of the inspection data can be aligned to such swaths of the inspection data.

For example, as shown in Figure 13, a swath (e.g., Swath # N + 1) may be aligned to a previous swath (e.g., Swath #N) using swath image alignment. Particularly, as shown in Fig. 13, swaths # N + 1 and # N partially overlap in region 41 in the wafer space. Thus, both swaths may contain inspection data for the features formed in region 41. [ As such, the inspection data for these features can be used to align one swath to another swath. In such an example, Fig. 14 shows the features 41a and 41b formed in the swath overlap region 41 in the wafer space in which the inspection data for two consecutive scans overlap. Features 41a and 41b may be used for Swath-Swarth registration. Features 41a and 41b may be further configured as described herein for other alignment features.

In this way, by arranging the data for the alignment site (s) in the daille column to the provided image from the design database or other predetermined alignment site data described herein, the first swath for the die array is aligned to the design data space , Subsequent swaths of the die row can be aligned using the techniques described herein. In particular, the position of swath # N + 1 relative to the design data space can be determined by using the location of the alignment feature in the swath and the location of Swath # N relative to the design data space. For example, the step of determining the position of swath # N + 1 may include storing an alignment feature image acquired during the swath # N acquisition scan and storing the alignment feature image in an image of the same feature acquired during acquisition of swath # N + . By determining the unaligned offset between the two alignment feature images, the absolute position of swath # N + 1 relative to the design data space can be determined.

During the setup of the inspection recipe, the wafer may be scanned with a relatively large overlap (e.g., 50% overlap) between successive swaths to determine an appropriate alignment site within the swath overlap region. These site locations can be used to determine the location of each swath for the corresponding previous swath. The position of the first swath for the design data space determined using the method described above to align the given alignment site to the alignment site on the wafer and the alignment site within the overlap area between the first and second swaths The second swath shift for the determined one can be used to determine the absolute position of the second swath for the design data space. By repeating this procedure for each subsequent swath, the pixels for the entire die can be mapped to the design data space.

An appropriate alignment site can then be selected such that there is at least one site within each inspection swath (i.e., the swath used during the inspection, which is the minimum overlap that ensures that the overlap between the swaths is fully scanned) (Using the method described above). The locations of these alignment sites in the design data space are stored in the inspection recipe along with the patch images of each alignment site. During the inspection, for each swath, the corresponding alignment site is searched from the recipe and its position is determined in the pixel stream acquired by the inspection system. Once the alignment site is located within the pixel stream, the position of the pixels within the inspection swath can be determined within the design data coordinate space using sub-pixel accuracy, also using cross-correlation or other image matching techniques. One advantage of this method is that the inspection swath can be acquired with a relatively small overlap (thus improving the speed), but the swath "stitching" used to map the pixels for the entire die to the design data coordinate space , And a set-up swath (used only for the recipe set-up) is acquired with a relatively large overlap, in order to find an appropriate alignment site in the space that occurs within each inspection swath. It should be appreciated that swath stitching techniques may be applied to other scanning patterns, such as field-wise acquisition using area sensors. The fields may be stitched together in a manner similar to that described above.

Another advantage of the above-described embodiments of each swath alignment to the design data space is that this technique requires that data for a smaller number of alignment sites be rendered from the design data. In addition, the rendering data from the design data to the alignment site can be challenged due to the complexity of the model that can be used to predict how a given feature will be printed on the wafer, particularly if the wafer has multiple layers formed thereon. Respectively. However, as described above, data for a given alignment site may be acquired in a plurality of different ways, the method being selected based on the layer being examined, Lt; / RTI >

As described above, swath stitching using "short swaths" in coverage mode can be used to align inspection data to design data. However, in some embodiments, as shown in FIG. 14A, the alignment site 302 may be located on a wafer that is spaced (e. G., Remote) from the area on the wafer that corresponds to the first inspection swath 304a have. This situation can only occur if an appropriate alignment site is separated from the area of the wafer being scanned for the first inspection swath. The position of the first inspection swath may be determined from the attention area specification (e.g., automatically defined or defined by the user). In such a situation, the method or system described herein can perform a series of "mini-scan" 306 on the wafer, and each die is as wide as shown in FIG. 14A. The swath acquired by the mini-scan is used to "stitch" the swath containing the alignment site with the first inspection swath 304a using the swath-to-edge alignment method described above. Subsequent check swaths 304b and 304c may be aligned to the first check swath 304a as further described above.

The methods and systems described herein can acquire inspection swaths for wafers in a plurality of different ways. For example, as shown in FIG. 14B, the system may acquire inspection swath 308 for a wafer in a 100% inspection mode. In particular, the system scans the wafer back and forth to obtain an operating span that can be used to check 100% of the area. In another example, as shown in FIG. 14C, the system can acquire inspection swath 310 for the wafer in standard coverage mode. In this coverage mode, the area on the wafer from which swath is obtained may be from about 25% to about 50% of the die area. The Swash shown in Figure 14c corresponds to a 50% coverage mode in which alternate Swarses are used for testing. In another example, as shown in FIG. 14D, the system may acquire scan swath 312 for the "smart scanning" mode. In this mode, about 50% of the die area is scanned, and the scanned area can be selected based on information about the design or the expected interaction between the design and the process. In addition, the system described herein may be configured to perform any of the various scanning methods described above (e.g., other scanning methods for other wafers). The method (or design analysis tool) described herein may also include using knowledge of the inspection system (e.g., scanning capacity) to determine an optimal "coverage" technique for the wafer.

In another embodiment, the method comprises the steps of aligning inspection data to design data, and converting the coordinates of additional inspection data to design data space coordinates using die corresponding design data space coordinates determined by such die alignment step . The transformation can be performed by extracting relevant information based on user input or from an appropriate design file and / or process recipe (stepper recipe). An alternative approach to determining the transformation without input from the user includes manually selecting the alignment site or aligning (e.g., overlaying) the inspection data to the design data using an algorithm overlay optimization approach . It should be noted that this is a die alignment technique. If die counter-coordinates are used (i.e., the inspection system already knows where an alignment site exists for each die), the wafer alignment technique may not be used.

The method described herein may or may not include the step of performing inspection of the wafer to obtain inspection data. That is, the method described herein can be performed by a system that does not include an optical or electronic inspection subsystem (such as that described further herein). Instead, the system may be configured as an "independent" system configured to receive inspection data from the inspection system. In this way, the independent system can obtain inspection data from the inspection system. Independent systems can acquire inspection data in any manner known in the art (e.g., via a transmission medium that may include "wired" and / or "wireless" portions). Alternatively, the method may be performed by a system comprising an inspection system. In this way, the inspection system can constitute a part of the system, and the inspection data can be acquired by the system by performing inspection of the wafers. Also, regardless of the manner in which the inspection data is acquired, the methods described herein may be performed using any type of inspection data known in the art in any of the formats known in the art. The inspection data may include data on the detected binding on the wafer. In another example, in one embodiment, the inspection data is obtained for a PWQ that is further described herein.

The methods described herein can be advantageously used to correlate the inspection space to the design data space with relatively high precision, and such correlation can be used in multiple steps as further described herein. For example, the location of the inspection data in the design data space may be advantageously used to determine whether the inspection data corresponds to a region of interest or a non-area on the wafer, and the inspection process may be performed on the area corresponding to the inspection data, . ≪ / RTI > For example, by moving the new image data relative to the inspected region so that the region of interest is substantially precisely aligned with a predetermined feature in the design or CAD database for every point over the die, An insignificant region, such as a fill region, is created to produce a substantially accurate caution region so that inspections can be performed only on critical locations on the die, such as via locations, while being ignored. These critical locations, or "areas to be inspected" may be entered into the recipe setup and performed using the results of CAD DRC, DFM analysis such as design scan and / or PWQ analysis, electrical test, FA, "Hot spot" analysis.

For example, in some embodiments, the methods described herein may provide design data and design data, such as attention areas, stored in a standard EDA layout format (e.g., GDSII, OASIS, etc.) generated from a layout analysis software tool, Into a usable format. In this manner, the method may include communicating attention area information from the design tool to the inspection system. For example, a translation module (not shown) may be configured to generate a scan protection area from a standard design format such as GDS or OASIS. Thus, the files in such a design format contain the resulting polygons from the design analysis performed by the EDA tool rather than the design. Thus, the conversion module allows efficient conversion between two spaces (i.e., design and inspection).

In another embodiment, the method further comprises the steps of determining the location of the detected defect on the wafer in the design data space based on the location of the inspection data in the design data space, which may be performed as described herein, Determining a value for one or more attributes of design data corresponding to a location of the defect using a data structure in which a predetermined value for one or more attributes of the design data is stored as a position function in the design data space. In this way, the value for the design data attribute corresponding to the defect location can be determined, for example, by determining a value for one or more attributes from a polygon in the structure (e.g., as a function of the polygonal structural drive) Can be determined from previously calculated attributes. In this manner, the design is processed to a polygonal level, and any attributes at the polygon level that can be determined can be stored in the data structure. As such, it may include a "superset" of data for the value of one or more attributes of the design data stored in the data structure. The predetermined value for one or more attributes of the design data as a function of position within the design data space may be generated using an EDA layout analysis tool or any other method or system known in the art. In this manner, the design can be preprocessed to determine one or more attribute values of the design data as a function of position across the design data space, and values for one or more attributes can be "actuated Quot; middle "data structure to determine the basis of the defect. The data structure in which a predetermined value is stored as a function of the design data space location may comprise any suitable data structure known in the art. In a similar manner, the data structure may include one or more attributes of the design layout for the design, one or more attributes of the plan of the design, one or more attributes of the cells in the design, any other information about the design, As a function of position in the design data space.

In one embodiment, the method may include determining a degree of sensitivity to detect defects on other portions of the wafer, as shown in step 18 of FIG. In one such embodiment, the method includes determining a degree of sensitivity to detect defects on other portions of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space do. In one such embodiment, the method may include performing design-based inspection by conveying attention area information from a design tool to an inspection system. For example, attention area information can be used to identify the different regions on the wafer and the sensitivity used to detect defects in that other region. As such, one or more attributes of the design data may include attention area information. However, one or more attributes of the design data may also (or alternatively) include any attributes of the design data described herein.

The data preparation step may include generating or acquiring data for one or more attributes of the design data. One or more attributes of the design data used to determine the degree of sensitivity to detect defects on other parts of the wafer may include process or yield information associated with the design data. For example, in one embodiment, one or more attributes of the design data may be associated with the design data, other design data, or some combination thereof, for the process layer from which the inspection data for the wafer is obtained, Is selected based on one or more attributes of inspection data previously acquired for a wafer, another wafer, or some combination thereof. In this manner, one or more attributes of the design data in the design data space used to determine the degree of sensitivity to detect defects on other parts of the wafer may be the same or different on the same or different designs on the same or different process layers, Lt; / RTI > and the attributes of the previously collected inspection data from < RTI ID = 0.0 > a < / RTI > The previously collected inspection data may be stored in a data structure such as a fab database or any other suitable database, file, or the like, or may be included in a knowledge base that may be configured as described herein. In this manner, in the present embodiment, one or more attributes of the design data may be selected based on a training set of cumulative learning, historical data or data.

In another embodiment, one or more attributes of the design data are selected based on a yield threshold of a previously detected defect at another site, an error probability of a previously detected defect at that site, or some combination thereof. In this manner, the sensitivity to detect defects may be based, at least in part, on one or more attributes of the design data selected based on yield thresholds and / or error probabilities of defects detected at other sites. Process or yield critical information may include, for example, a critical defect determined by the PWQ, a location of the interesting defect (DOI) based on the hot spot (e.g., determined from the inspection), hot spot information determined from the logic bitmap, The KP value determined from the test results for any other process or yield information described herein, or some combination thereof. The KP value can be determined as described further herein. In addition, the error probability can be determined in a manner similar to that described herein to determine the KP value for the defect. The yield threshold can be determined in a manner similar to that described further herein to determine the yield relevance of the defect.

Data for one or more attributes of the design data may include one or more attributes (e. G., Contact or dummy fill area, information of a "place to inspect" Quot; context "data that defines a structural area in a device design that has different values of the type of feature within the area, such as < RTI ID = The term context data is used interchangeably herein with the terms "context information" and "context map ". Context information may be obtained from a variety of sources including simulation, modeling, and / or analysis software products available from KLA-Tencor Corporation, other software such as DRC software, or some combination thereof. In addition, additional context data may be determined and combined with data on the attributes of the design data. Data structures, such as databases or files, including design data and / or context data, may have any suitable format known in the art.

The step of determining the degree of sensitivity as described above can be performed so that a defect detected at another part of the wafer corresponding to the design data having different values of one or more attributes of the design data is detected at different senses. In this manner, the method may also include determining, identifying, and / or selecting other portions based on values of one or more design data attributes as a function of design data space location. The dimensions of all or some of the other portions may be different and the value of the attribute of the design data may vary depending on the resolution at which it is available or acquired. For example, if a context map is used to determine the degree of sensitivity for another region, as described further herein, the dimensions of the other region may vary depending on the resolution of the context map.

In such an embodiment, the degree of sensitivity is determined based on the location of the inspection data in the context map and design data space, and as described further herein, the value for one or more attributes of the design data over the design data space . For example, the method may include using a context map to define a relatively high sensitivity area within the die on the wafer for the variable sensitivity area and the critical area based on the threshold of the context. In one example, segments of the design data may be defined to isolate dense arrays and logic, open regions, and grainy metal. A combination of image gray level and context may also be used to define one or more segments in the design data. For example, pixels with intermediate gray levels can be combined into one segment. The image gray level may be determined using an image acquired by the inspection system or another image acquisition system or a simulated image.

In some embodiments, determining the degree of sensitivity to detect defects on other portions of the wafer based on the context map and the location of the inspection data within the design data space may be performed by the inspection system during inspection of the wafer. For example, the context map may be used by an inspection system as described herein when inspecting the wafer. In another embodiment, the step of determining the degree of sensitivity to detect defects on other parts of the wafer based on the location of the inspection data in the context map and design data space is performed by the inspection system after the acquisition of the inspection data for the wafer is complete . For example, the context map may be used by the inspection system as described above after the inspection data becomes available offline. In both of these embodiments, the method may use a context map to automatically define a dummy area (non-inspection area) of the die on the wafer and to define a coarse area of the die where different sensitivity thresholds are used. For example, a context map (e.g., a context map that defines a dummy fill area) may be used to automatically define non-attention areas that do not require inspection, and thus are excluded from defect detection purposes. Such areas are typically less controlled and thus produce a relatively large amount of noise (as compared to die-die). Therefore, exclusion of such a region can increase the overall S / N of the inspection.

In one embodiment, the step of determining the degree of sensitivity to detect defects on other parts of the wafer based on the location of the inspection data in the context map and the design data space may include comparing the inspection data with the inspection data to detect defects on other parts of the wafer And the step of determining a threshold value for use together. In this way, one or more thresholds used for defect detection may be changed to change from the area-area, which is similar to the segmented automatic threshold (SAT) method. For example, low threshold (high sensitivity) detection can be used for critical areas, and high threshold (low sensitivity) detection can be used for non-critical areas. Based on one or more attributes of the design data, the overall sensitivity of the inspection process can be increased by segmenting the design data and changing the threshold used for defect detection. Thus, the methods and systems described herein provide improved defect detection.

The method may also include using the context map described above to perform a plurality of different steps. For example, a context map (whether a die-die check mode for defect detection, a standard reference die-die check mode or the like is used) may include determining the sensitivity, filtering the Newson defect, Steps to create a review sample, or steps to create a review sample for online or offline review, and are not limited to such steps. (E. G., Scanning a wafer) other inspection data or image pixels acquired during the inspection process to use the design or context information as further described herein is within a design data space (e. G., Design database coordinates) Lt; / RTI > Mapping the inspection data to the design data within half of the inspection pixel size may include substantially correct settings of the inspection threshold (substantially accurate separation of the critical area from unimportant areas), filtering of the Newson defect from the actual defect, , And may be performed as further described herein.

In addition, relatively high bandwidth, pixel-level context information, can be used for substantially very accurate mapping of inspection space to design space coordinates for a wide range of applications. For example, a relatively high resolution context map may be used to automatically define a pixel-level region that can be examined for different senses. A relatively high resolution context as described herein is relatively coarse (about 50 탆 x 50 탆) inaccurate due to ambiguity (e.g., about 5 탆 or greater spread) ). ≪ / RTI >

In one embodiment, the context map may be used at the pixel level to control the detection sensitivity at each pixel. However, a simpler approach (from a system complexity perspective) uses the context map only for post-processing of detected defects using a detection method that does not detect defects using context information. In this way, the inspection into the design data space or the mapping of the wafer space can be applied only to the inspection data corresponding to the detected defects. The location of the defects is determined within the design data space, as described above for die-to-die and standard reference die-die inspection. Thus, a patch image of the design data at the location of the defect in the design data space can be obtained, and this patch image can be used to determine the design context corresponding to the defect. Alternatively, the context map aligned to the design data can be used to determine the design data context corresponding to the defect based on the location of the defect in the design data space.

In the standard reference die-die inspection, determining the context of each pixel in the inspection data may comprise determining the context of each standard reference die pixel. Since the standard reference die image is acquired during the recipe set up step, the method comprises the steps of aligning the data for an alignment site (selected as described above) in a standard reference die image to data for a given alignment site, And performing a mapping transformation to determine the location of each standard reference die pixel within the pixel. These steps can be performed during the recipe setup step. The standard reference die may also be mapped to the context data based on a mapping of standard reference dies to the design data space, standard reference die pixels are stored offline along with the context corresponding to each pixel, Or may be acquired by it. This process can be performed off-line and only once during the recipe setup phase.

In such an embodiment, each standard reference die pixel may be associated (tagged) with the context information. In this manner, the context information may be "added" to a standard reference die pixel. In one example, if there are sixteen different possible contexts, a four bit tag may be added to each pixel. Alternatively, the context data may be compressed using an appropriate compression algorithm or method, or the context data may be represented in the form of a polygon. In this manner, during the inspection, the mapped (transformed) context data associated with the standard reference die pixel data and the standard reference die pixel data may be provided to or obtained by the image computer or other process of the inspection system. Thus, the context corresponding to the inspection data pixel can be determined based on the context information of the corresponding pixel in the standard reference die image. As such, the context information corresponding to the inspection data pixel may be available for defect detection and classification (and / or binning) applications, which may be performed as further described herein.

In another embodiment, the method may use a context map at any resolution to aid in wafer inspection. For example, a wafer variable resolution context map can be used to assist in wafer inspection and binning of defects. The resolution of the context map may vary depending on the accuracy with which the live pixel stream can be aligned with the design data and the accuracy requirements of the application. Context maps at different resolutions can be represented in a number of different ways. For example, an absolute representation of the context map in the form of a polygon (i.e., multiple decimal places of a micron) at an appropriate pixel size may be assigned to the inspection system to produce a pixel level context map. Also (or alternatively), the coarse context map may include a context for a relatively coarse area having a side dimension of, for example, about 1 mu m x about 1 mu m. The coarse area may be in the form of a "tile" that separates the design data. Context data such as feature types (e.g., dummy features, contacts, line ends), feature attributes (e.g., minimum line width / space between structures, etc.), or some combination thereof may be associated with each tile.

In one embodiment, the method generates a relatively high resolution context map using attribute information and locations for designs that can be obtained from any software program that can be used to analyze possible design rule violations and designs for critical areas . Such a context map may include some attributes (or labels) of each location that can be converted from commercially available analysis software (e.g., design scan) from KLA-Tencor or a format for use by inspection, And other software such as DRC software that generates a list of locations.

In another embodiment, the method includes extracting a feature vector from a CAD layout and using non-administrative clustering to define an equivalent context group, to produce a coarse context map with a relatively low resolution. For example, a method for generating a relatively coarse context map (e.g., about 1 micron by about 1 micron) may include processing a CAD layout file, rendering or analyzing tiles, And extracting the extracted data. For each region, multiple features may be extracted from a predefined feature set. The value of each feature is its feature vector. The feature vectors for each region can be combined into a set of feature vectors that can be used to evaluate clustering within the feature space to determine similarity of regions. These feature vectors (one or more vectors per tile) can be used in the feature space using any of the non-supervisory clustering algorithms and / or methods known in the art that can be used to find clusters of vectors (i.e. tiles with similar properties) Can be clustered. Examples of such algorithms and methods that can be used in the methods described herein are disclosed in U.S. Patent No. 6,104,835 (Han), which is incorporated herein by reference in its entirety. Each such cluster may be assigned a unique context or identity. The map of the die in which each tile is represented by this code or identity can be used by an inspection system as further described herein.

In another embodiment, the method may include rendering the CAD layout patch image and cross-correlating the CAD layout patch image to identify an equivalent context group (which may be used for binning as further described herein) And generating a coarse context map with a relatively low resolution. Another way to create a context map (e.g., a relatively tough context map) is to render the CAD layout file into a patch image, separate the design data into patch images, identify image cross-correlations between patch images, Allowing the patch images having a high cross-correlation to be binned into a group of patch images corresponding to the same text type.

In some embodiments, the context data used in the methods used herein may include context data for one or more layers that may be present or formed on the wafer. For example, some defects may not be located in critical areas within the layer where defects are detected. However, if a defect is located in an area on the wafer where critical areas within the overlying layer can be formed on the wafer, such non-critical defects can become significant. The context map used in any of the steps described herein may be a context map for multiple layers on a wafer.

In another embodiment, the method further comprises detecting the presence of inspection data in the design data space, one or more attributes of design data in the design data space, and defects on other portions of the wafer based on at least one attribute of the inspection data May also include determining a degree of freedom. The attributes of the design data used in this step may include any of the attributes described herein. In such an embodiment, where a defect is detected at another site, one or more attributes of the inspection data include one or more image noise attributes or some combination thereof. In this manner, one or more attributes of the inspection data used in the present embodiment may include image noise attributes and / or detection or non-detection of defects in other areas of the inspection data. The attributes of the inspection data used in this step may include any other attributes of the inspection data described herein. In this embodiment, the step of determining the degree of sensitivity may be performed for PBMT setup for the inspection process based on the image noise correlated to the design data. The step of determining the degree of sensitivity in this embodiment may be performed as described further herein.

In another embodiment, the method further comprises the step of providing at least one attribute of the schematic data for the design of the device being fabricated on the wafer, one or more attributes of the expected electrical behavior of the physical layout for the device, And modifying one or more parameters for detecting defects on the wafer based on the at least one parameter. In this manner, another electrical description of the expected behavior of the design outline data attribute and other physical design (layout) can be used to change one or more parameters for detecting the defect or any other parameter of the inspection process have. For example, such other information regarding the critical path and non-critical path, the active and non-active structures, and the expected electrical behavior or approximate data of the physical design (layout) may change the sensitivity to detect defects, (E.g., the attention area and the non-attention area), determine which part of the inspection data to use to detect the defect (for example, determine whether to use the mutual information from the wafer space for the design data space Association), can be used to change one or more other parameters of the inspection process.

In another example, data capture rate and electrical behavior monitoring may be performed based on the design / image context. For example, the electrical behavior can be monitored by performing electrical tests, FA, or any other test or analysis known in the art, or using such test or analysis results. The results of electrical tests, FAs, or other tests or analyzes can be correlated to the contextual information regarding the schematic data and the physical layout of the device. The monitored defect capture rate and electrical behavior can be correlated to the design / image context to determine information about detection defects on the wafer, information about the inspection process used to detect defects, and information about the design have. For example, the defect capture rate and electrical behavior monitoring results may indicate which type of defect is detected on the wafer, which defects should be detected (e.g., in an online inspection process), but which defects are not detected, Lt; / RTI > Such information may be used to alter the inspection process as further described herein.

In a further embodiment, the method includes modifying one or more parameters for detecting data on the wafer using inspection data based on one or more parameters of an electrical test process performed on the wafer. For example, one or more parameters for detecting defects on the wafer or any other parameters of the inspection process may be changed based on electrical test provisions associated with the corresponding (physical) design data space. In this manner, the inspection process can change based on how the electrical test is performed. In such an example, the area on the wafer to be analyzed by the electrical test process may be determined based on one or more parameters of the electrical test process, and one or more parameters for detecting defects or any other parameter of the inspection process The defect in the area on the wafer that is not to be analyzed in the electrical test process can be changed so that it can be inspected with appropriate detection.

In addition, one or more parameters of the electrical test process and the location of defects in the design data space or wafer space may be used to identify defects that will not be tested by the electrical test process (or "electrical test exclusion"). In such an example, the area on the wafer and the location of defects on the wafer to be tested in the electrical test process can be used to determine which defect to test by the electrical test process. In another example, the locations in the design and the defects within the design data space to be tested in the electrical test process can be used to determine which defects are not to be detected by the electrical test process. In a similar manner, one or more parameters of the electrical test process and the location of defects in the design data space or wafer space may be used to isolate or bin the defects into different groups depending on whether the defects are to be tested by the electrical testing process or not .

In the wafer space, information about the hot spot (e.g., information from the hot spot database) and attributes of the design data can be used to set up the inspection recipe in the monitoring step. For example, the attention area can be automatically defined in the wafer space in the monitoring step. Automatically defined areas may include macro and micro protection areas. Automatically defined protection zones may also include non-protection zones. In addition, inspection recipes can be used to automatically change the sensitivity, filter out Newson's defects, enhance the capture of known systematic defects (e.g., enhance sensitivity to hot spots or hot spot areas) Lt; RTI ID = 0.0 > defective < / RTI > In addition, the information about the hot spot and the attributes of the design data include setting up the inspection recipes into a better group and design data based binning using GDS (i.e., GDS pattern grouping) and / or GDS pattern grouping pareto And can be used for defect defects and sample defect classification or binning.

In a further embodiment, the method may comprise periodically varying one or more parameters of the inspection process performed by the inspection system based on the results of one or more of the steps of the method using feedback control techniques. In another embodiment, the method may include automatically changing one or more parameters of the inspection process performed by the inspection system based on the results of one or more of the steps of the method using feedback control techniques. The monitoring step may also include automatic process control (APC) for the inspection process, including changing the inspection recipe or parameters based on previous measurements in combination with previous knowledge of process area differences. The APC for the metering process may be performed based on systematic defects that may be identified in accordance with any of the embodiments described herein, in addition to the measurements to be performed in subsequent metrics, to determine where the measurements are to be performed. The APC for the test process can be performed based on systematic defects that can be identified in accordance with any of the embodiments described herein to determine the electrical parameters to be tested in the subsequent electrical test and the location where the test is to be performed .

In a further embodiment, the method includes generating a knowledge base using the results of one or more of the steps of the method, and generating an inspection process performed by the inspection system using the knowledge base. A knowledge base may be created by storing one or more attributes of one or more image attributes and / or design data in an appropriate data structure. The knowledge base may also include cumulative learning acquired by an inspection system that may be used to generate the inspection process. For example, in the inspection process, the knowledge base can be used to determine the cumulative result of the test, such as the frequency of defect detection and the percentage of detection defects that are Newson's defects, Can be used to determine information.

Such a knowledge base can be used to create an inspection process as further described herein. In this way, the knowledge base can be used to create a new inspection recipe. The knowledge base can also be used to create an inspection process for recipe setup and / or wafer-less recipe setup. Creating the inspection process may include selecting any one or more parameters of the inspection process. The knowledge base can also be used to change the inspection process by recipe optimization and automatic recipe optimization. For example, the method may include using a feedback mechanism for training a knowledge base for periodic or automatic optimization of one or more parameters of an existing inspection process. Modifying the inspection process may include modifying any one or more parameters of the inspection process.

In another embodiment, the method includes optimizing the wafer inspection process to determine printability of reticle defects on the wafer using the location of the inspection data within the design data space and the context map. In this manner, the method may include optimizing the wafer inspection process for the purpose of determining printability of defects detected on the reticle using the CBI in combination with a context map. Optimizing the wafer inspection process may include modifying any one or more of the parameters of the wafer inspection process, which may include any of the parameters of any of the wafer inspection processes described herein. Generally, the step of determining printability of a reticle defect on the wafer can include inspecting the wafer to detect defects on the wafer that may correspond to defects on the reticle. In this manner, optimizing the wafer inspection process to determine printability of the reticle defects may include optimizing the wafer inspection process to determine defects on the wafer that may correspond to defects on the reticle.

In one example, the method may include determining the position of the inspection data acquired for the wafer in the design data space, which may be determined as described herein, to identify the location of the inspection data that may be used to determine the printability of the reticle defect , And using the location of one or more reticle defects in the design data space. In this manner, the inspection data acquired for the wafer and the design data space location of the reticle defects can be used to determine the portion of inspection data that can be used to detect defects on the wafer that may correspond to reticle defects. Any attribute of the design data contained in the context map may be used to select one or more parameters of the wafer inspection process to determine printability of the reticle defects. For example, the context map may be used to determine one or more attributes of the design data corresponding to portions of the inspection data identified as described above. In this manner, one or more parameters of the wafer inspection process used for other parts of the inspection data identified as described above may be selected based on at least one attribute of the design data corresponding to that other area. As such, other portions of the inspection data identified above, corresponding to design data having different values of one or more attributes, may be processed by one or more other parameters to detect wafer defects that may correspond to reticle defects can do. In such an example, the text map may be used to determine a threshold of design data corresponding to another portion of the inspection data acquired for the identified wafer, as described above, Can be used to determine the degree of hazard. In such a particular example, other parameters of the wafer inspection process may be selected for different portions of the inspection data, such that the printability of one or more reticle defects may be higher in the critical areas of the design data than in the non-critical areas of the design data . ≪ / RTI >

One or more parameters of the wafer inspection process may be altered and / or optimized based on the location of the inspection data within the design data space, the context map, and any other information described herein. For example, one or more attributes of another portion of design data for which one or more reticle defects are detected may be determined using a context map, and wafer inspection for other portions of inspection data corresponding to other portions of the design data for which reticle defects are detected In order to select a process parameter, one or more design data attributes of the other region may be used in combination with one or more attributes of the reticle inspection data (e.g., attributes of one or more reticle defects). In such an example, one or more parameters of the wafer inspection process may be such that the printability of other types of reticle defects located at the site of the design data having substantially the same properties can be determined by one or more other parameters of the wafer inspection process You can choose. In another example, one or more parameters of the wafer inspection process may be selected such that the printability of a reticle defect of the same type located at a site having different values of the property can be determined by one or more other parameters of the wafer inspection process.

The context map used in the embodiment as described above to optimize the wafer inspection process to determine the printability of the reticle defects may be configured as described herein and may include any context map described herein . In addition, any information contained in the context map may be used in the embodiments described above to change one or more parameters of the wafer inspection process.

In some embodiments, the method includes modifying one or more parameters of an electrical test process performed on the wafer based on defects detected on the wafer using the inspection data. For example, in a test space, the monitoring step may include using identified systematic defects in accordance with any of the embodiments described herein to define or modify test patterns and / or other test parameters. In addition, the defects detected on the wafer using the inspection data are determined to not be tested by the electrical test process (or "electrical test avoidance") and one or more defects are tested by the electrical test process May be used to modify one or more parameters that define the area on the wafer on which the process is performed. In this manner, the results of the inspection process can be fed into the electrical test process to reduce a plurality of defects that have not been tested in the electrical test process. In addition, one or more parameters of the electrical testing process may be determined using the inspection data, such as the defects detected on the wafer, the location of the defects in the design data space or wafer space that can be determined as described herein, One or more attributes of the design data that may include one or more attributes of a defect that may include any attribute of a defect described herein, any design data attribute described herein, determined in any manner described herein, Any other information described herein, or some combination thereof. For example, the location of the joint, the nature of the defect, and the attributes of the design data can be used to determine the error probability value for one or more defects described herein. If a defect that is not to be tested by an existing electrical test process has a relatively low error probability value, then one or more parameters of the electrical test process may not be changed by the method. In contrast, if a defect that is not to be tested by an existing electrical test process has a relatively high error probability value, one or more parameters of the electrical test process may be modified by the electrical test process so that a defect having a relatively high error probability value is tested by the electrical test process . In a similar manner, one or more parameters of the metrology process, such as sampling of the metrology process, may be selected, determined, or changed as described above.

Alignment of the inspection data to the design data enables inspection of "hot spots" on the wafer. A "hot spot" may be generally defined as a location in the design data printed on the wafer where there may be a killer defect. In contrast, a "cold spot" can be generally defined as a position in the design data printed on a wafer on which Newson's defect may be present. An example of Newson's defect is a variation in the critical dimension (CD) of the feature that does not substantially affect the yield of the device formed on the wafer, but which causes the inspection system to indicate that there is a defect at that location. Some defects may be killer defects only under certain circumstances, such as when the defects are contacted by device structures formed in different layers of the wafer. Thus, the location at which such defects may be present in the design data printed on the wafer may be generally referred to as a "coordinating hot spot ".

In a further embodiment, as shown in step 20 of Figure 1, the method includes determining if the defect detected on the wafer is a Newson defect. Whether or not the defect is a Newson defect is determined based on the position of the inspection data in the design data space and one or more attributes of the design data. For example, in some embodiments, the method includes determining a location of a defect in a design data space based on a location of inspection data in a design data space, determining a location of a defect in the design data space, And determining whether the defect is a Newson defect based on the above attribute. One or more attributes of the design data used to identify the Newson defect at this stage may include any of the attributes described herein. For example, one or more attributes of the design data may be defined in the context map. In this manner, the method may include, without limitation, applying a context map to the defect data to filter out faults (e.g., Newson defect) that are deemed unimportant in an application such as, for example, a PWQ. As such, portions of the tongue close to the limits of the capacity of the manufacturing process are separated into critical and non-critical portions based on the context. In another example, the attributes of the design data used to identify Newson's defects at this stage include hotspot information for the design data. In this manner, the location of the defects and the hotspot information in the design data space can be used to identify the defects detected in the coldspots in the design data as Newsonian defects.

The PWQ application for lithography can be used to expose dies on a wafer at different exposure amounts and focus offsets (i.e., adjusted dose and focus), determine systematic defects in the die that can be used to determine the design vulnerability area, And < / RTI > An example of a PWQ application for lithography is disclosed in commonly assigned U.S. Patent Application Serial No. 11 / 005,658 (filed December 7, 2004; Wu et al.), Which is incorporated herein by reference in its entirety . Several artifacts of focus and exposure adjustments may appear as defects (die-standard reference die differential), but are actually Newson's defects. Examples of such artificial elements may include CD variation and line-end pullback or shortening of the area where such artificial elements have no or less effect on the yield or performance of the apparatus. However, the location of the defects can be determined substantially precisely for the design layout using the methods described herein. In addition, the method described herein can be used to determine the protection area with relatively high accuracy as described above. The "micro" protection zone can be focused on a known hot spot and can be inspected with a relatively high sensitivity, or focused on a cold-spot (systemic news) known as a non-attention zone or a relatively low detection zone.

Thus, as described above, the method may include determining whether the defect is a Newson defect based on the location of the defect for the design data space and whether the location is within the area of interest. Defects may be filtered according to context, size, redundancy, PWQ "rules ", or some combination thereof. For example, in process space, PWQ analysis and DOE analysis can be performed using hot spots in the monitoring phase. In addition, the method described herein can be used to extend the PWQ application below the 65 nm design rule, where the currently used noise filter is faulty due to the limited resolution. Thus, one advantage of the method described herein is that the method can be used to extend the BF test to detect systematic defects and DFM defects. In particular, as described herein, CBI can enable additional functionality for BF inspection systems such as systematic defect inspection and / or DFM applications below 65 nm design rules. The method may provide or support a relatively quick determination of the root cause of a DFM systematic defect. The determination of the root cause can be performed as described further herein.

In another embodiment, as shown in step 22, the method may be based on one or more attributes of the design data in the design data space (which may be defined in the context map, as described above) And determining whether a defect that is not determined as a Newson defect is a systematic or random defect. ≪ RTI ID = 0.0 > [0033] < / RTI > Also, any defects that are not of interest may not be Newson's defects. For example, a systematic defect with relatively low or no effect on yield may be a Newson defect, but not a defect of interest. Such defects can appear on the active pattern or in the device region of the wafer. The method described herein may include identifying such defects. Such a defect, or a defect located in a cold spot, can be used to determine a design context (e.g., redundant via), modeling (e.g., design scan), PWQ, inspection and review, A relatively high stacking defect density at the location of the substrate). Further, monitoring of these defects can be performed by comparing the positions of the defects with the positions of the hot spots and the cold spots. If the patterns in which these defects are located are common, they can be binned separately from other systematic defects using the design data based grouping method described herein. In addition, the search for systematic faults can be performed by correlating multiple input sources from the design, modeled results, test results, metrology results, and test and FA results.

Systematic DOIs can include all pattern-dependent defect types. Identifying systematic defects is advantageous because the effect that defects can have on the device can be analyzed. The random DOI may contain statistical samples of random defects of an important type. It is advantageous to analyze random defects because it is possible to analyze the important types of random defects and determine the impact that defects have on the device. Further, by analyzing the random defects, one or more inspection process parameters can be modified to suppress the detection of random defects that can be considered as Newson defects. In addition, inspection process parameters can be modified to distinguish Newson defects from systemic causes (cold spots).

The determination of whether the defect is a Newson defect, a systematic defect, or a random defect is advantageous because the yield can be more accurately predicted based on the type of defect detected on the wafer and the relation to the yields of other types of defect. Also, possibly in combination with yield prediction, the results of the methods described herein can be used to make one or more decisions regarding design data and manufacturing processes. For example, the results of the method described herein can be used to demonstrate the IC design. In another example, the results of the method described herein may be fed back to the IC design process so that the IC design generated by the process may be less systematic and / or less systematic. In such an example, the results of the methods described herein may be used to modify the design and / or optical rules used in the IC design process. In another example, the methods described herein can be used to modify one or more parameters of a process used to fabricate the wafer level being inspected. Preferably, one or more parameters of the process, such as fewer systematic defects and / or fewer types of systematic defects, and possibly less important random defects and / or fewer types of critical random defects are caused by the process Is changed.

In some embodiments, as shown in step 24, the method includes classifying one or more defects based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. For example, the location of defects in the design data space can be determined from the location of the inspection data in the design data space. In addition, one or more attributes of the design data associated with the location of the defects in the design data space may be determined from the context map or in any other manner described herein, and one or more attributes associated with the location of the defects may be used to classify the defects have. In another embodiment, the method includes the location of a portion of inspection data corresponding to a defect in the design data space and a value for one or more properties of the design data over the design data space, as further described herein And classifying defects detected at other portions of the wafer based on the context map that can be detected. In this way, the method can use a context map to classify defects by context. Classifying defects at this stage may be performed in any of the other ways described herein.

In such an example, the defect classification is performed by the inspection system during inspection of the wafer. For example, the context map may be used by the inspection system to classify defects as described herein during wafer inspection. In such another embodiment, the defect classification is performed after the inspection data acquisition for the wafer is completed. For example, after the inspection data is available offline, the context map may be used by the inspection system to classify the defects, as described herein below. In this manner, the method may be used to classify defects either online (e.g., using the inspection system) or offline (e.g., using the SEM review station) at HRDC in a second pass high resolution defect classification (HRDC) Context maps may be used. Typically, the second pass fault classification includes re-detection and classification of defects, whether performed online by the inspection system or offline in the review system (optical or SEM). Both re-detection and classification can be performed manually or automatically by the user (i.e., automatic defect classification (ADC)). As design rules shrink, the likelihood of identifying an erroneous object as a defect in the review process increases. The design data and context map may be useful both in re-detection and classification.

In redetection, the context map provides local background information about a defect that allows the user or system to locate the corrected defect in the field of view of the review system. For example, the local image of the wafer generated by the review system can be aligned to the design data, thereby allowing the location of defects in the design data space to be substantially accurately identified in the aligned local image. Further, the simulated image of the design data (e.g., a grayscale image) can be used by the review system for alignment with the local image, and the location of the defect in the design data space can be used to determine the location of the defect in the local image . Such simulated images can be used for fine alignment and redetection of defects in the review process. An example of such a simulation is disclosed in U.S. Patent No. 6,581,193 (McGhee et al.), Which is incorporated herein by reference as if fully set forth herein. The methods disclosed herein may include any step of the method disclosed in such patent documents. Thus, the methods and systems disclosed herein can be used to perform defect detection with relatively high accuracy.

In classification, the context map may provide additional information (along with data obtained by review) that may be used to determine the class to which the defect belongs. Reviews can also be performed using context maps, data obtained by reviews, and inspection data. For example, the patch image acquired by the time delay integration (TDI) camera of the inspection system, and / or the patch image acquired by the inspection system, may be sent to the review along with the defect sample. The patch image can be used in combination with a context map for optical or SEM review and classification. In this manner, the coordinate accuracy at which a defect location can be determined as described above allows the system to classify the defect substantially accurately based on the design context and / or the DRC error code.

The one or more steps described above may be performed in a monitoring step in which systematic defects are identified and sorted (or binned) using test results and any other result described herein. The monitoring step may include deviation monitoring and baseline enhancement. The monitoring step can be performed during product ramp and manufacturing. The step of identifying and classifying systematic defects detected by inspection, in multiple source spaces (which may include a correlation between design, wafer, reticle, test, and any of the process spaces) May be used. In addition, one or more multiple source space steps may be used to demonstrate systematic fault identification in any combination thereof.

In addition, the location of defects in the design data space can be used in conjunction with inspection data, design data, or classification data to identify systematic defects (e.g., defects located in hot spots or cold spots) at the monitoring stage. The identified hotspot may also be used to determine the design context for a test result in which there is a " hit "at the hotspot location, which may be an on-tool in the post- - Can be performed with tools. The yield (or KP value) associated with the design data space can be used as an attribute to monitor systematic faults. In addition, one or more defect attributes may be used to estimate associations to hot spots if there are multiple hot spot candidates.

In reticle space, the monitoring step may include generating information about a hot spot (e.g., generating a hot spot list) that can be compared to a defect result to isolate known systematic defects from random defects. In addition, one or more hotspot attributes, such as context information for hotspots, may be used to determine whether a hotspot can be shared across a plurality of technologies, layers, devices, and in which case, what technology, layer, or device . In addition, systematic defects identified by inspection can be used to define or modify one or more parameters of the metrology process, such as metrology site locations, measurements, or other parameters.

In some embodiments, the method includes determining an error probability value for one or more defects detected on the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space . The method may also include determining an error probability attribute value of a defect detected on another location of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space . As further described herein, the error probability value for the defect can be determined based on the design data space location of the inspection data corresponding to the defect and one or more attributes of the design data in the design data space.

In another embodiment, the method includes determining position coordinates of defects detected on a wafer in a design data space based on the location of inspection data in the design data space, determining the position coordinates of the defects based on a top view of the design data To the design cell coordinates. In one such embodiment, the method includes determining an alternate area around the defect using an overlay tolerance, and using the area to perform a defective repeater analysis for one or more cell types, Determining if the type is systematically a defective cell type and systematically determining one or more locations of one or more systematically defective structures within the defective cell type. In this manner, the method may include using cell-based coordinates for repeater analysis. In particular, defect repeater analysis is performed for each cell type (e.g., a two-dimensional region around each defect) using an overlay tolerance to determine the presence of a systematic defective cell type and the presence of a systematically defective structure The position can be determined. The method may also include cell-based binning of defects based on cell context. Such binning may be performed as further described herein. In one such embodiment, the method may be based on systematically determining one or more properties, structures, or some combination of design data for cells located close to a defective cell type, and systematically locating systematic defects in the defective cell type And if so, whether it occurs. In this way, the design context (peripheral cell or structure) of a spatially organized defective cell can be used as an attribute to further specify the appearance of spatially organized defects.

In another embodiment, as shown in step 26, the method may include determining a defect (e.g., all or part of a defect) based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space Group into a group. For example, the location of defects in the design data space can be determined from the location of the inspection data within the design space as described herein. One or more attributes of the design data used to bin the defect can be determined based on the location of the defect in the design data space. One or more attributes of the design data used in this embodiment may be combined with design data (e.g., yield impact) in combination with other inspection results (e.g., integrated defect organizer (iDO) results and integrated automatic defect classification (iADC) Value of the design data described herein. In addition, one or more attributes of the design data associated with the location of the defects in the design data may be determined from the context map. In this manner, the method may include applying a context map to a detected defect during wafer inspection to classify the defect into a context.

Thus, the method described herein may include context-based background binning for wafer inspection. For example, as described above, the method may use a context map to bin a defect by context. In such an example, defects remaining after Newson's filtering may be classified by context or other information described herein to identify defects that are systematic defects rather than random defects. The context may be used in conjunction with other image-guiding attributes associated with the defect to perform binning and classification.

The defects may also be binned based on expected electrical parameters of the defects and / or expected electrical parameters of the device features near the defective locations in the design data space. The expected electrical parameters of the defect and device characteristics can be determined based on previous electrical tests, simulation of the electrical parameters of the defects, review of defects, or some combination of the ones. In addition, fault simulation for one or more defects may be based on the location of defects in the group and / or design data space in which the defect is to be binned.

In some embodiments, the method further comprises the step of determining, based on at least one of the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the reticle inspection data required for the reticle on which the design data is printed, Into a group. In this way, the reticle inspection data can be used as a binning attribute. In particular, the reticle inspection data attribute can be used to bin the defects detected on the wafer. In the present embodiment, one or more attributes of the design data may include any attributes of the design data described herein. One or more attributes of the reticle inspection data may include a defect detected on the reticle, a position of a defect detected on the reticle in the reticle space, one or more attributes detected on the reticle, one or more attributes of the design data printed on the reticle, Such as the reticle inspection data. One or more attributes of the detected defects on the reticle may include any of the defect attributes described herein. In addition, one or more attributes of the design data printed on the reticle may include any design data attribute described herein.

The attributes of the reticle inspection data may be determined in any suitable manner (e.g., using the output of the reticle inspection system) by the methods and system embodiments described herein. Alternatively, or in addition, the attributes of the reticle inspection data may be obtained by a method and system described herein from a reticle inspection system that determines the storage medium and / or properties for which the attributes are stored.

The step of binning the defect based at least in part on one or more attributes of the reticle inspection data may include the step of removing the defect on the reticle that may cause defects on the reticle, one or more attributes of the reticle defect that caused the defect on the wafer, May be used to separate defects based on whether they are caused by one or more attributes of the printed design data. As such, the resulting binning may provide additional information as to the cause of the defect and / or how the reticle affects the defect and / or the design data printed on the wafer. Such binning results may include one or more parameters of the reticle manufacturing process, one or more parameters of the reticle inspection process, one or more parameters of any other reticle-related or design-related process, one or more of the other processes described herein Parameters, or some combination thereof. The binning of defects in this embodiment is performed based on the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the reticle inspection data, and any other information described herein can do.

In another embodiment, the method may include grouping the defects into groups based on the location of the inspection data in the design data space, one or more properties of the design data in the design data space, and one or more properties of the inspection data . In this manner, one or more attributes derived from the inspection data may be used for the binning operation. In the present embodiment, one or more attributes of the design data may include any attributes of the design data described herein. In addition, one or more attributes of the inspection data used for binning may include any attributes of the inspection data described herein. Defects can be binned in this embodiment using any other information described herein. The binning in this embodiment can be performed as described further herein.

In a further embodiment, the method further comprises the step of determining the position of the inspection data within the design data space, one or more attributes of the design data in the design data space, one or more properties of the inspection data, And binning the defect into a group based on at least one attribute of the inspection data. In this way, the reticle inspection data can be used as a binning attribute. In particular, reticle inspection data attributes can be used for defect binning on a wafer. One or more attributes of the design data in the design data space used for binning in this embodiment may include any attributes of the design data described herein. One or more attributes of the inspection data used for binning in this embodiment may include any attributes of the inspection data described herein. One or more attributes of the reticle inspection data used for binning in this embodiment may include any attributes of the reticle inspection data described herein. The binning in this embodiment can be performed as described further herein. In addition, the binning result of this embodiment can be used to perform any of the steps of any of the methods described herein.

In some embodiments, the method further comprises the steps of: locating the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, Layer, or some combination thereof, based on one or more attributes of inspection data previously obtained for a wafer, another wafer, or some combination thereof, for design data, other design data, or some combination thereof, As shown in FIG. In this manner, attributes determined from inspection data previously collected for the same or different wafers, the same or different designs, and the same or different process layers can be included in the binning operation. The previously collected inspection data may be stored in a data structure or included in a knowledge base that may be configured as described further herein. In this manner, one or more attributes of the previously acquired inspection data can be determined from the training set of accumulated learning data, historical data, or data. In the present embodiment, one or more attributes of the design data may include any attributes of the design data described herein. In addition, one or more attributes of the inspection data used for binning may include any attributes of the inspection data described herein. Defects can be binned in this embodiment using any other information described herein. The binning in this embodiment can be performed as described further herein.

In any of the embodiments described above, the binning can be performed on-tool, off-tool, or any combination thereof.

In a further embodiment, as shown in step 28, the method may be implemented in combination with the location of the design data in the design data space and other inspection results (e.g., iDO results and iADC results), such as the yield effect associated with the design data And selecting at least a portion of the defects for review based on the one or more attributes of the design data in the data space. One or more attributes of the design data used to select defects for review may include any attributes of the design data described herein. In addition, the location of the inspection data in the design data space can be used to locate defects in the design data space as described herein, which can be used for attribute determination of the design data corresponding to the defect, as described herein . In some such embodiments, the Newson defect may be filtered from other defects as described herein, and the DOI (or non-Newson defect) may be maintained for review or further analysis. In another embodiment, the defect list and the identified hot spots, the classification of defects and hot spots, and the design context can be used to improve review sampling (which may include sub-sampling) in the monitoring step, Or off-tool during post-processing.

In another embodiment, defect selection for review is performed as a function of the binning result. For example, defects in some groups may be selected for review, but defects in other groups may not be selected for review. In another example, some groups of defects may be sampled more extensively than other groups (i.e., more defects from some groups may be selected for review). The extent to which the groups and groups of sampled defects are sampled may be determined based on, for example, one or more attributes of the design associated with each group or any other information described herein associated with a group of defects. The choice of defect for review can be performed as a function of the yield relevance associated with the defect or defect bin. For example, the population of defects may be divided into random defects and systematic defects, and a different sample plan may be used for each different defect type. In this manner, the sampling strategy for other types of defects can be very different.

In some embodiments, the method includes selecting at least a portion of a defect for review, including at least one defect located within each portion of the design data in a design data space having different values of one or more attributes of the design data . ≪ / RTI > In this manner, defects in different portions of the design data can be sampled for review. For example, the context of each defect may be used to classify defects for review (e.g., by context thresholds), to generate a review sample that ensures that all contexts in which a defect is detected are represented by review samples .

In a further embodiment, as shown in step 30, the method includes determining a sequence in which the defect is to be reviewed, based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space . For example, the method may include using a context map to classify defects based on priorities for offline review (e.g., optical or SEM review). The context of each defect may classify defects for review (e.g., by context threshold) such that systematic defects and potential systematic defects are given a higher priority than other defect types.

Aligning the inspection data stream at a given alignment site at a sample point across the die on the wafer provides several advantages to provide sub-pixel alignment of inspection data at all points on the wafer. For example, since the raw data stream is substantially precisely aligned to the design data, the defect location in the design data space can be determined with sub-pixel accuracy (e.g., 1000 nm accuracy versus less than 100 nm accuracy). A defect location of substantially high accuracy can greatly improve the accuracy of any subsequent review process and the speed at which defects can be located, imaged and analyzed in a SEM or FIB system. In addition, the context information associated with the defect can be used in the inspection system in the second pass review or in the HRDC step, which can be performed in an offline SEM or optical review station. Such information may be provided to or obtained by another system, such as an automatic defect location (ADL), in addition to other local context information about the defect, which may assist in locating the defect automatically or manually. The review system can also use such information to create logic for the appropriate physical coordinate transformation for the system and wafer under the measurement parameters.

In some embodiments, the method further comprises the step of determining, based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space, And extracting the predetermined attribute. In this manner, the method may be based on the location of the inspection data in the design data space and the predetermined signal or image (s) for the inspection data area (e.g., a particular subset of the area being inspected) based on one or more attributes of the design data in the design data space And extracting the attribute. The extraction attributes of the output from one or more detectors may include, for example, the brightness or standard deviation of the image or signal for the pixel at another site. In addition, the wafer may be a patterned wafer on which a pattern corresponding to the design data is printed. Therefore, the attribute of the output can be extracted based on the information about the output corresponding to the pattern formed on the wafer. Further, the information on the structure in the pattern formed on the wafer can be extracted from the output from one or more detectors.

The extracted attributes of the output from the detector can be used to generate an image of the attribute over other parts of the wafer. In this manner, the method may include generating a "design aware image" of the surface of the wafer. The image can be used to determine one or more attributes of the wafer, such as the properties of the wafer, which can be determined by metrology. In this manner, the inspection system can be used similar to the metrology tool by extracting the attributes of the output from one or more detectors at substantially exactly specified locations based on the layout for the design data or design data. Thus, other parts of the wafer can be essentially treated as metrology sites in this embodiment. In addition, one or more extracted predetermined attributes of the output from the one or more detectors of the inspection system may be compared to those described in commonly owned U.S. Patent Application Serial No. 60 / 772,418 (Kirk et al .; filed February 9, 2006) Can be used to perform one or more of the same steps, and the patent literature is incorporated by reference as fully described herein.

One or more attributes of the design data used in the present embodiment may include any attributes of the design data described herein. In one such embodiment, one or more of the attributes of the design data may be associated with design data, other design data, or some combination thereof, in the process layer, other process layers, or some combination thereof from which inspection data for the wafer is obtained Based on one or more attributes of previously acquired inspection data for the wafer, another wafer, or a combination thereof. In this manner, one or more attributes of the design data in the design data space used in the present embodiment may include attributes of previously collected inspection data from the same wafer or other wafer for the same or different designs for the same or different process layers On the basis of the correlation. The previously collected design data can be stored in a data structure or included in a knowledge base that can be configured as described herein. In this manner, one or more attributes of the design data may be selected in this embodiment based on cumulative learning, historical data, or a training set of data.

In another embodiment, the method further comprises the steps of: acquiring 1 < st > of the inspection system acquired for the other part of the wafer based on the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, And extracting one or more predetermined attributes of the output from the detector. One or more attributes of the design data used in the present embodiment may include any attributes of the design data described herein. In addition, one or more attributes of the inspection data may include any attributes of the inspection data described herein. For example, in one embodiment, one or more attributes of the inspection data include one or more image noise attributes, one or more defects detected at another site, or some combination thereof. In this manner, one or more attributes of the inspection data may include, without limitation, image noise features and / or detection / non-detection of defects in the inspection data area. Extracting one or more predetermined attributes of the output may be performed as further described herein. The extracted attributes of the output can also be used as described further herein.

Each embodiment of the method described herein may comprise any other step of any of the methods described herein. Also, each embodiment of the above-described method may be performed by any other system described herein.

Figure 15 shows another embodiment of a computer-implemented method for determining the location of inspection data within a design data space. It should be noted that the steps shown in Fig. 15 are not necessary for the embodiment of the method. One or more steps may be excluded from the method shown in Fig. 15, and the method can still be practiced within the scope of this embodiment.

The method shown in Fig. 15 can be generally used for CBI. In this embodiment, the data preparation step 42 includes the step of creating the database 44. The database 44 includes a CAD layout for design data and a context hierarchy for design data. The database 44 may have any suitable configuration known in the art and may include any other data or information described herein. In addition, the data in the database 44 may be stored in any other suitable data structure. The database 44 may be generated by the software 46 using the GDSII file 48 and the context layer 50 as inputs. The software 46 may comprise any suitable software known in the art. Generally, the software includes program instructions (such as shown in FIG. 15) that can be executed on a processor (which may be configured as described further herein but in FIG. 15) to generate a database using the GDSII file and context hierarchy (Not shown). Context layer 50 may be obtained or generated in any manner known in the art, and may include any contextual information or data described herein. In addition, the GDSII file 48 may be replaced with any other suitable data structure in which the design data is stored.

The method shown in Fig. 15 also includes a recipe setup step 52. Fig. The recipe set-up step 52 includes a step 54 that can be performed to determine the alignment information 56. Step 54 may include scanning the die on the wafer, which may be performed by an inspection system configured as described further herein. Step 54 may also include scanning the wafer and selecting the alignment site on the wafer using the acquired information. The alignment sites on the wafer are selected as described herein. In addition, the alignment site on the wafer may be selected based on the inspection swath layout information 58 and any other suitable information as further described herein. The check swath layout information may include any swath information described herein, and may be determined as described herein. Selection of alignment sites on the wafer can be performed automatically, semi-automatically (or user-assisted) or manually, as further described herein.

Step 54 may include rendering the image or obtaining other suitable data corresponding to the alignment site on the wafer from the CAD layout information in database 44. [ For example, step 54 may be performed on a computer-readable medium such as a computer-readable medium, such as a computer-readable medium, such as a CAD And using patch 60. Step 54 may also include computing an (x, y) mapping from the CAD layout information of the alignment site on the wafer to the information obtained. The alignment information 56 includes the data for a given alignment site and the (x, y) position of a given alignment site within the design data space.

The method shown in FIG. 15 may include a wafer inspection step 62. The wafer inspecting step 62 may include an initialization step 64 and a driving step 66. As shown in step 68, during the initialization step 64, the method includes arranging information 56 that includes information about a given alignment site and the (x, y) location of a given alignment site within the design data space, And a preloading step. As shown in step 70, the initialization step may also include preloading the context layer 72 from the database 44. The initialization step may also optionally include rendering the data for a given alignment site from a polygon to a pixel, as shown in step 74, which may be performed as described herein. Context layer 72 may include any context information described herein.

During the actuation step 66, as shown at step 76, the method includes performing an alignment and mapping of the inspection data to the design data space. This step can be performed during inspection of the wafer. Alignment and mapping can be performed as further described herein. The actuation step may also include applying a mapping to the context map, as shown in step 78. [ The context data may be mapped as further described herein. The actuation step may include applying a context map to the inspection data during inspection, as shown in step 80, which may be performed as described herein. The driving step may also include mapping the defect coordinates to the context map, as shown at step 82, which may be performed as described herein. The actuation step may include an additional step 84, which may include filtering the detected data by context, classifying the defect, creating review samples, other steps described herein, or some combination thereof . Each additional step 84 may be performed as further described herein. Each embodiment of the method shown in FIG. 15 may include any of the other steps described herein. Further, each embodiment of the method shown in Fig. 15 can be performed by any of the systems described herein.

Program instructions embodying methods such as those described herein may be transmitted via a carrier medium or stored therein. The carrier medium may be a ROM, a RAM, a magnetic or optical disk, or a storage medium such as a magnetic tape.

Figure 16 shows various embodiments of a system configured to determine the location of inspection data within a design data space. In one embodiment, the system includes a storage medium 86 that includes design data (not shown in FIG. 16). The storage medium 86 may also include any other data and information described herein. The storage medium may comprise any of the above-described storage media or any other suitable storage medium known in the art. In this embodiment, the system also includes a processor 88 that is defective in the storage medium 86. The processor 88 may be coupled to the storage medium in any manner known in the art. In this embodiment, the system may be configured as a stand-alone system that does not constitute part of a process, inspection, metrology, review or other tool. In such an embodiment, the processor 88 may be configured to receive and / or acquire data from other systems by a transmission medium that may include "wired" and / or " In this manner, the transmission medium may act as a data link between the processor and another system. The processor 88 may also transmit data to other systems via a transmission medium. Such data may include, for example, design data, context data, results of the methods described herein, an inspection recipe or other recipe, or some combination thereof.

The processor 88 may take various forms, including a personal computer system, a mainframe computer system, a workstation, an image computer, a parallel processor, or any other device known in the art. In general, the term "computer system" may be broadly defined to include any device having one or more processors that execute instructions from a memory medium.

However, in other embodiments, the system includes an inspection system 90. The inspection system 90 is configured to acquire data for an alignment site on the wafer 92 and inspection data for the wafer. In an embodiment of the system including the inspection system, the processor 88 may be coupled to the inspection system in any manner known in the art. For example, the processor 88 may be coupled to the detector 94 of the inspection system 90 such that the processor can receive the inspection data generated by the detector and the data at the alignment site on the wafer. The processor may also receive image data and any other output of the detector, such as a signal. Further, when the inspection system includes the above detectors, the processor may be coupled to each detector as described above.

The processor 88 is configured to align the data acquired by the inspection system with the data for a given alignment site for alignment sites on the wafer. The processor may be configured to align data according to any of the embodiments described herein. The processor 88 is also configured to determine the position of the alignment site on the wafer within the design data space based on the position of the predetermined alignment site within the design data space. The processor may be configured to determine the position of the alignment site on the wafer within the design data space according to any of the embodiments described herein. The processor 88 is also configured to determine the location of the inspection data acquired for the wafer by the inspection system in the design data space based on the location of the alignment site on the wafer within the design data space. The processor may be configured to determine the location of inspection data within the design data space in accordance with any of the embodiments described herein. The processor may be configured to perform other steps of any method embodiment described herein.

In one embodiment, the inspection system 90 includes a light source 96. Light source 96 may comprise any suitable light source known in the art. The light source 96 may be configured to advance light to a beam splitter 98. The beam splitter 98 may be configured to advance light from the light source 96 to the wafer 92 at a substantially vertical incidence angle. The beam splitter 98 may comprise any suitable optical element known in the art. The light reflected from the wafer 92 passes through the beam splitter 98 and proceeds to the detector 94. Detector 94 may comprise any suitable detector known in the art. The output generated by the detector 94 may be used to detect defects on the wafer 92. For example, the processor 88 may be configured to detect defects on the wafer 92 using the output produced by the detector. The processor may use any method and / or algorithm known in the art to detect defects on the wafer. During the inspection, the wafer 92 is placed on the stage 100. Stage 100 may comprise suitable mechanical and / or robotic assemblies known in the art. The inspection system shown in Fig. 16 may comprise any other suitable element (not shown) known in the art.

As shown in Figure 16, the inspection system is configured to detect mirror reflected light from the wafer. In this manner, the inspection system shown in Fig. 16 is configured as a BF inspection system. However, the inspection system can be replaced by a inspection system configured as a DF inspection system, an EC inspection system, an aperture mode inspection system, or any other optical inspection system known in the art. Further, the inspection system shown in Fig. 16 can be configured to perform the DF inspection by changing the angle of incidence of light to the wafer and / or the angle at which light is collected from the wafer. In another example, the inspection system may include one or more optical elements (not shown), such as apertures, positioned within the illumination path and collection path, such that the inspection system can perform the ECM mode of inspection and / Or < / RTI >

In addition, the optical inspection system shown in FIG. 16 may include a commercially available inspection system such as 2360, 2365, 2371, and 23xx available from KLA-Tencor. In another embodiment, the optical inspection system shown in Fig. 16 can be replaced with an electron beam inspection system. Examples of commercially available electron beam inspection systems that may be included in the system shown in Figure 16 include the eS25, eS30, and eS31 systems from KLA-Tencor. The embodiment of the system shown in Fig. 16 can be further configured as described herein. In addition, the system may be configured to perform any of the other steps of any method embodiment described herein. The embodiment of the system shown in Fig. 16 has all the advantages of the method embodiment described above.

The above-described method and system generally performs sorting of inspection data and design data by aligning the acquired data (e.g., BF patch image) with the data for a predetermined alignment site (e.g., GDSII file) for the alignment site on the wafer do. The additional methods and systems described herein generally perform an alignment between inspection data and design data and use similar techniques such as statistical techniques (e.g., no patch image or SEM image) to determine similarities between different defects .

The embodiments described herein may be used for context-based setup, inspection, binning, review, measurement, testing, analysis, or some combination thereof. The context data used in the embodiments may be a design database or a file (e.g., a GDS file, an OASIS file, an open access file, a net-list, etc.); Process simulation results; Electrical simulation results; Pattern of interest; Hotspot information (e.g., OPC, electrical test results, test results); And may include design information or design data stored in a data structure such as process tool data (work in progress; or some combination thereof). Embodiments may also be implemented in embodiments described herein Prediction of the yield impact of one or more defects and / or defects of one or more groups based on the results produced by the method. The step of predicting yield impacts may be performed as further described herein . In addition, the embodiments described herein may be advantageously used to provide relatively quickly yieldable, yield-related information.

The information described herein may be used to group defects detected by the inspection system to precisely determine the defect location coordinates (i.e., the actual defect may be located near the reported coordinates, but not exactly in the reported coordinates) . For example, the methods and systems described herein can be used to search patterns that are at least similar to those reported near the reported defect location, by attempting to align the patterns relative to each other, thereby ensuring that the defect coordinates reported by the inspection system are perfect But also allows for improved grouping of defects even if not precise. In another example, the acquired review image (e.g., SEM image) or inspection image close to the reported defect location can be determined by comparing the actual location of the defect in the wafer space (as opposed to the location of the defect reported by inspection) Can be compared to or overlaid with the design data to determine an accurate representation of the data. At least all instances of a similar pattern are identified in the design data (including rotated, flipped, or otherwise tilted instances of the pattern) and are binned into a pattern group. The actual defect locations in the wafer space determined as described above are compared with the locations for the pattern groups and the defects located at locations for the pattern groups within a given tolerance are binned into groups. Such grouping of defects may be performed on-tool or off-tool, and may improve the performance of the method described herein (e.g., if there is coordinate inaccuracy in the defect location coordinates reported by the inspection, In particular, in coordinate inaccuracy, the source pattern determined based on the reported test coordinates is the approximate source pattern (unless the pattern is isolated or the coordinates of the defect are substantially accurate). Of course, the embodiments described herein can be used as a result of a test generated by a high-precision inspection system.

One embodiment relates to a computer-implemented method of binning detected defects on a wafer. Generally, in the method described herein, the population of defects is selected by selecting source defects and design data ("source design data") that is close to the location of the source defects in the design data space to a location close to the location in the design data space of the target defects By assigning target defects to the target design data when there is a match or at least similarity between the compared design data compared to the design data ("target design data") (eg, all or part of the defect population) (E.g., GDS design data). The comparison may be based on a direct comparison of the source and target design data. The comparison can also be performed after minor coordinate inaccuracies are corrected between the source defect and the target defect in the design data space. The comparison may also include retrieving the source design data in the target design data to account for coordinate inaccuracies in the source and target defect locations. Alignment and searching can be improved by using sub-pixel alignment techniques that can be performed as described herein. In addition, a comparison of the source and target design data may be performed to determine whether there is a correct match between the source and target design data, or a similar but inaccurate match between the source and target design data. Each of the above-described steps may be performed further as described herein.

After the target defect population has been tested for source defects, the following source defects may be selected. Defects not yet grouped are selected as the next source defect. The above steps can be repeated until all the defects are grouped (or at least tested). The defect population used in the methods described herein may include all defects detected on the wafer and may include all defects detected on a plurality of wafers or a subset of defects detected on one or more wafers Defects that are detected and identified as proximate to the hot spot). In addition, the methods described herein can be performed on a total defect population or a subset of defects in the entire defect population (which may be selected based on design functional blocks such as logic, memory, etc.). Binning can be performed with automatic single-pass or multi-pass grouping.

The method includes comparing design data portions that are close to the location of the defects in the design data space. For example, as shown in FIG. 17, the method may include placing a portion 102 of design data (not shown) near the location of a defect 104 in a design data space 106 within a design data space 106, To a portion 108 of design data (not shown) that is close to the location of the design data (not shown). The defect 104 is referred to herein as a "source defect " and the defect 110 is referred to herein as a" target defect ". The design data near the location of the defects in the design data space defines background pattern data or background information on the defects.

As shown in FIG. 17, the portion 102 is larger than the defect 104. The dimensions of the portion 102 (in the x and y directions) may be selected by the user. Also, the portion 108 is larger than the defect 110. The dimensions of the portion 108 can also be selected by the user. The dimensions of portion 108 are typically larger than the dimensions of portion 102, as further described herein. Alternatively, the dimensions of the part may be selected (e.g., automatically) by the computer-implemented method described herein.

In one embodiment, the dimensions of the part (in the x and y directions) can be detected by detecting defects, coordinate inaccuracies of the inspection system, one or more attributes of the design data, defect sizes, defect size errors in the inspection system, Based at least in part on the location of the defect reported by the inspection system used to detect the defect. For example, the method may include defining a portion of the defect data centered at the reported defect location (i. E., The "pattern window"). The pattern window may have a width and height greater than the dimensions of the defect and is selected to account for errors in the defect location due to coordinate uncertainty. For example, if the coordinates of the defect locations reported by the inspection system are accurate to about +/- 3 microns, the pattern window is calculated from the x and y coordinates of the reported defect locations for the total minimum size of about 6 microns by about 6 microns And may be defined to include at least 3 mu m in all directions. In this way, the better the coordinate accuracy of the inspection system, the smaller the pattern window can be, which can result in faster and more accurate grouping. The dimensions of the pattern window may be selected such that the pattern window contains a "sufficient" amount of background pattern data such as a sufficient number of features in the design data. In addition, when the design data in the pattern window is compared to a clip, the pattern window dimension can be selected to include the entire polygon where the pattern window is only partially contained in the clip.

The portion of the design data used in the method described herein may include a clip of the design taken around the location of the defect in the design data space. The term "clip" is generally defined as the area within the design data around the defect, and can be considered as the neighborhood of the defect. A polygon defines a pattern in a clip, but a polygon can extend partially beyond a clip. Clips used in the methods described herein for some of the defects may have one or more other dimensions. However, the portion of the design data used in the method described herein may include design data in an extended bounding box (EBB) around the extent of the portion where the defect may be located. EBB can be selected based on the coordinate accuracy of the inspection system used to detect the defect and the defect size (and the defect size error of the inspection system). For example, the larger the coordinate accuracy of the test, the smaller the dimension of the EBB can be. Since the location of the defect can be more accurately determined in the smaller EBB at the larger EBB, a smaller EBB is preferred and at least one attribute of the defect (e.g., location of the defect with respect to the polygon in the design, A more accurate fault location within EBB can be used to determine the root cause). Also, at least one dimension of the EBB used may differ for at least some of the defects. EBB is generally smaller than a clip and indicates which defects can be located).

In another embodiment, the dimensions of at least some of the portions are different. For example, as shown in FIG. 17, the difference between the dimensions of the portion 108 and the defect 110 is greater than the difference between the dimensions of the portion 102 and the defect 104. That is, the region of the target portion around the target defect is larger than the region of the source portion around the source defect. In this manner, the target portion may contain more design data than the source portion.

The source portion of the design data can be compared to other regions of the target portion of the design data. In this manner, the method may include searching for a source portion of design data in the target portion. For example, as shown in the overlay 112 of the source and target portions, the source portion of the design data can be compared to one region of the target portion. After such comparison, the position of the source portion relative to the target portion may be changed such that the design data in another region of the target portion can be compared to the source portion of the design data. In this manner, the method may include "sliding" the source portion of the design data around the target portion until a match is identified or until all regions of the target portion are compared to the source portion.

The step of comparing portions of the design data may be performed with any information available for the comparison step. For example, the portion of the design data to be compared may be part of the design data contained in the data structure, such as a GDS file. In addition, comparing the portions of the design data may include comparing the polygons in the portion. In another embodiment, the method includes converting the portion of the design data near the location of the defect in the design data space to a bitmap prior to the comparing step. For example, polygons within portions of design data can be converted to bitmaps for rapid processing. Portions of the design data may be converted to bitmaps using any suitable method known in the art. For example, the method and system disclosed in U.S. Patent No. 7,030,997 (Neureuther et al.), Which is incorporated herein by reference as if fully set forth herein, can be converted into bitmaps. In one such embodiment, comparing the portions of the design data includes comparing bitmaps to each other. The step of comparing bitmaps to each other may be performed using any suitable method. In addition, comparing the portions of the design data may include comparing one or more properties of the design data in the portion. The one or more attributes to be compared may include any attributes of the design data described herein.

The method also includes determining, based on the result of the comparing step, whether the design data in the portion is at least similar (similar or exactly the same). If one or more attributes of the design data in the portion are determined, the grouping may be based on a common pattern similarity, a common attribute similarity, a common attribute similarity within a feature space, or some combination thereof. For example, in one embodiment, determining whether the design data in the portion is at least similar may include determining if the common pattern in the design data in the portion is at least similar, which may be accomplished as further described herein . In another embodiment, determining whether the design data in the portion is at least similar resides in determining whether the common attributes of the design data in the portion are at least similar, which may be performed as further described herein have. In a further embodiment, the step of determining if the design data in the portion is at least similar resides in determining whether the common property in the feature space of the design data in the portion is at least similar, As shown in FIG. The method may also include determining how other regions similar within the portion are present. Further, even if the design data in the portion are slightly offset from one another or include a different design structure slightly, if the portion has a remarkable common structure, the portions can be determined to be similar to each other. The method includes comparing design data close to the location of each defect in the design data space with design data close to the location of all defects in the design data space to determine which defects are similar based on the & .

It is desirable that the step of determining whether the design data in the portion is at least similar is not performed based on whether or not the defect is located at the same position in the design data. That is, defects that are grouped into groups based on their "background" by the method described herein may not need to be located at the same location for a pattern, feature, polygon, or structure in the design data. Without depending on the matching of the position of the defects to the design data, the method can provide more accurate defect binning. For example, although two defects exist in the same type of pattern, they may be located at different locations within the pattern. Also, systematic defects in the POI may be localized, but may also not be localized. However, such defects can be caused by, or related to, the same pattern-based issues. Thus, defect binning that does not rely on similarity between actual defect locations within the design data can allow for more accurate binning, which can be used for control and prediction of yield based on these systematic issues, and for more accurate demonstration of systematic issues . The step of determining whether a portion of the design data is at least similar may be performed using any suitable algorithm. Thus, the method can be used as a "similarity checker. &Quot; Since the target portion can be larger than the source portion compared to its target portion, the similarity checker can be advantageously used when there is coordinate inaccuracy at the actual defect location in the design data.

In the embodiment shown in Fig. 17, the entire source portion is compared to the other region of the target portion. In some embodiments, the method includes comparing the entire design data in at least a portion of the portion to design data in another portion. The method may also include comparing the entire source portion of the design data to another region of the target portion of the design data. As such, the method may include searching the target portion for design data that is at least similar to the entire source portion of the design data.

The method further comprises binning the defects into groups such that at least portions of the design data that are close to the location of the defects of each group are at least similar. In this manner, the method includes binning the defects based on the context of the design data and / or the design data near the location of the defects in the design data space. For example, in order to group defects in a non-supervised manner, a polygon in the portion of the design data that is at least similar or matched may be used. In addition, the binning step may include binning at least two defects into at least one group such that the design data close to the location of the at least two defects in the at least one group is at least similar. Also, in rare instances where there is no part of the design data near the location of the defects in the design data space, which are determined to be at least similar, the method does not bin the defects into groups.

The method also includes storing the result of the binning step on a storage medium. The result of the binning step may include any result described herein. The storing step may also include storing the result of the binning step in addition to any other result of any of the steps of any of the method embodiments described herein. The results may be stored in any other manner known in the art. The storage medium may also include any of the storage media described herein or any other suitable storage medium known in the art. After the results are stored, the results can be accessed and used within the storage medium by any method or system embodiment described herein. The results may also be stored "permanently "," semi-permanently ", temporarily or for some period of time. For example, the storage medium may be a RAM, and the result of the binning step may not need to remain in the storage medium.

The step of determining whether a portion of the design data is at least similar may comprise comparing the result of the comparing step with a predetermined criterion for similarity. For example, the result of the comparison step may be compared with a threshold value. If the design data in that portion is at least as similar as at least such a threshold, the method can bin defects into groups. In another example, the result of the comparison step may be compared to a "percent similarity" value. If the design data in that portion is at least as similar as at least that percentage, the method can bin the defect into groups.

In any case, if a similarity check is performed between two or more parts of the design data (e.g., a GDS pattern clip) and a common pattern within two or more parts is identified, the method includes binning the defect do. The result generated by the step of determining whether the design data in the portion is at least similar may include an indication of whether design data in the source portion has been found in the target portion. In addition, the center point of the common structure can be regarded as near to the design data space location of systematic defects. Therefore, the (x, y) coordinates of the design data space position of the defect in each group can be adjusted (moved) to the center point of the structure corresponding to each group. The coordinate correction vector (or error vector) may be determined for each binned defect based on the design data space coordinates of the defect and the center point of the common structure corresponding to the group in which the defect is to be binned. Design of Defect Location In order to determine the total systematic uncertainty in the data space coordinates (design data space movement error + wafer space for errors in the reported coordinates), the method includes moving or error vectors for a statistically significant number of defects And determining the average of the two. The method may further comprise determining a standard deviation of all error vectors and determining an average of only the vectors within +/- 1 standard deviation or +/- 3 standard deviation. In this way, an ideal value that can compromise the average value can be removed from the operation. The determined average value can be used as an overall correction value. For example, this global correction value is applied to additional design data space coordinates of the defect location determined by the wafer space, so as to design the data movement such that a more accurate overlay can be determined in subsequent data processing steps.

The result of the determination step may also include x and y offsets between the target portion and the location of the source portion in the target portion at least where similar design data is found. The x and y offsets may be used to optimize the binning method. For example, in an initial comparison of portions, the source portion may be positioned so that the center points of the two portions are aligned within the target portion. However, if it is determined that there is some predictable or repeated offset (in the x and / or y direction) between the initial use position of the source portion in the target portion and the position of the source portion in the target portion where at least similar design data is found , This offset can be used to adjust the overlay used in the comparison step of the binning method.

In some embodiments, the design data in the portion includes design data for one or more design layers. In this manner, the method may include checking a design layer for background similarity of defects, binning the defect, or checking a set of design layers for background similarity of defects (i.e., multi-layer background similarity) The method may further include the step of binning. For example, during inspection of a polysilicon layer (e.g., a gate electrode layer) on a wafer, underlying diffusion layers may be visible to the inspection system and thus affect inspection results. As such, the design data contained in that portion may include design data for the polysilicon layer and the diffusion layer to increase the accuracy of the background-based binning. However, by using design data for one or more design layers, defects located at least close to portions of the design data that reside at least on non-similar design data on the underlying layer can be binned into different groups.

Regardless of whether the design data in the source portion is found in the target portion, the method may include comparing the source portion with another portion of the design data that is close to the location of another defect in the design data space. A step of comparing the design data in the source portion to the design data in the multiple target portion may be performed since at least one target defect located at least close to the design data at least similar to the design data in the source portion may be detected on the wafer.

17, portion 102 may be compared to portion 114 of design data (not shown) that is close to the location of defects 116 in design data space 106. In this example, The dimensions of portion 114 can be selected as described above. The source portion of the design data can be compared to design data in other areas of the target portion, as further described herein. The method may include determining if the design data in the source portion is at least similar to at least a portion of the design data in the target portion, which may be performed as described above. The overlay 118 of portions shows at least the location of the source portion within the target location where similar design data was found. Thus, the method includes binning the defects 104 and 116 into a group, since the design data in the portion 102 is determined to be at least similar to at least a portion of the design data in the portion 114. [ Also, since the design data in the source portion is determined to be at least similar to at least some of the design data at both target portions, the defects 102, 110, and 116 are binned into a single group.

In such a further example, portion 102 may be compared to portion 120 of design data (not shown) that is close to the location of defect 122 in design data space 106. The dimensions of portion 120 may be selected as described above. The source portion of the design data may be compared to design data in other regions of portion 120, as described above. The method also includes determining whether the design data in portion 102 is at least similar to at least a portion of the design data in portion 120, based on the result of the comparison, which may be performed as described above. The overlay 124 of portions 102 and 120 shows at least the location of portion 102 within portion 120 where similar design data is found. Thus, the method includes binning the source defects and target defects 112 into a group. Further, since the design data of the source portion is determined to be at least similar to at least part of the design data of the three target portions, the source defect and the three target defects are binned into one group. The above steps can be performed until background information for each defect detected on the wafer is compared with background information for all other defects detected on the wafer.

As described above, the method is based on the context of the design data and / or the design data located close to the location of the defects in the design data space, possibly with other information such as one or more attributes of the design data and / And binning the defects in combination. In contrast to other methods of binning defects based on contextual information, the method described herein does not perform binning based on background information as printed on the wafer. Instead, the method described herein performs binning based on background information as specified in the design data. In this way, the method described herein can perform background-based binning regardless of how design data is printed on the wafer or not.

Such independence from design data as printed on a wafer can be particularly advantageous for the PWQ method and the focus exposure matrix (FEM) method, in which design data such as printed on a wafer is used for such a method (Sometimes dramatically) over the process window parameters, thereby degrading the accuracy of the defect binning method based on the image of the design data printed on the wafer. In such an application of an experimental technique such as PWQ, the method can provide an improved background-based binning by using an excerpt of defect data at the location of the defect in the design data space or a GDS clip. As such, binning can be performed by a common pattern. The binned defects may be classified individually or collectively as further described herein. For example, the method may include classifying defects based on one or more attributes of the design data (e.g., one or more attributes of the design data located close to a defect location in the design data space) As shown in FIG.

The position of the defect in the design data space can be determined before the binning is performed since the defect detected on the wafer is binned by the design data close to the design data space position of the defect. In one embodiment, the method includes obtaining data (or determining a shift function) for the x and y coordinates of the location of the detected defect in the design data space, which is performed as described herein can do. In another embodiment, the method includes determining a location of a defect in a design data space by comparing data obtained by the inspection system with respect to an alignment site against data for a predetermined alignment site. The step of acquiring data for an alignment site on the wafer includes determining an appropriate wafer space location of the alignment site on the wafer using product layout data, optionally reticle frame data, and stepper data (or input to the stepper) , And acquiring data at the appropriate position. Such comparison and determination steps may be performed as described above. The method may also include determining the location of at least a portion of the defects in the design data space by comparing data for a given alignment site with data acquired by the inspection system for alignment sites on the wafer. The determined location for at least some of the defects can be used to determine the location of other defects in the design data space (e.g., by creating and using transforms to move the reported defect locations to the design data space). The step of determining the location of the defects in the design data space may be performed according to any of the embodiments described herein.

Sometimes, all of the foregoing data may be unavailable, or the wafer may not be properly aligned according to design data. In such an example, it may be useful to determine experimentally from a wafer during inspection or review of a portion of the conversion information. In one embodiment, the method includes determining a location of a defect in the design data space by comparing data acquired by the inspection system during the detection of the defect to data acquired by the review system at a location within the design data space determined by the review . In this manner, the method may include aligning the test results for one or more defects to review results obtained at a design data space location determined by the review. The method also includes determining a position in at least a portion of the design data space of the defect by comparing the data acquired by the inspection system during the inspection of the defect to the data obtained by the review system at a location within the design data space determined by the review . ≪ / RTI > The location determined for at least a portion of the defects can be used to determine the location of other defects in the design data space (e.g., by generating and using information to move the reported defects location to a defective location in the design data space). However, this approach provides a wafer scale offset that can be complicated by the coordinate inaccuracies of the inspection system. Thus, if there is coordinate inaccuracy in the reported position of the defect, it may be advantageous to base the transform function on a statistical sample of the measurement.

After the location of the defect in the design data space is determined, a portion of the design data around the determined location can be extracted so that the extracted portion of the design data can be used to bin the defect and perform the other steps described herein. Also, before using the extracted portion of the design data for binning, each (or one or more) extracted portions are mirrored to produce a subset that corresponds to and includes each of the extracted portions, Rotated, scaled, moved (shifted), or some combination thereof. A set of portions can be used for binning to increase the accuracy of the binning method.

The method may be implemented in any combination of dimensions (e.g., width) in the x direction, dimensions in the y direction (e.g., length), and dimensions in the z direction (e.g., height) And determining at least one attribute of the same detection defect. One or more attributes may be organized and / or stored in any suitable structure, such as a table or list. In another embodiment, the step of binning a defect includes binning a defect into a group such that at least a portion of the design data near the design data space location of the defect in each group is at least similar and at least one attribute of the defect in each group is at least similar. . In one such embodiment, the one or more attributes of the defect include one or more attributes of the inspection result where the defect is detected, one or more inspection parameters, or some combination thereof. One or more attributes of the inspection result may include, for example, other inspection parameters such as optical mode and / or polarization, collection angle, angle of incidence, etc., in which defects are preferentially detected. Additionally (or alternatively) one or more attributes may include any other attribute of the defect described herein. In this way, binning can be performed to isolate defects into design data and defect attributes. Such binning may be performed so that defects having other defect types or other attributes located within at least similar portions of the design data can be separated into different groups.

In some embodiments, the binned defects are detected by optical or electron beam inspection as described herein. The optical and electron beam inspection can be performed by the inspection system described herein. In another embodiment, the binned defect as described herein is detected in a PWQ or FEM method, which can be performed as described herein. The embodiments described herein may be particularly useful for defects detected in PWQ or FEM methods. For example, the methods described herein can be used to filter defects detected in PWQ and FEM methods, so that potential systematic issues can be more easily and accurately identified, which can be performed as further described herein . In addition, the method embodiments described herein can be used to bin defects detected by PWQ and FEM methods into useful groups, which can be performed as further described herein. In addition, the method embodiments described herein may be used to prioritize the PWED and FEM defects for review, measurement, or testing, which may be performed as further described herein. The method may also include binning the inspection and / or electrical test defects into groups based at least on a similar design / layout pattern.

In one embodiment, the inspection system used to detect the vened defect in the embodiments described herein may be aligned to three or four alignment sites on the wafer. Also, the alignment site may be selected as further described herein. In addition, one or more alignment features, patterns, and / or structures that are visible on a physical wafer or in design data or layout may be selected for use in the methods described herein. After the inspection system is aligned to the alignment site, stage position accuracy, any rotation errors, x and y movement errors, scaling (scaling) errors, or any combination thereof can be corrected. Such correction may occur during the inspection process or may be performed with a post-process (e.g., performed after the inspection results are generated). The correction may be based at least in part on a comparison of coordinates for the alignment sites reported by the inspection system and reference coordinates for the same alignment site.

In some embodiments, the method may comprise obtaining coordinates for three or four alignment sites in a plurality of dies on a wafer, such as a die at the left, right, top, bottom and center of the wafer. In another embodiment, alignment sites on the wafer are located at three different sites on the wafer. One such embodiment is shown in Fig. As shown in FIG. 18, the wafer includes a plurality of dies 128. Alignment site 130 may be located within dies 128a, 128b, and 128c. It should be appreciated that although the measurement sites are shown on only three dies, the alignment sites can be located on each die on the wafer. A subset of alignment sets within each die or an alignment site within a subset of dies can be used in the methods described herein.

The method may include identifying three common alignment sites (i. E., A die printed on a wafer and an alignment site common to design data (e. G., A GDS layout)) with a triangular distribution within the die. For example, as shown in FIG. 18, alignment sites 130 are arranged in a triangular distribution within dies 128a, 128b, and 128c. In one such embodiment, three different die may be distributed across the wafer in a predetermined arrangement (e.g., triangle or other arrangement). For example, as shown in FIG. 18, the dies 128a, 128b, and 128c are positioned in a triangular array 132 on the wafer 126. In this manner, the method may include aligning an alignment image (e.g., BF and / or DF image) acquired by the inspection system with respect to the alignment site on the wafer to data for a given alignment site. The method may include mapping the coordinates of the inspection data acquired by the inspection system to design data coordinates (e.g., GDS coordinates, and deploying the transformation matrix). The transformation matrix may be implemented in any suitable manner Lt; / RTI >

The coordinates of these alignment sites can be used to perform "tool matching" (e.g., perform automatically) to eliminate coordinate differences between inspection systems. One advantage of such a method is that it can be determined individually and automatically for all inspection wafers, thereby generating a correction factor set per wafer. Another advantage of such a method is that the determined coordinates are used to determine coordinate drift (e.g., cumulative error, stage shift error, and errors caused by mechanical, electrical, and thermal noise) in the inspection system or other inspection systems across the wafer Otherwise it can be used to determine the alignment accuracy of the inspection data for the design data.

As described above, comparing design data in a portion may include comparing the entire design data in at least a portion of the portion to design data in another portion. In this way, such a comparison result can be used to determine whether all of the design data in the source portion is at least similar to at least some of the design data in the target portion. However, in an alternative embodiment, comparing the design data in the portion may include comparing design data in at least a portion of the portion with design data in another portion, as described further herein Can be performed. The design data in the plurality of regions of the source portion may also be at least similar to or identical to the design data in the region of the target portion, Can be used to identify the largest area of data. In this manner, the method may include determining whether the design data near the target defect and source defect locations in the design data are "similar" or at least similar. Thus, such a method may be more effective at certain design layers in background-based binning of defects as described herein.

One such embodiment of the method is shown in Fig. For example, as shown in FIG. 19, the method may include defining a portion 134 of design data (not shown) that is close to the location of the defect 136 in the design data space 138. The defects 136 are referred to herein as "source defects. &Quot; The step of defining portion 134 of the design data may include selecting a dimension of the portion, which may be performed as further described herein. The method may also include separating, segmenting, or partitioning portions of the design data into one or more other regions. For example, as shown in FIG. 19, the portion 134 may be divided into four different regions 140, 142, 144, and 146. The other portion in which the portion 134 is separated inward can be referred to as "source quadrant" in this example. Although the portion 134 is shown as being divided into four source quadrants in Fig. 19, it should be understood that the portion can be divided into any suitable number of regions. All regions may have the same size, or all or some of the regions may have different sizes.

In this example, the method includes comparing the design data in the source quadrant 140, 142, 144, and 146 to design data (not shown) close to the location of the defect 150 in the design data space 138 do. Defects 150 are referred to herein as "target defects. &Quot; As shown in FIG. 19, portion 148 is larger than defect 150 and is at least as large as portion 134. The dimensions of portion 148 can be selected as described above.

The design data in each source quadrant can be compared to design data in other areas of the target portion. In this manner, the method may include a search step for design data within each source quadrant within the target portion. In this example, the method includes determining, based on the result of the comparing step, whether the design data in the source quadrant is at least similar to the design data in the target portion. For example, the method may include determining how the design data within each source quadrant is similar to the design data in the target portion. As such, it can be determined that the design data in a portion or all of the source quadrant is at least similar to the design data in the target portion, or that none of it is similar. The design data within the three of the four source quadrants can be within the region of the portion 148 at the location of the source quadrant 140, 144 and 146 shown in the overlay 152, Is at least similar to the design data.

In this manner, the method may include comparing the design data in the source quadrant to the design data in the target portion to determine which defects can be at least grouped into the group based on the corresponding design data have. The determination result of whether the design data in each of the source quadrant and the target portion is at least similar includes an indication of how many and which of the source quadrant is determined to include at least similar design data in the design data in the target portion can do. The result of the determination step may also include at least x and y offsets between each source quadrant and the target portion in the target portion where similar design data is found. Whether or not the source defect is grouped with the target defect is determined by determining how many and which of the source quadrant are determined to include design data at least similar to the design data in the target portion, Based on the offset between the source quadrant and the target portion within each source.

In some embodiments, the design data in each source quadrant and target portion includes design data for one or more design layers. In this manner, the method includes at least checking one design layer for similar design data to bin the defects, or at least checking a set of design layers (e.g., multi-layers) for similar design data to bin the defects Step < / RTI >

Regardless of whether the design data in the source quadrant is at least similar to the design data in the target portion, the method includes comparing each source quadrant with another portion of the design data near the location in the design data space of the other defect May also be included.

In such an example, the design data in the source quadrant 140, 142, 144 and 146 is compared to the portion 154 of the design data (not shown) close to the location of the defect 156 in the design data space 138 . The design data in the source quadrant and portion 154 can be compared as described above. The method also includes determining whether the design data in each source quadrant is at least similar to the design data in the portion 154, which may be performed as described above. As shown in the overlay 158, two of the quadrants (e.g., quadrants 144 and 146) have design data at least similar to those in the portion 154 at the quadrant location shown in overlay 158 . Thus, the method can determine if the design data near the location of the defects 136 and 156 in the design data space is less similar to the defects 136 and 150. Whether the design data near the location of the defects 136 and 156 in the design data space is sufficiently similar to the defects 136 and 156 to bin the same group can be determined as described above.

In such a different example, the design data in the source quadrant 140, 142, 144 and 146 is compared to the portion 160 of the design data (not shown) close to the location of the defect 162 in the design data space 138 . The design data in the source quadrant and portion 160 can be compared as described above. The method also includes determining whether the design data in each source quadrant is at least similar to the design data in portion 160, which may be performed as described above. As shown in the overlay 164, two of the four quadrants (e.g., quadrants 142 and 144) are aligned with the portion 160 of the design data at the location of the source quadrant shown in overlay 164, It is determined to include similar design data. Thus, the method can determine if the design data near the location of defects 136 and 162 in the design data space is less similar than the design data near the location of defects 136 and 150 in the design data space. Whether or not the design data close to the location of the defects 136 and 162 in the design data space is sufficiently similar to the defects 136 and 162 to bin the same group can be performed as described above.

The quadrant information determined as described above can be stored and / or displayed. This information can be used for setup, verification, and repair of errors.

The method may dynamically compile a table, list or other data structure of a specific pattern in the design data, and may compare portions of the design data near the location of the defects in the design data space to patterns in a table, Tool classification of systematic defects and Newson defects (e.g., in the case of non-real defects or uninteresting defects). The dynamically generated pattern set (or set of static patterns) may be stored in a data structure such as a library with a design-based classification (DBC) associated with each pattern. In this way, the DBC can define the group in which the defect can be binned, and the unique pattern can include POI design examples. As such, the design data close to the design data space defect location is compared with the specific pattern in the pattern set generated dynamically, not the design data close to other design data space defect locations. For example, one embodiment that may utilize such data structures (which may or may not be dynamically generated) is a computer-implemented method for assigning categories to defects detected on a wafer, as described below.

Further, in some embodiments, the computer-implemented method is performed by a testing system used to detect defects. In this way, the step of binning the defect can be performed as an "on-tool ". One advantage of the method is that the time to results can be fast. The method may be performed at any time after the defect is detected (e.g., during an inspection during or after another defect is being detected, during analysis of a test result, during review, etc.) on-tool. In addition, the location of potential systematic defects or systematic defects (hot spots) and the data used for binning may be stored in a data structure (e.g., a hot spot database) and used for inspection comparison (monitoring). Thus, the binning can be performed during the inspection to provide a better classification (binning, filtering or monitoring for the search).

In an alternative embodiment, the computer implemented method is performed by a system other than the inspection system used to detect defects. In this manner, the method embodiments described herein can be performed "off-tool ". Systems that perform this method with an off-tool are well known in the art such as, for example, a microscope (optical or electron beam), a review system, a system without a wafer loaded (e.g., an independent computer system) And any other suitable system known. For example, the method may be performed after defect detection during a second pass of a wafer in which a microscope is used to obtain an image of at least a portion of the detected defect. Such image acquisition can be performed using an optical microscope since the electron beam microscope can not capture some defects (e.g., defects that are not visible to the electron beam microscope such as defects located under the top surface of the wafer). Image acquisition is performed off-line and can be used to provide better sampling of defects for review. The binning of defects can be used to analyze and sample defects as further described herein.

In some embodiments, the method includes identifying a hot spot in the design data based on a result of the binning step. In this way, design-based binning can be used for navigation of hot spots. In addition, the search of hot spots can be performed with an on-tool. The method may include generating a data structure that includes one or more attributes of the hotspot, such as the hotspot, location, design data near the location of the hotspot, and the like. The data structure may include lists, databases, files, and the like. Hot spots can be used for hot spot management (possibly on-tool). Hot spot management may include searching for hot spots, which may be performed as further described herein. In addition, hotspots discovered by design-based binning can be used as inputs for design scans, PWQs, DOEs, and reviews. Alternatively, the hot spots used in the methods described herein may be explored using any other method and system known in the art, such as a reticle inspection system.

FIG. 20 illustrates one embodiment of an input to and output from a module 166 configured to perform a computer-implemented method for binning a detected defect on a wafer in accordance with the embodiments described herein. Module 166 may be configured to function as a GDS pattern checker (the location of design data near the design data space location of any two defects or the accuracy checker of the design data) and / or the similarity checker (non-accuracy checker). The module is configured to perform one or more of the steps described herein with an on-tool or an off-tool. For example, a module may be configured to perform one or more of the steps described herein with an on-tool post-process (e.g., on-tool, post-defect detection). The module may also be configured to perform one or more of the steps described herein during defect detection. If a module is configured to perform one or more of the steps described herein with an on-tool, the module may be configured to perform other functions described herein, such as defect organization.

The input to module 166 includes a defect list 168. In one embodiment, the defect list 168 may include defect information, such as information contained in a KLARF file or other standard file that may be generated by the inspection system. The input to the module may also include coordinate conversion information, which may be determined as described above, and design data. In such an embodiment, the module 166 may be configured to convert the location of the defect in the defect last 168 as reported by the inspection system to the location of the defect in the design data space.

Alternatively, module 166 may be configured to perform functions within a wafer space by accessing transformed design data space coordinates provided through other software modules (software modules configured to perform translation functions). In another alternative, the defect list 168 may include the location of a defect in the design data space. In such an embodiment, the defect location reported by the inspection system can be translated by another software module into a defect location in the design data space. Such defect information may be entered into module 166 either on the same computing hardware or between sets of networked computing hardware, in a suitable data file format, or via programming means, either within the process or via inter-process communication. In this manner, the defect information may be provided to the module 166 by another system via a transmission medium that couples the module to another system. The transmission medium may comprise any suitable transmission medium known in the art, and may include "wired" or "wireless" transmission media, or some combination thereof.

Additional inputs (not shown in FIG. 20) may be provided in module 166 that may be used by the module to perform one or more of the steps of one or more of the embodiments described herein. Additional inputs include electrical inspection data, defect information for one or more wafers, hot spot or weak spot information ("wickspots" are model-based simulations such as, without limitation, post-opc verification software, , A search window size (e.g., a dimension of the design data portion that is close to the location of the source and target defects in the design data space as described above) , Or some other criteria (e.g., similarity threshold) for similarity, or some combination thereof, and / or design data information that is available .

In addition, the hot spots can be grouped in advance based on the design data. For example, hot spots located at least close to similar design data are correlated, and the method and system embodiments described herein can perform such correlation of hot spots. The correlated hot spots can be used to bin defects as further described herein. In such an embodiment, module 166 may be configured to group defects into groups such that the defects in each group have positions in the design data space that are at least similar only to locations of hot spots that are correlated with each other. In this way, the module can be configured to bin defects without using design data. In addition, one or more attributes of the correlated hot spots may be determined for later analysis (e.g., yield information such as KP may be determined for correlated hot spots). In this way, when a defect is binned into a group corresponding to an interconnected hot spot, the module may report the expected yield impact determined for the correlated hot spot for the defect group.

Module 166 may be configured to function as a GDS pattern checker by "checking" design data that is close to the location of another defect in the design data space and binning the defect in defect list 168. In this manner, the module 166 can be configured to group defects into groups such that the defects in each group are located in a design data space that is close to the matching design data. Module 166 may also be configured to function as a similarity checker by checking the similarity of the design data near the location of other defects in the design data space and binning the defects in the defect list 168 .

The output of the module 166 may include an output 170. The output 170 may include x and y coordinates of the defect location as reported by the inspection system, x and y coordinates of the defect location in the design data space, identities of the group where the defect is binned into the same group (e.g., , 3, a, b, c, etc.) (e.g., if defects are binned in the same group, their identities may be the same) and match design data in the center and source portions of the target portion, Lt; / RTI > in the x and / or y direction between the centers of the regions in the target portion where the target portion is located. The output may include one or more data structures having any suitable format (e.g., a simple text file format) known in the art. The output may also be stored in any suitable storage medium known in the art such that its output can be accessed and / or analyzed at a later time. The outputs may be stored and used as further described herein.

21, the output of the module 166 may be designed such that the design data near the location of each defect in the design data space is close to the location of each other defect in the design data space (e. ≪ RTI ID = 0.0 & And may include a table indicating how similar (e.g.,% similar) to the data. In the example shown in Fig. 21, the portion of the design data close to the positions of the defects 1 and 2 in the design data space is 40% similar, but the position of the design data near the positions of the defects 1 and 3 in the design data space Is 95% similar. In this way, the method can use the output shown in Figure 21 to determine which defects to bin into the same group. For example, if parts of the design data near the location of the defects in the design data space are more than 90% similar, the defects can be binned into the same group. 21, the portion of the design data close to the position of the defect 1 in the design data space is 90% or more of the portion of the design data close to the positions of both defects 3 and 4 in the design data space. The above is similar. In this way, defects 1, 3 and 4 can be binned into the same group.

In another example, as shown in FIG. 22, the output of module 166 may include a graph (e.g., a bar graph) showing the number of defects (e.g., defect count or frequency) as a function of different groups. Each different group includes defects located at design data space locations that are close to the same or at least similar design data as described above. In this way, the output shown in Figure 22 provides information as to which pattern in the design is more defective. The chart may provide an error pattern type by various design contexts (e.g., background pattern context by function block). The information in the Chad can be further divided into annular or angular regions, as further described herein, to provide information on the spatial distribution of defects located within the design data space close to the common design pattern. This information and similar or other information may be used to perform one or more steps of the methods described herein (e.g., defect sampling based on background pattern context). Additional information regarding the defects binned into each group may be determined using any of the steps of any of the methods described herein.

Module 166 may provide output in only one format as shown in Figures 20-22. However, the module may provide more than one output of the format shown in Figures 20-22.

Additional examples of other inputs and outputs of module 166 are shown in FIG. As shown in FIG. 23, one input to the module 166 may include a wafer map 172 indicating the location of detection defects on the wafer. The wafer map can be generated by the inspection system. The wafer map may indicate the location of defects on the wafer, but not any other information about defects. For example, the bar graph 174 corresponding to the wafer map 172 represents all of the detection defects in a single group corresponding to the layer of the tested wafer.

The output of the module 166 may include a wafer map 176 that indicates the location of detected defects on the wafer and defects that are binned into the same group may have the same characteristics (e.g., Symbol). Defects can be binned as further described herein (e.g., automatic grouping of defects by a common GDS layout). In this manner, the wafer map 176 indicates the location of the individual defects on the wafer and the group into which the individual defect is binned. The output can be transmitted and used by a spatial signature analysis (SSA) tool, such as the KLARITY DEFECT SSA, commercially available from KLA-Tencor, to enhance monitoring and root cause determination.

The output of the module may include a stacked die map, a stacked reticle map, or a stacked wafer map, where defects are marked to represent a pattern group. Lamination maps can be used to illustrate that systematic defects tend to occur statistically across multiple dies, reticles, or wafers, and are useful for identifying spatial signatures. In addition, any output of the modules described herein may also include one or more GDS clips, one or more SEM images, one or more optical images, or some combination thereof. The output of the module may be represented by the same user interface in a user interface embodiment further described herein.

The bar graph 178 corresponding to the wafer map 176 represents the number of defects binned in each group. Also, the layout pattern signature corresponding to each group of defects is the same as the bar graph. In this way, the bar graph shows the pattern in the design that shows (or causes) the most defects. For example, a relatively large number of defects binned in a group of layout pattern signatures (2) indicate a potential pattern dependent error mechanism corresponding to the layout pattern signature. This information can be used to perform one or more steps of the method described herein (e.g., defect sampling based on design background context). Additional information regarding defects that have been grouped may be determined using any of the steps of any of the methods described herein. Module 166 may generate an output that includes wafer map 176 and bar graph 178. The output of the module may be represented by a user interface such as one of the user interface embodiments described further herein.

One example of how the output of module 166 can be used in the method described herein is the correlation of different defects with different density regions in the device layout. For example, the device layout may be partitioned into different areas. The different areas can be determined based on the design pattern density of different areas of the device, as shown in Fig. In one example, the main cell block in the device may be partitioned into different areas. In another example, the device layout can be automatically partitioned based on the density of various device structures (e.g., contacts, vias, metal lines, etc.) across the device layout. In one embodiment, the method embodiment described herein includes determining a defect density for another portion of the design data. For example, the method described herein may use information about the compartmentalization of the device layout to determine the defect density of other portions of the cell in the design data. In such an example, the number of defects detected in each area in the design data can be determined. Such information may be plotted into a bar graph or any other suitable output format.

In another example, the module 166 divides the design data into "functional blocks" or "cell blocks. &Quot; Cell blocks are defined within the design data and identify the boundaries of the main and lesser major sub-cells of the design such as input / output (I / O) blocks, digital signal processor (DSP) The module determines the frequency of defects in each cell block. In this way, it can be determined whether the major or less major cells in the design are more or less sensitive to yield issues.

The embodiments described herein may use statistical approaches to determine the design cell in which the defect is located. For example, in some embodiments, the method may include determining if the defect is a systematic defect, determining if more than one systematic defect is located in at least one portion of the design data, and if there is a correlation between systematic defects and potential And determining if the received message is a response message. In particular, as described further herein, design data (i.e., hierarchical design data) can be used in combination with the location of defects in the design data space to determine the hierarchy of defects in the design data, such as cells in the design data have. As further described herein, the hierarchy in the design data can be used to determine which portions of the design data may or may not be used for yield improvement. One difficulty in determining the layer of faults is that the smaller the cell, the smaller the size of the cell is than the coordinate accuracy of the inspection system, thereby reducing the accuracy with which the cell in which the defect is located can be determined. To overcome this difficulty, statistics can be used to determine the probability that a defect is located in various parts of the design data (the probability that each defect is located in a different cell). In this way, for systematic defects, statistics can be used to determine if there is a correlation between the probability that a defect is located in various parts of the design data and a systematic combination.

In another embodiment, the input provided to module 166 may include design data (e.g., GDS layout), inspection data (e.g., physical defect data), and optionally memory bitmap and / or logic bitmap. A module may use some or all of its inputs to perform one or more additional steps such as, but not limited to, searching, characterizing, monitoring, and disposition (e.g., making one or more executable decisions). The module may be configured to perform the steps described above in addition to one or more of the following steps: generating a hotspot / weakspot data structure, using the design data to identify defects (e.g., defects detected by optical or electron beam inspection systems (E.g., a defect detected by an electrical inspection indicated by a bitmap), a review sample plan, optimization of an inspection recipe, modification of a review recipe (e.g., decision to review), optimization of review recipe , By changing the defect analysis recipe (e.g., by design context, in combination with the inline FIB process and / or any other information described herein as possibly to be analyzed during the FA process), optimizing the defect analysis recipe, Generating a sampling recipe for the FIB process, an EDX process, or other defect analysis process, generating a sampling recipe for the metrology process, DOI and possibly one or more attributes of the DOI such as type and location. In addition, any of the sampling plans or sampling recipes described above can be dynamically determined based on the results of the binning. In such an example, the module may be configured to analyze design data or to obtain analysis results of design data, such as results from DRC, to predict potential DOIs that may be detected in inline defect data and bitmap data .

As described above, the module 166 may be configured to generate a data structure, such as a database. For example, in some embodiments, the method includes generating a data structure comprising a location of systematic defects and potential systematic defects within a design data space, and one or more attributes of systematic defects and potential systematic defects. Such a database is generally referred to as a "hot spot" database. The database may include information about a week spot, a coordinating hot spot, and a cold spot (non-critical areas of the design data that have little or no yield impact, such as a dummy structure, a dummy fill area, etc.) . The database may include locations of potential defects and actual systematic defects and other attributes (e.g., design context, KP, other yield characteristics, etc.).

The data in the hot spot database can be acquired from various sources. For example, the database may be configured as a flexible database that contains data about systematic issues from all (or at least some) possible sources. For example, some of the inputs to the module may be included in the database. In such an example, the inspection results (e.g., PWQ results, defects detected by BF and / or DF inspection, memory bitmaps, logic bitmaps, etc.) may be included in the database. In some embodiments, the database may include design rules for one or more semiconductor manufacturing processes, such as lithography and CMP. In another embodiment, the database may include simulations performed on design data such as the results of an OPC simulation. In this manner, multi-source correlations can be used to identify hot spots and systematic defects.

As described above, the method includes binning a defect based on design data. In one such embodiment, the method described herein includes determining if the defect is a Newson defect based on one or more attributes of the design data. In this way, Newson's defects can be identified based on the context information. In some embodiments, the method includes removing a portion of the defect from the result of the inspection process in which the defect was detected, based on design data close to the location of the defect, to increase the S / N of the inspection process result . In this way, information about the design located close to the location of the defects in the design data space can be used to reduce the noise in the inspection results, thereby increasing the S / N of the inspection results. For example, a defect in a non-functional area of a design may be binned into a group and filtered as a newsworth from the inspection results before the inspection results are used for subsequent analysis. In another example, the defects can be separated based on whether the defect is located in the region of interest or the non-region of the wafer. In a further example, a defect located in a part of the design that is systematic but known to cause Newson's defect (e.g., non-DOI) may be removed from the test results to increase the S / N of the result for the DOI. One or more portions of the design known to cause Newson defects can be determined by the user and stored in a data structure such as a design library. For example, portions of the design known to cause Newson's defects may include polygons that the user has chosen to use for supervised binning. Also, if the POI is defined prior to performing the binning method, the binning method may perform the supervised binning using the specified POI. Alternatively, the POI may be determined by a method as further described herein. The method described herein may include performing supervised binning on the inspection system and excluding the Newson defect from the inspection results.

Increasing the S / N of the test results by removing a part of the defects as described above may be advantageous for the post-treatment of test results. For example, removing a portion of the defect (e.g., a defect that does not affect the yield) may be performed prior to the binning of the defect and may increase the S / N of the binning result for a defect of the type of interest. In addition, when the S / N of the result is high and contains a small amount of noise, the analysis of the test result of the method described herein can be quick and more accurate. In one particularly advantageous example, in the PWQ method, the main source of noise is the line end shortening (LES) detected as a defect. However, LES generally does not have a significant effect on yield. Thus, the user does not pay attention to the LES and since the LES may appear as a relatively large number, the detected LES may overwhelm other defects more relevant to the yield. As such, removing the detected LES from the test results, as described herein, is particularly advantageous for further processing of the test results. Defects may include defects detected by optical or electron beam inspection systems. Further, as further described herein, an inspection recipe may be generated based on a design context to distinguish these defects during inspection. In this way, the methods and systems described herein can be used to detect many DOIs, suppress many Newson defects, and generate inspection recipes that can classify systematic and random defects and patterns based on binning of systematic defects .

In another embodiment, the method includes reviewing at least a portion of a defect of one or more groups and determining one or more groups corresponding to the Newson defect from the result of the inspection process in which the defect was detected to increase the S / And determining if the one or more defects correspond to Newson's defects. The step of reviewing at least a portion of the defects may be performed as described herein or in any other suitable manner known in the art. The determination of whether one or more defect groups correspond to Newson's defects can be performed using any review results in any suitable manner. If one or more of the defect groups corresponds to a Newson defect, the one or more groups may be removed (filtered) from the test results to increase the S / N of the DOIs in the test results.

As described above, the embodiments described herein can advantageously use defect locations in design data and design data to bin defects as opposed to background information and / or defect information as printed on the wafer. However, design data in the design data space may be used in combination with other information to bin the defect (e.g., for better separation between defects that have been binned into different groups). For example, in one embodiment, the step of binning defects may be performed in a manner such that the locations of design data that are close to the locations of defects in the design data space of each group are at least similar and one or more attributes of defects in each group are at least similar, Group into a group. The attribute of the defect may include any of the attributes described herein. In addition, the defect attribute may include any defect attribute that can be determined from the inspection result. As such, the binning step may be performed using a combination of design and one or more attributes. In this way, the method can separate defects into groups based on design data and defect attributes. Thus, different types of defects located in the design data space within portions of at least partially similar design data can be isolated. Such a binning step can be advantageously used to identify the rate at which different defect mechanisms occur and the different defect mechanisms within the design data area. In another embodiment, a portion of the design data that is close to the location of the defect may include design data where the defect is located. That is, portions of the design data compared for the binning may contain defective "rear" design data. In this manner, the binning may include structure binning by use of the structure in the design data where the defect is located. Such binning can perform binning for defects where the defect location is reported with a relatively high coordinate accuracy, such that the probability that the correct structure is used for binning is relatively high. Since the design data used in this embodiment is not the design data as printed on the wafer, it is possible in the embodiments described herein to use the defect "rear" design data. In contrast, defects on the wafer can obscure the design data printed on the same location on the wafer or in areas around the defect, which further degrades the accuracy of the method for defect binning based on design data as printed on the wafer can do. In another embodiment, the portion of the design data near the location of the defect used in the embodiments described herein includes design data around the location of the defect. In addition, the binning can be performed using a structure in which the defect is located and a structure around or close to the position of the defect in the design data.

As described above, the binning can be performed without considering the position of the defect in the portion of the design data. Such binning is particularly beneficial for defects detected by inspection systems that report defect locations with relatively low accuracy. In addition, such binning can produce a binning result of substantially high accuracy while providing important information such as which portions of the design data exhibit particularly high defects and / or particularly high defect rates. However, in a further embodiment, the binning of the defects is such that the portions of the design data that are close to the location of the defects in each group are at least similar and the defects in each group to the polygons within the portion are at least similar, . In this manner, the binning can be performed using a combination of a portion of the design data near the location of the defect in the design data space and a location of the defect in the portion of the design data. As such, the binning may be performed based in part on the location of the defect in the structure. In other words, the binning can be performed based on the position of the part of the defect in combination with the design data close to the inter-part position. Such binning is preferably performed for defects where the position is reported with a relatively high coordinate accuracy such that a substantially correct inter-part position of the defect is used for the binning. In this manner, defects that affect the device in different ways due to different inter-part positions can be separated, although they are located in the same part of the design data. For example, using such a binning, a defect located between two features in one portion of the design data and having a relatively high probability of causing an open in the device is located entirely within one of the two features, Can be separated from defects that are much less likely to cause it. Thus, such binning can be advantageously used to identify defects in which different yield impact defects occur and yield impacts on one area of the design data are different.

In some embodiments, binning the defects so that the portions of the design data that are close to the location of the defects in each group are at least similar and the hotspot information about the portion of the design data that is close to the location of the defects in each group is at least similar. . Hotspot information may include any hotspot information described herein or any other hotspot information known in the art. Hotspot information may be determined for different parts of the design data as further described herein. In this way, the method can perform binning using a combination of design data and hotspot information. In such an example, before the method is performed, the hotspots in the design data with similar effects on yield can be binned as described above. Thus, defects can be binned based on design data similarity, and the resulting defect groups from this binning can be separated into sub-groups of similar defects in yield impact. In such an example, for example, if a portion of a location is located above or below non-similar design data, then at least portions of similar design data may not be associated with the same hotspot information. As such, defects located close to at least similar portions of the design data can be separated based on hot spot information for each portion of the design data. In this way, the overall yield of the process used to make the wafer can be quickly and accurately evaluated. Hotspot information can also be used for binning to check or verify whether the similarity of portions of the design data has been accurately determined. For example, if at least a portion of the design data determined to be similar is not associated with at least similar hotspot information, defects corresponding to portions of the design data may not be binned into the same group.

In another embodiment, the method is based on at least one attribute of the design data near the location of the defect in the design data space, one or more attributes of the defect, or a combination of some of them, whether the defects in one or more groups are systematic defects or random defects And determining whether or not there is a difference. In this manner, the method may include collectively grouping defects into groups. For example, systematic defects can be grouped into Newson's defects or defects of interest. However, such classifications can be performed on individual defects. The nature of defects that can be used to determine whether a defect is a systematic defect or a random defect can be determined, for example, if the defect is at approximately the same location in the die in one or more of the dies, The distribution of one or more defects may be sequential and / or dense. In one example, defects that appear only on one die on the wafer can be classified as random defects, and defects that appear on multiple dies at nearly the same location can be classified as systematic defects. Thus, the method described herein can be used to determine the cause of defects detected on the wafer by the inspection process (in-line inspection process and / or electrical inspection process) using information about the defect.

In some embodiments, the method comprises classifying defects of one or more groups based on review results of at least some defects in the one or more groups, one or more attributes of design data, one or more attributes of defects, or some combination thereof . Reviews of at least some of the defects in the one or more groups may be performed as described herein or in any suitable manner known in the art. One or more attributes of the design data or one or more attributes of the defects may include any of the attributes described herein. In this manner, defects can be grouped collectively as a group based on the amount of substantial information, thereby providing a relatively fast and relatively accurate defect classification.

In another embodiment, the method includes determining whether a group to which the defect is benigned includes a systematic defect or a potential systematic defect, as described herein. In this way, defects can be grouped collectively as systematic defects or potential systematic defects. However, defects can be classified individually as systematic defects or potential systematic defects. For example, a defect can be classified in this embodiment based on the position of a defect with respect to a polygon in the design and whether the hot spot, the cold spot, and the like are located at substantially the same position. Thus, the method described herein can be used to determine the cause of defects detected on the wafer by the inspection process (in-line inspection process and / or electrical inspection process) using such information as design data.

In some embodiments, the method includes monitoring systematic defects, potential systematic defects, or some combination thereof over time using the results of the binning step. For example, the results of the binning phase may be used to identify systematic issues in the design data, and the identified systemic issues may be monitored for re-emergence across the wafer and / or over time. Monitoring systematic defects and / or potential systematic defects may be performed using any result of any of the methods described herein.

In addition, monitoring systematic defects and / or potential systematic defects may be performed in a manner similar to the statistical process control (SPC) method. For example, monitoring the systematic defects, potential systematic defects, random defects, or some combination thereof can be used for yield-based SPCs where different SPC methods and / or algorithms are used for different types of defects. In such an example, the SPC parameters can be used to monitor different types of defects and the SPC parameters can be determined or selected based on the potential yield impact of different types of defects that can be determined as described herein. In this way, different types of defects are monitored simultaneously for SPC, at different SPC parameters. In another embodiment, only a subset of defects detected by inspection can be used for the SPC. For example, only non-Newson systematic defects and / or potential systematic defects can be monitored for SPC purposes so that the process can be monitored for design-based process margins. In a further example, only systematic defects determined to have a potentially large impact on yield can be monitored for SPC so that changes in the yield of the manufacturing process caused by changes in defects can be detected relatively early on have. In addition, using other methods to estimate the yield impact of systematic defect groups and random defects can advantageously provide more accurate prediction, monitoring, and control of yield related issues. In this manner, the method can be used to provide information about the manufacture of a device that can be used to monitor and improve manufacturing yields (e.g., an increase in systematic defects over time, a decrease in systematic defects over time, And the like) can be provided.

In one embodiment, the method may include determining the cause of a pattern-based defect (e.g., a systematic defect). For example, if one or more pattern-based defect groups are dominant, the method may include obtaining in-line inspection data and / or electrical inspection data for a plurality of different wafers for the same layer and the same device. For example, inline inspection data and / or electrical inspection data may be obtained for about 100 to about 1000 different wafers. Such data may be obtained from a storage medium such as a defect database or a fab database. If such data is not available, the method may include inspecting a wafer that has already been processed in a process performed on a wafer for which systematic defects have been detected, and then generating such information and then inspecting the wafer.

The method may include performing pattern-based binning of detected defects on additional wafers, which may be performed as described herein. The method may include determining if at least one pattern-based defect group is dominant for an additional wafer. If additional wafers exhibit commonality of dominant pattern-based defects, such a method may include determining whether the wafers have been processed through common equipment (or process tools). In this way, the method can perform equipment commonality analysis. The method is based on the assumption that the dominant pattern-based defect group is a specific equipment, a particular chamber (e.g., equipment or chamber whose parameters drift for some reason). Or a particular root-step (e.g., an integrated issue between equipment and two or more steps). If a dominant pattern-based defect group is associated with a particular device or a particular chamber, the cause of the pattern-based defect group is isolated and possibly identified. The method may include stacking data to determine if there is a spatial signature for the group of interest. Spatial signatures can be useful in locating or determining the cause of process issues, OPC issues, or design related systemic issues, or combinations thereof.

If a dominant pattern substrate defect group can not be associated with a particular equipment or a particular chamber, the method may include performing data mining to attempt to correlate defects with other process factors. Data mining may be performed in any suitable manner known in the art based on any information regarding defects and design data, and any information generated during device fabrication, which may be stored on one or more storage media, such as a fab database . If a relatively strong correlation is identified between one or more other process factors and the defect, the process factor associated with the defect can be identified as the cause of the defect. If the relatively strong association between the one or more process factors and the defect can not be identified, the method may include performing an arbitrary pattern search of the design for the potential POI, determining a new inline hot spot And building up the monitor. However, when process conditions are excluded, the process itself or the design itself must be evaluated and, if necessary, adjusted to reduce or eliminate the problem. Also, by comparing the attributes of a systematic defect to the outcome of the process window mapping, it is possible to refer to possible sources and / or root causes.

The method may use information on systematic defects and / or potential systematic defects to perform data cleanup. For example, there may be 50,000 to 200,000 or more hot spots generated by a full-die pattern based search for a single POI or from experimental techniques such as electrical function tests and lithography PWQ results. Thus, in order to process and analyze this data in a meaningful and timely manner, a data processing technique may be performed on the data. In such an example, for pattern-based hotspots, the method may include binning the hotspots into a "similar" group. For example, each group may include hotspots located close to at least similar patterns in the design data and / or close to design data having at least one similar property (e.g., hot spots located in a relatively low pattern density region of the design Can be binned into one group). As such, the method may include binning a hot spot based on design context and / or design attributes. In a further example, in an empirical technique such as PWQ, the method may include removing defects near the location of the design (cold spot) with little or no yield impact from the defect population from which review sampling is performed. By performing the data cleanup as described above, it is possible to generate better (e.g., more yield related) review samples using the summarized data as further described herein.

The methods and systems described herein may include CBI in combination with design-based and yield-based post-processing (performed with on-tool or off-tool). For example, after Newson's defects, systematic defects and random defects are identified, the defects can be organized in some way (e.g., using a defective organizer (DO) or an inline defective organizer (iDO)). In one example, the results are stored in a data structure such as a database. In another example, as described above, after a defect is binned based on the position of the design data near the position of the defect in the design data space, the defect in the group is classified into one or more attributes of the design data close to the position of the defect in the design data space , One or more attributes of the defect, or some combination thereof. Defects can be separated based on one or more attributes of design data and / or one or more attributes of defects using iDO. In this way, design-based binning can be used in combination with the iDO in the embodiments described herein. In particular, the output of the design-based binning can be input to the iDO.

One or more attributes of the design data, which are used to further separate the defects into grouped defects based on the design data, may include one or more attributes of the pattern or structure in the design data near the location of the defects in the design data space, A pattern density close to the location of the defect in the space, a functional block in which the defect is located, and one or more attributes of the device (e.g., n-MOS or p-MOS). One or more attributes of a defect used to further separate the binned defect include, but are not limited to, size, shape, brightness, contrast, polarity, and texture.

The results of design-based binning and iDO can be shown in a bar graph. The bar graph may show the number of defects in the sub-group as a function of the pattern and pattern in the design data in which the total number of defects versus defects was detected. Using design-based binning in combination with iDO, as described above, can be used to separate random and systematic defects, prioritize defective groups, and / or identify and possibly make changes that must be made to the design data May be used to prioritize (e.g., using the potential yield impact of the defect group, which may be determined as described further herein). In particular, the values provided by design-based binning for separation of systematic and random defects can be increased using iDO for further separation of systematic (and possibly random) defects. In addition, the values that design-based binning provides for the separation of systematic defects and random defects can be increased by using yield associations, possibly in combination with iDO, for the separation of systematic (and possibly random) defects.

In this manner, the systematic defect population and the random defect population can be handled independently (e.g., the systematic defect population and the random defect population can be sampled separately). Different populations or other information about systematic and random defects may be used to produce individual results for systematic defects and random defects. For example, systematic defects and random defects can be shown in different bar graphs, or different graphs or textual representations, that can be automatically processed and / or used by the user. After defect sampling for review, some of the systematic defects, and optionally random defects, can be reviewed using a suitable review system (e.g., a relatively high magnification optical review system or SEM). Defect review results can be used to normalize the defect density of both systematic and random defects. The methods and systems described herein provide several advantages to the user. For example, the method and system provide sufficient baseline yield enhancement, better excursion detection, improved review system efficiency, more effective root cause detection, and improved knowledge retention. In addition, the results of the embodiments described herein may include various other types of information useful to the resulting consumer (e.g., a customer of the device manufacturer). Such other types of information may include information such as process tool owners, designers, integration engineers, and the like.

It is also estimated that more than 50% of the yield loss in the 90nm design rule is caused by systematic issues. Likewise, systematic yield issues are significant in the 90nm design rule, and dominant in the 90nm design rule. Thus, separating systematic defects from Newson defects and random defects as described herein allows for better evaluation, analysis, and control of systematic issues. In addition, the location of systematic defects can be compared to the location of functional blocks in the design data. In this way, systematic defects are correlated to one or more functional blocks, and this information can be used to improve S / N. In particular, the method may include separating defects based on functional blocks in which defects are located to improve S / N. In a similar manner, the method may include isolating defects based on hierarchical cells in which the design data is organized by design. Thus, in order to improve the S / N, defects that are grouped and / or DBC allocated can be separated based on functional blocks (or any hierarchical level) where the defects are located (e.g., memory or logic) have. The portion of the design data used in the embodiments described herein may correspond to any cell structure or hierarchy of cells.

The percentage of defects per functional block can be determined by the method described herein. In this way, functional blocks including design issues can be identified based on the percentage of defects detected in each functional block and / or grouped into groups corresponding to the functional blocks. Additional information about the defects located in the functional blocks can be used to identify design issues within each block. The information can be used to select and / or prioritize design issues for correction based on how many defects can be eliminated by correction. For example, if it is determined that about 70% of the defects are caused by four design issues in four different functional blocks of the design, only these four design issues may be selected for correction, or these four design issues may be arbitrary The others may be selected for correction before being corrected (e.g., prioritizing design issues based on the number or percentage of defects caused by design issues). A user (e.g., a chip designer) can select a cell design to use, select a cell design that exhibits historically less systematic defects, and such information about the cell design can be generated using the embodiments described herein .

In another embodiment, the method includes prioritizing one or more POIs in the design data and optimizing at least one of the one or more POIs based on the results of the prioritizing step. In one such embodiment, the POI may be prioritized based on the number of defects detected in the POI. The number of defects detected in each POI can be determined, for example, by comparing at least one attribute of the POI or POI to a design data portion corresponding to the group and comparing at least a portion of the design data (or a portion of the design data By assigning to the POI the number of defects in the group corresponding to the number of defects in the group corresponding to the number of defects in the group. In this way, the POI with the largest number of defects detected is assigned the highest priority, and the POI with the next largest number of defects detected is assigned the next highest priority.

In another embodiment, the method may include prioritizing one or more systematic fault types (e.g., by changing process parameters, design, OPC, etc., or a combination thereof) for yield optimization. In one such embodiment, the systematic fault type can be classified as a POI or POI group, and the POI can be prioritized based on the number of defects detected on or near the POI. The priorities can be further enhanced using the threshold of systematic faults detected at the POI, the frequency of the POIs in the design, and the degree of detection of the POIs for process variations, in order to prioritize systematic faults.

In addition (or alternatively), the POI may be prioritized based on any other result of any of the steps described herein, or any combination thereof. For example, prioritizing the POI may include determining a defect threshold index (DCI) for one or more defects detected in the POI and prioritizing the POI based on the DCI for the one or more defects have. The DCI may be determined in this embodiment as further described herein. In another example, prioritizing the POI includes determining a KP value for one or more defects detected in the POI and prioritizing the POI based on the KP value for the one or more defects . In another example, the POI may be prioritized based on the number of defects detected in or near the POI and the DCI for one or more defects detected in or near the POI. In this manner, prioritization of the POI may include prioritizing the POI based on the defect indicated by the POI so that a high priority POI is assigned a higher priority.

In addition, the POI may be identified and / or prioritized based on one or more attributes of the POI, possibly in combination with other results described herein. The one or more attributes of the POI may include, for example, the dimensions of the features in the POI, the density of the features in the POI, the type of feature contained in the POI, the location of the POI in the design, the sensitivity of the yield impact of the POI to the defect, . ≪ / RTI > In such an example, a POI that is more sensitive to yield impact due to defects may be assigned a higher priority than a POI that is less sensitive to the impact of defects on yield.

In addition, the POI may be prioritized based on one or more attributes of the design, possibly in combination with one or more attributes of the POI and / or other results described herein. One or more attributes of the design may include redundancy, electrical connectivity, electrical properties, etc., or some combination thereof. In particular, a cell in the design data may have a context that is more than a pattern contained within the cell. Such a context may include, for example, a hierarchy of cells, redundancy, and the like. Thus, the one or more attributes used in the embodiments described herein may include the context of the cell in which the POI is located, which may be determined based on the location of the POI in the design data space and / or the design data of the POI If the design data is specific to a cell in the design data). In such an example, a non-redundant POI (non-array) in the design data may be assigned a higher priority than a redundant POI (e.g., array). The POI may be prioritized based on the link redundancy between cells (e.g., routing or redundancy vias). Such a context of the design may be obtained and / or determined in any manner known in the art.

Wherein optimizing at least one of the POI based on the result of the prioritizing step includes altering any one or more of the attributes, such as the dimensions of the features of the POI, the density of the features of the POI, or any combination thereof . One or more attributes of the POI may be changed by changing the design data corresponding to the POI. Preferably, the POI is used to alter one or more attributes (e.g., DCI, KP, etc.) of the detected defect in the POI to reduce POI defects (e.g., the number of defects detected in the POI) / RTI > and / or < RTI ID = 0.0 > POI. ≪ / RTI > In addition, prior to the POI having a lower priority as determined by the prioritizing step, the POI having a higher priority as determined by the prioritizing step can be changed and optimized. In this way, the defects with the greatest impact on defects and / or yields can be altered and / or optimized before defects with low defects and / or yields are small. As such, the result of the optimization step indicates which POI can be changed and / or optimized to show the greatest improvement in yield, and the POI can be changed and / or optimized prior to another POI.

Thus, without timely guidance as to which POI has the greatest effect on yield, the design data and / or changes made to the manufacturing process are delayed, leading to slower improvements in yield and increased time to market The present embodiment is advantageous over the methods and systems used. In addition, although the POI changed at this stage includes only the POIs contained within the design printed on the wafer prior to the detection of the binned defect in the embodiments described herein, the modified POI is included in one or more designs to optimize the POI Gt; POI < / RTI > For example, if one or more design data includes a POI based on prioritization and / or any other result of the methods described herein, then the POI in the other design can be modified and optimized so that each different design Thereby increasing the yield of the device.

In a further embodiment, the method includes prioritizing one or more POIs in the design data and optimizing one or more RET features of the one or more POIs based on the results of the prioritizing step. The POI prioritizing step in this embodiment can be performed as described above. The optimized RET feature at this stage may include any RET feature (e.g., OPC feature) included in the design. The step of optimizing one or more RET features of the one or more POIs based on the results of the prioritizing step may include optimizing one or more RET features of the one or more POIs based on one or more attributes of the RET (e.g., dimensions of the RET feature, shape of the RET feature, ). ≪ / RTI > One or more attributes of the RET feature that are modified at this stage preferably include any attributes of the RET feature that will reduce defects in the POI and / or increase the yield.

In addition, optimizing the one or more RET features based on the results of the prioritizing step in the present embodiment may further include, prior to optimizing the RET feature for the other POI, the RET feature for the POI determined to have the highest priority And < / RTI > In this way, the RET feature of the POI with the highest priority can be changed before the RET feature of the POI with the lower priority is changed. In this manner, the RET feature of the POI that exhibits the greatest defect and / or the largest defect impact on the yield is modified and / or optimized prior to the RET feature of the POI where the defect and / . As such, the result of the prioritization step indicates which POI can be changed and / or optimized to exhibit the greatest improvement in yield, and the RET feature of the POI may be changed and / or modified prior to the RET feature of the other POI Can be optimized.

Thus, without timely guidance as to which POI has the greatest effect on the yield, the change to the design is delayed, the improvement in yield is slower and the time to market is increased, This embodiment is advantageous. Also, even though the RET feature of the modified POI at this stage includes only the RET feature of the POI included in the design printed on the wafer prior to the detection of the binned defect in the embodiments described herein, the modified and / or optimized POI The RET feature of the POI may include the RET feature of the POI included in one or more designs. For example, if one or more design data includes a POI having the same RET feature based on prioritization and / or any other result of the method described herein, the RET feature of the POI in the other design may be changed and optimized Thereby increasing the yield of the device manufactured with each of the different designs.

In some embodiments, the method includes modeling the electrical characteristics of the device fabricated using design data regarding the defective location, and determining the parameter relevance of the defects at the defective location based on the modeling result do. In this way, the result of the modeling step can be used to determine the parameter relevance of the defect. For example, the result of the modeling step can be used to determine how a defect changes one or more electrical parameters of a device being manufactured using the design. The defects for which the parameter relevance is determined as described above may be systematic defects. The parameter relevance can be used at any stage of the method described herein. For example, in combination with possibly other information described herein (e.g., one or more defect attributes, one or more attributes of design data, etc.), the parameter relevance may be determined by determining the DCI of the defect as described above, It is possible to use it for making.

In this embodiment, the step of modeling the electrical characteristics of the device may be performed using any suitable method known in the art. The electrical characteristics of the modeled device may include any one or more electrical characteristics of the device. The parameter relevance of defects can be determined using modeled electrical characteristics and designed electrical characteristics. For example, an electrical feature modeled to determine the degree to which a defect modifies an electrical feature may be compared to a designed electrical feature. The parameter relevance can be determined based on the degree to which the defect alters the electrical characteristic (e.g., a defect that alters the electrical characteristic to a large extent is more parametrically relevant than a defect that alters the electrical characteristic to a minor extent). The parameter relevance can be determined in a similar manner using the modeled electrical characteristics and the range of suitable electrical characteristics of the device. For example, the modeled electrical characteristic can be compared to its range, and whether the modeled electrical characteristic is within or outside the range can be used to determine parameter relevance. In such an example, if the modeled electrical characteristic is near or within an acceptable range, it can be determined that the defect is more parametrically relevant than if the modeled feature is within an acceptable range. The parameter relevance may be determined based at least in part on information from a plurality of different sources, including, but not limited to, simulations, optical inspection associations, defect review results, electrical test results, or some combination thereof.

In one embodiment, the method includes assigning priorities to systematic defects or potential systematic defects based on systematic defects and parameter relevance determined or related to potential systematic defects. For example, the priority or focus of the hot spot may be ranked based on the parameter relevance. The parameter relevance can dictate how defects in a hot spot will affect the electrical parameters of the device, or how many defects.

The parameter relevance can be used to isolate or prioritize defects that may further cause parameter issues (e.g., yield loss) for the device. For example, other information about the electrical characteristics of the device, such as electrical test results or resistance, capacitance, timing, etc., may be combined with one or more attributes of the design data near the location of the defects in the design data space and / So that it is possible to determine which defects affect the electrical characteristics of the device and which defects do not. Other information regarding electrical test results or electrical characteristics may be determined using the method (e.g., using simulations) or may be obtained from other sources (e.g., netlist information). In this way, defects that are more likely to cause parameter issues can be separated from defects that are less likely to cause or will not cause parameter issues. As such, defects that affect only the structural configuration or material properties of the device can be separated from defects that affect whether the device can operate according to its intended purpose. Further, in combination with one or more attributes of the design data and / or one or more attributes of the defects, the electrical test results or other information relating to the electrical characteristics of the device may be used to identify electrical defects as major parameter defects (e.g., (E. G., Electrical defects that can affect the electrical characteristics of the device) and non-critical parameter defects (e. G., Electrical defects that do not significantly affect the electrical characteristics of the device).

In some embodiments, the method includes determining a DCI for a defect (e.g., one or more defects). The DCI may be determined based on one or more attributes of the design data near the location of the defects in the design data space, one or more attributes of the defects, or some combination thereof. For example, one or more attributes of the design data near the location of the defects in the design data space, one or more attributes of the defects, or some combination thereof may be used to determine the design-based potential yield impact, thereby increasing the value of the defect data . In a particular example, the DCI can be determined using the location and defect size of a defect in the design data to determine the likelihood that the defect will cause an electrical error. DCI can be used to indicate the yield relevance of defects. In particular, the defect size can be used to determine the probability that a defect will kill the die or alter one or more attributes of the device being fabricated on the wafer. For example, as the defect size and pattern complexity increase, the likelihood of a defect breaking the die or changing one or more electrical properties of the device also increases. Thus, the relationship describing the probability of a defect breaking a die or changing the one or more electrical properties of the device in terms of defect size and pattern complexity can be used to determine the relative risk of each defect on the wafer. The relative risk of each defect can be determined immediately after the test, allowing a better decision to be made based on the relative risk.

Alternatively, the DCI may have a defect for the different types of defects and possibly different types of defects (possibly across the entire die), which may be used to determine the DCI for the defect, And determining the likelihood of changing the attribute. For example, in one embodiment, the method may include one or more attributes of the design data near the location of the defect in the design data space, one or more attributes of the defect (e.g., defect size) Based on the location of the defects detected, the co-ordination inaccuracies of the inspection system, or some combination thereof, one or more defects in the fabricated device may cause one or more electrical failures (or alter one or more electrical properties of the device) Determining a DCI for one or more defects based on the probability; and determining a DCI for one or more defects based on the probability. The probability can be determined in this manner using any suitable statistical method known in the art.

The DCI for defects can be determined in a number of ways in the embodiments described herein, such as sampling to select defects for review. Specifically, for each defect category or group of defects, instead of performing random sampling of commonly classified defects or commonly-borne defects, the DCI may be used to sample defects that have the same category or are grouped into the same group Can be used. By using DCI for sampling, the distribution of DCI can be used to determine which defect is most likely to break a die or change one or more electrical properties, and can be used to determine whether a defect that is likely to break a die or alter one or more electrical properties You can sample more intensively. As such, defects that are more likely to affect the yield can be sampled more intensively for review, and thus generate defect review results that are particularly useful for identifying and classifying defects that are more likely to affect yield . DCI can be used to sample random faults as well as potentially systematic and systematic faults.

In some embodiments, the method includes determining a high density area on the electrical error density map. The error density map can be generated by creating a "logical bitmap" or physical translation of an error test chain or an error flip-flop (detected by a structural test that is a scan-based test type). All error lines or areas found by scan-based testing are shown as in the graphic rendering of a die under test (DUT). The terms "logic bitmap" and "bitmap" are used interchangeably herein. Logic bitmaps for different die of the same layer and design are stacked (i.e., overlaid) to indicate the number of errors at each point of the die, thereby creating an error density map. A defect appearing in the error density map with a frequency greater than a predetermined value can be regarded as a systematic defect. Defects found close to hot spots within the die coordinate space can be viewed as yield impact systematic defects or systematic candidates.

In some embodiments, the result of the electrical inspection process (e.g., bitmap) may be analyzed using information from the inline inspection results to determine if the cause of the electrical defect can be determined from the inline inspection results. In order to correlate the inline test results with the electrical test results, different test results may be aligned with one another as described herein. In addition, the different inspection results can be sorted first in the design data, and then the inspection results can be aligned with each other. In either case, the bitmap result can be overlaid on the inline check result.

The method may include determining the cause of the electrical defect in the bitmap based on the inline inspection data and the design data. In addition, other error types and their candidate locations or paths can be analyzed to determine how many electrical errors overlap with physical defects. In this manner, the hit ratio for the type of error can be determined as the number of errors of the type corresponding to the reported physical defect, divided by the number of errors of that type. The hit ratio can be evaluated to determine if the error type tends to be associated with the reported physical defect. In addition, the inline test results and hit ratio of physical defects can be used to determine how many of the same type of defects are caused by electrical errors. In this way, the number of defects of the same type that caused electrical errors can be used to determine the statistical prediction of the yield importance of defects.

Additional information about physical faults can be used to determine the cause of bit errors. Such information may include, but is not limited to, images of physical defects corresponding to locations of bit errors, classification results of physical defects, binning results for physical defects, or some combination thereof, (E.g., to show the repeatability of electrical errors across the die), a bitmap Pareto diagram, and detailed information about the bitmap results (e.g., For example, data in a table or a list).

In some embodiments, the method may include using a defect transition table (DTT) method to identify hot spots where no defects are detected or non-breaking or non-significant defects are detected. In general, the rows of the DTT include the results of tests for different defects, and the other columns of the DTT include test results generated by tests performed at different times. Test results can be arranged in chronological order across the rows. In this way, the table shows which defects are redetected in different layers during the semiconductor manufacturing process. The table may contain additional information about defects detected in different layers or may provide access thereto (e.g., links). In this manner, additional information, such as an image of the defect, can be used to determine if the defect is changed in a different layer or how it is altered.

In a further embodiment, the method includes determining a KP value for one or more defects based on one or more attributes of the design data, one or more attributes of the defects, or some combination thereof. In a similar manner, the method may include calculating a KP value for a defect of at least one group of defects based on at least one attribute of the design data corresponding to the at least one group, one or more attributes of the defects in the at least one group, And a step of determining the number The KP value for systematic defects can be used to determine additional attributes of systematic defects such as yield ratios. The KP value can also be used to perform the additional steps described herein. For example, the KP value for systematic defects can be used to determine which defects are to be selected for review. In particular, systematic defects with relatively high KP values can be selected for review. The method may also include monitoring a KP value for systematic defects and generating an output signal when the KP value exceeds a predetermined KP value. The output signal may be an automatic report, a visible output signal, an audible output signal, or some other output signal that can be used to alert the user of a potential problem with the process. In this manner, the output signal may be a warning signal.

As further described herein, one advantage of the methods and systems described herein is that information from a plurality of different sources can be correlated, stored, displayed and / or processed with one another. Such information may include information in the GDS file, information about the process performed on the wafer (commonly referred to as WIP data, which may be obtained from a source such as a fab manufacturing execution system (MES) database) In-line metrology or measurement results, electrical test results, and end-of-line yield information. Such information can be used to determine yield related information on systematic defects. In addition, other yield related information determined for yield ratios or systematic defects can be used to assign yield related contexts to systematic defects. Both yield related context information and design context information can be assigned to systematic defects. In one embodiment, instead of classifying defects based on a design context, systematic defects can be classified based on yield-specific contexts.

As further described herein, a hot spot based inspection of systematic defects can produce a systematic defect and a test result that includes a design context corresponding to the systematic defect. In this manner, the margin characteristics in the design data can be identified and used for SPC applications. For example, the SPC can be performed by monitoring the position of the margin feature in the design data, as the feature tends to be error first if the process drifts from the process limit. Thus, an SPC can be performed more quickly by monitoring a subset of all the features in the design that include the most important features in the design, instead of every feature in the design, and features in the design that are most sensitive to changes in the process are monitored during the SPC Therefore, the drift in the process can be detected more quickly. In a similar manner, the margin feature information may be used to generate a recipe for the metrology process, such as a CD measurement process. The CD measurement process may include any suitable CD measurement process known in the art (e.g., CDSEM, scatterometry CD measurement, etc.). Creating a recipe for the CD measurement process may include determining a location on the wafer where the CD measurement is to be performed during the process (e.g., the margin feature is to be printed). In addition, the results of inspection of the wafer, such as the BF image acquired at the location on the wafer where the CD measurement is to be performed, can be provided to the metrology system such that the results can be used by the metrology system moving to a recipe or to a location on the wafer for measurement have.

However, with the addition of test data, the design portion corresponding to a systematic defect can be associated with the yield probability of the semiconductor manufacturing process and the KP of the systematic defect. In such an embodiment, the inspection system or any other system described herein can produce yield results for systematic defects, such as the probability of each defect having the greatest effect on the yield, have. A systematic defect KP can be used for SPC applications. For example, the probability of each defect having the greatest impact on yield may be used to improve SPC monitoring application and review sampling. In this manner, the SPC can be performed based on the context-based yield. In addition, improved SPC monitoring and review sampling can improve root cause analysis and baseline reduction.

In a further embodiment, the method includes monitoring the KP value for a group of defects over time, and determining the importance of the defect group based on the result of the inspection. For example, over time, as KP values are continually updated, hot spots with low KP values may be removed or down-graded against a coordinating hot spot, weak spot, or cold spot. In this manner, the identified potential hotspots may be assigned a low or zero KP value (i. E., A cold spot). In another embodiment, the method includes determining a KP value for a group of defects based on an electrical error density associated with the design data. In this manner, a hot spot determined to not overlay a relatively high error density region on the electrical error density map can be downgraded at KP and optionally removed from the hot spot database and / or its associated inspection recipe .

In one embodiment, the method comprises the steps of monitoring a KP value for one or more POIs in the design data, and if the portion of the design data is close to the location of the defect being binned into one or more groups corresponding to one or more POIs, And assigning a KP value for the POI to one or more groups. For example, monitoring the KP value for one or more POIs in the design data may include monitoring the KP value for one or more POIs in the design data, such as electrical errors, electrical error density, any other attribute of the electrical error, , And based on the inspection results obtained for one or more POI over time. Any other attribute of electrical error, electrical error density, and electrical error may be determined using any suitable method or system known in the art. The test results can be obtained as described herein. Although the checking of the KP value is performed by the method in this embodiment, the step of monitoring the KP value can be performed by another method or system, and the above-described allocation step can be performed by that method. In addition, the step of monitoring the KP value can be performed during the setup step prior to performing the binning step, so that the time between the step of inspecting and assigning the KP value to the defect of one or more groups can be reduced. Assigning a KP value for one or more POIs to one or more groups may include comparing a portion of the design data near the location of at least some of the defects binned in the at least one group to a portion of the design data corresponding to the one or more POIs . ≪ / RTI > If the portion of the design data near the location of at least some of the defects in the group is at least similar to the portion of the design data corresponding to the POI that can be determined based on the result of the comparison step, then the KP value corresponding to the POI may be a defect , All defects).

The methods described herein may include generating information for one or more diagnostic or repair processes that are hot spot sensitive (e.g., having a high signal and low noise for a hot spot). The information may be used to automate or optimize one or more diagnostic or repair processes for hot spots. One or more processes can be used to differentiate between hotspot demonstration and analysis, acquisition of new learning, non-attention area and Newson defect filtering optimization, reporting, design and process margins. In this way, the method can be applied to a variety of applications including wafer inspection, reticle inspection, optical inspection, macro-defect inspection, electron beam inspection, optical defect review, SEM defect review, ellipsometry and CDSEM Measurement processes, defect analysis processes, FIB and other FA processes, and recipe for diagnostic and repair processes such as defect repair processes.

In some embodiments, the method includes prioritizing one or more POIs in the design data, and optimizing one or more processes to be performed on the wafer to which the design data is to be printed based on the prioritizing step . The step of prioritizing one or more POIs may be performed as described herein. Optimizing the one or more processes in this embodiment may include optimizing the focus, the exposure dose, the exposure tool, the regression sheet, the post exposure bake (PEB) time, the PEB temperature, the etch time, the etch gas composition, , Deposition time, and the like, of the at least one process. Preferably, the parameters of the process change the one or more attributes (e.g., DCI, KP, etc.) of defects detected in the POI to reduce POI defects (e.g., the number of defects detected in the POI) And / or to increase the yield of the device containing the POI.

In addition, one or more parameters of the one or more processes may be optimized only for a POI with the highest priority as determined by the prioritization step or for a POI with a relatively higher priority as determined in the prioritization step. In this manner, one or more parameters of the one or more processes can be altered and / or optimized based on the POIs with the greatest defects and / or impacts on the yields showing the greatest defects. As such, the result of the prioritization step indicates which POI should be used to modify and / or optimize one or more parameters of the one or more processes to indicate the largest yield improvement.

Thus, without guidance as to which POI has the greatest impact on yield, beneficial opportunities to optimize the process for yield and stability may not be timely identified or achieved, thereby increasing market turnover time, The present embodiment is advantageous over previously used methods and systems.

Further, even though the process modified and / or optimized at this stage includes only those processes used to print POIs in design data on the wafer prior to the detection of a binned defect in the embodiments described herein, One or more processes may include any process used to print other design data, including POIs. For example, if one or more design data includes a POI based on prioritization and / or any other result of the methods described herein, one or more processes used to print one or more designs may be modified and optimized , Increasing the yield of the device made with each different design.

In another embodiment, the method may be performed on a wafer based on the results of the binning step and / or any other result of any of the other steps of any of the methods described herein, or may be performed on one or more parameters of the process to be performed on the wafer And changing the variable. The process may include any process known in the art, such as CMP, deposition (electrochemical deposition, atomic layer deposition, sophisticated vapor deposition, physical vapor deposition), lithography, etch, ion implantation, and cleaning. The one or more parameters may be altered based on the results of the binning so that the defect binned in one or more groups can be reduced for subsequent wafers of the wafer or reduced for other wafers after processing of the other wafers.

For example, where an etch process is performed on a wafer prior to inspection, one or more parameters of the etch process may be selected such that other wafers processed in the etch process, preferably with changed parameters, Defects, fewer defects with relatively high DCI, fewer defects with relatively high KP values, or the like, or some combination thereof. Such changes in parameters can be performed based on the prioritization of defect groups or other information described herein, such as DCI and KP values. In this way, the process can be changed based on the group of defects with the greatest impact on yield.

In another example, when an etch process is performed on a wafer prior to inspection, one or more parameters of the post-etch process to be performed on the wafer are preferably determined based on whether the post-etch process is performed Then the wafer is subjected to a feedforward operation to exhibit fewer defects in one or more groups, fewer defects with a relatively high DCI, fewer defects with a relatively high KP value, and the like, or some combination thereof. Can be changed using control techniques. The parameters of the post-etch process or other process may be changed as described above.

Modifying one or more parameters of a process as described above includes determining how one or more parameters should be changed and changing the value of one or more parameters in the recipe to be used to perform the process . Such changes may be made by the methods and systems described herein, for example, by connecting to a recipe in a storage medium coupled to a process tool for performing the process, or in a fab database, and by directly changing the recipe.

Alternatively, modifying one or more parameters of the process as described above may include determining how one or more of the parameters should be changed, and determining whether the one or more parameters in the recipe to be used to perform the process (E. G., A fab database or processor coupled to a process tool for performing the process). ≪ / RTI > The one or more parameter values to be modified may be transmitted with other information such as a recipe entity, a process tool identity, an instruction to change one or more parameters, etc. so that the process can be changed by other methods or systems.

In one embodiment, the method includes modifying a process for inspecting a wafer based on a result of the binning step. The process for wafer inspection can be changed based on any of the binning results described herein. In addition, any parameters of the process for inspecting the wafer can be changed in this embodiment. For example, one or more parameters of the process for wafer inspection that can be changed based on the results of the binning step may include one or more of the following: , Or some combination thereof. ≪ RTI ID = 0.0 > In one particular example, the result of the binning may include the number of defects contained within one or more groups, and the region of interest may be a location on the wafer corresponding to a location in the design data space of the defect in the group that includes a relatively large number of defects . ≪ / RTI > In another example, the process for inspecting the wafer may be changed to more or different inspections based on the results of the binning step. The process for wafer inspection may be modified based on any result of any of the steps described herein.

As described herein, a defect can be detected by an inspection process. In one embodiment, the method includes the steps of: reviewing a location on the wafer on which one or more POIs in the design data are printed; determining if a defect has been examined at a location of one or more POIs based on the result of the reviewing step; And modifying the inspection process to improve one or more defect capture rates. The location review step in this embodiment may be performed using any method or system known in the art. In this manner, reviewing the location on the wafer may be performed at the location of the POI to determine if a defect has been detected at the location of the POI. In one such embodiment, the method may comprise any pattern searching step for identifying the location of one or more POIs in the design data and determining the location of one or more POIs from the location of one or more POIs in the design data have. The step of determining the location of the POI in this manner can be performed as further described herein.

In addition, in some embodiments, the method may include displaying POIs with hits and POIs without hits during the review step to aid review. As such, the results of the review can be used to determine where a defect has occurred but has not been captured by the inspection system. The POI can be reviewed to find defects that have been lost (or unacknowledged defects) to know where to make changes or optimizations to the inspection process.

(E.g., one or more attributes of a defect, one or more attributes of design data, etc.) in addition to the review results, preferably at a higher rate than in a subsequent review, One or more parameters of the inspection process, such as angle, angle of incidence, etc., may be changed. In this manner, the method may include a setup adjustment step based on an analysis of defect coverage in the POI. One or more parameters of the inspection process to be changed may be determined in any suitable manner, such as using a rules database. One or more defect coverage rates that may be improved in this embodiment include defect coverage for one or more defect types in one or more POIs. In a similar manner, the above-described embodiments for improving one or more defect capture rates may be performed by reviewing the location on the wafer corresponding to the location of one or more hot spots in the design, instead of reviewing the location on the wafer on which one or more POIs are printed .

Also, the above-described method is performed for one or more POIs, the POIs may be prioritized as further described herein, and the inspection process may determine the defect capture rate for POIs having the highest priority or higher priority Can be changed. In this manner, the inspection process can be optimized for the highest priority POI or higher priority POI (although such optimization may also result in optimization of the inspection process for a lower priority POI).

In another embodiment, the method includes modifying the process for inspection of the wafer during the inspection based on the inspection results. In this manner, the method may include modifying the inspection process using an in-situ process control technique. The test results used to modify the inspection process may include any of the results described herein. Further, the step of modifying the inspection process in this embodiment may include the step of modifying any one or more parameters of the inspection process.

As further described above, the method may include optimizing the inspection recipe. The inspection recipes to be optimized may include inline inspection recipes and / or electrical inspection recipes. In one embodiment, the method may include modifying a process for wafer inspection based on hot spot information. In another embodiment, the method includes generating a process for wafer inspection based on hot spot information and design data. The method may also include modifying or creating a process for wafer inspection based on hot spot information and / or predicted POI. For example, the inspection recipe may be configured such that only the locations of hot spots and POIs are inspected and / or the location of systematic Newson defects are not inspected, or data acquired at such locations is otherwise suppressed. In another example, as described above, the method embodiments described herein may include identifying hot spots in the design (e.g., based on systematic defects). In this manner, the method embodiment can be a source of hotspots, and the location of the hotspots in the design can be used to modify the inspection process using feedforward control techniques.

The method may include modifying the process for inspecting the wafer based on any other available information. In one such example, the method may include modifying the inspection recipe based on the hotspot information in addition to the design data, the inspection results, and the one or more bitmaps. In this manner, any information available to the method can be used to detect defects that do not affect the yield, reduce the sensitivity of the test recipe, and reduce the sensitivity of the test recipe to detect defects that may affect yield It can be optimized. The generation and optimization of the inspection recipe may be performed as further described herein (e.g., based on the probabilities for the DOI).

In some embodiments, the method may include determining a degree of sensitivity for detecting defects on the wafer based on design data. In some such embodiments, at least two portions differ on the wafer corresponding to at least two portions of the design data. The method may also include identifying a "region of interest" (or "region to be inspected") on the wafer. The inspection result may not be acquired in the non-attention area, and the defect detection may not be performed on the inspection result obtained in the non-attention area. However, if data acquisition and defect detection are performed in the non-critical area before additional processing of the inspection result, such as binning, is performed, the method includes determining whether the detected defect is present in the attention area or non-critical area . ≪ / RTI > If the defect is located in the non-critical area, no further processing may be performed on the defect. In this manner, pattern-based binning can be limited to sensitive areas within the design data to optimize the throughput of the binning process. In another embodiment, after defects are grouped by common design data (e.g., pattern grouping or other context data), the grouping information is added here for improved counting, binning, monitoring, analysis, sampling, review, As shown in FIG.

The method embodiment may or may not utilize hotspot information. For example, based on knowledge of design data, the method may include identifying portions of design data that are more critical to yield and / or more sensitive to yield-lowering defects. In this manner, the sensitivity to detect defects in that portion of the design data may be higher than the sensitivity to detect defects in other portions of the design data. As such, during acquisition of inspection data, the method may include aligning inspection data to design data, which may be performed as further described herein. The sensitivity of the inspection process can be changed based on the location of the inspection data in the design data space. In such an embodiment, the sensitivity of the inspection process can be changed in real time. Additional examples of design-based tests or measurement recipes are described in U.S. Patent 6,886,153 (Bevis) and U.S. Patent Application Serial No. 10 / 082,593, filed on February 22, 2002, by Hamamatsu et al., U.S. Patent Application Publication No. US2003 / Quot; filed "), which are incorporated by reference as if fully set forth herein. The methods described herein may include any of the steps disclosed in the above patents and patent applications.

In one embodiment, the method includes selecting at least some of the defects for review based on the results of the binning step. For example, the results of the binning step can be used to determine which defects are most important (e.g., by determining DCI for defects), as described herein, and most significant defects can be selected for review. In another example, the binning results can be used to determine which defect is a systematic defect, as further described herein. In this manner, the method may include review sampling from a portion of the design data that the DOI is likely to occur. In addition to information about which defects are systematic, information about whether systematic defects are visible and / or systematic defects are yield related to a review system such as SEM can be used to select at least some defects for review (E.g., only defects visible to the SEM are selected for review). Defect selection in such a manner is particularly advantageous, since re-localization of defects during review is relatively difficult and can be relatively time consuming, especially if the review system spends a lot of time looking for actual invisible defects in the review system. The defect selection result for the review may include the location of the selected defect on the wafer and other results of any of the steps described herein.

In another embodiment, the method includes generating a process for sampling a defect for review based on a result of the binning step. Thus, instead of or in addition to a choice of defects for review, the method can be used to sample a defect for review (e.g., by way of that method, another method, system configured to perform the method, To create a process). Such a process can be used for sampling of defects detected on a plurality of wafers for review and / or for defects for review performed by a plurality of review systems for review. The process for sampling is performed such that the detected defect in the portion of the design data corresponding to the vened defect group containing a relatively large number of defects is the portion of the design data corresponding to the group of the vened defect containing a relatively small number of defects Based on the results of the binning step, so that it can be sampled more intensively than the detected defects within the bin. The process for sampling the defect for review is based on the results of the binning step in combination with DCI for the defect, KP value for the defect, and any other result of any of the steps of any of the methods described herein .

In another embodiment, the method includes generating a process for selecting a defect for review based on hotspot information. The process of selecting defects for review can be generated based on hotspot information as well as any other information available to the method. For example, the process of selecting a defect for review may be generated based on design data, one or more attributes of a defect, one or more bitmaps, and hotspot information. Preferably, the process of selecting a defect for review is selected for review for a particular type of defect, such as a defect detected in a hot spot or a systematic defect, and a defect and a Newson defect detected in a cold spot are selected for review . In this manner, the method described herein generates defect samples that contain a large number of defects that can affect yield, while eliminating most of the defects that will not affect yield, from the review samples, increasing the throughput of the review process can do.

In another embodiment, after the defect has been binned by at least similar design data as described above, the method may be used to create CDSEM, optical or other types of physical defect review, and more than one " ≪ / RTI > In one such embodiment, the method includes generating a pattern group pareto as described above, wherein the pattern group identities are represented on the x-axis and the number of defects detected in each pattern group on the y-axis. In this way, the chart shows the number of defects detected in different patterns. However, other data indicating the number of defects detected in other patterns may be used in the method steps described herein. The embodiments described herein may include generating electrical, systematic, and / or random Pareto charts.

The method may include analyzing data for one or more different patterns shown in the chart to determine one or more types of physical defects detected in each pattern type. One or more defect types can be detected in one pattern group. The method may also include analyzing data for one or more other spatial signatures shown in the chart to determine one or more attributes of a defect that has been binned into one or more groups corresponding to one or more different signatures . Defect attributes may include, but are not limited to, size, die position (or die identity), and any other attribute known in the art. The die position indicates whether the pattern has a high frequency of occurrence at a particular position, zone, or region of the wafer, e.g., edge, center, 3 o'clock position, and so on.

The defect sampling plan can be determined from the results of the above analysis steps. For example, the method may include determining whether a strong signal occurs from the analysis step described above. This strong signal indicates which defect (e.g., which pattern determined by the analysis step and which defect type and / or attribute) should be sampled at a high or low rate. The above-described sampling plan is useful for increasing the throughput of a relatively slow review system such as an electron beam based review system and an atomic force microscope (AFM) or other scanning probe microscope based review system.

The method described here can be used to optimize the review recipe. For example, in one embodiment, the method includes modifying a process for reviewing defects on a wafer based on hot spot information and optionally other information available in the method. The parameters of the review recipe changed or selected based on this information may include any data acquisition parameters and any data processing parameters of the review process. The method may include selecting a type of review system (e.g., optical or electron beam) to use to review the defect and additional parameters of the review process, such as the manufacturer and model of the review system used to review the defect . ≪ / RTI >

The method may include providing the review system with information that can be used to assist in determining the location on the wafer on which the review is performed. For example, the location of the defect to be reviewed may be reported to the review system as a design data space, a die space, and / or a wafer space. In addition, other information regarding defects and / or defect locations may be provided to the review system. For example, an image or an overlay of defects generated by inline inspection may be provided to the review system in addition to portions of the design data corresponding to the defect locations. In this manner, the review system may use some or all of its information to locate the selected defects on the wafer during review. In addition, the results of one or more of the steps described herein may be provided to a review system so that the review system can use the results to perform automatic defect locating (ADL) based on edge placement errors. The method may also include determining where to measure or test for review based on test results and systematic identities (perhaps with yield relevance and / or process window mapping). The review is based on co-assigned U.S. Patent Application Serial No. 11 / 249,144 (filed October 14, 2005; Teh et al.), Published as U.S. Patent Application Publication No. 2006/0082763 (Apr. 20, 2006) And may include user-assisted reviews that may be performed using the same methods and systems as those disclosed, which are incorporated by reference as if fully set forth herein. Thus, the user case for the binning method (and how to assign the category to the defects described further herein) includes systematic exploration and user-assisted review.

In one embodiment, the method includes modifying the metrology process for the wafer based on the result of the binning step. For example, the metrology process can be changed so that most major defects as determined from the results of the binning step are measured during the metrology process. Thus, modifying the metrology process may include changing the location on the wafer where measurements are performed during the metrology process. In addition, the results of the inspection and / or review, such as the BF image and / or the SEM image of the defect selected for measurement, are provided to the metrology system and the results can be used to determine where the measurement is to be performed. For example, the metrology process may include generating an image of the proper location of defects on the wafer, and if necessary, the metrology system corrects the position on the wafer so that the measurement is performed at the correct wafer location, The image may be compared to the results of the inspection and / or review of the defect. In this way, the measurement can be performed at a substantially precise location on the wafer. The step of modifying the metrology process may also include modifying any other one or more parameters of the metrology process, such as the type of measurement being performed, the angle at which the measurement is performed, etc., or some combination thereof. The metrology process may include any suitable metrology process known in the art, such as a CD metrology process.

In another embodiment, the method includes modifying a sampling plan for the metrology process of the wafer based on the result of the binning step. Thus, the method may include adaptive sampling. For example, the sampling plan for the metrology process can be varied such that a large number of the most significant defects as determined from the results of the binning step are measured during the metrology process. In this manner, the most critical defects can be sampled more intensively during the metrology process, thereby beneficially generating a large amount of information about the most critical defects. The metrology process may include any metrology process known in the art. In addition, the metrology process can be performed by any suitable metrology system known in the art, such as SEM. The metrology process may also include performing any suitable measurements known in the art for any suitable properties of features or defects formed on the wafer, such as profile, thickness, CD, and the like.

In a similar manner, the method includes modifying a process for analyzing (e.g., measuring or configuring) defects on a wafer based on hot spot information and optionally any other information available to the method can do. For example, the method may include altering a process, such as electronically dispersed x-ray spectroscopy (EDS or EDX) or repair of defects or FIB process for FA to analyze the composition of the defect. The process for analyzing or repairing defects may be changed as described herein for changing other processes. For example, the defect or repair process may be altered such that the analysis and / or repair is performed only at the location of the selected defect, and such a selection may be made as described herein. In addition, one or more parameters of the analysis or repair process may be selected and modified based on the results of any of the steps described herein. Such results may include, for example, a defect category, a defect root cause, a defect size, a defect criticality (which may indicate the accuracy with which analysis and / or repair should be performed), a yield effect, The density of features, the layer, the redundancy, etc.) (which may indicate whether analysis and / or repair should be performed and the accuracy with which analysis and / or repair should be performed, etc.). A further example of a method and system for generating a recipe for a metrology tool is disclosed in U.S. Patent No. 6,581,193 (MaGhee et al.), Which is incorporated by reference as fully described herein. The methods and systems described herein can be configured to perform any of the additional steps described in the patent.

In some embodiments, the method includes determining a root cause of the defect based on one or more attributes of the design data. In another embodiment, the method includes determining the root cause of the one or more groups on which the defect is to be benigned. For example, in one embodiment, the method may be used to determine the root cause of a defect in one or more groups based on at least one result of a defect in one or more groups, one or more attributes of design data, one or more attributes of a defect, . In this manner, the method may include determining the root cause of the defects individually or collectively as a group. The root cause of a defect or group defect can be determined, for example, by measuring the composition of the defect, based on the analysis results from the diagnostic system, such as the EDS system, which can be used to analyze the defect. An example of an EDS system is disclosed in U.S. Patent 6,777,676 (Wang et al.), Which is incorporated by reference as fully described herein.

The root cause step may include identifying a correction for source, cause, and / or systematic defects. The root cause step can be performed in multiple source spaces using correlation between any design, wafer, reticle, test and process space. For example, in one embodiment, the method includes determining a root cause of at least one group defect by mapping at least a portion of the defects in the at least one group to an experimental process window result. Experimental process window results may be generated by the above method, another method, a system configured to perform the method, or a system other than a system configured to perform the method. The experimental process window results may also be used to detect defects on the wafer after the PWQ method or other experiments using the PWQ method or any other suitable experiment (e.g., by performing an etch process on different wafers at one or more different parameters) . The experimental process window results may include any results obtained by inspection and / or review of defects detected on the wafer. For example, the empirical process window results may include an image of the defect, a portion of the design data that is close to the location of the defect in the design data space, a location of the defect in the design data space that can be determined as described herein, Inspection and / or defect review results.

The step of mapping at least some of the defects to the experimental process window results can be performed using the results of the inspection process. For example, if the experimental process window result includes a portion of the design data near the location of the defect in the design data space and an image of the defect on the wafer, then mapping the defect to the experimental process window result may include a defect To an image in the experimental process window result for the detected defect near at least similar design data to design data near the location of the vened defect in the design data space. In another example, if the empirical process window result includes the location of the defect in the design data space, mapping the binned defect to the empirical process window result in the present embodiment may be performed on the defect in the design data space And comparing the location to the location of the binned defect in the design data space.

In this way, the result of the mapping step can indicate where in the process window space the process performed on the wafer is performed before defect detection. In particular, if the mapping results indicate that the defects contained in the experimental process window results and the bound defects are at least similar and at least close to similar design data, One or more parameter values may be correlated to the binned defect, determined as the root cause of the binned defect, or used to determine the root cause of the binned defect.

In another embodiment, the method includes determining a root cause of at least one group defect by mapping at least a portion of the defects in the at least one group to a simulated process window result. The simulated process window results may include similar results to the experimental process window results described above. However, the simulated process window results are obtained by simulating an image describing how the design data is printed on the wafer at the values of one or more various parameters of the process, rather than performing an experiment on the physical wafer. The process may include any process involved in the manufacture of the device corresponding to the design data. For example, the present embodiment may include modeling a patterning process (e.g., lithography or etch) with respect to a systematic defect location, and the results of such modeling may be used to determine the root cause of systematic defects. The simulated process window results may be generated by any suitable method or system known in the art. For example, the simulated process window results may be generated by PROLITH software commercially available from KLA-Tencor. In addition, the simulated process window results may be generated by the above method, another method, a system configured to perform the method, or a system other than a system configured to perform the method. The step of determining the root cause in this embodiment may be performed as given in the experimental process window results.

The root cause step may include determining the source and / or correction for systematic defects. One possible source for systematic faults is the process window shift. In addition, knowledge of the hotspot signature can provide information about where in the process window the process is operating. The root cause step may also include a step of determining the most important opportunity for process improvement to extend the process window. In addition, the root cause step may include determining the most important systematic issues to improve the reticle design. The root cause step may further include a step of determining the most important systematic issue to improve and / or implement the next generation technology.

In some embodiments, the method includes determining a percentage of die formed on a wafer affected by a defect of at least one group. For example, the percentage can be determined by determining the number of inspection dies on the wafer where the defects in the group have been detected at least once and by dividing the number of inspection dies detected at least once into defects in the group by the total number of inspection dies. The number of inspection dies on the wafer where the defects in the group have been detected at least once can be determined based on the design data space location of the defect, the design space location of the die printed on the wafer, and information about the inspection process used to detect the defect have. The result of these steps is multiplied by 100 to reach a percentage. In one particular example, there are 300 defects binned in one group, the defects in the group are located on five dice on the wafer, and if there are 6,000 die on the wafer, the percentage is [(5) 100)] / (6000) or 0.083%. The percentage thus reflects the die impact margin on the group of defects. Such a percentage can be determined for one or more group defects, and each (or at least a percentage) of the percentages can be represented by a chart such as a bar chart that can be generated by the method. Thus, the chart shows the die impact margin as a function of the group to which the defect is to be binned. Such a chart may be represented in a user interface that may be configured as further described herein. The method may also include the step of prioritizing defects of one or more groups based on the percentage determined in the present embodiment. The steps of such prioritization may be performed as further described herein, and the results of such prioritization may be used as further described herein.

In another embodiment, the method further comprises determining at least one POI in the design data corresponding to at least one group, determining at least one POI in the design data corresponding to the at least one group corresponding to at least one POI, Of the number of < / RTI > One or more POIs in design data corresponding to at least one group may be determined as further described herein. If all instances of one or more POIs are not inspected during the inspection process used to detect defects, the number of locations of one or more POIs on the wafer used in this embodiment may be the number of inspected locations of one or more POIs on the wafer. In this manner, the method may include performing a margin analysis by determining the percentage or percentage of POIs detected on the wafer, the number of locations of the POIs printed on the wafer (or the number of inspected locations of POIs on the wafer) Step < / RTI > In such an embodiment, the number of locations of POIs on the wafer may be identified by any pattern search. The number of inspected locations of POIs on the wafer may be performed using any pattern search, using information about the inspection process and the results of any pattern searches to determine the number of inspected locations of POIs on the wafer . In addition, the method described herein can identify the location of the POI on the wafer and include any pattern search to determine the area of the POI. The area of the POI on the wafer and the number of locations of the POI (or the number of inspected locations of the POI on the wafer) can be used to determine the defect density by the POI. The method may also include prioritizing one or more POIs based on the ratio determined in the present embodiment. Such prioritization may be performed as further described herein, and such prioritization results may be used as described herein.

In a further embodiment, the method comprises determining at least one POI in the design data corresponding to at least one group, determining the number of POI locations in the design data (or the location of one or more POIs in the design data) Determining the ratio of the number of binned defects in at least one group corresponding to one or more POIs to the number of inspected locations of one or more POIs in the design data if not inspected during the inspection process used to detect . In this manner, the method comprises performing margin analysis by determining the percentage or percentage of defects in the group corresponding to the POI for the number of locations of the POI in the design (or the number of inspected locations of the POI in the design) . In such an embodiment, the number of locations of the POI in the design data may be performed by any pattern search. In addition, the number of inspected locations of the POI in the design can be determined as described above. One or more POIs corresponding to at least one group may be determined as further described herein. This method may also include prioritizing one or more POIs based on the ratio determined in the present embodiment. Such prioritization may be performed as further described herein, and such prioritization results may be used as described herein.

In a further embodiment, the method comprises the steps of determining a POI in design data corresponding to at least one group, determining the percentage of die formed on the wafer on which the defect to be binned in at least one group is located, And assigning a priority to the POI based on the percentage. In this manner, the method may include performing a margin analysis based on a percentage of the die affected by the defect. For example, the number of defects binned in a group can be divided by the number of design instances of the POI on the reticle used to print the design data on the wafer and the number of times the reticle is printed on the wafer. The result of this step is multiplied by 100 to reach a percentage. In one particular example, there are 300 defects grouped into one group, 2000 design instances of POIs corresponding to groups on the reticle, and if the reticle is printed 1000 times on the wafer, the grouped defect is located The percentage of die formed on the wafer is [(300) (100)] / [(2000) (1000)] or 0.015%, which is essentially a wafer-based margin for a group of defects.

In this manner, the method may include prioritizing systematic defects by the number of inspection dies on the wafer where the defects are detected at least once. For example, a higher priority may be assigned to a POI if systematic defects occur at 10% of the design instance of the POI in the die, for 1% of the design instance of the POI in the die. In another example, a group of defects detected on multiple die on a wafer may be assigned a higher priority than a group of defects detected on a small number of die on the wafer. The method may also include generating a chart such as a bar chart showing the percentage of dies formed on the wafer where the defects binned into different groups are located. Thus, the chart graphically represents die-based margins for different defect groups. Such a chart may be displayed on a user interface that may be configured as described herein. The results of such prioritization can be used as described herein.

In another embodiment, the method includes prioritizing one or more groups by the number of overall design instances on the wafer for which defects in one or more groups are detected. The number of design instances on the wafer used in this embodiment may be the total number of inspected design instances on the wafer if all design instances on the wafer were not inspected during the inspection process used to detect defects. In this manner, the method may include prioritizing known systematic defects with a total number of design instances on the wafer (or a total number of inspected design instances). As such, the method may include prioritizing known systematic defects based on wafer-based margins. For example, a group of defects detected in a large number of design instances on a wafer may be assigned a higher priority than a group of defects detected in a small number of design instances on the wafer. Such prioritization may be performed based on the percentage of the position of the design instance (or inspected design instance) on the wafer from which the defect is detected. For example, the number of detected and binned defects can be divided into a total number of design instances on the wafer (or a total number of inspected design instances). The result of this step can be multiplied by 100 to reach the aforementioned percentage. The method may also include generating a chart such as a bar chart showing the number of design instances (or the number of inspected design instances) on the wafer for which different groups of defects have been detected. Such charts may be displayed on a user interface that may be configured as described herein. Such prioritization may be performed further as described herein, and the prioritization results may be used as described herein.

In some embodiments, the method includes prioritizing one or more groups with the number of design instances on the reticle that are used to print design data on the wafer at which defects within one or more groups are detected at least once. The number of design instances on the reticle used in this embodiment may be the number of design instances inspected. In this manner, the method may include prioritizing systematic defects known by the number of design instances on the reticle where the defects are found at least once. For example, a group of defects detected in a large number of design instances on the reticle may be assigned a higher priority than a group of defects detected in a small number of design instances on the reticle. The method may also include generating a chart such as a bar chart showing the number of design instances on the reticle on which defects of different groups have been detected. Such charts may be displayed on a user interface that may be configured as described herein. Such prioritization may be performed further as described herein, and the prioritization results may be used as described herein.

In another embodiment, the method includes comparing the number of positions on the reticle where a defect binned in one or more groups is detected and the design data printed on a reticle at least similar to the portion of the design data that is close to the position of the defect, Determining a reticle based margin for the one or more groups based on the total number of portions of the reticle. The number of positions on the reticle used in this embodiment may comprise the number of positions examined. For example, the reticle-based margins can be determined by dividing the number of positions in the stacked reticle map in which at least one defect in a group is detected by the total design instance on the reticle. The result of this step may be multiplied by 100 to reach a percentage of the location of the design instance corresponding to the group in which the defect was detected. In one particular example, if there are 2000 design instances for a POI corresponding to a group of 300 defects and a group corresponding to a group on the reticle, and a defect grouped in a group is detected at 50 different locations in the reticle (50) (100) / (2000) or 2.5%. The reticle-based margin in this group of defects may be [(50) (100)] / The method may also include generating a chart such as a bar chart showing percentages of locations where defects of different groups have been detected or reticle based margins. Such charts may be displayed on a user interface that may be configured as described herein. The method may also include the step of prioritizing defects of one or more groups based on the reticle based margins determined for the one or more groups. For example, a group representing a relatively high reticle based margin may be assigned a higher priority than a group of defects representing a relatively low reticle based margin. Such prioritization may be performed further as described herein, and the results of such prioritization may be used as described herein.

The steps of the above-described embodiments may be performed on individual defects that have been grouped into groups or groups of defects as described above.

Each embodiment of the above-described method may comprise any other step of any of the methods described herein. Further, each of the above-described method embodiments may be performed by any of the systems described herein.

As mentioned in detail above, a method embodiment for binning defects may include determining the DCI. In addition, some methods may include determining the DCI for one or more defects detected on the wafer, and may or may not include the step of binning the detected defects on the wafer. For example, one embodiment of a computer-implemented method of determining DCI for defects detected on a wafer is to determine, based on one or more attributes of the design data for devices near the location of the defects in the design data space, And determining a probability of changing one or more electrical properties of the device being manufactured. The probability that a defect will change one or more electrical properties of the device may be the probability that the defect will alter one or more electrical parameters of the device and / or break the die for the device. One or more attributes of the design data may include any of the design data attributes described herein. The probability can be determined based on at least one attribute of the design data in combination with at least one attribute (e.g., defect size) of the defect. The probability can also be determined based on one or more attributes of the defect, the location of the defect reported by the inspection system used to detect the defect, and one or more attributes of the design data in combination with the coordinate accuracy of the inspection system.

In one particular example, determining the probability may include determining at least one attribute of the design data, such as a key region, for a defect in the design data. In this manner, the critical area, the reported defect size, and the reported defect location can be used to determine the probability that the defect will change one or more electrical attributes of the device. For example, the larger the defect size and the greater the pattern complexity, the greater the probability that a defect will change one or more attributes of the device. Thus, the relationship describing damage or alterability within one or more electrical properties of the device as a function of defect size and pattern complexity can be used to determine the relative risk of each defect on each wafer.

In another example, the probability may be determined based on design data close to the location of the defect in the design data space, the probability of the location of the defect in the design data, the defect size as entered into the model to determine whether the defect will change one or more electrical properties of the device ≪ / RTI > In this way, the probability is a probability of changing one or more electrical attributes of the device if the defect is located in a particular spot in the design layout.

The method also includes determining a DCI for the defect based on a probability that the defect will change one or more attributes of the device. For example, the DCI may be at least approximately an index correlated to the probability. In one example, a high DCI can be determined for a defect for which a relatively high probability is determined. That is, the DCI is high for defects with a relatively high probability of changing one or more electrical properties of the device. The DCI may be determined from probabilities using any suitable method, algorithm, data structure, etc., or some combination thereof, describing the relationship between the DCI and the probability. The methods described herein may be implemented using experimental results (e.g., inspection, measurement, review, test, or some combination thereof), simulation results, experimental data, design information, historical data, , Such methods, algorithms, data structures, rules, and the like. In addition, the DCI may have any suitable format (number, alphabet, string, etc.). The DCI can be expressed in such a way that the user can easily understand the value of the DCI. For example, DCI is assigned a value between 1 and 10, 10 is the highest DCI, and 1 is the lowest DCI. The DCI may be expressed in a manner such that the method or system as used in one or more of the embodiments described herein may use the DCI to perform one or more of the steps described herein.

The method further comprises storing the DCI in a storage medium. The storing step may also include storing the DCI in addition to any other result of any of the method embodiments described herein. The DCI may be stored in any manner known in the art. The storage medium may also include any storage medium described herein or any suitable storage medium known in the art. After the DCI is stored, the DCI may be accessed and used within the storage medium by any method or system described herein. In addition, the DCI may be "permanently "," semi-permanently ", or temporarily stored for any period of time. In addition, the step of storing the DCI may be performed in any other manner described herein.

In one embodiment, the defect for which the DCI is determined includes a random defect. In another embodiment, the defects for which the DCI is determined include systematic defects. In this way, DCI can be determined for both random defects and systematic defects. The defects can be determined as random defects or systematic defects as further described herein. Further, although embodiments of the present method are described as including a step of determining DCI for a defect, the method may include determining DCI for one defect, some defect, or all defects detected on the wafer have. The defects for which the DCI has been determined in this way can be selected by the user. Alternatively, the defect for which the DCI is determined in the above manner can be selected by the method (e.g., one or more attributes of the defect, one or more attributes of the design data near the location of the defect in the design data space, And / or any other information of the design data, or some combination thereof).

In some embodiments, the one or more electrical attributes include functionality of the device. In this manner, the DCI may be determined based on the probability of a defect where the defect may cause the device to fail or not function. In another embodiment, the at least one electrical property of the device comprises at least one electrical parameter of the device. In this manner, the DCI can determine based on the probability that the defect will change one or more electrical parameters of the device. As such, the probability may be the probability that a defect will cause an electrical parameter issue. The electrical parameter issue is not qualified as an electrical defect in the electrical test and can be initiated to cause electrical defects over time on other wafers if the defect changes the electrical performance of the device and the defect persists It can be an instruction. The electrical parameters may include any electrical parameters known in the art such as speed, drive current, signal integration, and power distribution of the device.

In one embodiment, the one or more attributes of the design data include redundancy, a netlist, or some combination thereof. In another example, one or more attributes of the design data include the dimensions of the features in the design data, the density of features in the design data, or some combination thereof. Such an attribute can be used to determine the probability as described above. In a further embodiment, one or more attributes of the design data include one or more attributes of design data for one or more design layers of the device. In this way, the probability can be determined based on multi-layer context information for the defect, because the defect is propagated through the device and because the device formed on the wafer is typically formed in multiple layers, It is beneficial if it affects. Thus, a defect can change design data printed on one or more layers of a device, and changes to any layer, to some layer, or to all layers can change one or more attributes of the device. As such, by using one or more attributes of the design data to determine a probability, the probability can be determined based on how it affects one or more layers of the device, thereby possibly determining the probability and the determined DCI can further direct potential parameter issues and make them more yield related.

In some embodiments, the probability determination step includes determining a probability using a correlation between an electrical test result for the design data and one or more attributes of the design data. For example, the method may include performing data mining to determine whether there is a correlation between at least one attribute of the design data and the electrical test result. In particular, one or more attributes of the design data such as line width, spacing, etc. printed on the wafer can be measured and the electrical test results for the wafer can be used to determine the correlation between the attributes of the design data and the design data test results have. The electrical test results may include measurements of one or more attributes of one or more devices formed on the wafer, or may be used to determine one or more electrical attributes of the device. Thus, the correlation can be determined as a correlation between one or more attributes of the design data and one or more electrical attributes. The electrical test results can be any suitable electrical test result generated using any method or system known in the art. The defects may be identified as random defects in accordance with any of the embodiments described herein. Such correlation can be used to determine the probability for both systematic and random defects. Using such a correlation to determine the probability is advantageous because one or more attributes of the design data located close to the location of the correlation and defects in the design data space can be used to determine the probability relatively quickly.

In another embodiment, the step of determining the probability comprises determining the probability of the location of the defect in the design data space, the location of the defect reported by the inspection system used to detect the defect, the coordinate accuracy of the inspection system, Or a combination of some of these, to determine a probability based on one or more attributes of the design data. In one such embodiment, the defect includes random defects. In this manner, the defect size, the location of the defect reported by the inspection system, and the coordinate accuracy of the inspection system can be used to determine the DCI for the random defect. Using the defect size, defect size error, reported defect location, and coordinate accuracy to determine the DCI as described above is advantageous because the size and location of the random defect is relatively unpredictable. Thus, using such information to determine the DCI can increase the accuracy of the DCI.

In a further embodiment, determining the probability comprises determining a probability based on one or more attributes of the design data in combination with one or more attributes of the defect. In one such embodiment, the defects include systematic defects. In this way, a systematic defect attribute can be used to determine the DCI for systematic defects. Defects can be identified as systematic defects in accordance with any of the embodiments described herein. Since systematic defects in the design data can be determined with relatively high accuracy in the embodiments described herein, one or more attributes of the systematic defect can be used to determine the DCI for the defect.

In one embodiment, determining the DCI comprises determining a DCI for the defect based on a probability in combination with the category assigned to the defect. For example, the DCI may be determined based on probability, and the DCI may be modified based on the defect category to improve its DCI. In such an example, if the defect category indicates that the defect is a bridging defect, the DCI for the defect may be changed so that the modified DCI indicates a higher criticality for the defect than the originally determined DCI. In another example, if the defect category indicates that the defect is a partial bridging defect, the DCI determined for the defect may be changed so that the modified DCI indicates a lower threshold for the defect than the originally determined DCI. The category of defects used in this embodiment may be determined or assigned to defects according to any of the embodiments described herein or any other method or system for classifying defects known in the art. In addition, the DCI may be modified using any other result (e.g., KP value for the defect) or any other available information (e.g., hotspot information) of any of the steps of any of the methods described herein.

In some embodiments, the method includes determining the location of the inspection data within the design data space to determine design data that is close to the location of the defect in the design data space. In another embodiment, the method includes determining design data that is close to the location of a defect in the design data space by defect alignment that can be performed as described herein. In a further embodiment, the method can be used to determine the position of the defect reported by the inspection system used to detect the defect, the coordinate accuracy of the inspection system, one or more properties of the design data, defect size errors of the inspection system, Based on at least in part, the design data near the location of the defect. In this manner, design data near the location of the defect in the design data space can be determined based at least in part on the reported location of the defect and where the defect may be located within the coordinate accuracy of the inspection system. The design data beyond the location where the defect may be located can be determined in a similar manner.

In one embodiment, the method includes modifying the DCI based on the sensitivity of the yield of design data to the defect. In this manner, the DCI can be modified based on the sensitivity of the yield impact within an area of the design (e.g., a cell or a functional block). For example, the method may include determining the location of a defect in a design data space that may be performed as described herein, and may include determining the location of a defect located at such location and / Can be determined. Such yield sensing can be determined using any of the embodiments described herein. For example, the method may be implemented using design data relating to locations in the design data space for one or more different values of the design data, which may be selected based on how one or more of the attributes may be modified by the defect Modeling the electrical characteristics of the device. Such modeling may be performed as described herein and the modeled electrical characteristics may be used to determine how the yield changes as the value of one or more attributes of the design data change, Can be used to determine the yield of the design data for defects and / or defects in the design data near that location. In this manner, the location of the defects in the design data space can be used to determine the yield sensitivity of the design data for the defects. If the yield sensitivity of the design data for the defect is relatively high, the DCI for the defect can be modified so that the modified DCI indicates a higher threshold than the originally determined DCI. Similarly, if the yield sensitivity of the design data for a defect is relatively low, the DCI for the defect may be modified such that the modified DCI indicates a lower threshold than the originally determined DCI.

As described above, the DCI can be used in a number of ways in the embodiments described herein. For example, in one embodiment, the method includes modifying a process performed on a wafer based on a DCI determined for a defect. In one such embodiment, the process may be a metrology process or may comprise one or more measurements on the wafer. In this manner, the method may include employing a measurement process based at least in part on the DCI. In another example, the process is a defect review process. As such, the method may include employing a defect review process based at least in part on the DCI. Modifying a process as described above may include modifying any one or more of the parameters of the process. Such modifications may also be performed as further described herein.

In another embodiment, the method may include modifying a process used to detect a defect based on a DCI determined for the defect. Modifying the process used to detect the defect may include modifying any one or more of the parameters of the process as further described herein. In addition, changing the process used to detect defects based on DCI may be performed using feedback control techniques. In such an example, if the DCI for the fault indicates that the defect is relatively significant, the process used to detect the defect may be one or more locations on the wafer where the defect corresponding to the determined defect may potentially be located May be altered so that they may be inspected at a higher detection rate than previously used to inspect these locations. Other parameters of the process may be changed in a similar manner.

In some embodiments, the method includes generating a process for inspection of additional wafers to be fabricated, based on the DCI determined for the defect. In this manner, instead of changing a previously used process in which a defect is detected, the method can create an entirely new inspection process. A new inspection process may be generated for any one or more layers of additional wafers. For example, a process may be created for a layer where a DCI is determined to detect a defect. However, such inspection process may also be generated for one or more other layers of additional wafers. For example, if the DCI for a defect indicates that the defect is relatively significant, the process for inspecting a layer that is subsequently formed on the wafer may be such that a defect where the DCI can be caused by the determined defect is potentially located May be generated by selecting one or more parameters of the inspection process so that one or more locations on the subsequently formed layer may be inspected at a relatively high sensitivity. Other parameters of the process may be selected in a similar manner. The step of creating a process for inspecting additional wafers may be performed as further described herein.

In one embodiment, a computer-implemented method for determining a DCI is performed by an inspection system used to detect a defect. In this way, the method can be performed with an on-tool. In another embodiment, a computer-implemented method for determining DCI is performed by a system other than the inspection system used to detect the defect. As such, the method can be performed with an off-tool. The system used to perform the method with an off-tool can be configured as described further herein.

The DCI for defects can be used in a number of ways in the embodiments described herein, such as in sampling where defects for review are selected. For example, instead of performing random sampling of grouped defects, for each group where the defect is binned, a DCI may be used for sampling. In addition, the DCI determined for each defect can be used to determine which defect has a high probability of changing one or more electrical properties of the device, and a defect with a high probability of changing one or more electrical properties is sampled more intensively . DCI can be used to sample random faults as well as systematic faults.

Each embodiment of the method for determining the DCI described above may include any other step of any of the methods described herein. Also, each embodiment of the method for determining the DCI described above can be performed by any of the system embodiments described herein.

Another embodiment relates to a computer-implemented method for determining a memory repair index (MRI) for a memory bank formed on a wafer. The memory die includes a memory bank (often several memory banks). Each memory bank includes an array block area (or raw area) and a redundancy area. The redundancy area contains a plurality of columns and a plurality of rows and is used to repair the memory banks. The number of columns and rows contained in the memory bank is user-defined. The array block may be generally rectangular or rectangular in shape. Redundant rows can be formed along one side of the array block area, and redundant rows can be formed along the other side. The memory bank may also include a column decoder adjacent to the redundancy column, a row decoder adjacent to the redundancy row, and a sense amplifier amp adjacent to the row decoder. The method may also include detecting redundant rows and columns, sense amplifiers, and the location of the decoder for each array block region. Such a location can be determined using any method or system known in the art.

The method includes determining a plurality of redundancy rows and a plurality of redundancy rows required to repair a memory bank based on a defect located in an array block region of the memory bank. For example, in some embodiments, the method may include determining if any of the defects located in the array block area can cause the bits in the memory bank to fail, and determining if the bits are defective based on the location of the defects And determining the location of the failed bit. Alternatively, the method may include determining which defects in the array block area may cause the bits in the memory bank to fail, and determining whether the defective bits in the array block area may cause failures in the memory bank based on the location of the defects, And determining the position of the first antenna. Determining which defects in the array block area cause or cause a bit to fail may be performed using one or more attributes of the defect, which attributes may include any of the defect attributes described herein and / Or the results of one or more other steps of any of the methods described herein. For example, in combination with the DCI for defects, possibly possibly determined as described herein, and possibly in combination with electrical test results for associated test and / or memory banks, the reported defect locations, defects The defect size, and the defect size inaccuracy of the inspection system can be used to determine if a defect may or may not cause a bit failure.

In one such embodiment, the step of determining the number of redundant rows and the number of redundant rows required to repair the memory bank is performed using the location of the failed bit. This step may alternatively be performed using the location of the failing bits. For example, individual fault bits need not be replaced on a one-to-one basis with redundancy columns and rows. Instead, if the individual fault bits are "adjacent" to one another along the same logical column or row, the entire column or row becomes a candidate for substitution by the reserved redundant column or row. Thus, the locations of the failing or failing bits can be used to determine which failure bits are "adjacent" to one another along the same logical column or row, and determine the number of redundant columns and rows needed to repair the memory bank Can be used. In this manner, the method may include a predictive bit failure estimation, which may be used to determine and / or monitor the amount of redundancy that may be consumed by the failed bit.

Also, although the two memory bits may be physically adjacent to each other within the layout, they may belong to different logical columns or rows. That is, physical adjacency may not be associated with logical or electrical adjacencies. For example, if logical column 1 contains 256 bits, then 256 bits do not need to touch each other within the physical layout of the bank or segment. As such, the physical (or topology) address may be translated to a logical (or electrical) address through a mapping function that may differ for each device. Such mapping can be performed using any suitable method or system known in the art. For example, a commercially available Klarity Bitmap from KLA-Tencor provides a graphical or easy way to create a topological-to-electrical mapping. Thus, using such a mapping function in the present method may allow the determination of the MRI to reflect the repairability of the memory bank.

Defects located within the array block area can be identified from the location of the memory bank. For example, the test can detect defects in both the array block area and the redundant area (or across the entire memory bank), and the defects are separated into defects in the array block area and defects in the redundant area based on the location of the defects Which may be determined according to any of the embodiments described herein. Separating the defects into array block regions, redundancy regions, decoder regions, and sense amplifier regions provides an improved value for the test results because such isolation can be used to isolate repairable defects from non-repairable defects . In addition, the separation of defects into artifacts, redundancy, decoders, and defects in the sense amplifier area can be rule-based or area-based.

The method includes comparing the number of redundancy columns required to repair a memory bank to the number of redundancy rows available for a memory bank. The method also includes comparing the number of redundancy rows required to repair the memory banks to the available redundancy rows for the memory banks. In some embodiments, comparing the number of redundant rows is performed independently for each bank of memory dies, and comparing the number of redundant rows is performed independently for each bank of memory dies. The steps of comparing the number of redundant rows and comparing the number of redundant rows may be performed in any suitable manner.

In another embodiment, the method includes determining an amount of available redundancy row and an incentive of the available redundancy row based on a redundancy located in the redundancy column and the redundancy row of the memory bank. The redundancy column and the defects located in the row can be identified as described above. Since the memory bank failure may occur if the redundancy is sufficiently defective, it may be advantageous to determine the amount of available redundancy as described above. Also, when the redundancy is spatially defective, the amount of redundancy available for repairing the memory bank is reduced, and the memory bank is irreparable if the number of defects exceeds a non-defective redundancy. As noted, since each bank has its own redundant column and row set, and the fault bits in each bank can only be replaced by the available redundant columns or rows in the same bank, the amount of available redundancy is dependent on the amount of available redundant bank ≪ / RTI >

The amount of available redundancy can be determined based on one or more attributes of the defect located in the redundancy area and the defect located in the redundancy area. The one or more attributes used in this step may include one or more of the attributes described herein. The determination of the available redundancy can also be performed (or alternatively) using any result of any of the steps of any of the methods described herein. For example, the reported defect size of the defect in the redundant area, the coordinate accuracy of the inspection system used to detect the defect, and the category assigned to the defect can be used to determine whether the defect can cause a failure in the redundant area , Which can be used to determine the amount of available redundancy.

The method further includes determining an MRI for the memory bank based on the results of comparing the number of redundant rows and comparing the number of redundant rows. The MRI indicates whether the memory bank is repairable. For example, if the number of redundant rows and / or rows required to repair a failed bit is greater than the number of available redundant rows and / or rows, the memory bank is unrepairable and the die is unrepairable. The MRI may be determined based on the compared comparison and may be assigned a value indicating whether the memory bank is repairable or not. For example, if the memory bank is repairable, a first value may be assigned to the MRI, and a second value may be assigned to the MRI if the memory bank is unrepairable. Different values for MRI can be represented in any suitable format (e.g., such that the value is easily understood by the user and / or the value can be used by the method embodiments described herein). Suitable formats may include, without limitation, numbers, alphabets, strings, and the like.

The method also includes storing the MRI in a storage medium. The storing step may include storing the MRI in addition to any other result of any of the method embodiments described herein. In addition, the storage medium may comprise any of the storage media described herein, or any other suitable storage medium known in the art. After the MRI is stored, the MRI may be accessed and used within the storage medium by any method or system embodiment described herein. In addition, the MRI can be stored "permanently "," semi-permanently ", or temporarily for any period of time. The step of (or alternatively) storing the MRI may also be performed as described herein.

Thus, the exemplary method embodiments can be used for the initial detection of memory loss using MRI, which is advantageous for a number of reasons and can be used in a number of ways. For example, in one embodiment, the method includes determining an MRI for one or more memory banks formed in the die, and predicting the repair yield for the die based on the MRI for the one or more memory banks. Because each bank or segment of the die has a corresponding set of redundant columns and rows available for repair, it is advantageous to predict the repair yield for the die based on the MRI determined for the memory bank in the die. Only the fault bits in a particular bank or segment can be replaced by the corresponding redundant column or row. Thus, it is possible to "run out" redundancy for one bank while the other banks in the die have available redundancy. In this case, because the at least one bank or segment is irreparable, the die is no longer completely repairable. As such, based on the MRI for the memory bank in the die, the method can determine the yield of the repair process performed on the die. In addition, an MRI indicating that the die is repairable may be determined for the die based on the MRI determined for the memory bank in the die. For example, if the MRI for a memory bank indicates that any memory bank is irreparable, the MRI may be determined to be a value indicating that the memory die is irreparable.

In another embodiment, the method includes determining an MRI for each memory bank in at least one die on the wafer, and determining a memory yield for one or more die based on the MRI for each memory bank do. These steps can be performed as described above. This embodiment of the method can be used to determine the die-die memory yield. Also, the memory yield for one or more dice can be used to determine the memory yield for the wafer.

In another embodiment, the method includes combining a memory yield prediction with an out-of-memory yield outcome to determine an overall yield prediction.

In a further embodiment, the method includes performing a wafer placement based at least in part on one or more memory yields for one or more dies on the wafer. For example, the method described herein can be used to perform in-line placement of wafers, thereby allowing for better (e.g., more effective) WIP planning and reduced manufacturing costs. For example, the number of dies with memory yields below some predetermined threshold may be determined and used to determine whether repair should be performed on the wafer, whether the wafer should be rewritten, whether the wafer should be scrapped, and so on. In such an example, the number of dies with memory yields below a certain threshold may be compared to other predetermined thresholds, and both thresholds may be used to indicate the minimum wafer-based yield required to determine whether repair should be performed on the wafer Can be selected. For example, the threshold is selected such that the estimated value of the wafer corresponds to a minimum memory yield that does not exceed the cost of completing the wafer (e.g., by the user or by one or more embodiments described herein). In another embodiment, the method may comprise determining a memory yield for the wafer based on memory yield for one or more dies on the wafer. Thus, if a memory repair process is performed on more than one die on a wafer, the memory yield may be the yield after that memory repair process. The memory yield for the wafers can be used to place the wafers as described above. For example, the value of the wafer after the memory repair process may be determined based at least in part on the memory yield, and the value may be compared to the cost of completing the wafer to determine if the wafer should be scrapped.

In one embodiment, comparing the number of redundant rows includes determining a fraction of redundant rows required to repair a memory bank, wherein comparing the number of redundant rows includes comparing the fraction of redundant rows required to repair the memory bank Wherein determining the MRI for the memory bank comprises determining the MRI based on the fraction of redundant rows and the fraction of redundant rows.

The method comprising determining the MRI based on the fraction as described above may comprise any of the other steps described herein. For example, in one such embodiment, the method includes determining an MRI for each memory bank in at least one die on the wafer, and determining memory yield for one or more die based on the MRI for each memory bank . The steps of this embodiment may be performed as further described herein. In another example, in another such embodiment, the method further comprises determining an MRI for each memory bank in the at least one die on the wafer, and determining a memory yield for one or more die based on the MRI for each memory bank Determining a memory yield for the wafer based on the memory yield for each of the one or more dies. The steps of this embodiment may be performed as further described herein. In this manner, the method may include using MRI to predict memory yield on a wafer-to-wafer basis. In a similar manner, the MRI can be determined for each die on the wafer, and the MRI for each die can be used to determine the wafer-based memory yield. For example, the wafer-based memory yield may be determined by dividing the sum of the MRIs for each die on the wafer by the number of die on the wafer to determine the fraction of die on the wafer that is good or repairable for the memory. The fraction of die on a good or repairable wafer may possibly be used in combination with information about the repair process, such as historical yield or success rate.

In some embodiments, the MRI may also indicate a probability that the memory bank can not be repaired. In this manner, the MRI can indicate whether the memory bank is repairable and how the memory bank is unrepairable. The probability that the memory bank is unrepairable may be determined by comparing the number of available redundant rows that may be performed as described above to the number of redundant rows required for repair and comparing the number of available redundant rows to the number of redundant rows required for repair Possibly in combination with one or more attributes of the defect, one or more attributes of the memory design, and one or more attributes of the repair process. Such an attribute may include, for example, the historical success rate of the repair process performed in another memory bank whose design is at least similar to the memory bank for which the probability is being determined. The MRI can be represented by two values, one indicating that the memory bank is not repairable and the other indicating the probability that the memory bank is unrepairable. Alternatively, the MRI may be represented by a single value indicating whether the memory bank is repairable and whether the memory bank is non-repairable. The two values and the single value can be expressed in any of the formats described herein. In one such embodiment, the method includes determining an MRI for each memory bank in at least one die on the wafer, and determining an MRI for the one or more die based on the MRI for each memory bank in the at least one die . These steps may be performed as described herein. In such an embodiment, the MRI for one or more dice indicates the probability that one or more die may be unrepairable (the MRI for each memory bank indicates the probability that the memory bank may be unrepairable, Since the possibilities are related to the repairability of the memory bank as further described herein). In one such embodiment, the method includes determining a wafer-based memory yield based on a threshold of MRI for at least one die on the wafer. The wafer-based memory yield prediction can be performed as described above, but the yield of the wafer may not be the yield of the repair process as described above.

In some embodiments, the method includes identifying non-repairable defects in the memory bank based on one or more defects located within the decoder region of the memory bank, one or more defects located within the amplifier region of the memory bank, or some combination thereof do. For example, a check of a memory bank may be performed to detect defects in all areas within the memory bank (including around logic, decoder areas, and sense amp areas), and may be determined according to any of the embodiments described herein The location of a defect in a memory bank may be used to determine which region of a memory bank each or one or more defects are located. The number of non-repairable defects in the memory bank may be determined, at least in part, by the number of defects detected and positioned within the decoder region and the sense amplifier region. The method may also include estimating memory yield based at least in part on non-repairable defects in the memory bank, which is advantageous because non-repairable defects can damage the die.

In one embodiment, the method includes modifying one or more parameters of the electrical test process based on MRI using feedforward control techniques. In another embodiment, the method further comprises altering one or more parameters of the electrical test process based on the MRI using a feedforward technique so that the die on which the memory bank is located is not tested during the electrical test process if the memory bank is unrepairable . For example, memory testing takes a relatively long time. Thus, based on a prediction that the memory bank or memory die, which may be determined as described above, is irreparable, the information may be stored in a probe or other memory test system such that the affected unrepaired die is skipped during the memory test. Can be supplied. In this way, the amount of test can be reduced, thereby reducing the cost of the memory test. Memory tests may also include open / short tests, functional tests, and electrical parameter tests. If such a test can be eliminated using the method described herein to determine which die can be repaired, the memory test process can be performed in a much shorter period of time. Alternatively, the electrical test process may be modified to collect more relevant test data for additional FAs on the die that can not be repaired, and the test may be performed at a specific location based on the predicted impact of various possible error mechanisms Lt; / RTI > The memory repair may also include laser or electrical means for blowing the fuse, thereby re-routing the decoder to the redundant column and / or row. The memory test can be performed after memory repair to verify repair and to perform additional tests such as stress testing. Thus, by determining which die can be repaired, as described herein, memory repair and additional memory testing can be performed only on a repairable die, thus significantly reducing time.

In some embodiments, the method includes modifying one or more parameters of the repair process based on at least one attribute of the defect located within the array block of the memory bank, the MRI, or some combination thereof. For example, the memory repair process may be changed so that repair is not attempted for a memory die that includes a memory that is determined to be non-repairable. In addition, the memory repair process may be modified to increase the probability that the repair is successful. One or more parameters of the repair process modified in this embodiment may include any parameters of the repair process.

In some embodiments, the defect includes a defect detected in the gate layer of the memory bank. In another embodiment, the defect includes a defect detected in the metal layer of the memory bank. For example, in memory fabrication, inspections can be performed on the gate and metal layers. The methods described herein can be performed on defects detected in one or more of these layers. Also, although most memory fabrication involves inspection at the gate and metal layers, and inspection results generated at the gate and metal layers are sufficient to predict yield, inspection may also be performed at the capacitor layer for bit repair. Thus, test results generated in gates, metals, and capacitors can also be used to predict yield. In addition, the embodiments described herein can be performed for defects detected in the capacitor layer.

In one embodiment, the method includes predicting a bit error mode of the defect based on the location of the defect in the memory bank. In this way, the location of the defect can be used to predict the bit error mode. Such information may be useful in determining the amount of redundancy needed to repair a memory bank. For example, a defect in the n-MOS region of a memory bank may cause a sense amplifier error, thereby consuming more redundancy than a defect in the n-MOS region. One or more attributes of the design data near the defect and / or one or more attributes (e.g., size) of the defect may be used to improve the prediction of the bit error mode. In addition to supporting the prediction of the redundancy required for repair, the prediction of the error mode will lead to a quick or better identification of the defect causing the bit error. All predictions can allow the DOI to be identified and reviewed, which is impossible without FA if the bit error is not detected in the test. It is possible to identify and review defects responsible for potential errors in the device and to use available redundancy to reduce the potential error rate. In this manner, the defects can be mapped to areas of memory (e.g., sense amplifiers) and defects and / or design attributes can be used in combination with the rules for predicting the bit error mode

In some embodiments, the method includes determining, based on the MRI, the amount of available redundancy rows in the memory bank, the amount of available redundancy rows, or some combination thereof, to be evaluated by a memory bank designer. In this manner, the method may include performing a "redundancy analysis" to suggest to the designer whether the step of adding more rows or columns in the redundancy area should be performed in a particular memory bank. The method described herein is particularly advantageous in providing feedback on the design of the die because the method described herein can be used for the initial detection of lethal wafers and allows rapid yield learning.

In another embodiment, the method includes determining a DCI for one or more defects located within the array block area. The DCI for one or more defects may be determined as described herein. In one such embodiment, determining the number of redundancy columns required for repair of the memory bank and determining the number of redundancy rows is performed using the DCI for one or more defects. In another embodiment, determining the number of redundancy rows required for repair of a memory bank and determining the number of redundancy columns includes determining a DCI for each defect located in an array block region of a memory bank, , Comparing the DCI to a predetermined threshold, and determining the number of redundant rows and redundant rows required to repair all defects with a DCI above a predetermined threshold. For example, the DCI may be determined for all defects located within the array block area. The DCI may be performed for defects located within the array block as further described herein. The method may also include using DCI to predict the number of column or row errors caused by the defect. For example, if the number of defects having a DCI that is greater than a predetermined value that can be user defined is greater than the number of rows or columns in the redundant area, then the MRI (in this example redundant row or row (Defined as a ratio) may be determined to be greater than one (failure). In contrast, if the number of defects having a DCI that is smaller than the second predetermined value, which may be user-defined and may differ from the first predetermined value, is less than the number of rows or columns in the redundant area, then the MRI is determined to be less than one (Pass, perhaps with some repairs). The method may also include determining a maximum count or percentage of available redundant rows and / or rows that may be needed to repair a memory bank if all defects with DCI above the threshold require repair.

Because the actual yield impact of individual defects may vary depending on pattern errors caused by the defects, one or more attributes such as the location of the defect (e.g., top of the layer, buried in the layer, etc.), defect size, It is advantageous to use the DCI to determine if it is repairable. The DCI can be determined based on such variations in defects as described herein, thereby reflecting how the different defects affect the actual yield. In addition, since systematic defects have more actual yield impacts, the methods described herein can be used to determine which defects detected in a memory bank are systematic defects, and the steps described herein based on the criticality of systematic defects As well as determining the MRI. Systemic defects may be identified in accordance with any of the embodiments described herein.

In some embodiments, the method includes determining an MRI for an error in a memory bank due to a defect located in an array block area of the memory bank. In this manner, the method may include determining an index for a segment error due to a detected defect in a non-redundant area of the memory bank. In a similar manner, the method may comprise determining an index for a segment error due to a detected defect in a redundant area of a memory bank.

In another embodiment, the method includes determining an MRI for a memory bank error due to a defect located in the redundant column and redundant rows of the memory bank. In this manner, the method may include determining an index for logical column and / or row errors. Such an index may be used to change one or more parameters of the test process as described above.

In some embodiments, the method includes generating a stack map of a pseudo memory bank design that represents a spatial correlation between detected defects in a memory bank. In this manner, the method may include generating a stack map showing spatial correlation. Such a lamination map may be generated in any suitable manner known in the art.

In one embodiment, the method includes determining MRI based on a die. In a similar manner, the method may include determining MRI on a wafer substrate and / or on a lot basis. The step of determining the MRI based on die-based, wafer-based, and / or lot-based may be performed as described herein.

In another embodiment, the method includes determining an index or memory yield prediction that indicates that the die on the wafer is failing due to a defect located in the array block area. In this manner, the method may include determining the index or probability that the die will fail due to a bad memory bank. Such an index can be determined as further described herein.

In a further embodiment, the method includes the steps of determining an MRI for a memory bank in a die on a wafer, generating a stack map of the die representing a spatial correlation between two or more memory banks indicated by the MRI as unrepairable . The step of determining the MRI for the memory bank in the die may be performed as described herein. The lamination map may also be generated in any suitable manner known in the art.

In a further embodiment, the method includes determining an MRI for a memory bank in a die on a wafer, and forming a memory bank on the wafer indicative of a spatial correlation between the two or more memory banks indicated by the MIR as unrepairable And generating a stack map of the used reticle. The lamination map may also be generated in any suitable manner known in the art.

In some embodiments, the method includes identifying a memory bank of the die affected by the detected defect in the die, and rating the memory bank based on the effect of the defect on the memory bank . In this manner, the method may include the step of rating the affected memory bank list. The effect of a defect on a memory bank may be determined based on any of the information described herein (e.g., one or more attributes of a defect, one or more attributes of design data for a memory bank, etc.). The effect of a defect on a memory bank, which is used to rank the memory bank, may include any effect (e.g., any adverse effect) that is defective for the memory bank. Memory banks are rated in such a way that a memory bank that is most affected by a defect is assigned a highest rating and a memory bank that is least affected by a defect is assigned a lowest rating. Such a rating of a memory bank may be used, for example, to determine the relationship between the location of the memory bank in the die and the degree to which the defect affects the memory bank. Such a relationship may also be used to predict the cause of at least some of the defects, which may reduce defects on additional wafers and / or affect the memory bank prior to reducing small defects (e.g., (E.g., using one or more of the change steps described herein, such as changing a process performed on a memory bank prior to the detection of a fault, to reduce the number of defects that have the greatest effect on the memory bank) ). ≪ / RTI >

In another embodiment, the method includes determining a percentage of a memory bank formed on a wafer affected by a defect in a non-repairable area of the memory bank. The memory bank affected by the defects in the non-repairable area of the memory bank may be determined as described herein. The percentage can be determined based on the number of such memory banks and the total number of memories formed on the wafer. The method may also include determining a percentage of the die affected by errors that are affected by and / or unrecoverable errors due to possible redundancy errors. Possible redundancy errors and irreparable errors can be identified as described herein. Also, the die affected by possible redundancy errors and / or non-repairable errors may be identified as described herein. The number of dies affected and the total number of dies formed on the wafer may be used to determine the percentage of die affected by possible redundancy errors and / or unrepairable errors.

In some embodiments, the method includes generating a stacked wafer map of possible errors in a memory bank formed on the wafer that exhibits spatial correlation between possible errors. In this manner, the method may comprise generating a laminated wafer map of binned wise (for spatial correlation) or possible errors. Possible errors can be identified as described herein, and laminate wafer maps can be generated in any suitable manner. The stack map may alternatively display or overlay the probability that the die will have a memory error by the same method as the color coding probability bin.

In another embodiment, the method includes determining an MRI for one or more dies formed on a wafer, and rating the one or more dies based on the MRI. In this manner, the method may include generating a ranked list of the affected die on the wafer. The MRI for one or more dies can be determined as described herein. In addition, the step of rating one or more dies based on the MRI may be performed as described herein, and such grades may be used as described herein.

The method for determining the MRI described above may include any other step of any of the methods described herein. Further, each embodiment of the method for determining the MRI described above can be performed by any of the system embodiments described herein.

Another embodiment relates to another method of binning detected defects on a wafer. The method includes comparing a location of a defect in the design data to a location of a hotspot in the design data. Hot spots located at least close to similar design data are correlated with each other. Hot spots are correlated by any other method or system. Alternatively, the hot spots may be correlated to each other by one embodiment of the method. For example, in one embodiment, the method may include identifying locations of POIs in the design data associated with systematic defects to correlate hotspots, correlating POIs with similar patterns in the design data, And correlating the location of the POI with the location of a similar pattern in the design data as the location of the hotspot. In such an embodiment, systematic defects may be included in a data structure, such as a list, database, or file of systematic defects for design data, which may be generated by other methods or systems. In another such embodiment, the method includes identifying systematic defects and / or determining a POI in design data for systematic defects. For example, a systematic defect can be identified by binning the detected defect on the wafer based on the portion of the design data that is close to the location of the defect in the design data space, which can be performed as described above. The POI may be determined by extracting patterns in the design data portion corresponding to the group of binned defects and hot spots may be correlated with each other using design background grouping, which may be performed as further described herein . Also, hot spots can be correlated with each other by binning hot spots, which can be performed as described further herein. The steps of associating the hot spots with each other can be performed with an on-tool. The location of the correlated hotspots may be stored in a " hotspot list "or any other suitable data structure, including some indication of which hotspots are related to each other, the identity of the hotspots in the list, and Contains the location of the hotspot in the list. This list can be used essentially as reference data in the binning method.

The method also includes associating a defect with a hot spot having at least a similar location. In particular, hot spots and defects having at least similar locations within the design data space can be determined based on the results of the above-described comparison step. Hot spots and defects having locations within the design data space are associated with each other in any suitable manner. The method also includes grouping the defects into groups such that defects in each group are associated only with hot spots that are correlated with each other. In this manner, each group of defects can correspond to an interrelated group.

The method further comprises storing the result of the binning step on a storage medium. The storing step may include storing the result of the binning step in addition to any other result of any of the method embodiments described herein. The results of the binning step may be stored in any manner known in the art. In addition, the storage medium may comprise any of the storage media described herein or any other suitable medium known in the art. After the results of the binning step are stored, the results of the binning step may be accessed and used by any method or system as described herein. In addition, the results of the binning step may be stored "permanently "," semi-permanently ", or temporarily for any period of time. Storing the results of the binning step may be further performed according to any of the other embodiments described herein.

In one embodiment, the method comprises assigning a DBC to one or more groups. The step of assigning the DBC to one or more groups may be performed according to any of the embodiments described herein. In another embodiment, the method includes determining a DCI for one or more defects. The step of determining the DCI for one or more defects in this embodiment may be performed according to any of the embodiments described herein.

In another embodiment, a computer-implemented method is performed by an inspection system used to detect defects on a wafer. In this way, the computer-implemented method can be performed with an on-tool. The method may also include performing hot spot management with an on-tool. Hot spot management may include, for example, hot spot navigation, hot spot monitoring, hot spot revision, or some combination thereof, each of which may be performed as further described herein. For example, in some embodiments, a hot spot is identified by an inspection system used to detect defects on the wafer. In this way, hot spots can be identified or searched on-tool. Such identification or searching of hot spots may be performed as described herein (e.g., by performing a design background based grouping of defects detected on the wafer).

In another embodiment, the method includes monitoring a hot spot using the inspection results of one or more wafers on which design data is printed. The step of monitoring the hot spot based on the result of the inspection can be performed as described herein. Such monitoring of hot spots can be performed on-the-fly. Hotspot monitoring is the result of assigning one or more DBCs to one or more defects that can be performed as described herein as a result of one or more of the binning methods described herein, (Or alternatively) using any other result of the method, or some combination thereof.

In another embodiment, the method includes examining a wafer based on a correlation between hot spots. For example, the locations on the wafers corresponding to different groups of interconnected hot spots can be examined differently. Wafer inspection based on correlation between hot spots can also be performed based on one or more attributes and correlations of design data corresponding to groups of interconnected hot spots. For example, the location of a group of interconnected hot spots corresponding to design data, particularly those with high yield sensitivity to defects, can be used to determine the location on the wafer to be inspected at a higher detection rate than usual. One or more attributes of the design data used in the present embodiment may include one or more design data attributes described herein. In addition, one or more parameters of the inspection process can be altered so that the locations on the wafer corresponding to different groups of interconnected hotspots can be examined differently. One or more parameters of the test may include one or more parameters as described herein.

In some embodiments, the method includes monitoring systematic defects, potential systematic defects, or some combination thereof over time using the results of the binning step, which may be performed according to any of the embodiments described herein . In another embodiment, the method includes identifying systematic defects and potential systematic defects in the design data based on the results of the binning step, and monitoring the occurrence of systematic defects over time and potential systematic defects . The steps of this method embodiment may be performed as described herein.

In another embodiment, the method includes performing a review of the defect based on the result of the binning step. For example, a review of a defect may be performed (e.g., using at least one different value of one or more parameters of the review process) for a group of defects corresponding to different groups of interconnected hotspots to be reviewed differently. The wafer review based on the results of the binning step may be performed based on the binning results and one or more attributes of the design data corresponding to the groups of hot spots correlated. In this manner, a review of the defect based on the result of the binning step can be performed as described above for the step of inspecting the wafer based on the correlation between the hot spots.

In a further embodiment, the method includes generating a process for selecting a defect for review based on a result of the binning step. The step of creating a process for selecting defects for review in this embodiment may be performed according to any of the embodiments described herein. In addition, the process for selecting a defect for review may be combined with information on correlated hot spots associated with a group of defects, possibly as a result of any other step of any of the methods described herein, (E.g., one or more attributes of the design data, one or more attributes of the defect, etc.). In addition, creating a process for selecting a defect may include selecting a value for any one or more of the parameters of the process used to select the defect.

In another embodiment, the method includes generating a process for inspecting a wafer on which design data is printed based on the result of the bitmap step. The step of creating a process for inspecting wafers in this embodiment may be performed according to any of the embodiments described herein. In addition, the process for inspecting the wafers may be performed in combination with information about interconnected hot spots associated with a group of defects, possibly as a result of any other steps of any of the methods described herein (e.g., The above attributes, one or more attributes of the defects, etc.), based on the result of the binning step. In addition, creating the process for inspecting the wafer may include selecting a value for any one or more of the parameters of the process used to inspect the wafer.

In a further embodiment, the method includes modifying a process for inspecting a wafer on which design data is printed based on a result of the binning step. The step of changing the process for inspecting the wafers in this embodiment may be performed according to any of the embodiments described herein. In addition, the process for inspecting the wafers may be performed in combination with information about interconnected hot spots associated with a group of defects, possibly as a result of any other steps of any of the methods described herein One or more attributes of the defect, one or more attributes of the defect, and the like). In addition, modifying the process for inspecting the wafer may include selecting a value for one or more parameters of the alteration process used to inspect the wafer.

In some embodiments, the method includes determining a percentage of a die formed on a wafer affected by a defect of at least one group. In such an embodiment, the percentage of die may be determined according to any of the embodiments described herein.

In another embodiment, the method includes determining a percentage of a die formed on a wafer on which a defect binned into at least one group is located, and assigning a priority to at least one group based on the percentage do. The determination and assignment of priorities may be performed according to any of the embodiments described herein.

In a further embodiment, the method includes prioritizing one or more groups by the number of total hot spots correlated with the hot spots associated with the defects in the at least one group and the number of defects within the at least one group. For example, the number of hot spots in an interconnected hot spot group may be compared to the number of defects in a group corresponding to a hot spot group. As such, the degree of defect of an interconnected hot spot group can be determined (e.g., determining the fraction of correlated hot spots in which a defect was detected and / or determining the percentage of correlated hot spots in which a defect was detected due to). Thus, the group of defects can be prioritized by the degree of defect of the correlated hot spots. For example, a large percentage of defects, large fractions, or corresponding hot spots within a group that are detected in large numbers may be assigned a higher priority than a small percentage of detected defects, a small fraction, or a small percentage of corresponding hot spots have. Thus, the group of defects can be prioritized according to the degree of hot spot defect across the wafer.

In a further embodiment, the method comprises prioritizing one or more groups by a number corresponding to hot spot locations on a reticle used to print design data on a wafer on which defects in one or more groups are detected at least once . For example, a defect group corresponding to a plurality of hot spot positions on the reticle may be assigned a higher priority than a defect group corresponding to a few hot spot positions on the reticle. Thus, the group of defects can be prioritized based on the degree of potential defect across the wafer. In addition, when the number of times a reticle is printed on a wafer is known or determined, the potential defectivity of the group across the reticle can be used to determine or estimate the degree of potential defect of one or more groups across the wafer. The results of the prioritization step may be used to perform one or more of the steps described herein.

In some embodiments, the method further comprises determining, based on the number of positions on the reticle where a defect binned in one or more groups is detected, and the total number of hot spot locations on the reticle correlated to a hot spot associated with a defect in the one or more groups, And determining a reticle-based margin for the one or more groups. For example, the number of locations where defects in a group of interconnected hot spots on the reticle are detected may be compared to the number of locations where defects in the group corresponding to the group of interconnected hot spots are detected. Thus, reticle-based margins may be based on such comparisons and may be a measure of the degree of defect over the location of the correlated hot spots across the reticle. Such reticle based margins can be used in one or more steps as described herein.

Each of the method embodiments for boring a defect as described above may include any other step of any of the methods described herein. Further, each of the method embodiments for boring a defect as described above may be performed by any of the system embodiments described herein.

Another embodiment relates to another method for binning detected defects on a wafer. In such an embodiment, the method includes comparing at least one attribute of the design data near the location of the defect in the design data space. In one embodiment, the one or more attributes comprise a pattern density. In another embodiment, the one or more attributes include one or more attributes within the feature space. The feature space may include one or more features derived from the design data. Unlike the design space, the feature space has the ability to effectively consider various attributes that may be useful in determining a group of defects in a supervised manner (e.g., nearest neighbor binning technique) or non-supervised manner (e.g., natural grouping technique) Respectively. One or more attributes of the design data used in this step may also (or alternatively) include any other attributes of the design data, defect data, hotspots, or POIs described herein.

The method also includes determining if at least one attribute of the design data near the location of the defect is at least similar based on a result of the comparing step. The determination of whether one or more attributes are at least similar may be performed in a manner similar to other steps for determining the similarity described herein. The method also includes grouping the defects into groups such that at least one attribute of the design data near the location of the defects in each group is at least similar. The binning step may be performed in a similar manner to the other binning steps described herein. The method further comprises storing the result of the binning step in a storage medium, which may be performed as described herein.

In some embodiments, the method includes determining if the defect is a random or systematic defect using an attribute. Attributes can also be used directly for random or systematic defects. One or more attributes may be used to determine whether the binned and / or non-binned defects are random or systematic defects. One or more attributes of the design data may be combined with any other result described herein and / or any other information described herein (e.g., one or more of hotspot information and defects), to determine if the defect is a random defect or a systematic defect. Attribute). In one example of the above-described embodiment, one or more attributes of the design data used to determine whether the defect is systematic or random may include one or more attributes of the characteristics of the design data at the location of the defect for the feature. For example, if one or more attributes of the design data near the location of the defects in the design data space have relatively high pattern densities and relatively small feature dimensions, and if the design data having such properties are known to be systematic defects , Simulations, or any other suitable method or system), the defect is determined to be a systematic defect.

In another embodiment, the method includes rating one or more groups using attributes. The one or more attributes used to rank the defects of one or more of the binned groups may include any of the attributes described herein. In one example, because the defect located in the high pattern density region of the design may have a more deleterious effect on the yield, the group of the binned defects may have a higher defect density than the group of defects associated with the higher pattern density And may be graded based on the pattern density so as to be graded high. Such a ranking result may be used as described herein (e.g., the result may be used in place of the prioritization result in the step comprising the prioritization result).

Attributes may also be used to rank defects in a group. For example, in a further embodiment, the method includes rating the defects into at least one group using one or more attributes. The attributes of the design data used to rank defects into groups may be any of the attributes described herein. In addition, the attributes used to bin defects may or may not be the same as those used to rank defects in the group. The binning and grading step in this embodiment can advantageously provide a fine separation of defects into groups and grades, which can provide more information about the impact of defects on yield. The step of grading the defects in the group can be performed as described herein. Also, defects in one or more groups may be individually graded within its group. The result of grading the defects in the group may be used in one or more of the steps described herein.

Attributes may also be used to bin defects within a group. For example, in a further embodiment, the method includes binning a defect in at least one group into a sub-group using one or more attributes. The attributes of the design data used to bin the defects in a group into sub-groups may include any of the attributes described herein. Also, the attributes used to group defects into groups may or may not be the same as those used to bin the defects into sub-groups. The step of binning defects into groups and sub-groups in this embodiment can advantageously provide a finer separation of defects into groups and sub-groups, which provides more information about the impact of defects on yield . The steps of binning a defect within a group into a sub-group may be performed as described herein. Also, defects in one or more groups can be individually binned into one or more subgroups. The results of binning the defects into the groups and sub-groups may be used in one or more of the steps described herein.

In some embodiments, the method includes analyzing a defect in at least one group using one or more attributes. In this way, attributes can be used to analyze defects within a group. The DCI decision is an example of this type of analysis. For example, in a further embodiment, the method includes assigning a DCI to one or more defects using an attribute. The attributes of the design data used to analyze the defect may include any of the attributes described herein. The analysis may also (or alternatively) include any other analysis described herein.

In another embodiment, the method includes determining yield relevance of one or more defects using one or more attributes. In this manner, the attributes can be used to estimate the yield relevance of individual defects. One or more attributes used to determine yield relevance may include any of the attributes described herein. In such an example, a defect located close to the design data having a relatively high pattern density can be determined to be more yield related than a defect located close to the design data having a relatively low pattern density. In addition, the yield relevance can be determined based on one or more attributes of the design data and how the defects affect the yield based on such one or more attributes. Defects for which yield relevance is determined may or may not include binned defects.

In a further embodiment, the method includes using attributes to determine the overall yield relevance of the one or more groups. Thus, an attribute can be used to estimate overall yield relevance. The overall yield relevance can be determined as described above.

In some embodiments, the method includes separating design data that is close to the location of the defect into design data within the defect perimeter area and design data within the area where the defect is located, which may be performed as described herein . The attribute can also be used to distinguish the vicinity of the bond from the region where the defect is to be located.

In another embodiment, the method includes identifying a structure in the design data for binning or filtering using rules and attributes. For example, the method may include identifying structures such as LES sensitive structures, large poly blocks, and the like using one or more attributes and rules of the design data, and the defects located close to such structures may be grouped Be binned and / or filtered from the result. The rules may be generated by the methods described herein using experimental results and / or simulation results or any suitable method.

In another embodiment, the method includes determining a location on the wafer on which a review, measurement, test, or some combination thereof is to be performed, based on the inspection results produced during the detection of the defect and the defect identified as a systematic defect , Which may be performed according to any of the embodiments described herein. In some embodiments, the method includes determining a position on the wafer on which a review, measurement, test, or some combination thereof is to be performed based on the inspection results produced during the detection of the defect, the defect identified as a systematic defect, , Which may be performed as described herein. In a further embodiment, the method determines the location on the wafer on which the review, measurement, test, or some combination thereof will be performed based on the inspection results produced during the detection of the defects, the defects identified as systematic defects, and the process window mapping , Which may be performed as described herein.

In some embodiments, the method includes performing a systematic search using the results of the binning step and the user-assisted review. For example, the results of the binning step may be used to assist the user in a review (e.g., to determine where to review, how to review, etc.). The review may include generating a review result (e.g., a high magnification image) of at least one defect in the one or more groups, and generating a result of the review so that the user can identify one or more defects or one or more group defects as systematic defects As shown in FIG.

In another embodiment, the method includes separating defects based on the functional block in which the defect is located, prior to the comparing step, to improve the S / N in the result of the binning step. The functional block in which the defect is located can be determined as described herein. By separating the defects by functional blocks prior to the comparing step, defects in some (e.g., non-yield related) functional blocks can be eliminated from use in other steps of the method, resulting in S / N . In addition, the binning can be performed based on one or more attributes of the design data in combination with the functional block in which the defect is located, thereby providing better isolation and higher S / N in the binning result. Also, binning can be performed for each functional block or for one or more different functional blocks, thereby increasing the S / N for the binning result.

In another embodiment, the design data is organized into hierarchical cells, and the method further comprises separating defects based on the hierarchical cell in which the defects are located, prior to the comparing step, to improve the S / N in the result of the binning step . The design data may be organized into hierarchical cells as further described herein. The step of separating the defects based on the hierarchical cell can be performed as described above for functional block based separation. The step of separating defects based on the layer cells can be used to improve the S / N of the result of the binning step as described above.

In a further embodiment, the design data is organized into hierarchical cells by design, and if a defect can be located in one or more hierarchical cells, the method may include determining a region of the hierarchical cell, a defect location probability, And correlating the defects to the respective layer cells based on the probability that the defects are located in the respective layer cells based on the combination. In this way, if a defect can be located in multiple cells, the defect is correlated to that cell based on the probability that the defect is located in a different cell, which can be determined based on the region of the defect location probability. The probability can be determined in any manner known in the art.

In some embodiments, the defect is detected by an inspection process, the method comprising the steps of: reviewing the location on the wafer where at least one POI in the design data is printed; and determining whether the defect should have been detected at the location of the POI Determining a result based on the result, and modifying the inspection process to improve one or more defect capture rates, which may be performed as further described herein.

Each embodiment of the method for binning the above-described defects may comprise any other step of any of the methods described herein. In addition, each embodiment of the method for binning the above-described defects can be performed by any of the system embodiments described herein.

As described above, the location of the design data near the location of the defect may be compared to design data (e.g., a POI design example) corresponding to a different DBC (e.g., DBC bin specification) stored in a library or other data structure. One embodiment that can use such a library or data structure is a computer-implemented method for assigning categories to defects detected on a wafer. The method includes comparing a portion of the design data that is close to the location of the defect in the design data space to design data corresponding to a different DBC. The step of comparing the portion of the design data (or "source portion" of the design data) to the design data (or "target portion" or "reference pattern" of the design data) corresponding to the different DBCs is performed as described herein . In some embodiments, the method includes comparing one or more attributes of a portion of design data to one or more attributes of design data corresponding to different DBCs. The step of comparing one or more attributes of design data in that portion and one or more attributes of design data corresponding to different DBCs being compared in this step may include any of the attributes described herein. In addition, the one or more attributes used in the comparing step may include one or more attributes in the feature space. The comparing step may also include comparing the portion of the design data to a reference pattern to determine whether there is an exact match or similarity between the source and the reference pattern. The comparing step may also include using rules based on any of the rules described herein or any method for performing the comparison steps described herein. The comparing step may also include comparing the location of the defect in the design data space to the location of the hotspot in the design data space, which may be performed as described herein.

The dimensions of at least some of the portions are different in some embodiments, and the dimensions may be selected and / or determined as further described herein. In another embodiment, the design data in that portion includes design data for one or more design layers. Such portions of the design data may be constructed and used in a manner as further described herein. The design data in that portion may include any other design data described herein. For example, the design data near the location of the defect includes design data where the defect is located in one embodiment. In this manner, the design data used in the method may include design data below or behind the defect, or design data where the defect will be located. In another embodiment, the design data near the location of the design data includes design data around the location of the defect.

In a further embodiment, the method further comprises the steps of: prior to said comparing step, converting part of the design data close to the location of the defect into a first bitmap, which can be performed as described herein, And converting the design data corresponding to the DBC into a second bitmap, which can be performed as described herein. In one such embodiment, the comparing comprises comparing the first bitmap and the second bitmap. Such a comparison step may be performed as further described herein. An embodiment of a method for assigning a category to a defect may include determining the location of a defect in the design data space according to any of the embodiments described herein.

In one embodiment, the DBC identifies one or more polygons in the design data where the defect is located or where the defect is located. In this manner, one or more polygons where the defect is located or one or more polygons located near the defect may be identified by the DBC assigned to the defect. As such, one or more polygons that are affected or can be affected by the defect can be determined. Also, one or more polygons where the defect is located or one or more polygons located near the defect can be identified, and the information about these polygons can be used to determine the location of the defect for the polygon in the design data. In some embodiments, the DBC identifies the location of a defect in at least one polygon in the design data. Thus, the method may include determining, based on the DBC assigned to the defect, the location at or near which the defect in the polygon is located.

In another embodiment, the method includes separating design data near the portion of the defect into design data in the defect peripheral region and design data in the region where the defect is located. In this manner, the method may include the step of distinguishing the perimeter of the defect from the area where the defect will be located. Such separation may be performed as further described herein. Such a separation may also be used in a computer implemented method for assigning a category to a defect, as further described herein.

The design data corresponding to the different DBCs and the different DBCs are stored in the data structure. Further, the design data corresponding to different DBCs and the different DBCs may be stored in the data structure as described above. In particular, the design data corresponding to different DBCs and the different DBCs can be stored as DBC library files in the data structure. Further, in one embodiment, the data structure may be a library including examples of design data organized by a description, a process, or some combination thereof. In this manner, the data structure may include a set of POI design examples that may be used to classify defects as on-tools, and POI design examples may be organized by techniques, process steps, or any other suitable information. The data structure may comprise any suitable data structure known in the art and may be stored in a storage medium such as the one described herein or any other suitable storage medium known in the art.

The method also includes determining whether the design data in the portion is at least similar to the design data corresponding to the different DBC, based on the result of the comparing step. This determination step may be performed according to any of the embodiments described herein. In some embodiments, such determination may include determining that the design data in the portion is at least similar to design data corresponding to a different DBC, and determining whether the design data in that portion is based on design data corresponding to a different DBC And determining whether the attribute is at least similar to the one or more attributes. One or more attributes may include any of the attributes described herein. For example, one or more attributes may include information about the inspection system used to detect the defect (e.g., type of inspection system, one or more parameters of the inspection system on which the inspection system operates at the time the defect is detected, etc.) and / (E.g., size, rough bin, polarity, etc.).

The method also includes assigning a DBC corresponding to at least similar design data to a defect in the design data in the portion. The allocation step may be performed in any suitable manner. In some embodiments, the assigning step includes assigning a DBC corresponding to design data that is at least similar to design data in the portion and having at least one attribute that is at least similar to at least one attribute of the design data in the portion, to the defect . In one embodiment, the one or more attributes may include one or more attributes of the inspection results for which a defect was detected, one or more attributes of the inspection, and some combination thereof. One or more attributes may also (or alternatively) include any other attributes described herein.

The method further comprises storing the result of the allocating step on a storage medium. The results can be stored in any suitable manner or storage medium as described herein. The storage medium may comprise any of the storage media described herein or any other suitable storage medium known in the art.

The computer-implemented method described above is performed by an inspection system used to detect defects in one embodiment. In this manner, assigning categories to defects as described herein may be performed on-the-fly. In another embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect defects. In this manner, the step of assigning categories to defects as described herein can be performed with an off-tool.

In one embodiment, the method includes binning the defects assigned to one or more DBCs into groups such that the locations of defects in each group for the polygons in the portion of the design data near the location of the defect are at least similar. In this manner, the method may include separating the defects into groups based on the location of the defects in the DBCs and portions. The location of the defect for the polygon can be determined as described herein. Further, such binning may be performed additionally as described herein.

In some embodiments, the method includes monitoring hot spots in the design data based on the assigning step. For example, design data corresponding to a DBC or a different DBC may be associated with a hot spot in the design data. The hotspots can be identified in the design data as described herein. The step of monitoring hot spots in the design data as described above may include determining whether the number of defects assigned to the design data associated with the hot spot and corresponding to the DBC or different DBC associated with the hot spot varies over time . The step of monitoring hot spots in the design data based on the results of the allocating step may also include the step of comparing the results of the allocating step with the results of the allocating step in combination with any other data described herein, . ≪ / RTI > The method may also include monitoring a hot spot based on a location (e.g., a nearby location). In another embodiment, the method may include binning a hot spot based on design data corresponding to the DBC. Such binning of the hot spot may be performed as described herein. The step of binning the hotspot may include generating one or more data structures (e.g., a list, database, file, etc.) of the hotspot that include the location of the hotspot and indicate which hotspots are at least similar . Such a binning step of a hot spot can be performed with an on-tool.

In another embodiment, the method includes monitoring over time systematic defects, potential systematic defects, or some combination thereof, using the results of the allocating step. For example, the results of the assignment step can be used to identify systematic issues in the design data, and the identified systematic issues can be monitored across the wafer and / or over time. The systematic issue can be determined based on the results of the allocation step as further described herein. In addition, systematic defects, potential systemic defects, or some combination thereof may be performed additionally as described herein.

In one embodiment, design data corresponding to different DBCs is identified by grouping defects detected on one or more other wafers based on a portion of the design data that is close to the location of the defects detected on one or more other wafers in the design data space. Such grouping of defects can be performed as described herein. The results of the grouping can be used to identify design data corresponding to different DBCs. For example, design data corresponding to each group of defects may be identified as design data corresponding to different DBCs. Further, different DBCs corresponding to the design data may be classified into a group of defects that can be performed as described herein, one or more attributes of the design data, one or more attributes of the defects, any other information described herein, And may be determined by some combination of these.

In another embodiment, the method further comprises determining whether the defect is a Newson defect based on the DBC assigned to the defect, determining whether the defect is a Newson defect from the result of the inspection process in which the defect is detected to increase the S / And removing the defect. In this manner, the method may include Newson's filtering. A defect determined as a Newson's defect is a defect assigned to a Newson's DBC (e.g. DBC of LES), a defect not assigned DBC, or a DBC indicating that the defect is not a yield related defect or that the defect is an uninteresting defect It can be an allocated fault. Increasing the S / N of the test results is particularly advantageous, especially if the test results are used to perform one or more other steps to increase the S / N of the other step results.

In some embodiments, the method includes determining one or more POIs in the design data by identifying one or more features in design data that indicate a pattern-dependent defect. In this manner, the method may include identifying the POI in the design data. One or more features in the design data indicative of the pattern-dependent defect are determined based on experimental results, simulation results, binning results, other results described herein, or some combination thereof. Such results may be generated as described herein. One or more POIs may be determined using the identified features to perform any pattern search of the design data. A pattern in the design data determined by any pattern search, which is at least similar to the identified feature, can be identified as a POI. One or more POIs may be determined in this manner for one or more pattern dependent defects.

In the method described here, defects assigned DBC are detected in the inspection process. In one embodiment, the method includes the steps of reviewing a location on the wafer on which one or more POIs in the design data are printed, and determining whether a defect should have been detected at one or more locations of the POI based on the result of the review step And modifying the inspection process to improve one or more defect capture rates. Each step of this embodiment can be performed as described herein.

In another embodiment, the method includes determining a KP value for one or more defects. In a further embodiment, the method includes determining a KP value for one or more DBCs based on one or more attributes of the design data corresponding to the DBC. In a further embodiment, the method includes determining a KP value for one or more defects based on at least one attribute of the design data corresponding to the DBC assigned to the one or more defects. Each of these steps may be performed as described herein. In some embodiments, the method includes monitoring a KP value for one or more DBCs and assigning a KP value for the DBC assigned to the defect to the defect. The KP values for one or more DBCs can be monitored as described herein. In this manner, the KP value for one or more DBCs can be modified over time, and / or at the time the defect is detected, the KP value for the DBC assigned to the defect can be assigned to the defect with relatively high accuracy . The step of assigning the KP value to the defect based on the DBC assigned to the defect may be further performed as described herein.

In some embodiments, the method includes selecting at least some of the defects for review based on the results of the allocating step. For example, the result of the assignment step can be used to determine which defects are most important as described herein (e.g., based on one or more attributes of the DBC assigned to the defects) and the most important defects are selected for review .

In another example, the result of the allocation can be used to determine which defect is a systematic defect, as described herein. In this way, the method may include review sampling from areas in the design data where DOIs are likely to occur.

In one embodiment, the method further comprises the steps of determining whether the DBC assigned to the defect corresponds to a systematic defect visible to the review system, and selecting only the defect that is visible to the review system for review and sampling the defect for review . The DBC corresponding to systematic defects that are not visible or visible to the review system can be determined in any manner known in the art. A DBC corresponding to systematic defects visible to the review system may be determined prior to the method and the DBC may be assigned some identity indicating whether the DBC corresponds to a defect that is not visible or visible. In this way, defects can be selected for review based on this identity. Selecting only the defects that are visible to the review system may be performed so that defects that are not visible to the review system, such as SEM, are not selected for review. Defect selection in such a manner is particularly advantageous, since re-localization of defects during review is relatively difficult and can be relatively time consuming, especially if the review system spends a lot of time looking for actual invisible defects in the review system. The defect selection result for review may include the location of the selection defect for review on the wafer and other results of any of the steps described herein.

The method may include employing a process, measurement or test based on the results of the assigning step. For example, in another embodiment, the method includes generating a process for sampling a defect for review based on a result of the assigning step. Thus, instead of or in addition to a choice of defects for review, the method can be used to sample a defect for review, a method configured otherwise, a system configured to perform the method, or a process that can be used by another system And a step of generating the data. Such a process can be used for sampling of defects detected on a plurality of wafers for review and / or for defects for review performed by a plurality of review systems for review. The process for sampling may be generated based on the result of the allocation step such that a relatively large number of defects assigned the same DBC can be sampled more focusfully than a relatively small number of defects allocated the same DBC. The process for sampling the defect for review is generated based on the result of the assignment step in combination with DCI for the defect, KP value for the defect, and any other result of any of the steps described herein can do.

In a further embodiment, the method includes modifying the process for wafer inspection based on the result of the allocating step. Any parameters of the process for wafer inspection can be changed in this embodiment. For example, one or more parameters of the process for wafer inspection that can be changed based on the results of the allocation step may include one or more of the following: one or more of the following: a region of interest (or alternatively, a non-region of interest) Will be examined, or some combination thereof. In one particular example, the result of the assigning step may indicate the number of defects for which different DBCs are assigned, and the area of interest may be within a design data space that also includes design data corresponding to the DBC to which a relatively large number of defects are allocated May be changed to include a location on the wafer corresponding to the additional location. In another example, the process for wafer inspection may be modified to further or differently inspect based on the results of the assigning step. The process for wafer inspection may be modified based on any result of any of the steps described herein.

In some embodiments, the method includes modifying a process for inspection of a wafer during an inspection based on the inspection results. The step of changing the inspection process in this embodiment can be performed as described further herein.

In a further embodiment, the method includes modifying the metrology process for the wafer based on the result of the assigning step. For example, the metrology process may be modified such that the most critical defects, as determined from the results of the assignment step, are measured during the metrology process. Thus, modifying the metrology process may include changing the position on the wafer where measurements are performed during the metrology process. In addition, the results of the inspection and / or review, such as the BF image and / or the SEM image selected for the measurement, are supplied to the metering process and the result can be used to determine where the measurement is to be performed. For example, the metrology process can include generating an image of the near position of the defect on the wafer, and if necessary, the metrology system can calibrate the position of the wafer so that metrology can be performed on the correct defect along with the correct wafer location , Such an image may be compared to the results of the inspection and / or review of the defect. In this way, the measurement can be performed at a substantially precise location on the wafer. Modifying the metrology process also includes changing any one or more other parameters of the metrology process, such as the type of measurement being performed, the wavelength at which the measurement is performed, the angle at which the measurement is performed, etc., or some combination thereof can do. The metrology process may include any suitable metrology process known in the art, such as a CD metrology process.

In some embodiments, the method includes modifying a sampling plan for a metrology process based on a result of the assigning step. Thus, the method may include adaptive sampling. For example, the sampling plan for the metrology process can be varied such that a large number of the most significant defects as determined from the results of the binning step are measured during the metrology process. In this manner, the most critical defects can be sampled more intensively during the metrology process, thereby beneficially generating a large amount of information about the most critical defects. The metrology process may include any metrology process known in the art. In addition, the metrology process can be performed by any suitable metrology system known in the art, such as SEM. The metrology process may also include performing any suitable measurements known in the art for any suitable properties of features or defects formed on the wafer, such as profile, thickness, CD, and the like.

In another embodiment, the method includes prioritizing one or more DBCs (e.g., DBCs assigned to defects), and determining, based on the results of the prioritizing step, one or more And optimizing the process. In such an embodiment, the DBC may be prioritized based on the number of defects to which the DBC is assigned. The number of DBC allocated faults can be determined from the result of the allocation step. In such an example, the DBCs allocated to the maximum number of faults may be assigned the highest priority, and the DBCs allocated to the next maximum number of faults may be assigned the next highest priority.

(Or alternatively), the DBC may be prioritized based on any other result of any of the steps of any of the methods described herein, and any step result of any of the methods described herein . For example, DBC prioritization may include determining a DCI for one or more defects to which the DBC is assigned, and prioritizing the DBC based on the DCI for the one or more defects. The DCI may be determined as described further herein in this embodiment. In another example, prioritizing the DBC includes determining a KP value for one or more defects to which the DBC is assigned, and prioritizing the DBC based on the KP value for the one or more defects . In yet another example, the DBC may be prioritized based on the number of defects that the DBC is assigned and the combination of the DCI for one or more defects to which the DBC is assigned. In this manner, the step of prioritizing the DBC prioritizes the DBC based on the degree of defect detected in the design data corresponding to the DBC so that the highest priority is assigned to the DBC corresponding to the highest degree of defectiveness .

In addition, the DBC may be prioritized based on one or more attributes of the design data corresponding to the DBC, possibly in combination with other results described herein. The one or more attributes of the design data may include, for example, the dimensions of the features in the design data, the density of the features in the design data, the types of features included in the design data, the location of the design data corresponding to the DBC in the design, The sensitivity of the effect, etc., or some combination thereof. In such an example, the DBC corresponding to the design data more sensitive to the yield impact due to defects may be assigned a higher priority than the DBC corresponding to less sensitive design data of the impact of defects on the yield.

In addition, the DBC may be prioritized based on one or more attributes of the design, possibly in combination with one or more attributes of the design data corresponding to the DBC and / or other results described herein. One or more attributes of the design may include, for example, redundancy, netlist, etc., or some combination thereof. In particular, the POI in the design data may have a context beyond the pattern contained within the POI. Such context may include, for example, the label of the cell containing the POI, the hierarchy of cells on the cell containing the POI, the effect of redundancy of systematic defects on the POI, and the like. Thus, the one or more attributes used in the embodiments described herein may include the context of the POI in which the design data corresponding to the DBC is located, which may include the location of the design data corresponding to the DBC in the design data space and / (When the design data corresponding to the DBC is specific to the cell in the design data). In such an example, a DBC corresponding to design data that has redundancy and systematic defects may not have a yield effect in the design, rather than a DBC corresponding to design data that does not have redundancy and can have a significant yield effect, May be assigned a lower priority. Such context of the cell may be acquired and / or determined in any manner known in the art.

The optimization of the one or more processes in this embodiment may be performed in any suitable manner, including but not limited to focus, exposure dose, exposure tool, resist, PEB time, PEB temperature, etch time, etch gas composition, etch tool, deposition tool, deposition time, CMP tool, One or more parameters of one or more processes, such as one or more parameters, and so on. Preferably, the parameters of the process are selected in the design data corresponding to the DBC, in order to reduce the degree of defect of the design data corresponding to the DBC (for example, the number of defects detected in the design data corresponding to the DBC) To change the one or more attributes (e.g., DCI, KP, etc.) of the DBC, and / or to increase the yield of the device containing the design data corresponding to the DBC.

In addition, one or more parameters of the one or more processes may be optimized only for the DBC having the highest priority as determined by the prioritization step or for the DBC having the relatively higher priority as determined by the prioritization step . In this manner, one or more parameters of the one or more processes may be altered and / or optimized based on the design data corresponding to the DBC that represents the degree of defect with maximum defectivity and / or maximum yield impact. As such, the result of the prioritization step indicates which DBC should be used to modify and / or optimize one or more parameters of the one or more processes to indicate the maximum improvement in yield.

Thus, the present embodiment can be made to the process without any guidance on which DBC has the greatest effect on the yield, with many changes being made to the process without any major or any improvement in throughput, so that the change time and cost The present embodiment is advantageous over previously used methods and systems for changing and /

Also, even though the process that is changed and / or optimized at this stage includes only the process used to print the design data corresponding to the DBC on the wafer prior to the detection of the DBC assigned defect in the embodiments described herein, / Or one or more processes optimized may include any process used to print other designs that contain design data corresponding to the DBC. For example, if one or more designs include design data corresponding to a DBC based on prioritization and / or any other result of the methods described herein, then one or more processes used to print one or more designs may be changed and / Can be optimized, thereby increasing the yield of the device made with each different design.

In a further embodiment, the method includes determining the root cause of the defect based on the DBC assigned to the defect. For example, the root cause may be determined based on at least one attribute of the design data corresponding to the DBC assigned to the defect. The attributes of the design data used to determine the root cause may include any of the design data attributes described herein. In addition, any other information and / or the results of any of the steps of any of the methods described herein may be used in combination with the attributes of the design data to determine the root cause of the defect.

In a further embodiment, the method includes mapping at least a portion of the defect to an experimental process window result to determine the root cause of at least a portion of the defect, which may be performed as described herein.

In another embodiment, the method includes determining a root cause corresponding to one or more DBCs and assigning a root cause to a defect based on a root cause corresponding to the DBC assigned to the defect. For example, the root cause of a previously detected defect in the design data corresponding to the DBC may be related to the DBC. The root cause of previously detected defects can be determined in any of the ways described herein or in any other suitable manner known in the art. In this manner, the root cause of the fault may be the root cause associated with the DBC assigned to the fault.

In a further embodiment, the method includes determining a percentage of die formed on a wafer affected by a defect to which more than one DBC is assigned. For example, the percentage may be determined by the number of dies across the wafer at which defects assigned the same DBC are detected at least once. Such a percentage may be determined by dividing the number of dies where at least one defect assigned the same DBC is detected divided by the total number of dies inspected. The result of such a step is multiplied by 100 to reach a percentage. Thus, the percentage reflects the die impact margin of the defect to which the same DBC is assigned. Such a percentage may be determined for one or more DBCs assigned to the defect, and each or at least some of the percentages may be represented by a chart such as a bar chart that may be generated by the method. Thus, the chart shows the die impact margin as a function of the DBC assigned to the defect. Such a chart can be represented in a user interface that can be configured as further described herein. The method may also include prioritizing defects assigned by one or more DBCs based on the percentage determined in the present embodiment.

In some embodiments, the method includes determining a POI in design data corresponding to at least one DBC and determining a ratio of the number of defects assigned by at least one DBC to the number of locations on the wafer do. In this manner, the method may include performing a margin analysis by determining a percentage or percentage of the number of DBCs allocated to the number of positions of the POI corresponding to the printed DBC on the wafer. In such an embodiment, the position of the POI on the wafer may be identified by any pattern search. The method described herein may also include an optional pattern searching step to identify the location of the POI in the inspection area of the design and a step of determining the accumulation area of the POI in the inspection area of the design. The ratio of the number of DBC allocated defects to the cumulative area of the POI in the inspection area of the design can be used to determine the defect density of the DBC corresponding to the POI. The method may also include prioritizing one or more DBCs determined in the present embodiment.

In another embodiment, the method includes determining at least one POI in design data corresponding to at least one DBC, determining a number of POIs in the design data corresponding to at least one POI in the design data, And determining a ratio. In this manner, the method comprises performing a margin analysis by determining the percentage or percentage of the number of defects allocated by the DBC corresponding to the POI found on the wafer relative to the number of positions of the POI in the design over the inspection area of the wafer . ≪ / RTI > In such an embodiment, the position of the POI on the wafer may be identified by any pattern search. This method may also include prioritizing one or more DBCs based on the ratio determined in the present embodiment.

In a further embodiment, the method further comprises the steps of determining a POI in the design data corresponding to at least one DBC, determining a percentage of the die formed on the wafer on which the at least one DBC is assigned the defect, And assigning a priority to the POI based on the POI. In this manner, the method may include performing a margin analysis based on a percentage of the die affected by the defect. For example, the number of defects assigned the same DBC can be divided by the number of design instances of the POI in the reticle used to print the design data in the inspection area on the wafer and the number of times the reticle is printed and inspected on the wafer. The result of this step is multiplied by 100 to reach a percentage. In this manner, the method may include prioritizing known systematic defects by the number of dies across the wafer at least once the defects are detected. For example, if the POI appears at 10% of the die compared to 1% of the die, a higher priority may be assigned to the POI where systematic defects are detected. In another example, defects assigned to the same DBC, detected in a large number of dies on the wafer, may be assigned a higher priority than defects assigned different DBCs, which are detected in a smaller number of dies on the wafer. The method may also include generating a chart such as a bar chart showing the percentage of dies formed on a wafer on which defects with different DBCs are located. Thus, such charts graphically represent die-based margins for different DBCs. Such a chart may be displayed on a user interface that may be configured as described herein.

In a further embodiment, the method includes prioritizing one or more DBCs by the number of defects for which more than one DBC is assigned to be detected. In this manner, the method may include prioritizing systematic defects known by the total number of defects of the defects to which the DBC is assigned. As such, the method may include prioritizing known systematic defects based on wafer-based margins. For example, a DBC assigned to a defect detected in a large number of design instances on a wafer is assigned a higher priority than a DBC assigned to a defect detected in a small number of design instances on the wafer. Such prioritization may be performed based on a percentage of the location of the design instance across the wafer on which the defect was detected. For example, the number of detected and DBC allocated defects can be divided into a fully inspected design instance corresponding to a DBC across the wafer. The result of this step is multiplied by 100 to generate the above-mentioned percentage. The method may also include generating a chart such as a bar chart showing the number of design instances across the reticle to which different DBCs are assigned. Such charts may be displayed on a user interface that may be configured as described herein.

In some embodiments, the method includes prioritizing one or more DBCs by the number of design instances on the reticle used to print the design data on the wafer for which at least one DBC assigned defect has been detected at least once. In this manner, the method includes prioritizing systematic defects known by the number of design instances across the reticle where the defects are found at least once. For example, a DBC assigned to a defect detected in a large number of design instances on the reticle may be assigned a higher priority than a DBC assigned to a defect detected in a small number of design instances on the reticle. The method may also include generating a chart such as a bar chart showing the number of design instances across the reticle for which different DBCs have been assigned defects. Such charts may be displayed on a user interface that may be configured as described herein.

In another embodiment, the method further comprises designing data that is printed on a reticle at least similar to a portion of design data that is closer to the location of a defect on which more than one DBC is assigned, Based margins for one or more DBCs based on the total number of portions of the reticle-based margin. For example, the reticle-based margins can be determined by dividing the number of places in the laminate reticle map in which at least one defect assigned DBC has been detected by the total inspection design instance across the reticle. The result of this step is multiplied by 100 to generate a percentage of the location of the design instance corresponding to the DBC to which the DBC is assigned the detected defect. The method may also include generating a chart such as a bar chart showing the percentage of locations where defects assigned different DBCs have been detected or reticle-based margins. Such charts may be displayed on a user interface that may be configured as further described herein. The method may include prioritizing one or more DBCs based on the reticle-based margins determined for one or more DBCs. For example, a DBC exhibiting a relatively high reticle-based margin may be assigned a higher priority than a DBC exhibiting a low reticle-based margin. The steps of the embodiments described herein may be performed on a group of defects to which the same DBC is assigned or on individual defects to which the DBC is assigned.

Each embodiment of a method for assigning a category to the above-described defects may include any method embodiment described herein. In addition, each embodiment of the method for assigning categories to the aforementioned defects can be performed by any of the system embodiments described herein.

Another embodiment is directed to a method of altering an inspection process for a wafer. This method includes reviewing a location on the wafer where at least one POI in the design data is printed. The method also includes determining whether a defect should have been detected at one or more POI locations based on the results of the review step. The method also includes modifying the inspection process to improve the S / N for one or more defect coverage and / or defects located in at least a portion of the at least one POI. Each of these steps may be performed as further described herein. For example, one or more parameters of the inspection process may be changed based on prioritization of the POI, which may be determined as described herein.

One use case for the above method is a photo sensing application. For example, in one embodiment, modifying the inspection process includes altering the optical mode of the inspection system used to perform the inspection process. In this manner, the optical mode used for inspection may be modified to improve the S / N to detect one or more defects corresponding to at least a portion of one or more POIs. The optical mode may comprise any optical mode known in the art.

In another embodiment, the method includes determining an optical mode of the inspection system used to perform the inspection process based on a result of determining whether a defect should have been detected at a location of one or more POIs. In this way, the optical mode with the highest S / N for the defect that should have been detected can be determined. The optical mode may comprise any optical mode known in the art. In addition, the determined optical mode and / or defects that should have been detected can be used to select other parameters of the modified inspection process, such as the type of inspection system used to perform the inspection process.

In some embodiments, modifying the inspection process includes modifying the inspection process to increase acquisition of the DOI associated with the one or more POIs. Modifying the inspection process to increase acquisition may include modifying any one or more parameters of the inspection process. Enhanced detection by changing the parameters of the inspection process can include detection of DOIs associated with the POIs in the inspection results (e.g., increasing defect counts for yield deterministic systematic DOI, etc.). One or more parameters modified to increase acquisition may be based on any result of the inspection process and / or any result of the review step (e.g., not only as a result of reviewing a location on the wafer on which one or more POIs are printed) Can be selected.

In some embodiments, modifying the inspection process includes modifying the inspection process to suppress noise in the results of the inspection process. Modifying the inspection process to suppress noise may include modifying any one or more parameters of the inspection process. The noise suppressed by changing the parameters of the inspection process may include any noise (e. G., Background noise, Newson defect, etc.) in the inspection results. One or more parameters that are altered to suppress noise may be included in any result of the inspection process and / or any result of the review step (e.g., not only as a result of reviewing a location on the wafer on which one or more POIs are printed) Can be selected on the basis of.

In a further embodiment, the inspection process includes modifying the inspection process to reduce the detection of uninteresting defects and to improve the binning of uninteresting defects. Modifying the inspection process to reduce the detection of unattractive defects may include modifying any one or more parameters of the inspection process. Unfamiliar defects that are less well inspected by changing the parameters of the inspection process may include any uninteresting defects (e.g., non-yield related systematic defects, defects in cold spots, etc.). One or more parameters altered to reduce the detection of uninteresting defects may include any result of the inspection process and / or any result of the review step (e.g., not only the result of reviewing a location on the wafer on which one or more POIs are printed ). ≪ / RTI >

Modifying the inspection process to improve one or more defect capture rates may include modifying any one or more parameters of the inspection process. For example, in one embodiment, modifying the inspection process includes modifying the algorithm used in the inspection process. The altered algorithm may be a defect detection algorithm or any other algorithm used in the inspection process. The altered algorithm may comprise any suitable algorithm known in the art. In addition, altering the inspection process may include altering one or more algorithms used in the inspection process.

In a further embodiment, modifying the inspection process includes modifying one or more parameters of the algorithm used in the inspection process. An algorithm in which one or more parameters have been altered may include a defect detection algorithm or any other algorithm used in the inspection process. In addition, altering the inspection process may include altering one or more parameters of the one or more algorithms used in the inspection process. One or more parameters in the algorithm may include parameters that affect any parameters of the algorithm, preferably defect coverage.

Each embodiment of a method for modifying an inspection process for a wafer as described above may include any other steps of any method embodiment described herein. Further, each embodiment of the method for modifying the inspection process for a wafer as described above may be performed by any of the system embodiments described herein.

A further embodiment relates to a system configured to display and analyze design and defect data. One embodiment of such a system is shown in Fig. As shown in FIG. 25, the system includes a user interface 182. The user interface 182 displays one or more design layouts 184 for a semiconductor device, inline inspection data 186 obtained for a wafer on which at least a portion of the semiconductor device is formed, electrical test data 188 acquired for the wafer . In one embodiment, the electrical test data includes logic bitmap data. Design, inspection (or measurement), test and overlay data are represented in a design, device, reticle or wafer space. The user interface can be configured to display modeled data for the semiconductor device and / or FA data for the wafer. In addition, the user interface can be configured to display information about a particular hot spot or DOI based on input from the user (e.g., hot spot or DOI selection by the user). In this manner, the user interface can be configured to display information about different hot spots or DOIs at different times. However, the user interface may be configured to simultaneously display information about different hot spots or DOIs using one or more different markers (e.g., color, symbol, etc.) to indicate different hot spots or DOIs (e.g., Bar graph). Using the display of information in the hotspot database, the user can create one or more hotspot lists by selecting a subset of hotspots of interest by a given analysis or inspection recipe. The user interface may be displayed on the display device 190. Display device 190 may include any suitable display device known in the art.

The system also includes a processor 192. The processor 192 is configured to analyze one or more design layouts, inline inspection data, and electrical test data upon receiving an instruction from the user to perform an analysis via a user interface. The processor may be configured to analyze the modeled data and / or FA data as described above. For example, the user interface 182 may be configured to display one or more icons 194. Each icon may correspond to another function that may be performed by the processor. In this way, although five icons are shown in Fig. 25, the user interface can be configured to display any number of icons corresponding to the number of possible functions. A user may instruct the processor to perform one or more functions by selecting (e.g., clicking) one or more icons. In addition, the user interface may display various functions that are made available to the user in any other manner known in the art (e.g., a drop-down menu). In this manner, the user interface can be configured as a single integrated user interface that combines design / layout visualization and analysis operations with inline process data visualization and analysis operations and functional / structural electrical test data visualization and analysis operations.

The system can be configured to process data at increased resolution, which is commonly referred to as "drill down capabilities. &Quot; For example, the system may be configured to select two or more dies for stacking, to select the defects shown in die stack results, and to use inputs such as wafer maps representing defects detected on the wafer to perform some function on defects . The system may be configured to use data from more than one domain together, which is commonly referred to as "drill across capabilities ".

In one embodiment, the user interface is configured to display at least two overlays 196 of the design layout, inline inspection data, electrical test data, and any other information described herein. In one such embodiment, the electrical test data includes logic bitmap data. In such an embodiment, the processor may be configured to overlay different data according to any of the embodiments described herein. In this manner, the system can be configured to generate and display an overlay of data from two or more of the three domains (e.g., design, test, and electrical tests). Such overlay of data maps the physical location of the defect to a logical location using mapping and electrical test results (e.g., electrical errors) to identify defects that affect the electrical test results (e.g., by causing electrical errors) Can be used.

In one embodiment, the processor is also configured to determine a defect density in the design data space upon receiving a command to perform a determination from the user via the user interface. In this manner, the system may be configured to perform error density calculations as further described herein. The user interface can be configured to display the result of the error density calculation.

In a further embodiment, the processor is configured to receive an instruction to perform defect sampling from a user via the user interface and to perform defect sampling for review. In a further embodiment, the processor is configured to group defects based on the similarity of the design layouts close to the location of the defects in the design data space to receive grouping from the user via the user interface. In this manner, the system can be configured to perform sampling and data reduction (e.g., data reduction by pattern dependent binning) techniques. Such techniques may be performed as further described herein.

In some embodiments, the processor is configured to monitor the KP value of the defective group over time and to determine the importance of the defect group based on the KP value over time. In this manner, the system may be configured for defect tracking (e.g., using the DTT method and / or using an image). The user interface can be configured to display the result of monitoring the importance of the defect group and the KP value that is time-correlated. The processor and system shown in Fig. 25 may be configured as described further herein. For example, the processor and system may be configured to perform any of the other steps of any of the other methods described herein. Further, the system shown in Fig. 25 may include other components as described herein, such as an inspection system, which may be configured as described further above. The system shown in Fig. 25 has all the advantages of the method described herein.

A further embodiment relates to a computer-implemented method for determining the root cause of an electrical defect detected on a wafer. In one such embodiment, the result of the inspection of the wafer for electrical defects may include a bitmap for the logic device. The method includes determining the location of an electrical defect in the design data space. The location of electrical defects in the design data space can be determined as described herein.

In some embodiments, the method includes correlating a spatial signature of a defect, such as a systematic defect, to a process condition. For example, after converting scan-based and structural test results to wafer space coordinates, a particular spatial signature may be correlated to one or more process conditions. Methods and systems for performing spatial signature analysis of defect data are disclosed in U.S. Patent 5,991,699 (Kulkarni et al.), 6,445,199 (Satya et al.), And 6,718,526 (Eldredge et al. , The patent document is incorporated by reference as fully described herein. The methods and systems described herein can be configured to perform any of the steps of any of the methods described in that patent document.

The method includes determining whether the location of the electrically defective portion defines a spatial signature corresponding to one or more process conditions. This step can be performed in any suitable manner, by comparing the spatial signature of the electrically defective portion to a set of spatial signatures corresponding to the process conditions, applying the rule to the location of the electrically defective portion, or the like. Further, when the location of the electrically defective portion defines a spatial signature corresponding to one or more process conditions, the method includes identifying the root cause of the electrically defective portion as one or more process conditions. In this manner, the method described above may include performing a spatial signature analysis on the logic bitmap data. The method further comprises storing the result of the identifying step on a storage medium. The result of the identifying step may include any result described herein. The method can also perform a storage step as further described herein. The storage medium may comprise any of the storage media described herein.

Each embodiment of the method for determining the root cause of the electrical defects described above may include any other step of any method embodiment described herein. Further, each of the embodiments of the method for determining the root cause of the above-described electrical defects can be performed by any of the system embodiments described herein.

The root cause of other defects can also be determined in the methods described herein. For example, wafer-based or reticle-based spatial signatures (and combinations thereof) by pattern groups mapped across process windows are particularly useful for correlations for assistance in root cause determination. In one example, at one edge of the process window, defects x and y are marginal and tend to be erroneous from the outside of the wafer first. At the other edge of the process window, the defect z tends to be erroneous at the edge of the wafer first. Thus, the possible root cause can be determined by observing which systematic defect is most often (and probably against the outer annular ring) on the wafer.

Another embodiment relates to a computer-implemented method for selecting defects detected on a wafer for verification / root cause analysis, including review, search for category / investigation, and on-tool, off-tool and on- will be. The method includes identifying at least one region of the wafer. One or more regions are associated with the location of one or more defect types on the wafer. One embodiment of one or more such regions is shown in Fig. As shown in FIG. 26, the area 198 on the wafer 200 can be identified as being associated with the location of one or more defect types on the wafer. For example, such areas may be associated with types of defects caused by focus errors near the outer edge of the wafer during lithography processes or etch changes from wafer center to wafer edge.

The method includes selecting defects detected in at least one region for review. For example, as shown in FIG. 26, the wafer map 202 may overlap with the layout of the area 198. In this manner, the defects shown in the wafer map 202 can be selected for review based on the area in which they are located and one or more defect types associated with that area. In such an example, if the area shown in FIG. 26 is associated with a de-focus error near the outer edge of the wafer, the method may select (only, preferentially, or focus) . Alternatively, the defect can be selected from a region on the wafer other than the region 198.

Although only one region is shown in FIG. 26, it should be understood that the wafer may be separated into any suitable plurality of regions. Further, the region can be defined on the wafer as an annular region, an angular region and a radial region as shown in Fig. 26, and a rectangular region. However, the region may have an irregular (e.g., polygonal) shape. Also, all, some, or none of the regions may have the same characteristics, such as shape and / or size.

The method described above can be used to provide a defect sample so that the review result of the defect sample can be interpolated from the die to the wafer. In contrast, a typical review sample plan includes 100 to 200 defects for recipe optimization and 10 to 100 defects for monitoring spread across the entire wafer. However, tens of thousands of hot spots can exist only on one die. Hot spots can be reviewed for navigation. Systematic defects can be reviewed for monitoring and verification. Thus, even after selecting 100 or 200 defects from this population, preferably not all of them are reviewed on the same die. Instead, it is preferable that the selected defects extend over a plurality of dies. The method described above uses area analysis results to identify a correlation between a particular type of defect and a particular area on the wafer. As such, the methods described herein can be used to identify wafer position-specific defects. In this manner, the method may include deflecting the sampling plan into these areas to provide results suitable for use in die-wafer interpolation. The method further includes storing the result of the selection step in a storage medium. The result of the selection step may include any result described herein. The method may also be carried out as described further in the storage step. The storage medium may comprise any of the storage media described herein.

Each embodiment of the method for selecting defects for review described above may include any other step of any method embodiment described herein. Further, each embodiment of the method for selecting defects for review as described above may be performed by any of the system embodiments described herein.

Another embodiment relates to a computer-implemented method for evaluating one or more yield related processes for design data. One such embodiment is shown in Fig. The steps shown in Fig. 27 are not essential for carrying out such a method. One or more steps may be excluded or added to the method shown in FIG. 27, and the method may still be practiced within the scope of this embodiment.

As shown in FIG. 27, the method includes identifying potential errors in the design data using rule checking, as shown in step 204. Alternatively, potential errors in the design data may be identified using a potential hot spot observed from a repeater analysis or defect density map. The potential errors identified at this stage may include one or more other types of DOIs. In some embodiments, the potential error identified in this step may include a post-pattern potential error (e.g., post-etch potential error). Also, once a potential error is identified, it can be propagated throughout the design through the design, which can be detected by searching for a common pattern in the design (e.g., an arbitrary pattern search). In some embodiments, the method includes any pattern searching step to identify the location of all similar POIs. The common pattern can be identified by searching for a rotated or flipped pattern to find all potential errors. Further, potential errors in the design data may be identified at step 204 using any other suitable method (e.g., modeling), software, and / or algorithms known in the art. In addition, the potential error may be caused by an area or pattern within the design data that may cause errors in the device being fabricated for the design data, or that may change one or more of the electrical parameters of the device in an undesirable manner, . ≪ / RTI >

As shown in step 206, the method also includes determining one or more attributes of the potential error. The attribute of the determined potential error may include, for example, a type. The attributes of the potential error can be obtained by an empirical test, a simulation result, design data or any other method. Because the method includes identifying potential errors as described above, the method may include modifying the design data prior to manufacturing to eliminate as many potential errors as possible. Such modification of the design data can be performed as described herein. However, it can be considered that not all potential errors can be eliminated prior to fabrication. In addition, potential errors identified in the methods described herein may or may not actually produce errors during manufacturing, or may or may not affect yield. Thus, although some of the potential errors may be eliminated prior to manufacturing (and thus inspection), the methods described herein may be used to determine where a design check should be performed so that if a potential error actually becomes an error, Can provide important information for the user. It should also be noted that the method described herein can also be applied to the case where the inspection of the area on the wafer where the design data portion contains potential errors in the design can be performed with the most suitable inspection parameters, In order to increase the probability of being inspected by the inspection, it is possible to provide important information as to how different areas of the design should be inspected.

As shown in step 208, the method includes determining that a potential error is not detectable based on one or more attributes of the potential error. Whether or not a potential error is detectable can be determined based on the nature of the potential error in combination with the known capabilities of the various inspection systems. As shown in step 210, the method determines which of a plurality of different inspection systems (e.g., BF, DF, voltage contrast, EC, electron beam, etc.) is most suitable for detecting a potential error based on one or more attributes .

In some embodiments, the method includes selecting one or more parameters of the inspection system that are determined to be most suitable, as shown in step 212. In one such embodiment, the parameter is selected based on one or more parameters of the potential defect. The parameters may be selected as further described herein. Also, the parameters selected at this stage may include any parameters of the inspection system that can be changed and / or controlled. An example of such a parameter is an optical mode or an inspection mode. Preferably, the parameter is selected to optimize the inspection of the wafer for potential errors (e.g., to increase the defect coverage of the defect at the location of the potential error, increase the sensitivity to the defect in the potential error, etc.) do.

In some embodiments, the method may be implemented in combination with any other information possibly described herein (e.g., sensitivity of design data for a defect, sensitivity of an electrical parameter corresponding to design data for a defect, etc.) And prioritizing one or more potential errors based on one or more attributes of the design data near the location of the potential errors. Such prioritization may be performed as further described herein. In addition, the parameters of the most suitable inspection system and inspection system can be selected based on the results of such prioritization as further described herein. For example, in such an embodiment, the most appropriate inspection system and the parameters of the inspection system may be selected to optimize inspection for potential errors with the highest priority so that the most critical defects are detected in the inspection process. The determination of such a most suitable inspection system and the selection of parameters may or may not result in optimization of the test for potential errors with the lowest priority.

In another embodiment, the method includes determining the effect of a potential error on the yield of the device fabricated with the design data, as shown in step 214. In this way, the method can be used for recipe optimization and monitoring. In a further embodiment, the method may include determining the effect of a potential error that is undetectable but determined to affect yield. In this manner, the method may include determining a percentage of yield loss that is not detectable by inspection. An example of a yield prediction method that can be used in the methods disclosed herein is disclosed in U.S. Patent No. 6,813,572 (Satya et al.), Which is incorporated herein by reference as fully mentioned herein.

Thus, the method described above can be used for fully automatic prediction, tracking, and validation of hot spots (after some initial manual setup is performed). The method further comprises storing the determination result in a storage medium which of the plurality of different inspection systems is suitable for detecting a potential error. The result of this step may be any result described herein. In addition, this method can perform a storage step as further described herein. The storage medium may comprise any of the storage media described herein.

Each of the embodiments for evaluating the one or more yield related processes described above may include any other steps of any of the methods described herein. In addition, each embodiment for evaluating one or more of the above-described yield related processes may be performed by any of the systems described herein.

The methods and system embodiments described herein can be used to provide a total design. For example, as described above, the method may include separating defects (as detected by inline and / or electrical inspection) into systematic defects and random defects. The methods and systems described herein can be used to manage hot spots.

The defect-related parametric yield loss can be used as an input to a simulation, such as a simulation, that determines the electrical parameters of the device based on one parameter of the semiconductor manufacturing process. In this manner, defects associated with loss of parametric yield can be used in combination with information about the process performed on the wafer to adjust or optimize the simulation. In addition, the simulation results can be used to identify parameters of a process performed on a wafer that may be altered to reduce defects associated with parametric yield loss. In addition, the results of the simulations and methods described herein can be used to identify which parameters of the process are important to reduce parametric yield loss.

Defects related to systematic patterning losses can be used to identify pattern defects associated with the interaction between the device design and the process. In this manner, information about defects can be used to reduce defects, change processes, change designs, and change processes and designs.

The above steps may be performed during a design feedback step that is used to improve the future design in view of the lessons learned. That is, knowledge transfer and monitoring steps from the hot spot database may be provided at the design stage (e.g., technology search and development, product design, EET design, etc.). This step may be performed in a multi-source space (e.g., using a correlation between any of the designs, wafers, tests, and process space). This step may include improving the design based on a hot spot having a strong correlation to a particular cell design. This step may also include the step of improving the design using a hot spot having a strong correlation to the proposed design rule.

Information about random defects can be used to determine the defect limited yield (i. E., The maximum possible yield that can be achieved if all systematic and repeater defects are removed). Such information can be used for on-line and off-line monitoring, in combination with simulations that determine the impact of random defects on the device to identify random defects that are high yield defects.

The method described herein may include monitoring the semiconductor manufacturing process using the results of the method. The results used to monitor the semiconductor manufacturing process may be based on any of the results described herein (e.g., inline inspection data, systematic defect information, random defect information, error density maps, binning results, etc.) . ≪ / RTI > The methods described herein may also include altering one or more parameters of one or more semiconductor manufacturing processes based on the results of any of the methods described herein. The parameters of the semiconductor manufacturing process may be controlled using feedback techniques, feedforward techniques, in situ techniques, or some combination thereof. In this way, the methods described herein and the results produced by the method can be used for SPC applications.

As further described herein, the methods and systems described herein may be used for on-tool yield prediction based on design data for improved binning, review sampling, test setup, and any other analysis described herein Can be used. The methods and systems described herein have numerous advantages over currently available methods and systems. For example, methods and systems currently used for KP analysis use historical yield data for predicting overall random yield loss by considering defect density by size distribution and / or category. One disadvantage of such methods and systems is that other defect groupings (e.g., size bin, category beam, layer) are not considered in calculating the probability that one or more defects break the die. In addition, these methods and systems require statistically significant historical data for setup. In another example, methods and systems currently used for KP analysis use historical yield data and yield loss per defect prediction by considering the size and / or category within a region to better predict the KP of the detected defect . One disadvantage of such methods and systems is that statistically significant historical data is needed for setup. In a further example, the methods and systems currently used for critical area analysis (CAA) determine the yield loss prediction by a defect and determine the yield loss prediction by the structure (line width, spacing) for various defect sizes Calculation of the major area over the die. The approach is relatively computationally intensive, but once computed, defects with areas larger than the major area based on location are predicted as the breaker. One disadvantage of such methods and systems is that statistically significant historical data is required for setup. In addition, such methods and systems include computationally intensive pre-processing, and the accuracy of such methods and systems is limited by fault location accuracy.

In contrast, the methods and systems described herein utilize very high coordinate accuracy, which results in improved yield prediction accuracy for the CAA and method described herein. The methods and systems described herein can be used for active CAA. For example, instead of pre-processing data to create a look-up table across multiple sizes and locations, this approach calculates yield based on the improved location and size. This requires the design data to be available to the inspection system and has a more computationally efficient potential. In addition, the methods and systems described herein may include saving an analysis of systematic defects or by pattern grouping, which may further improve operational efficiency. In addition, the methods and systems described herein can be used to predict the yield of on-tool results, as the results are reviewed (e.g., manual review for recipe optimization, high resolution Image grab, etc.) that are used to prioritize defects.

Additional variations and alternate embodiments of various aspects of the invention will be apparent to those skilled in the art in light of the present description. For example, a method and system for utilizing design data in combination with inspection data is provided. Accordingly, the description is merely illustrative and should be understood as directed to teach those of ordinary skill in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are taken as presently preferred embodiments. As will be apparent to those skilled in the art after taking advantage of the present embodiments of the present invention, elements and materials may be substituted for those shown and described herein, and portions and processes may be reversed, Can be utilized. Modifications may be made to the elements described herein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims (3)

A method of inspecting a wafer,
Determining one or more parameters for an inspection process performed on the wafer based on context data for the wafer; And
And inspecting the wafer according to the inspection process,
The context data defining a geometrical area in the device design for the wafer having different values of one or more attributes,
Wherein the context data comprises context data for more than one layer, which is on the wafer, or to be formed on the wafer, or formed in a previous step in the processing of the wafer. Way. 2. The method of claim 1, wherein the at least one parameter comprises sensitivity to detect defects on different portions of the wafer. A method of inspecting a wafer,
Determining one or more parameters for an inspection process performed on the wafer based on context data for the wafer; And
And inspecting the wafer with more than one channel of the inspection system in accordance with the inspection process,
Wherein the context data defines a geometric area in the device design for the wafer having different values of one or more attributes.

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