KR20130043223A - Methods and systems for utilizing design data in combination with inspection data - Google Patents

Abstract

Various methods and systems are provided for utilizing design data in combination with inspection data. One computer-implemented method for determining the location of inspection data within a design data space includes aligning data obtained by the inspection system with respect to the alignment site on the wafer with data for a given alignment site. The method also includes determining the location of the alignment site on the wafer in the design data space based on the location of the predetermined alignment site in the design data space. The method also includes determining a position of inspection data acquired for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. In one embodiment, the location of the inspection data is determined with sub-pixel accuracy.

Description

METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA}

Priority claim

This application is directed to US Provisional Patent Application No. 60 / 737,947, filed November 18, 2005, entitled "Methods and Systems for Utilizing Design data in Combination with Inspection Data," and "Methods and Systems for Utilizing Design Data in "Combination with Inspection Data" claims the priority of US Provisional Patent Application No. 60 / 738,290, filed November 18, 2005, which is incorporated by reference as if fully set forth herein.

The present invention relates to a method and system for using design data in combination with inspection data. Certain embodiments relate to computer-implemented methods for determining the location of inspection data within a design data space and / or for determining the location of a design space location on a wafer substantially accurately during an inspection process.

The following description and examples are not allowed to be prior art due to its inclusion in this section.

Integrated circuit (IC) designs may be developed using methods or systems such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. The circuit pattern database contains data representing a plurality of layouts for various layers of the IC. The data in the circuit pattern database can be used to determine the layout for the plurality of reticles. The layout of the reticle generally includes a plurality of polygons that define the features in one pattern on the reticle. Each reticle can be used to make one of the various layers of the IC. The layer of the IC may include, for example, a connection pattern in a semiconductor substrate, a gate insulator pattern, a gate electrode pattern, a contact pattern in an interlayer insulator, and an interconnection pattern on the metallization layer.

As used herein, "design data" generally refers to data derived from the physical design (layout) and complex simulation of the IC or its physical design through simple structure and Boolean manipulation.

Semiconductor device design is demonstrated by different procedures prior to fabrication of the IC. For example, semiconductor device designs are checked by software simulation to verify that all features are printed correctly after lithography in manufacturing. Such checks typically include steps such as design rule checking (DRC), optical rule checking (ORC), and more complex software-based verification approaches, including measured process simulation for specific fabs and processes. The output of the physical design verification phase can potentially be used to identify a number of critical points (sometimes referred to in the design as "hot spots").

Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a substrate, such as a semiconductor wafer, using a plurality of semiconductor fabrication processes to form various features and multiple layers of the semiconductor device. . For example, lithography is one semiconductor fabrication process that includes transferring a pattern from a reticle to a resist aligned on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical mechanical polishing (CMP), etch, deposition, and ion implantation. The plurality of semiconductor devices are manufactured in batches on a single semiconductor wafer and then separated into individual semiconductor devices.

The inspection process is used at various stages during the semiconductor manufacturing process to detect defects on the wafer in order to promote high yield of the manufacturing process and thus high profit. Inspection has become an important part of the manufacture of semiconductor devices such as ICs. However, as the dimensions of the semiconductor device decrease, inspection becomes more important in the successful manufacture of acceptable semiconductor devices because small defects can cause the device to fail. For example, as the dimensions of a semiconductor device are reduced, even a relatively small defect can cause unwanted deformation in the semiconductor device, so a detection of a defect of a reduced size is required.

Another important part of manufacturing yield control is determining the cause of defects on a wafer or reticle so that the cause of the defects can be corrected to reduce the number of defects on other wafers or reticles. Often, determining the cause of the defect includes identifying the defect type and other attributes of the defect, such as size, shape, configuration, and the like. Defect review because inspection typically only includes detecting defects on the wafer and providing limited information about the defect, such as the location on the wafer or reticle, the number of defects on the wafer or reticle, and sometimes the defect size Is often used to determine more information about individual defects that can be determined from inspection results. For example, a defect review tool can be used to revisit a detected defect on a wafer or reticle and inspect the defect in an automatic or manual additional manner.

Defect review typically involves generating additional information about the defect at high resolution using a high magnification optical system or a scanning electron microscope (SEM). The high resolution data generated by the defect review is more suitable for determining the nature of defects such as profile, roughness, more accurate size information, and the like. Defect analysis can be performed using a system such as an electron scattering x-ray spectroscopy (EDS) system. Such defect analysis can be performed to determine information such as the composition of the defect. The nature of a defect determined by inspection, review, analysis or some combination thereof may be used to identify the type of defect (ie, defect category) and possibly the root cause of the defect. This information can be used to monitor and change one or more parameters of one or more semiconductor manufacturing processes to reduce or eliminate defects.

However, as the design rules decrease, the semiconductor manufacturing process can be manipulated close to the limits on the performance capabilities of the process. In addition, as design rules decrease, small defects can affect the electrical parameters of the device, leading to one or more sensitive inspections. Thus, as the design rules decrease, the population of potentially yield-related defects detected by the inspection dramatically increases, and the population of Newson's defects detected by the inspection also increases dramatically. Thus, more and more defects are detected on the wafer, and the step of calibrating the process to remove all the defects can be more difficult and expensive. As such, the step of determining which of the defects actually affects the electrical parameters and yield of the device is that the process control method concentrates and permits only those defects, while largely ignoring other defects. Also, in small design rules, process guidance errors can be systematic in some cases. That is, process induction errors tend to be errors in certain design patterns that are often repeated several times in a design. Spatially, systematically and electrically related defects are important because the removal of such defects can have a significant overall impact on yield. Whether a defect affects device parameters and yield can often not be determined from the inspection, review, and analysis processes described above, because these processes cannot determine the location of the defect with respect to the electrical design.

Some methods and systems have been developed to align defect information into electrical designs. For example, the SEM review system can be used to determine more accurate coordinates of the defect location for the combined sample, and the defect coordinates reported by the SEM review system can be used to determine the location of the defect in the electrical design. Another method includes aligning an inspection attention area (eg, an area of the device pattern formed on the wafer on which the inspection is to be performed) to a physical location of the pattern printed on the wafer. However, at present, the area of interest can be aligned to the pattern printed on the wafer with an accuracy of only 2 μm due to system errors and defects. For example, some bright field (BF) inspection systems have a coordinate accuracy of about +/− 1 μm. In addition, the test attention area in the currently used methods is relatively large and includes several non-major features as well as the desired main features. In an attempt to maximize the sensitivity of an inspection system to capture spatially systematic design-for-manufacturability (DMF) defects resulting from design and process interdependencies, the system can generate millions of non-critical regions, such as CMP filled regions. Can be overwhelmed by events. For example, these Newsons events need to be filtered from the test results by post-processing the test data. In addition, Newsons event detection limits the ultimately achievable sensitivity of the inspection system for DFM applications. High rates of Newson's defect data can overload the run-time data processing capability of the inspection system, resulting in lower throughput and / or loss of data.

Substantially very accurate "contexts" of design data are not limited to defect detection algorithms or methods, detection sensitivity tailoring, nusons defect filtering, defect classification, defect grouping, and use of design context as part of sampling techniques. How to align inspection data with sub-pixel accuracy (the size of a pixel can be as large as the structure being inspected) in the design data so that it can be utilized to perform one or more context-based functions such as defect sampling for review. And developing a system may be beneficial.

Summary of the Invention

The following description of various embodiments of the methods and systems is not to be taken as limiting the scope of the appended claims.

One embodiment relates to a computer-implemented method for determining the location of inspection data within a design data space. The method includes aligning data acquired by the inspection system with respect to alignment sites on the wafer with data (eg, design data) for a given alignment site. Data for a given alignment site and data acquired by the inspection system for the alignment site on the wafer are obtained separately. For example, data for a given alignment site is not obtained using a wafer on which the alignment site is printed. The method also includes determining a location of the alignment site on the wafer in the design data based on the location of the predetermined alignment site in the design data space. Determining the position of the alignment site on the wafer within the design data space may be performed based on the design layout on the wafer and / or the orientation of the wafer during inspection. The method also includes determining a position of inspection data acquired for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. The location of the test data can be stored and used as described further herein. In one embodiment, the location of the inspection data is determined with sub-pixel accuracy.

In other embodiments, data for a given alignment site may be stored in a data structure such as a graphical data stream (GDS) file, any other standard machine-readable file, any other suitable file known in the art, and a design database. Contains design data to be stored. GDSII files are a category of files used for the representation of design layout data. Other examples of such files include GL1 and OASIS files. Some embodiments are described herein with respect to GDS or GDSII files, but the embodiments are equally applicable to the entire category of files, regardless of data structure organization, storage format, or storage mechanism. In another embodiment, the data for a given alignment site includes one or more simulated images that indicate how the given alignment site will be printed on the wafer.

In some embodiments, the data for a given sorting site includes one or more attributes of a given sorting site, the data for the sorting site includes one or more attributes of a sorting site, and the sorting step includes one of the sorting sites. Sorting the at least one attribute to at least one sorting site of the sorting site. In one such embodiment, one or more attributes of a given alignment site include the center of a given alignment site and one or more attributes of the alignment site include the center of the alignment site.

In a further embodiment, the data for a given alignment site includes data that is acquired by an inspection system or other image acquisition system and aligned to design data stored in a data structure, such as a GDSII file for design data. In yet another embodiment, the data for a given alignment site includes at least a portion of a standard reference die image aligned to design coordinates in the design data space. The standard reference die image may be a reference image obtained, simulated, enlarged, or a combination thereof.

In some embodiments, a given alignment site includes at least one alignment feature having one or more attributes unique in the x and y directions. In another embodiment, a given alignment site includes at least two alignment features. The first of the two alignment features has one or more attributes unique in the x direction. The second of the two alignment features has one or more attributes unique in the y direction.

In a further embodiment, the method includes selecting a predetermined alignment site using a inspection system. In one such embodiment, the imaging mode of the inspection system or other image acquisition system used to select a given alignment site is different from the imaging mode of the inspection system used to acquire inspection data. In some embodiments, determining the location of the alignment site is performed prior to the inspection of the wafer, and determining the location of the inspection data is performed during the inspection of the wafer. In another embodiment, the step of determining the location of the inspection data is performed subsequent to the inspection of the wafer. In one such embodiment, determining the location of the inspection data is performed on the portion of inspection data corresponding to the defect detected on the wafer, not on the portion of inspection data not corresponding to the defect. In this manner, the location of inspection data in the design data space is determined only for inspection data (eg, patch images) acquired at a defective location on the wafer.

In another embodiment, the data for the alignment site is within a swath of the inspection data. In one such embodiment, determining the position of the swath in the design data space based on the position of the alignment site in the design data space, and the position of the additional swath of inspection data in the design data space based on the position of the swath. Determining a step.

In one embodiment, the method includes determining a sensitivity for detecting a defect on another portion of the wafer based on the location of the inspection data in the design data and one or more attributes of the design data in the design data space. It includes. In one such embodiment, the one or more attributes of the design data are relative to the process layer, another process layer, or some combination thereof, for the design data, other design data, or some combination thereof, for which the inspection data for the wafer is obtained. The selection is made based on one or more attributes of inspection data previously acquired for a wafer, another wafer, or some combination thereof. In such other embodiments, the one or more attributes of the design data may include yield criticality of defects previously detected at other sites, fault probability of defects previously detected at other sites, or portions thereof. It is selected based on the combination.

In another embodiment, determining a sensitivity for detecting a defect on another portion of a wafer based on a context map and a location of inspection data in a design data space, wherein the context map is a design data space. Contains values for one or more attributes of the design data across. In one such embodiment, determining the sensitivity includes determining a sensitivity threshold used for inspection data to detect defects on other portions of the wafer. In another such embodiment, determining the sensitivity is performed by the inspection system during inspection of the wafer. In such further embodiments, determining the sensitivity is performed after acquisition of inspection data for the wafer is complete.

In a further embodiment, the method includes detecting for detecting a defect on another portion of the wafer based on the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. Determining the degree. In one such embodiment, the one or more attributes of the inspection data include one or more image noise attributes, whether a defect was detected at another site, or some combination thereof.

In some embodiments, the method comprises one or more properties of schematic data about the design of the device being manufactured on a wafer, one or more properties of expected electrical behavior of the physical layout for the device, or some combination thereof. Based on the step of changing the one or more parameters for detecting a defect on the wafer. In another embodiment, the method includes changing one or more parameters for detecting defects on the wafer using inspection data based on one or more parameters of an electrical test process performed on the wafer. In a further embodiment, the method includes changing one or more parameters of an electrical test process performed on the wafer based on defects detected on the wafer using inspection data.

In a further embodiment, the method uses a feedback control technique to periodically change one or more parameters of the inspection process performed by the inspection system based on the results of the one or more steps of the method. It includes. In another embodiment, the method includes using a feedback control technique to automatically change one or more parameters of the inspection process performed by the inspection system based on the results of the one or more steps of the method. In another embodiment, the method may further comprise generating a knowledge base using the results of one or more steps of the method, and generating a test process performed by the inspection system using the knowledge base. It includes.

In another embodiment, the method includes classifying the detected defect on another portion of the wafer based on the location and context map of the portion of the inspection data corresponding to the defect in the design data space, the context map comprising the design. Contains values for one or more attributes of the design data over the data space. In one such embodiment, the sorting step is performed by the inspection system during inspection of the wafer. In another such embodiment, the sorting step is performed after the acquisition of the inspection data for the wafer is completed.

In another embodiment, the inspection data includes data about defects on the wafer. In one such embodiment, the method includes determining a location of a defect in a design data space based on a location of inspection data in the design data space, and at least one of the location of the defect in the design data space and the design data in the design data space. Based on the attribute, determining whether the defect is a nuisance defect. In one such embodiment, based on one or more attributes of the design data in the design data space, determining whether the defect that is not determined to be a Newson's defect is a systematic or random defect. Determining whether a defect is spatially systematic or random is based on one or more attributes of the design data in the design data space, in combination with other information, such as historical fab data or other data corresponding to hot spots in the design data. Can be done. In one such embodiment, the method may also include determining whether the defect is a systematic or random defect based on the location of the inspection data in the design data space and one or more statistically determined attributes of the inspection data. In one embodiment, test data is acquired for process window qualification (PWQ). In another embodiment, the method includes classifying the defects based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space.

In one embodiment, the method includes binning a defect based on a location of the inspection data in the design data space and one or more attributes of the design data in the design data space. In some embodiments, the method is based on the location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the reticle inspection data obtained for the reticle from which the design data is printed above. Binning the defects into groups. In a further embodiment, the method includes binning the defects into groups based on a location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. In some embodiments, the method further includes the location of inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, and the reticle inspection data obtained for the reticle to which the design data is printed above. Based on one or more attributes, binning the defects into groups. In a further embodiment, the method includes a location of inspection data in a design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, and a process hierarchy from which inspection data for the wafer is obtained, another process. For a layer or some combination thereof, group defects based on one or more attributes of inspection data previously acquired for a wafer, another wafer, or some combination thereof, for design data, other design data, or some combination thereof. Binning.

As discussed above, the inspection data may include data about defects on the wafer. In one such embodiment, the method includes selecting at least a portion of the defect for review based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. In such further embodiments, the method includes determining a sequence in which defects are reviewed based on the location of inspection data in the design data space and one or more attributes of the design data in the design data space. In another such embodiment, the method includes selecting at least a portion of a defect for review, wherein at least a portion of each of the design data in the design data space has a different value of one or more attributes of the design data. At least one defect located within the portion. Defect review sampling may also be performed (or alternatively) based on one or more attributes of the group in which the defect is binned. Defects may be binned as described further herein, and one or more attributes of the group may be determined based on one or more attributes of the design data or in any other manner described herein.

In another embodiment, the method further comprises one of the outputs from one or more detectors of the inspection system, acquired for other portions of the wafer, based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. And extracting the above predetermined attribute. In one such embodiment, the one or more attributes of the design data are relative to the design data, other design data, or some combination thereof, for the process layer, another process layer, or some combination thereof, from which inspection data for the wafer is obtained. The selection is made based on one or more attributes of inspection data previously acquired for a wafer, another wafer, or some combination thereof.

In another embodiment, the method includes an inspection acquired for another portion of the wafer based on the location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. Extracting at least one predetermined attribute of the output from at least one detector of the system. In one such embodiment, the at least one attribute of the inspection data includes at least one image noise attribute, whether at least one defect was detected at the other site, or some combination thereof.

In some embodiments, the method includes determining an error probability value for one or more defects detected on the wafer based on the location of the inspection data in the design data space and the one or more attributes of the design data in the design data space. do.

In another embodiment, the method includes determining position coordinates of a defect detected on a wafer in the design data space based on a position of inspection data in the design data space, and based on a plan view of the design data, position coordinates of the defect. Moving to the design cell coordinates. In one such embodiment, the method uses overlay tolerance to determine different areas around the defect, determines whether one or more cell types are systematically defective cell types, and systematically defective cells. Performing defect repeater analysis for one or more cell types, using the region, to determine one or more locations of one or more systematically defective structures in the type. In one such embodiment, the method is based on one or more attributes, structures, or portions thereof of the design data for a cell located close to the systematically defective cell type, wherein the spatially systematic defect is within the systematically defective cell type. Determining whether it occurs in the.

In another embodiment, the method includes determining a location of a detected defect on a wafer in a design data space based on a location of inspection data in the design data space, and wherein the predetermined value for one or more attributes of the design data is determined. Using a data structure stored as a function of a location within the space, determining a value for one or more attributes of the design data corresponding to the location of the defect.

In a further embodiment, the image of the reticle generated by the reticle inspection system is used as design data in the design data space. The reticle is used to print design data on the wafer. In another embodiment, a simulated image showing how the reticle image will be printed on the wafer is used as design data in the design data space. In a further embodiment, the method includes generating a context map for the design data in the design data space based on the reticle inspection data obtained for the reticle used to print the design data on the wafer.

In one embodiment, optimizing the wafer inspection process to determine the printability of reticle defects on the wafer using the location and context map of the inspection data within the design data space. In another embodiment, the method includes detecting defects on the wafer using inspection data for standard reference die based inspection and standard reference die for standard reference die based inspection. In a further embodiment, the method detects defects on the wafer using a representation of wafer noise associated with inspection data, standard reference die, and standard reference die in a perturbation matrix for standard reference die based inspection. It includes a step.

In further embodiments, the wafer and additional wafers are processed using wafer level process parameter adjustments, which method compares inspection data for the wafers and the die on the additional wafers to conventional standard reference dies, thereby providing a wafer and additional wafers. Detecting a defect in the phase.

Each of the foregoing steps may be performed based on a close location of inspection data in the design data space, one or more attributes of the design data in the design data space, historical fab data, or other data corresponding to hot spots in the design data. In some embodiments, the method includes performing statistical process control (SPC) based on a defect and one or more attributes of the group in which the defect is binned, or any other result of any of the methods described herein. can do. Each embodiment of the foregoing method may include any other step of any of the methods described herein. Each embodiment of the method described above may be performed by any system embodiment described herein.

Another embodiment is directed to a system configured to determine the location of inspection data within a design data space. The system includes a storage medium containing the design data. The system also includes a processor coupled to the storage medium. The processor is configured to align the data obtained by the inspection system with respect to the alignment site on the wafer to the data for a given alignment site. The processor is further configured to determine the location of the alignment site on the wafer in the design data space based on the location of the predetermined alignment site in the design data space. The processor is also configured to determine the position of inspection data acquired for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. This embodiment of the system can be further configured as described herein.

Further embodiments relate to a system configured to determine the location of inspection data within a design data space. Such a system includes data for an alignment site on a wafer and an inspection system configured to obtain inspection data for the wafer. The system also includes a storage medium containing the design data. The system also includes a processor coupled to the inspection system and the storage medium. The processor is configured to align data for an alignment site on the wafer with data for a given alignment site. The processor is configured to determine the position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site in the design data space. The processor is also configured to determine the location of the inspection data in the design data space based on the location of the alignment site on the wafer in the design data space.

An additional embodiment is configured to determine the position of a design data-based attention area (eg, an inspection area, an area to be inspected with high sensitivity, or an area to be inspected with low sensitivity) in the inspection space during operation (eg, during the inspection process). . In addition, the system may be configured to assign the acquired pixels of data substantially accurately to the correct region of interest during the inspection process. The size and frequency of the attention area can approach the size and frequency of the design structure on the die. Such a system may be further configured as described herein.

Further embodiments relate to computer-implemented methods for binning detected defects on a wafer. The method includes comparing a portion of design data close to the location of a defect in the design data space. The method includes determining whether design data in the portion is at least similar based on the comparing step. Determining whether the design data in the portion is at least similar may include rotating and / or reflecting one or more portions. The method also includes binning the defects into groups such that portions of design data close to the location of the defects within each group are at least similar. The method further includes storing the result of the binning step in a storage medium.

In one embodiment, the dimensions of the portion may include the location of the defect reported by the inspection system used to detect the defect, coordinate inaccuracy of the inspection system, one or more attributes of the design data, a defect size error of the inspection system, or some combination thereof. Is determined based at least in part on. In other embodiments, the dimensions of at least some of the portions are different.

In one embodiment, the design data in that portion includes design data for one or more design layers. In this manner, the design data used in the methods described herein may include design data for one or more design layers. The use of design data for one or more design layers in the methods described herein means that when a defect is detected using bright field (BF) inspection that can detect defects on one or more layers, the criticality of the location is designed. It may be useful in instances such as depending on what happened on the layer before or after. The method described above may include binning some or all of the data of interest into a group having at least similar design data.

In another embodiment, the comparing step includes comparing all of the design data in at least a portion of the portion to design data in another portion of the portion. In another embodiment, the comparing step includes comparing another area of design data in at least a portion of the portion to design data in another portion of the portion.

In one embodiment, the method includes determining a location of a defect in a design data space by comparing the data obtained by the inspection system for the alignment site on the wafer with data for a given alignment site. In another embodiment, the method includes determining a location of a defect in the design data space by comparing the data acquired by the inspection system during the defect inspection to a location in the design data determined by the review.

Alignment accuracy depends on both the coordinate transformation from the design to the wafer and the coordinate accuracy of the inspection system. Thus, preferably, the coordinates reported by the inspection system are substantially accurate. In addition, measurements for alignment sites can be performed using logical check coordinates. (The inspection system outputs logical wafer coordinates, but defect review tools such as scanning electron microscopes (SEMs) measure the physical wafer coordinates. Thus, the physical coordinates on the wafer are compared with the reticle offset, when compared to the expected wafer layout. Can be corrected by the inspection system to account for differences in scaling and minute rotations As such, such correction is applied to SEM measurements to reduce errors between two coordinate systems from the reticle to the reticle Can be.

In one embodiment, the binning step includes binning the defects into groups such that portions of design data close to the location of the defects in each group are at least similar, and one or more attributes of the defects in each group are at least similar. In such embodiments, the one or more attributes include one or more attributes of the inspection results for which a defect is detected, one or more parameters of the inspection, or some combination thereof.

In some embodiments, the portion of design data close to the location of the defect includes design data at which the defect is located. In another embodiment, the portion of design data close to the location of the defect includes design data around the location of the defect.

In another embodiment, the binning step includes binning the defects into groups such that portions of design data close to the positions of the defects in each group are at least similar, and that the positions of the defects in each group with respect to the polygons within the portion are at least similar. do.

In a further embodiment, the method includes determining a defect criticality index (DCI) for one or more defects. In another embodiment, the method includes one or more attributes of the design data close to the position of the defect, one or more attributes of the defect, the location of the defect reported by the inspection system used to detect the defect, the coordinate inaccuracy of the inspection system, Or based on some combination thereof, determining the probability that the one or more defects will cause one or more electrical failures in the device being manufactured for the design data. In one such embodiment, the method also includes determining a DCI for one or more defects based on the probability.

In some embodiments, the method includes identifying one or more hot spots in the design data based on the results of the binning step. In another embodiment, the method includes selecting at least some of the defects for review based on the results of the binning step. In a further embodiment, the method includes generating a process for sampling a defect for review based on the results of the binning step. In a further embodiment, the method includes changing the process for inspecting the wafer based on the results of the binning step. In some embodiments, the method includes changing a process for inspection of a wafer during inspection based on inspection results. In another embodiment, the method includes changing the metrology process for the wafer based on the results of the binning step. In a further embodiment, the method includes changing the sampling plan for the metrology process for the wafer based on the results of the binning step. In another embodiment, the method includes monitoring over time a systematic defect, a potential systematic defect, or some combination thereof using the results of the binning step.

In another embodiment, a defect is detected by an inspection process, the method comprising reviewing a location on a wafer on which one or more patterns of interest (POI) in the design data are printed, and the location of the one or more POIs. Determining based on the results of the review step and altering the inspection process to improve one or more defect capture rates.

In some embodiments, the method prioritizes one or more POIs in the design data, and based on the results of the prioritization step, optimizing the one or more processes to be performed on the wafer on which the design data is printed. It includes. In another embodiment, the method includes prioritizing one or more POIs in the design data and optimizing at least one of the one or more POIs based on the result of the prioritizing step. In a further embodiment, the method prioritizes one or more POIs in the design data and optimizes the resolution enhancement technology (RET) features of the one or more POIs based on the results of the prioritization steps. It includes a step.

In one embodiment, the defect is detected by optical inspection. In some embodiments, the defect is detected by electron beam inspection. In another embodiment, defects are detected in a process window qualification (PWQ) method.

In some embodiments, the method reviews at least a portion of the defects in the one or more groups to determine if the defects in the one or more groups correspond to Newsons defects, and to increase the S / N of the results of the inspection process, Removing one or more groups corresponding to the Newson's defect from the results of this detected inspection process. In another embodiment, the method includes classifying the defects in the one or more groups based on a review result of at least some of the defects in the one or more groups, the one or more attributes of the design data, the one or more attributes of the defects, or some combination thereof. It includes. In a further embodiment, the method further determines the root cause of at least one group of defects based on a review of at least some of the defects in the at least one group, at least one attribute of the design data, at least one attribute of the defect, or some combination thereof. Determining.

In one embodiment, the method includes determining the root cause of the defects in one or more groups by mapping at least a portion of the defects in the one or more groups to an experimental process window result. In another embodiment, the method includes determining the root cause of the defects in the one or more groups by mapping at least a portion of the defects in the one or more groups to a simulated process window result.

In some embodiments, the method uses design data to model the electrical properties of the device being manufactured for the defect location, and based on the results of the modeling step, determine a parameter association of the defect at the defect location. It includes a step. In another embodiment, the method includes monitoring a kill probability (KP) value of one or more defects based on one or more attributes of the design data. In a further embodiment, the method further comprises: monitoring KP values for one or more POIs in the design data, and if the portion of the design data close to the location of the defects binned into one or more groups corresponds to the one or more POIs; Assigning a KP value for the at least one group.

In some embodiments, one or more steps of the methods described herein comprise an inspection system (ie, “on tool”) or a processor physically separated but coupled to the inspection system by a transmission medium (ie, “off tool”). (off tool) "). For example, in one embodiment, the computer-implemented method is performed by an inspection system used to detect a defect. In alternative embodiments, the computer-implemented method is performed by a system other than the inspection system used to detect the defect.

In another embodiment, the determining step includes determining whether a common pattern in the design data in the portion is at least similar. In a further embodiment, the determining step includes determining whether common attributes of the design data in the portion are at least similar. In a further embodiment, the determining step includes determining whether common attributes in a feature space of design data in the portion are at least similar.

In one embodiment, the method includes determining a percentage of the die formed on the wafer affected by the at least one group of defects. In another embodiment, the method includes determining one or more POIs in design data corresponding to one or more groups, binning into at least one group corresponding to one or more POIs for the number of locations of one or more POIs on a wafer. Determining a ratio of the number of defects. In a further embodiment, the method includes determining at least one POI in the design data corresponding to the at least one group, and in at least one group corresponding to the at least one POI for the number of locations of the at least one POI in the design data. Determining a ratio of the number of binned defects.

In a further embodiment, the method includes determining a POI in design data corresponding to at least one group, determining a percentage of the die formed on the wafer where the defects binned into the at least one group are located; Assigning a priority to the POI based on the percentage. In some embodiments, the method includes prioritizing the one or more groups by the number of total design instances on the wafer on which one or more groups of defects are detected. In another embodiment, the method includes prioritizing the one or more groups by the number of design instances on the reticle used to print design data on the wafer at which defects in the one or more groups are detected at least once. In a further embodiment, the method includes design data printed on a reticle that is at least similar to the number of locations on the reticle where defects binned into one or more groups are detected, and portions of design data close to the locations of defects binned into one or more groups. Based on the total number of portions, determining a reticle-based margin for at least one group.

In one embodiment, the method includes converting a portion of the design data close to the location of the defect in the design data space into a bitmap prior to the comparing step. In one such embodiment, the comparing step compares the bitmaps with each other.

Each embodiment of the foregoing method may include any step of any of the methods described herein. In addition, each embodiment of the method described above may be performed by any of the systems described herein.

Another embodiment is directed to a method for determining DCI for a defect detected on a wafer. The method includes for a device near a location of a defect in a design data space, based on one or more attributes of the design data, determining a probability that the defect will change one or more electrical attributes of the device being manufactured on the wafer. . The method also includes determining a DCI for the defect based on the probability that the defect will change one or more electrical properties. The method also includes storing the DCI in a storage medium.

In one embodiment, the defect comprises a random defect. In other embodiments, the defects include systematic defects. In further embodiments, the one or more electrical properties include the functionality of the device. In further embodiments, the one or more electrical properties comprise one or more electrical parameters of the device.

In one embodiment, one or more attributes of the design data include redundancy, a net list, or some combination thereof. In another embodiment, the one or more attributes of the design data include the dimensions of the features in the design data, the density of the features in the design data, or some combination thereof.

In one embodiment, determining the probability comprises determining the probability using a correlation between electrical test results for the design data and one or more attributes of the design data. In another embodiment, determining the probability includes determining the location of a defect in the design data space, the location of the defect as reported by the inspection system used to detect the defect, the coordinate inaccuracy of the inspection system, the size of the defect, Determining the probability based on one or more attributes of the design data, in combination with a defect size error, or some combination thereof. In one such embodiment, the defect includes a random defect.

In some embodiments, determining the probability includes determining the probability based on one or more attributes of the design data, in combination with one or more attributes of the defect. In one such embodiment, the defect includes a systematic defect.

In one embodiment, determining the DCI includes determining a DCI for the defect, based on the probability, in combination with the category assigned to the defect. In another embodiment, the one or more defects in the design data include one or more attributes of the design data for one or more design layers of the device.

In one embodiment, the method includes determining the location of the inspection data within the design data space to determine design data close to the location of the defect. In another embodiment, the method includes determining design data close to the location of the defect by defect alignment. In some embodiments, the method includes the location of a defect reported by the inspection system used to detect the defect, coordinate inaccuracy of the inspection system, one or more attributes of the design data, defect size, defect size error of the inspection system, or Determining design data close to the location of the defect based at least in part on some combination thereof.

In one embodiment, the method includes modifying the DCI based on yield sensitivity of design data for a defect. In another embodiment, the method includes changing the process performed on the defect based on the DCI determined for the defect. In a further embodiment, the method includes changing the process used to detect the defect based on the DCI determined for the defect. In a further embodiment, the method includes generating a process for inspection of an additional wafer to be fabricated above, based on the DCI for the defect.

In one embodiment, the computer-implemented method is performed by an inspection system used to detect a defect. In another embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect the defect.

Each embodiment described above may include any step of any of the methods described herein. In addition, each embodiment of the method described above may be performed by any of the systems described herein.

Another embodiment relates to a computer implemented method of determining a memory repair index (MRI) for a memory bank formed on a wafer. The method includes determining a plurality of redundant columns and a plurality of redundant rows needed to repair the memory bank based on defects located in the array block area of the memory bank. The method also includes comparing the number of redundant rows required to repair the memory bank to the number of redundant rows available for the memory bank. The method also includes comparing the number of redundant rows needed to repair the memory bank to the amount of redundant rows available for the memory bank. The method further includes determining an MRI for the memory based on the results of comparing the number of redundant columns and comparing the number of redundant rows. The MRI indicates whether the memory bank is repairable. The method also includes storing the MRI in a storage medium.

In one embodiment, the method includes determining which of the defects located within the array block area can cause a bit in the memory bank to fail, and based on the location of the defect that can cause the bit to fail. Thereby determining the location of the bit to fail. In one such embodiment, determining the number of redundant rows and redundant rows required to repair the memory bank is performed using the location of the failure day bit.

In another embodiment, the method includes changing one or more parameters of the electrical test process based on MRI using a feed forward control technique. In a further embodiment, the method uses feed forward technology to change one or more parameters of the electrical test process based on the MRI such that if the memory bank is unrepairable, the die on which the memory bank is located is not tested during the electrical test process. It includes a step. In a further embodiment, the method alters one or more parameters of the repair process based on one or more attributes of a fault located within the array block area of the memory bank, a fault located within the array block area of the memory bank, or some combination thereof. It includes a step.

In one embodiment, the defect includes a defect detected in the gates layer of the memory bank. In another embodiment, the defect includes a defect detected in the metal layer of the memory bank.

In some embodiments, the method includes predicting a bit error mode of the defect based on the location of the defect in the memory bank. In another embodiment, the method includes determining a DCI for one or more defects located within the array block area. In one such embodiment, determining the number of redundant columns required for repair of the memory bank and determining the number of redundant rows are performed using DCI for one or more defects.

In one embodiment, comparing the number of redundant rows is performed separately for each bank of memory dies, and comparing the number of redundant rows is performed separately for each bank of memory dies. In some embodiments, the method includes determining the amount of available redundant rows and the amount of available redundant rows based on defects located within redundant rows and redundant rows of a memory bank.

In one embodiment, the method includes determining an MRI for at least one memory bank formed in the die and predicting a repair yield for the die based on the MRI for at least one memory bank. In another embodiment, the method includes determining, based on the MRI, whether the amount of available redundant rows in the memory bank, the amount of available redundant columns, or some combination thereof is to be evaluated by the memory bank designer.

In some embodiments, the method includes determining an MRI for each memory bank in at least one die on a wafer, and determining a memory repair yield for at least one die based on the MRI for each memory bank. . In some such embodiments, the method includes performing a wafer placement based on one or more memory repair yields for one or more die on the wafer.

In one embodiment, comparing the number of redundant rows includes determining a fraction of redundant rows needed to repair the memory banks, and comparing the number of redundant rows comprises determining the fraction of redundant rows required to repair the memory banks. Determining the MRI for the memory bank, and determining the MRI based on the fraction of redundant columns and the fraction of redundant rows. In some such embodiments, the method includes determining an MRI for each memory bank in at least one die on a wafer and determining a memory repair yield for at least one die based on the MRI for each memory bank. Include. In a further such embodiment, the method includes determining a memory repair yield for the wafer based on the memory repair yield for each of the one or more dies.

In one embodiment, the MRI also indicates the probability that the memory repair bank cannot be repaired. In one such embodiment, the method includes determining an MRI for each memory bank in at least one die on a wafer, and based on the MRI for each memory bank in at least one die, determining an MRI for at least one die. Wherein the MRI for one or more dies indicates the probability that one or more dies cannot be repaired. In one such embodiment, the method includes determining a wafer based yield prediction based on a threshold of MRI for one or more dies on a wafer.

In one embodiment, the method determines the number of non-repairable defects in the memory bank based on the number of defects located in the decoder region of the memory bank, the number of defects located in the sense amplifier region of the memory bank, or some combination thereof. It includes a step.

In some embodiments, determining the number of redundant columns and the number of redundant rows includes determining a DCI for each defect located within an array block area of a memory bank, comparing the DCI with a predetermined threshold; Determining the number of redundant columns and redundant rows required to repair all defects having a DCI above a predetermined threshold.

In one embodiment, the method includes determining an MRI for an error in the memory bank due to a defect located within the array block area of the memory bank. In another embodiment, the method includes determining an MRI for an error in the memory bank due to a defect located in the redundant column and redundant row of the memory bank.

In some embodiments, the method includes generating a stacked map of the pseudo memory bank design indicative of the spatial correlation between defects detected within the memory bank. In another embodiment, the method includes determining an MRI on a die basis. In a further embodiment, the method includes determining an index indicating whether a failure on a die on a wafer is due to a defect located in an array block area.

In one embodiment, the method includes determining an MRI for a memory bank in a die on a wafer and generating a stacked map of the die indicating a spatial correlation between two or more memory banks indicated by the MRI as non-repairable. It includes. In another embodiment, the method is used to determine an MRI for a memory bank in a die on a wafer and to form a memory bank on a wafer that exhibits a spatial correlation between two or more memory banks indicated by the MIR as non-repairable. Generating a stacked map of the reticle.

In some embodiments, the method includes identifying a memory bank of a die affected by a defect detected in the die, and ranking the memory bank based on the impact of the defect on the memory bank. . In another embodiment, the method includes determining a percentage of the memory bank formed on the wafer affected by a defect in the non-repairable area of the memory bank. In some embodiments, the method includes generating a stacked wafer map of possible errors in a memory bank formed on a wafer that exhibits a spatial correlation between possible errors. In a further embodiment, the method includes determining an MRI for at least one die formed on the wafer and ranking the at least one die based on the MRI.

Each embodiment of the method described above may include any step of any of the methods described herein. In addition, each embodiment of the method described above may be performed by any of the systems described herein.

Another embodiment is directed to another computer-implemented method for binning detected defects on a wafer. The method includes comparing a location of a defect in a design data space to a location of a hot spot in the design data. Hot spots located at least close to similar design data are correlated with each other. The method also includes associating the defect with a hot spot having at least a similar location. The method also includes binning the defects into groups such that the defects in each group are associated only with hot spots that are correlated with each other. The method further includes storing the results of the binning step in a storage medium.

In one embodiment, the method includes correlating hot spots by identifying locations of POIs in design data associated with systematic defects, correlating POIs with similar patterns in design data, and correlated hot spots. Correlating the position of the POI with the position of a similar pattern in the design data as the position of.

In some embodiments, the method includes assigning a DBC to one or more groups. In another embodiment, the computer-implemented method is performed by an inspection system used to detect defects on the wafer. In a further embodiment, the method includes monitoring hot spots using inspection results of one or more wafers on which design data is printed.

In one embodiment, the method includes inspecting the wafer based on the correlation between hot spots. In another embodiment, the method includes monitoring over time a systematic defect, a potential systematic defect, or some combination thereof based on the result of the binning step. In a further embodiment, the method includes performing a review of the defect based on the result of the binning step. In a further embodiment, the method includes creating a process for selecting a defect for review based on the results of the binning step.

In one embodiment, the method includes identifying systematic and potential systematic defects in the design data based on the results of the binning step and the monitoring results of the appearance of systematic and potential systematic defects over time. . In another embodiment, based on the results of the binning step, generating a process for inspecting a wafer having design data printed thereon. In a further embodiment, modifying the process for inspecting a wafer having design data printed thereon based on the results of the binning step.

In some embodiments, the method includes determining a percentage of the die formed on the wafer affected by the at least one group of defects. In another embodiment, the method includes determining a DCI for one or more defects. In a further embodiment, the method includes determining a percentage of the die formed on the wafer at which the defects binned into the at least one group are located, and assigning a priority to the at least one group based on the percentage. do.

In one embodiment, the method includes prioritizing the one or more groups by the total number of hot spots correlated with the hot spots associated with the defects in the one or more groups and the number of the defects in the one or more groups. In another embodiment, the method includes prioritizing the one or more groups by the number of corresponding hot spot locations on the reticle used to print design data on the wafer at which defects in the one or more groups are detected at least once. do.

In some embodiments, the method is based on the number of locations on the reticle where defects binned into one or more groups were detected, and the total number of hot spot locations on the reticle correlated with hot spots associated with defects in one or more groups, Determining a reticle-based margin for one or more groups.

Each embodiment of the method described above may include any other step of any of the methods described herein. In addition, each embodiment of the method described above may be performed by any of the systems described herein.

Another embodiment is directed to another computer-implemented method for binning detected defects on a wafer. The method includes comparing one or more attributes of design data close to the location of a defect in the design data space. The method also includes determining, based on the comparison result, whether one or more attributes of the design data close to the location of the defect are at least similar. The method also includes binning the defects into groups such that at least one attribute of the design data close to the location of the defects in each group is at least similar. The method further includes storing the result of the binning step on a storage medium.

In one embodiment, the one or more attributes include pattern density. In another embodiment, the method includes determining whether the defect is a random or systematic defect using one or more attributes. In a further embodiment, the method includes ranking one or more groups using one or more attributes. In a further embodiment, the method includes ranking the defects in the at least one group using one or more attributes. In some embodiments, the one or more attributes include one or more attributes in the feature space.

In one embodiment, the method includes binning at least one group into a sub-group using one or more attributes. In another embodiment, the method includes analyzing defects in at least one group using one or more attributes. In a further embodiment, the method includes determining yield relationships of one or more defects using one or more attributes. In a further embodiment, the method includes determining the overall yield relevance using one or more attributes. In another embodiment, the method includes assigning the DCI to one or more defects using one or more attributes.

In some embodiments, the method includes separating design data near the location of the defect into design data in the area around the defect and design data in the area in which the defect is located. In another embodiment, the method includes identifying a structure in design data for binning or filtering using a rule and one or more attributes.

In one embodiment, the method includes determining a location on a wafer on which a review, measurement, test, or some combination thereof is to be performed, based on a test result generated during detection of a defect and a defect identified as a systematic defect. do. In another embodiment, the method is based on inspection results generated during detection of defects, defects identified as systematic defects, and yield relevance of defects to determine the location on the wafer where a review, measurement, test, or some combination thereof is to be performed. Determining. In a further embodiment, the method determines a location on the wafer on which a review, measurement, test, or some combination thereof is to be performed, based on inspection results generated during detection of the defect, defects identified as systematic defects, and process window mapping. It includes a step.

In one embodiment, the method includes performing a systematic search using the results of the binning step and the user-assisted review. In another embodiment, the method includes, prior to the comparing step, separating the defects based on the functional blocks in which the defects are located to improve S / N at the result of the binning step.

In some embodiments, the design data is organized into hierarchical cells by design, and the method prior to the comparing step detects defects based on the hierarchical cell in which the defects are located to improve S / N at the result of the binning step. Separating. In another embodiment, the design data is organized into hierarchical cells by design, and if the defects can be located within one or more hierarchical cells, the method may be based on a region of the hierarchical cell, a defect location probability, or some combination thereof. Correlating defects to each layer cell based on the probability of being located within each layer cell.

In one embodiment, a defect is detected by an inspection process, the method comprising reviewing a location on a wafer where one or more POIs in the design data are printed, and reviewing whether a defect should have been detected at a location of one or more POIs. Determining based on the results and modifying the inspection process to improve one or more defect capture rates.

Each embodiment of the foregoing method may include any other step of any of the methods described herein. In addition, each embodiment taught may be performed by any of the systems described herein.

Another embodiment is directed to a computer-implemented method for assigning categories to defects detected on a wafer. The method includes comparing a portion of design data close to the location of a defect in the design data space to design data (eg, a POI design example) corresponding to a different DBC (eg, different DBC non-regulation). Design data corresponding to different DBCs and their different DBCs are stored in a data structure. The method also includes determining, based on the results of the comparing step, whether the design data in the portion is at least similar to the design data corresponding to the different DBCs. And assigning a defect to the DBC corresponding to the design data at least similar to the design data in the portion. The method also includes storing the result of the allocation step in a storage medium.

In one embodiment, the computer-implemented method is performed by an inspection system used to inspect for defects. In another embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect the defect.

In one embodiment, the method includes monitoring hot spots in the design data based on the results of the allocation step. In another embodiment, design data corresponding to different DBCs is identified by grouping the detected defects on one or more other wafers based on the portion of the design data that is close to the location of the detected defect on the one or more other wafers in the design data space. do.

In some embodiments, a defect is detected in an inspection process, the method comprising reviewing a location on the wafer where one or more POIs in the design data are printed, and based on the review result, the defects are detected at the location of one or more POIs. Determining whether it should have been, and altering the inspection process to improve defect capture.

In one embodiment, the method comprises determining whether the defect is a Nuson's defect based on a DBC assigned to the defect and from the results of the inspection process in which the defect was detected to increase the S / N of the results of the inspection process. Removing the slack defect.

In another embodiment, the method includes determining a KP value for one or more defects. In a further embodiment, the method includes determining whether a DBC assigned to a defect corresponds to a systematic defect visible to the review system, and selecting only the defect visible to the review system for review to sample the defect for review. Include. In a further embodiment, the method includes determining one or more POIs in the design data by identifying one or more features in the design data indicating pattern dependent defects.

In one embodiment, the DBC identifies one or more polygons in the design data where the defect is located or near the defect. In another embodiment, the DBC identifies the location of one or more polygons in the design data. In further embodiments, the data structure includes a library containing examples of design data organized by technology, process, or some combination thereof (eg, POI design examples for DBC bean definitions).

In some embodiments, the method includes separating design data near the location of the defect into design data in the area around the defect and design data in the area in which the defect is located. In another embodiment, the method includes monitoring over time a systematic defect, a potential systematic defect, or some combination thereof using the results of the assigning step. In a further embodiment, determining the KP value for the one or more DBCs based on one or more attributes of the design data corresponding to the DBC. The KP value may be determined based on one or more attributes of the electrical test data and design data corresponding to the DBC. In a further embodiment, the method includes determining a KP value for one or more defects based on one or more attributes of the design data corresponding to the DBC assigned to the one or more defects. In another embodiment, the method includes monitoring KP values for one or more DBCs and assigning KP values for DBCs assigned to the defects to the defects.

In one embodiment, the dimensions of at least some of the portions are different. In another embodiment, the design data in that portion includes design data for one or more design layers. In another embodiment, the method includes determining a location of a defect in the design data space by comparing the data obtained by the inspection system for the alignment site on the wafer with the data for the predetermined alignment site. In a further embodiment, the method includes determining a location of a defect in the design data by comparing the data acquired by the inspection system during detection of the defect to a location in the design data determined for review.

In one embodiment, the assigning step comprises assigning a defect to the DBC corresponding to the design data having at least one attribute that is at least similar to the design data in the portion and at least similar to at least one attribute of the design data in the portion. do. In one such embodiment, the one or more attributes include one or more attributes of the inspection for which a defect was detected, one or more parameters of the inspection, or some combination thereof.

In one embodiment, the design data close to the location of the defect includes design data where the defect is located. In another embodiment, the design data close to the location of the defect includes design data around the location of the defect. In a further embodiment, the method includes binning the defects assigned to one or more DBCs into groups such that the position of the defects in each group relative to the polygons in the portion of the design data close to the position of the defects is at least similar.

In one embodiment, the method includes selecting at least a portion of the defect for review based on the result of the assigning step. In another embodiment, the method includes generating a process for sampling a defect for review based on the result of the assigning step. In a further embodiment, the method includes modifying the process for inspecting the wafer based on the results of the allocating step. In some embodiments, the method includes changing the process for the inspection during the inspection based on the inspection result. In a further embodiment, the method includes changing the metrology process for the wafer based on the result of the assigning step. In another embodiment, the method includes changing the sampling plan for the metrology process for the wafer based on the results of the assigning step. The method may also include determining a location on the wafer on which the measurement, test, review, or some combination thereof is to be performed upon driving based on the result of the assigning step.

In another embodiment, the method includes prioritizing one or more DBCs and optimizing one or more processes to be performed on the wafer on which the design data will be printed based on the results of the prioritization steps. .

In one embodiment, the method includes determining the root cause of the defect based on the DBC assigned to the defect. In another embodiment, the method includes determining the root cause of at least a portion of the defect by mapping at least a portion of the defect to an experimental process window result. In a further embodiment, the method includes determining the root cause of at least a portion of the defect by mapping at least a portion of the defect to a simulated experimental process window result. In a further embodiment, the method includes determining a root cause corresponding to one or more DBCs and assigning a root cause to the defect based on the root cause corresponding to the DBC assigned to the defect.

In one embodiment, the method includes determining the percentage of die formed on a wafer that is affected by a defect to which one or more DBCs are assigned. In another embodiment, the method includes determining a POI in design data corresponding to at least one DBC, and determining a ratio of the number of defects assigned at least one DBC to the number of locations on the wafer. do.

In some embodiments, the method includes determining at least one POI in the design data corresponding to the at least one DBC, and determining the number of at least one defect assigned a DBC for the number of locations of the at least one POI in the design data. Determining the ratio. In another embodiment, the method includes determining a POI in design data corresponding to at least one DBC, determining a percentage of the die formed on the wafer where the defect to which the at least one DBC is assigned is located, and the percentage thereof. Assigning a priority to the POI based on the.

In one embodiment, the method includes one or more DBCs assigned to one or more by the number of design instances (e.g., POI design examples from DBC bin regulations) on a wafer (e.g., on the inspection area of the wafer) where a defect has been detected. Prioritizing the DBC. In another embodiment, the method comprises one or more DBCs by the number of design instances on the reticle (eg, on the inspection area of the reticle) used to print design data on a wafer on which at least one defect has been assigned at least one DBC. Prioritizing.

In another embodiment, the method includes a number of locations on the reticle (eg, on the inspection area of the reticle) where a defect assigned one or more DBCs is detected and a portion of design data close to the location of the defects assigned one or more DBCs. Determining a reticle-based margin for one or more DBCs based on the total number of portions of design data (eg, POI design examples from DBC bin specifications) printed on similar reticles.

In some embodiments, the method converts a portion of the design data close to the location of the defect into a first bitmap, which may be performed as described herein, before the comparing step, and before the comparing step. Converting the design data corresponding to the DBC into a second bitmap, which may be performed as described herein. In one such embodiment, the comparing step includes comparing the first bitmap and the second bitmap.

Each embodiment of the foregoing method may include any other step of any of the methods described herein. In addition, each embodiment of the method described above may be performed by any of the systems described herein.

Further embodiments relate to a method of modifying an inspection process for a wafer. The method includes reviewing a location on the wafer where one or more POIs in the design data are printed. The method also includes determining based on the results of the review step whether a defect should have been detected at the location of one or more POIs. The method also includes modifying the inspection process to improve one or more defect capture rates for defects located in at least a portion of one or more POIs.

In one embodiment, the changing step includes changing the optical mode of the inspection system used to perform the inspection process. In another embodiment, the changing step includes changing an optical mode of the inspection system used to perform the inspection process based on the result of the determining step. In a further embodiment, the modifying step includes modifying the inspecting process to suppress noise in the results of the inspecting process. In a further embodiment, the modifying step includes modifying the inspection process to reduce detection of defects of no interest. In yet another embodiment, the changing step includes changing the algorithm used in the inspection process. In yet another embodiment, the changing step includes changing one or more parameters of the algorithm used in the inspection process.

Each embodiment of the foregoing method may include any step of any of the methods described herein. In addition, each embodiment described above may be performed by any of the systems described herein.

Further embodiments relate to a system configured to display and analyze design and defect data. The system includes a user interface configured to display a design layout for a semiconductor device, inline inspection data acquired for a wafer on which at least a portion of the semiconductor device is formed, and electrical test data acquired for the wafer. The user interface may be configured to display modeled data for the semiconductor device and / or error analysis data for the wafer. The system also includes a processor configured to analyze the one or more design layouts, inline inspection data, and electrical test data upon receiving instructions from the user through a user interface. The processor may be configured to analyze the modeled data and / or error analysis data as described above.

In one embodiment, the electrical test data includes logic bitmap data. In another embodiment, the user interface is configured to display at least two overlays of design layout, inline inspection data and electrical test data, possibly in combination with any other data described herein. In one such embodiment, the electrical test data includes logic bitmap data. In some embodiments, the processor is configured to determine a defect density in the design data space upon receiving a command from the user to perform a defect density determination step through the user interface. In a further embodiment, it is configured to perform defect sampling for review upon receiving an instruction to perform a defect sampling step from the user via the user interface. In a further embodiment, upon receiving an instruction to perform a grouping step from the user via the user interface, the defects are configured to be grouped based on the similarity of the design layout close to the position of the defect in the design data space. Each embodiment of the system described herein may be further configured as described herein.

 Further embodiments relate to computer-implemented methods for determining the root cause of electrical defects detected on a wafer. The method includes determining a location of an electrical fault within a design data space. The method also includes determining if the location of the portion of the electrical defect defines a spatial signature corresponding to one or more process conditions. If the location of the portion of the electrical defect defines a spatial signature corresponding to one or more process conditions, the method includes identifying the root cause of the portion of the electrical defect as one or more process conditions. In this manner, the method includes performing a spatial signature analysis on the electrical test results. The method includes storing the result of the identifying step in a storage medium. Embodiments of the method described above may include any other steps described herein. Embodiments of the foregoing methods may be performed by any of the system embodiments described herein.

Yet another embodiment is directed to a computer-implemented method of selecting a defect detected on a wafer for review. The method includes identifying one or more regions of the wafer. One or more regions are associated with the location of one or more defect types (eg, possibly systematic defects) on the wafer. The method includes selecting a detected defect in only one or more areas for review. The method also includes storing the results of the selection step in a storage medium. Such method embodiments may include any other steps described herein. Such method embodiments may be performed by any of the system embodiments described herein.

There are a plurality of review use cases in which the method as described above may be used. For example, the method described above can be used for systematic defect validation from a list of potential systematic defects, which can be performed during maintenance of the search phase or the monitoring phase. In addition, the method described above is a known hot spot or location having a local pattern (i.e., local design data) similar to a known hot spot (which can be identified by any pattern search, which can be performed during a search step or recipe setup). Can be used to capture systematic defects. The method can be used to verify or classify a defect detected at or near a hot spot, which can be performed during monitoring.

The aforementioned region information is not only for sampling defects from specific regions, but also the probability of sampling defects from all regions of the wafer in some intelligent manner and / or finding or locating specific types of design-determined key regions from the design. It can be used to correct the key areas extracted into specific areas of this high wafer. While the key areas extracted from the design data may be for a single device, the probability of finding actual inspection defects due to the key areas may be more pronounced in certain wafer areas than in other areas. In this manner, the method may include extrapolating defect information from the die to the wafer using the area analysis described above. This embodiment may use any other information described herein.

Another embodiment is directed to a computer-implemented method for evaluating one or more yield related processes for design data. The method includes identifying potential errors in the design data using rule checking or any suitable step or method described herein. The method also includes determining one or more attributes of the potential error. The method also includes determining whether a potential error is detectable based on one or more attributes. The method includes determining, based on one or more attributes, which of the plurality of different inspection systems is best suited for detecting potential errors. The method also includes storing, on a storage medium, the result of determination of which of the plurality of different inspection systems is best suited for detecting potential errors.

In one embodiment, the method includes selecting one or more parameters of the inspection system determined to be most suitable. The parameter is selected based on one or more attributes. In this manner, the best inspection system type can be estimated or selected based on the nature of the defect of interest. In another embodiment, the method includes determining the effect of potential error on the yield of the device manufactured by the design data. Each of the foregoing method embodiments may include any other step of any of the methods described herein. In addition, each of the foregoing method embodiments may be performed by any system embodiment described herein.

Further embodiments relate to a carrier medium containing program instructions executable on a processor to perform any of the computer-implemented methods described above. Additional embodiments relate to systems configured to perform any of the computer-implemented methods described herein. The system may include a processor configured to execute computer instructions for performing one or more computer-implemented methods described herein. In one embodiment, the system may be an independent system. In other embodiments, the system may be part of or coupled to an inspection system, such as a wafer inspection system. In other embodiments, the system may be part of or coupled to a defect review system. In another embodiment, the system can be coupled to a fab database. The system may be coupled to the inspection system, review system, and / or fab database by transmission media such as wires, cables, wireless communication paths, and / or networks. The transmission medium may include a "wired" or "wireless" portion.

A method and system are provided for aligning inspection data with design data with sub-pixel accuracy (the size of a pixel can be as large as the size of the structure being inspected).

Additional advantages of the present invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiments and accompanying drawings.
1 is a flow diagram illustrating one embodiment of a computer implemented method for determining the location of inspection data within a design data space.
2 and 3 are schematic diagrams showing a top view of another embodiment of a given alignment site.
4 is a hierarchical diagram illustrating various embodiments of a computer implemented method for performing inter-wafer comparisons.
5 is a schematic diagram illustrating one embodiment of a computer implemented method for performing inter-wafer comparisons.
FIG. 6 is a schematic diagram illustrating a top view of one embodiment of inspection data acquired for a wafer surface region separated by an annular ring. FIG.
7 is a schematic diagram showing a top view of one embodiment of inspection data acquired for a wafer surface area divided into radial sectors.
8 is a schematic diagram illustrating another embodiment of a computer implemented method for performing inter-wafer comparisons.
9 is a schematic diagram illustrating a top view of one embodiment of a die array printed on a wafer.
10 is a schematic diagram illustrating a top view of one embodiment of inspection data acquired for a print die on a wafer separated into frames.
11 is a schematic diagram illustrating another embodiment of a computer implemented method for performing inter-wafer comparisons.
12 is a schematic diagram illustrating a top view of one embodiment of a scan path on a wafer and a die arrangement printed on the wafer.
Fig. 13 is a schematic diagram showing a top view of a continuous swath of inspection data acquired for a wafer.
14 is a top view of an alignment site selected by a computer-implemented method for determining the position of swath N + 1 relative to swath N using the continuous swath of inspection data acquired for the wafer and the data in the swath overlap region. Schematic diagram showing a diagram.
14A is a schematic diagram illustrating a top view of one embodiment of another swath of inspection data acquired for a wafer where the alignment sites are relatively spaced apart from the first inspection swath.
14B to 14D are schematic diagrams showing top views of various embodiments of different swaths of inspection data acquired for a wafer.
15 is a flowchart illustrating another embodiment of a computer-implemented method for determining the location of inspection data in a design data space.
16 is a schematic diagram illustrating a side view of various embodiments of a system configured to determine a location of inspection data within a design data space.
FIG. 17 is a schematic diagram illustrating one embodiment of a computer implemented method for binning detected defects on a wafer. FIG.
18 is a schematic diagram illustrating a top view of one embodiment of an array site on a wafer in three different dies, positioned on the wafer in a triangular array.
19 is a schematic diagram illustrating another embodiment of a computer implemented method for binning a defect detected on a wafer.
20 is a schematic diagram illustrating one embodiment of an input to and output from a module configured to perform a computer implemented method for binning a defect detected on a wafer in accordance with an embodiment described herein.
21 and 22 are schematic diagrams illustrating another embodiment of the output of the module of FIG. 20.
FIG. 23 is a schematic diagram illustrating one embodiment of input and output of the module of FIG. 20; FIG.
24 is a schematic diagram illustrating a top view of one embodiment of the output of the module of FIG. 20.
25 is a schematic diagram illustrating a side view of one embodiment of a system configured to display and analyze defect data and designs.
FIG. 26 is a schematic diagram illustrating a top view of one embodiment of one or more regions on a wafer associated with locations of one or more defect types on a wafer. FIG.
FIG. 27 is a flowchart illustrating one embodiment of a computer implemented method for evaluating one or more yield related processes for design data. FIG.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. The drawings may not be scaled. The drawings and detailed description, however, are not intended to limit the invention to the particular forms disclosed, and include all modifications, equivalents, and alternatives within the spirit and scope of the invention as defined by the appended claims. Intended to.

As used herein, the term “wafer” generally refers to a substrate formed of a semiconductor or non-semiconductor material. Examples of such semiconductor or non-semiconductor materials include, but are not limited to, single crystal silicon, gallium arsenide, and indium phosphide. Such substrates can typically be found and / or processed within a semiconductor manufacturing facility.

The wafer may include one or more layers formed on the substrate. For example, such layers may include, but are not limited to, resists, dielectric materials, and conductive materials. Various other types of such layers are known in the art, and the term wafer as used herein is intended to include wafers that include all types of such layers.

One or more layers formed on the wafer may or may not be patterned. For example, the wafer may include a plurality of dies each having repeatable pattern features. Formation and treatment of such layers of material can ultimately result in the finished device. Various other types of devices, such as integrated circuits (ICs), may be formed on a wafer, and the term wafer, as disclosed herein, is intended to include a wafer on which any type of device known in the art is formed. .

Although embodiments have been described herein with respect to a wafer, it should be understood that the embodiments may be used for other specimens, such as reticles, which may be commonly referred to as masks or photomasks. Many other types of reticles are known in the art, and the terms "reticle", "mask", and "photomask" disclosed herein are intended to include all types of reticles known in the art.

The term "design data" as used herein generally refers to data derived from a physical design through the physical design (layout) of the IC and through complex simulations or simple boolean operations. In addition, an image of the reticle acquired by the reticle inspection system and / or its derivatives may be used as "proxy" or "proxies" of design data. The reticle image or derivative thereof can serve as a substitute for the design layout in any embodiment disclosed herein using the design data.

For example, in one embodiment, the image of the reticle generated by the reticle inspection system is used as design data in the design data space. The reticle is used to print design data on the wafer. In this manner, an image of the reticle produced by the reticle inspection system can be used as a substitute for design data. The image of the reticle used in this embodiment may comprise any suitable reticle image generated in any suitable manner by any reticle inspection system known in the art. For example, the image of the reticle may be a high magnification optical or electron beam image of the reticle acquired by each of the high magnification optical reticle inspection system or the electron beam based reticle inspection system. Alternatively, the image of the reticle may be an aerial image of the reticle acquired by the aerial imaging reticle inspection system. The image of the reticle may be used as a proxy for design data in any of the embodiments described herein that use design data to perform one or more steps.

In a further embodiment, the method includes generating a context map for the design data in the design data space based on the reticle inspection data obtained for the reticle used to print the design data on the wafer. In this manner, the reticle inspection data can be included as input to the creation of the context map. The context map may be configured as described further herein (eg, the context map may include values for one or more attributes of design data across the design data space). The reticle inspection data used to generate the context map may include any suitable reticle inspection data known in the art, such as one or more of the reticle images described above. Thus, in this embodiment, the reticle inspection data can be used to determine values for one or more attributes of the design data printed on the reticle across the reticle, which values are mapped to the design data space to generate a context map. mapping). Determining a value for one or more attributes of the design data printed on the reticle may be performed as described herein or in any suitable manner. One or more attributes of the design data may include any of the attributes described herein. The mapping of values for one or more attributes from the reticle space to the design data space may be performed as further described herein. Such a context map may be used in any of the embodiments described herein, including using the context map to perform one or more steps. In addition, such a context map may be further generated as described herein and / or based on any other information described herein.

An image derived from the reticle image can serve as a "proxy" to the design data. For example, a reticle image generated by a reticle inspection system or any other suitable imaging system generates a simulated image that describes how a reticle image can be printed on a wafer, which can be used as a "proxy" to design data. It can be used to In one embodiment, a simulated image showing how the reticle image is printed on the wafer can be used as design data in the design data space. In this way, simulation of how the reticle image appears on the wafer surface can serve as a substitute for design data. The simulated image can be generated in any manner using any suitable method or system known in the art. The simulated image can be used as a proxy for design data in any of the embodiments disclosed herein that use the design data to perform one or more steps.

In embodiments described herein where design data is used at least partially to perform one or more steps, the design data may include any of the design data or design data proxies described above or any combination thereof.

In the drawings, it should be noted that the drawings are not drawn to scale. In particular, the scale of some of the elements in the figures is very exaggerated to emphasize the features of those elements. It should also be noted that the figures are not drawn to the same scale. Elements shown in more than one figure that may be similarly constructed are indicated using the same reference numerals.

1 illustrates one embodiment of a computer-implemented method for determining the location of inspection data in a design data space. It should be noted that not all steps shown in FIG. 1 are essential for the implementation of the method. One or more steps may be omitted from, or added to, the method shown in FIG. 1, and the method may still be practiced within the scope of this embodiment.

In general, the method may include a data preparation step, a recipe setup step (eg, wafer inspection recipe setup), and the wafer inspection step itself. The method may also include review and analysis steps. The data preparation step is from a data structure such as design data (e.g., graphic data stream (GDS) file, GDSII file, or other standard file or database) that reflects the physical design layout of the device being manufactured on the wafer or to be manufactured on the wafer. Obtaining or obtaining the obtained information). Information from a GDS file, other file, or database may describe the physical design layout pre-decoration (ie, optical proximity correction (OPC) feature and any other added to the design). Without resolution enhancement technology (RET) feature.

The method shown in FIG. 1 generally includes aligning the inspection data stream with the design data within sub-pixel precision as described further herein. In this manner, the method described herein may be generally referred to as a “align to design” method for inspection (eg, wafer inspection). The method utilizes design data and optionally context data for wafer inspection. In this manner, the method described herein may also be referred to as a "Context Based Inspection (CBI)" method. Device design data and context data can increase wafer inspection sensitivity, dramatically reduce nuisance event detection, increase defect classification precision, and improve application to inspection systems such as process window qualification (PWQ). Can be used for Context data can be used to provide benefits to defect review processes and systems as described further herein. Examples of how to use design data and context data are described in U.S. Patent 6,886,153 (Devis) and U.S. Patent Application Publication No. 2005/0004774 (Volk et al.), Filed January 6, 2005, No. 10 / 883,372, filed January 1, 2004, which is hereby incorporated by reference as if fully set forth herein. The methods described herein may include any step of any of the methods described in such patents and patent applications.

The method described herein may include a hot spot search step. Hot spot search may be performed during technical research and deployment, product design, RET design, reticle design and manufacturing, and product ramp. The hot spot search step may include identifying hot spots for reticle design enhancement and defect monitoring and classification. The hot spot search step may also include creating a data structure that includes information about the hot spot, such as a hot spot database. In some embodiments, hot spot search may be performed using multiple sources. For example, hot spot search is performed using the correlation between design space hot spot search, wafer space hot spot search, reticle hot spot search, test space hot spot search, and process space hot spot search. Can be. In one example, the search for hot spots may be performed by correlating multiple sources of design, modeling results, search results, metrology results, and test and error analysis (FA) results. Any of the steps described herein can be used in any combination to search for hot spots.

In the design space, hot spots can be identified using the results of a design rule check (DRC) to generate a list of critical points in the design data. DRC is typically performed for quality control (QC) of reticle layout data prior to mask fabrication (pre-mask). Thus, the DRC may not create a hot spot. Instead, the results of the DRC can be used to identify new margin hot spots that are in the design manual or that are newly discovered rather than part of the DRC rules. In addition, hot spots can be explored using electron design automation (EDA). In this manner, during the hot spot search phase, design rules (DRC used as marginality checkers) and / or EDA design tools may be used as the source of the hot spots. Hot spots can also be explored using techniques for computer aided design (TCAD) tools and proxies. The TCAD tool is commercially available from Synopsis, Inc. of Mountain View, California. In addition, (or alternatively), design scan analysis software, any pattern search, and design context (eg, function blocks, design library elements) commercially available from KLA-Tencor, San Jose, CA , Cell, pattern or not, pattern density, dummy / fill versus activity, etc. can be used as the source of the hot spot. In another example, design data based grouping of defects (with or without pareto analysis) can be used to search for and group hot spots, which can be performed as described herein.

In a further example, in the design space, the hot spot search step includes aligning or overlaying a scanning electron microscope (SEM) image of the design data printed on the wafer with the design data to identify actual defect locations within the design data space. (Which may be performed as described herein), and any pattern search based on design data proximate the location of a defect in the design data space may be performed to identify similar possible hot spots in the design. . A repeater analysis performed on the original test results for the wafer, which can then be performed as described herein, can be used to identify systematic defects and their design groups in the design data. One advantage of this approach is that when target defects are positioned substantially precisely within the design data space, the pattern search window used for arbitrary pattern search and / or systematic defect identification can be adjusted per defect.

In wafer space, hot spots can each be performed as further described herein, repeater analysis, zonal / spatial signature analysis of systematic (eg process margin) defects, and transient signature analysis of systematic defects. As a property of stacked die (or reticle) results by design overlay to improve the signal-to-noise ratio (S / N) for searching within the reticle / die space, and defects to prioritize systematic or group of systematic defects. It can be searched using one or more of the yields (or kill probabilities) correlated to the defect space.

In reticle / die spaces, hot spots are applied to repeater analysis, defect density mapping, design pattern based grouping analysis, and design contexts (eg, functional blocks) to improve S / N, which can be performed as further described herein. Filtering by, reticle inspection to search for cold spots in the design can be searched using one or more of the identification of defects of interest.

In the test space, hot spots can be searched using one or more of the bit failure to design the mapping and the logic bitmap density to design the mapping, both of which are of interest (or in design). Combined with repeater analysis (perform in wafer space) or design data based grouping (perform in reticle / die space) to identify cold spots). Each of these steps may be performed as further described herein.

In the process space, the hot spot is a PWQ (using a die-die, standard reference die, or die-database method) as the source of the hot spot, and the DOE (design of the process) for determining critical design features and process windows as the hot spot. of experiments (using a die-die, standard reference die, or die-database method), each of which may be performed as further described herein.

In some embodiments, as shown in step 10 of FIG. 1, the method includes selecting a predetermined alignment site in the design data. The predetermined alignment site selection step may be performed using a inspection system. The desired alignment site can be selected during setup of the inspection process recipe. A "recipe" is generally defined as a set of instructions for performing a process such as an inspection. As described herein, recipe setup for wafer inspection can be performed automatically, semi-automatically (eg, user-assisted), or manually.

In one example, during the setup of the inspection process performed by the inspection system, in addition to the design data, inspection system parameters such as wafer swasing information, inspection system model number, optical mode to be used for inspection, and pixel size Information about the variable can be used to select a given alignment site. The desired alignment site can be selected based on one or more attributes of the wafer to be inspected. The data for a given alignment site (or marker that refers to this data) and / or its image may be stored in a recipe for the inspection process. For example, information about a given alignment site for a layer on a wafer may be stored as alignment data in an inspection process recipe for a layer on a wafer, which alignment data is used when the inspection system inspects a wafer of this particular device and layer. It can be used every time.

Although some embodiments include a "wafer scanning step" for acquiring data and / or images for a wafer, such data and / or images may be obtained using any suitable technique and / or system known in the art. You must understand that you can. For example, data and / or images for the wafer may be acquired by the inspection system described herein or other inspection system configured to perform field-specific image acquisition. In this manner, instead of scanning across the wafer, the inspection system may acquire data and / or images in a stepping manner. In another example, data and / or images for a wafer may be acquired by an inspection system described herein or another inspection system configured to perform point-to-point inspection, commonly referred to as automated process inspection (API).

Several methods can be used to select a given alignment site. In one embodiment, the method includes acquiring design data corresponding to a given alignment site. Data or images for a given alignment site that can be used in the methods described herein include a rendered GDS clip (the term "clip" as used herein refers to a relatively small portion of the design layout) and a rendered GDS. Contains an image generated by the inspection system aligned to the clip. Simulating (or "rendering") design data corresponding to a given alignment site may be used to generate an image that describes how the design data is printed on the wafer. The method includes performing cross-correlation of the simulated ("rendered") image with the design data or GDS clip, and recording the location of the simulated image in the design data space (ie, in coordinates in the design data space). It includes a step. Image simulations describing how design data corresponding to a given alignment site will be printed on a wafer as described above are known in the art such as any suitable method, algorithm, or PROLITH commercially available from KLA-Tencor. Can be done using built-in software.

In addition, after one or more processes have been performed on the wafer, a simulated image can be generated as described above that describes how a given alignment site will be printed on the wafer. One or more processes may include, for example, a combination of lithography, lithography and etch, other lithography processes, and the like. In this manner, the data for a given alignment site used in the methods described herein may include one or more simulated images that are selected or generated based on one or more processes performed on the wafer prior to inspection. Using different data for a given alignment site for alignment of inspection data obtained after another process has been performed on the wafer may increase the precision of the method described herein.

Selecting a given alignment site may include pre-processing the design data (eg, GDS data) to select a given alignment site that is compatible with the inspection process and system. For example, in some examples, the rendered GDS clip is data for a given alignment site in the method described herein, since the GDS clip is not affected by variations (eg, color variations) caused by the wafer fabrication process. There is an advantage to using it as. However, an image of a given alignment site acquired by the inspection system, aligned with respect to the rendered GDS clip "off-line", is an image of the alignment site on the wafer generated by the inspection system rather than the GDS clip from which the image was rendered. It may be advantageous to use with inspection data generated at a later stage of device fabrication, as it may be more similar to and thereby provide more precise alignment. Thus, in some embodiments, the alignment data used in the methods described herein is associated with the GDS clip and its GDS clip to ensure that a suitable match to the data for the alignment site on the wafer can be found during the test run. It can include both aligned images. Alternatively, one or more attributes of a given alignment site in the design data, such as the center of the given alignment site, may be determined, and the corresponding center of the image of the alignment site acquired by the inspection system may cause the inspection pixel data to be transferred to the design data. Can be determined and used to align.

The number of predetermined alignment sites selected per die can vary greatly. For example, a relatively sparse set of predetermined alignment sites may be selected. In addition, a given alignment site may be selected at any frequency across the die. Since a given alignment site may be included in the die itself, the given alignment site may be selected to include device features within the die and / or features located within the device area of the die. In this manner, a given alignment site may be selected to include pre-existing features of the design data. Such certain alignment sites are advantageous because the design data need not be modified to include the alignment features and the alignment features do not increase the size of the die.

The method may also include selecting a predetermined alignment site in the design data that can be uniquely identified within the data or image acquired by the inspection system (within some non-alignment tolerance window). For example, a given alignment site may be selected to include unique alignment features (ie, targets) within a given search range uncertainty. In this manner, given a particular positional uncertainty of the position of the alignment site on the wafer, the image or data is corrected to identify a relatively strong match of the two alignment sites without any ambiguity. This can be done.

In one embodiment, a given alignment site includes at least one alignment feature having one or more attributes unique in the x and y directions. One embodiment of such a given alignment site is shown in FIG. 2. As shown in FIG. 2, a given alignment site 32 includes an alignment feature 34. Alignment feature 34 has one or more attributes that are unique in the x and y directions. For example, the corners of the alignment features give unique alignment features in the x and y directions relative to other features in the die, and approximate the alignment features. Certain alignment sites may also include one or more such alignment features, which may be configured similarly or differently. In this way, the alignment feature may be unique in the x and y directions.

In an alternate embodiment, a given alignment site includes at least two alignment features. The first of the two alignment features has one or more attributes unique in the x direction. The second of the two alignment features has one or more attributes unique in the y direction. An embodiment of such a given alignment site is shown in FIG. As shown in FIG. 2, a given alignment site 32 includes an alignment feature 38. Alignment feature 38 has one or more attributes that are specific to the x direction but do not provide information about alignment in the y direction. For example, the vertical edges of the alignment features 38 can impart unique alignment features in the x direction relative to other features in the die, and can approximate the alignment features. Certain alignment sites may include one or more such features.

The given alignment site 36 includes an alignment feature 40. Alignment feature 40 has one or more attributes that are specific to the y direction but do not provide alignment information in the x direction. For example, the horizontal edge of the alignment features 40 can give unique alignment features in the y direction relative to other features in the die, and can approximate the alignment features. Certain alignment sites may also include one or more such features. In addition, a given alignment site may include two or more alignment features specific to the x and / or y directions. In this manner, a given alignment site may determine an absolute (x, y) offset between a “live” image or data (eg, an image or data acquired by the inspection system during inspection) and data for a given alignment site. To determine, it may be selected to include a set of alignment features, such as features 38 and 40 that in combination provide sufficient x and y alignment information.

The selection of a given alignment site can be performed manually, automatically, or any combination of both (ie, semi-automatic or user-assisted). Whether performed manually, automatically, or both, the desired alignment site selection can be performed using design data, optical or electron beam images of the wafer, or both. In the user-assisted selection of a given alignment site, the user may use a computer aided design (CAD) layout, a live or stored optical or electron beam image of the wafer, or to determine one or more predetermined alignment sites that meet the aforementioned specific criteria, or You can check both sides.

In the automatic or semi-automatic selection of a given alignment site, the method uses an inspection system to scan a row of die on the wafer and process each frame of the die to identify a unique alignment site (eg, By algorithm execution). The term "frame" is generally defined herein as data or an image for a portion of a die within a swath of inspection data or an image acquired during scanning of a wafer. Processing the frame includes determining an x and y gradient of features within the frame and selecting one or more features having a relatively strong gradient in the x and / or y direction for use with a given alignment site. do. The method includes performing a cross-correlation of a frame and a patch image containing such features to determine if only one relatively strong peak of the gradient is within a given search range. In this manner, unique alignment features within the pattern search window can be identified and selected for a given alignment site. The method includes accessing design data, assigning one or more relatively small areas of design data as one or more images, and performing the aforementioned steps to identify suitable alignment sites. The method includes displaying one or more potential alignment sites (eg, optical or electron beam and CAD image pairs for the potential alignment sites) identified by the method, and distributed over a die at a predetermined minimum spacing distance. Allowing the user to select the above suitable alignment site.

In another embodiment, the imaging mode of the inspection system or other image acquisition system used to select a given alignment site is different from the imaging mode of the inspection system used to acquire inspection data. In this manner, the method may include using another imaging mode for alignment site selection and wafer inspection. The alignment site selection step can be performed based on various imaging modes that can be used to inspect the wafer. For example, the inspection system may include a bright field (BF) mode, a dark field (DF) mode, an edge contrast (trademark of KLA-Tencor) mode, various aperture modes, and / or an electron beam imaging mode. It may be configured to use the same one or more inspection optical imaging mode. Edge contrast (EC) inspection is generally performed using circular symmetrical illumination apertures with complementary imaging apertures. The best imaging mode for inspection of a particular layer on the wafer is the imaging mode that maximizes the defect S / N, and the best imaging mode may vary depending on the layer type. In addition, the inspection system may be configured to inspect the wafer using one or more imaging modes simultaneously or sequentially. Since the alignment site image or data acquisition performed during wafer inspection uses the best imaging mode for wafer inspection, the alignment site selection preferably uses that mode to select appropriate alignment sites and alignment features.

However, in order to precisely determine the location of the selected predetermined alignment site in the design data space, the optical patch image of the predetermined alignment site (on the wafer) is aligned with the simulated image derived from the GDSII clip or design data as described above. Can be. Acquiring a simulated image with a quality suitable for the alignment of the optical and simulated images can be difficult for all imaging modes. However, the best match of the simulated image and the optical image can be obtained for a particular imaging mode (eg, BF mode). Thus, the method may also include scanning the wafer using the best imaging mode for inspection to select a suitable desired alignment site. The method involves revisiting a selected predetermined alignment site on a wafer using an inspection system to obtain an optical patch image using a mode that provides a simulated image or an image that best matches a GDSII clip. It may also include.

Images acquired using the best mode to match a simulated image or GDSII clip can be aligned to the simulated image or GDSII clip for the corresponding alignment site in the design data. By using the (x, y) position of the selected alignment site in the design data space determined by aligning the acquired image with the simulated image or GDSII clip using the best mode for the match, such x and y positions are best for inspection Lt; / RTI > may be associated with the acquired patch image using the mode of FIG. If there are some fixed offsets between the images collected for the same site in different modes (check mode and best mode for matching simulated images or GDSII clips), these offsets may be corrected using a suitable calibration target. Measurements and / or modifications may be made at the beginning (or after) of the examination.

In one such embodiment, the method includes a CAD to an optical or electron beam image of a given alignment site to determine the mapping (ie, to determine the location of individual pixels of the optical or electron beam image within the design data space). It may include off-line alignment of the simulated image or GDSII clip. For example, after selecting the predetermined alignment sites and acquiring images of these sites on the wafer using an imaging mode that can provide the best image for matching the simulated image, the design data corresponding to the predetermined alignment sites Can be obtained (in any format such as a polygonal representation) and then given as a simulated image of the appropriate pixel size using the appropriate transform function. Optical (or electron beam) images and simulated images can be aligned with each other using any suitable method and / or algorithm known in the art. Aligning the optical (or electron beam) image and the simulated image to each other may be a source of noise in the optical image, such that the previous layer structure may be removed from the optical image or otherwise considered to achieve sufficiently precise alignment. This may be done using other information about the design data, such as the previous layer structure (eg, in the design database).

The result of the process of setting up the recipe for inspection is one or more optical or electron beam patch images representing the desired alignment site, each position (eg, x and y coordinates) of the given alignment site in the design data space, and subsequent wafers. It can include any additional information that can be utilized by the inspection system to perform substantially precise alignment during the inspection.

As shown in step 12 of FIG. 1, the method includes aligning data acquired by the inspection system with respect to alignment sites on the wafer with data for a given alignment site. The data for a given alignment site may include any of the data described above. For example, the data for a given alignment site may include design data stored in a data structure such as a GDSII file or other standard device-readable file format. In another embodiment, the data for a given alignment site includes one or more simulated images that describe how the given alignment site will be printed on the wafer. One or more simulated images are mapped to a design data space as described further herein, such that the position of the alignment site on the wafer within the design data space is further described herein based on the position of the predetermined alignment site within the design data space. As can be determined.

In a further embodiment, the data for a given alignment site includes one or more attributes of the given alignment site, the data for the alignment site on the wafer includes one or more attributes of the alignment site, and the alignment step includes the predetermined alignment site. Sorting at least one attribute of the at least one attribute of the sorting site. The alignment site on the wafer used in this embodiment, and one or more attributes of the given alignment site may include any of the attributes described herein. For example, in one embodiment, one or more attributes of a given alignment site include the center of the given alignment site and one or more attributes of the alignment site on the wafer include the center of the alignment site. The center of the alignment site and the desired alignment site on the wafer may be the center of one or more alignment features within the site. In this manner, the method may include matching the center of the alignment site with the alignment site on the wafer to align the alignment site on the wafer with the alignment site. As such, the data for a given alignment site may include some features of the given alignment site, such as a center, which may be aligned to the corresponding feature of the data for the alignment site on the wafer. One or more attributes, such as the alignment site on the wafer and the center of a given alignment site, can be determined in any manner known in the art or as described herein.

In further embodiments, the data for a given alignment site includes data obtained by an inspection system aligned to design data stored in a data structure such as a GDSII file. The data obtained by the inspection system for a given alignment site can be aligned to the design as described herein. In some embodiments, the data for a given alignment site includes at least a portion of a standard reference die image aligned to design coordinates in the design data space. The standard reference die image may include any standard reference die image described herein, and the standard reference die image may be aligned to the design coordinates as described herein. For example, a standard reference die image can be mapped to the design space and then used for alignment.

Aligning the data for the alignment site to the data for the given alignment site may be performed using any suitable alignment method and / or alignment algorithm known in the art.

In one embodiment, step 12 may be performed during wafer inspection. This step can also be performed each time a wafer is inspected using an inspection process recipe. For example, it may include an initialization step that may be performed at the start of multiple wafer inspections and at the start of inspection of each wafer in a lot. During the initialization phase, the (x, y or two-dimensional) mapping of the given alignment site and the given alignment site in the design data space can be connected from the recipe setup result and obtained by the inspection system for the wafer being inspected. The patch image can be downloaded to an image computer processing node that can be used to perform alignment of the stored alignment patch image. The image computer and processing node may have any suitable configuration known in the art.

During the inspection process, the method may include scanning the wafer using an inspection system to obtain a swath of inspection data. Each swath can be obtained as a pixel stream of some height H (in the y direction) when the inspection system scans (in the x direction) across the die in columns or rows on the wafer. Each processing node in the image computer can process a portion of the swath. For example, a swath can be divided into portions or " pages ", and each portion of the swath can be directed to a different processing node. The processing node may be configured to perform defect detection using pixels in the portion of the swath received by the processing node. The method and image computer may use information regarding the location of the alignment site on the wafer (eg, location within each die) and the patch image (eg, downloaded during the initialization phase) of a given alignment site obtained from an image computer storage medium. Certain alignment sites may be aligned with live stream data for alignment sites on a wafer.

In some embodiments, a context map (eg, stored in a data structure such as a database) may be connected and downloaded to the processing node. Such context data may be stored in any suitable format known in the art. Such context data may be stored and / or used in a compact polygonal format rather than an image format. However, a context map can be assigned to an image so that the context map can be used for defect detection purposes. This grant may be performed once during initialization or whenever the context map is used during inspection. The advantage of the former approach is that giving a context map during initialization reduces the data processing cycles performed during the inspection process. However, a disadvantage of this approach is that storing a given image of the entire context map can require a relatively large amount of memory.

As shown in step 14 of FIG. 1, the method includes determining an alignment position on the wafer in the design data space based on the position of the predetermined alignment site in the design data space. For example, the (x, y) position of a given alignment site relative to the design data coordinates (ie, within the design data space) is determined, and because the data for the given alignment site is aligned to the data for the alignment site, The absolute position of the live pixel coordinates of the alignment site can be determined within the design data space. In another embodiment, determining the location of the alignment site on the wafer within the design data space may align the raw data stream (eg, live image) to the data (eg, reference image) for a given alignment site. It may include the step of. Determining the position of the alignment site on the wafer within the design data space may be performed prior to inspection of the wafer or after acquisition of inspection data for the wafer.

As shown in step 16 of FIG. 1, the method includes determining the position of inspection data acquired for the wafer by the inspection system in the design data space based on the alignment position on the wafer in the design data space. Inspection data for the location at which the design data is determined may include any data (eg, image data) acquired for the wafer by the inspection system during inspection. For example, the location of the inspection data can be determined for some or all of the data acquired by the inspection system during inspection of the wafer. For example, the position of the inspection data can be determined only for the inspection data acquired for the attention area on the wafer.

In one embodiment, after aligning the position of the new data stream corresponding to the alignment site on the wafer to the reference image of the predetermined alignment site as described above, the method sub-coordinates the coordinate offset between the inspection data stream and the design data. And measuring within pixel precision. In addition, the coordinate error between the live inspection data and the design data is such that the new inspection data image is a reference image for the given alignment site such that the alignment site on the wafer is aligned substantially exactly to the desired alignment site for all points across the die. By moving relative to. One significant advantage of the methods and systems described herein is that the location of inspection data within the design data space can be determined with sub-pixel precision. In this manner, the protective and non-cautionary areas on the wafer can be determined with a relatively high precision of less than 100 nm accuracy, as further described herein.

In another embodiment, data for a given alignment site may be used to determine a two-dimensional mapping transformation that may be used to map the live image pixel space to the design data space. For example, as described above, the method correlates the downloaded predetermined alignment site patch image (obtained during setup of the inspection process) with the live image data over a predetermined range, and between the downloaded image and the live image. Determining the offset of may include. The method further comprises using the offset to determine the correspondence between the live image pixel position and the design data coordinates, since the (x, y) position of a given alignment site in the design data space is determined during setup. It may include. The method may include determining a two-dimensional function for mapping the live pixel coordinate space to the design data space using the correspondence between the live image pixel location and the design data coordinates.

In one such example, by using a suitable polynomial fit of a grid of alignment sites for absolute coordinates in a design data space, it may be used to map any pixel in the inspection data (eg, a live pixel stream) to a corresponding location in the design data space. You can determine the mapping function. In a similar manner, any pixel in the inspection data can be mapped to its corresponding location in the context space as described below. Several other corrections can be used to provide a substantially accurate mapping. For example, the correction may be performed based on stage correction data and data provided by the inspection system, such as pixel size in the x direction that may be obtained by the runtime alignment subsystem (RTA) of the inspection system. . Mapping can be used for die-die inspection mode. The mapping of the live pixel stream as described above may be performed in real time during inspection of the wafer, or after acquisition of inspection data for the wafer. In this manner, positioning of inspection data within the design data space can be performed during inspection of the wafer. Alternatively, positioning of the inspection data in the design data space may be performed subsequent to inspection of the wafer.

The location of the inspection data in the design data space can be stored and used in any of the ways described herein.

In one embodiment, the method includes detecting defects on the wafer using inspection data and a standard reference die for standard reference die based inspection. In this manner, an embodiment of the method described herein may include performing a standard reference die based inspection. In some such embodiments, the method may include applying a mapping of a standard reference die image within the design data space to a live image acquired by the inspection system for the wafer in the standard reference die-die inspection mode. The term “standard reference die” refers to a reference die that is generally inspected but does not meet the usual adjacent constraints on the “test” die obtained for die-die inspection. Some commercially available inspection systems are configured to use some version of the standard reference die-die inspection mode. One implementation of the standard reference die-die inspection mode includes comparing one die to any die in a die string. In another implementation, the standard reference die image may be a stored image. Thus, the stored standard reference die-die inspection mode is similar to the standard reference die-die inspection mode, except that constraints using the reference die on the wafer are removed. One advantage of this inspection mode is that the stored reference die image can be modified to produce a "substantially defect free" standard reference die image. This inspection mode also makes it possible to use standard reference die images from other wafers, thereby enabling the simplest implementation of iPWQ applications, which is described further herein.

In one embodiment that can be used in the standard reference die-die inspection mode, the live image acquired for the die being inspected is aligned to and compared with the stored die image obtained from a known good die (standard reference die) on another wafer. . Such alignment and comparison can be performed as described herein. In this case, the mapping of the standard reference die pixels to the design data coordinate space can be done completely offline. For example, alignment sites in the standard reference die can be mapped in the design data space as described above, and the mapped standard reference die pixels can be stored offline during inspection and fed to the inspection system. In this manner, for the standard reference die-die inspection mode, the positioning of live inspection data within the design data coordinate space may be performed by aligning the live data with the standard reference die image or data mapped to itself in the design space.

In another embodiment, for standard reference die-die inspection, the known good die on the reference wafer is scanned in the selected pixel size and imaging mode, and the entire known good die image may be stored on an appropriate storage medium (eg, disk). . During inspection of the wafer, the swath of the appropriate standard reference die image is downloaded to the inspection system image computer, and as each die is scanned, the frame of the target die (ie, the die being inspected) is aligned with the corresponding standard reference die frame. do. Misalignment between frames can be corrected using interpolation of sub-pixels. The standard reference die image can then be compared with the image of the wafer to detect defects on the wafer (ie, to detect defective pixels). In this way, the same image can be used to align the inspection data to design data space coordinates and for defect detection.

In another embodiment, the method includes aligning alignment data for alignment sites on the wafer in the inspection data stream with GDS clips rendered for a given alignment site to correct errors in real time. For example, the method may include applying a mapping of the rendered GDSII clip in the design data space to data for alignment sites on the wafer for the die-die inspection mode. The method may include correlating live image data and downloaded alignment site patch images (selected during setup of the inspection process) over a predetermined search range. In another example, the step of aligning data for an alignment site on the wafer in the inspection data stream with data for a given alignment site may be performed as described further herein, center of one or more features in the alignment site. Or by sorting other attributes.

In one embodiment, for defect detection in die-die inspection mode, each scanned die frame is aligned with data for subsequent die frames in the swath. In this case, the mapping of a given alignment site to the alignment site on the wafer may not be performed offline because the location of the data for each die in the inspection data stream is at the mechanical error source and other error sources of the inspection system. . Thus, in this case, the method may include identifying an alignment site in each die during acquisition of inspection data (eg, using an image computer).

In another embodiment, defect detection may be performed in an inter-wafer inspection mode. In one such embodiment, data for alignment sites on one wafer may be aligned with data for an alignment site, and data for alignment sites on such wafers may be aligned with data for alignment sites on another wafer. . Alternatively, data for alignment sites on both wafers may be aligned with data for a given alignment site, including any of the data described herein. In this manner, after the data for the alignment sites on the wafer are aligned with the data for the given alignment sites, the inspection data for the wafers can be effectively aligned with each other and can be superimposed or compared for defect detection. In some embodiments, the inter-wafer inspection mode includes using a reference die that is external to the wafer being inspected (ie, off wafer reference). Since implementation of this method involves separating the currently used runtime feedback concept such that the inspection system can achieve die-to-die level overlay tolerances (eg, 0.1 pixels) to achieve adequate sensitivity results. There is never easy.

In one such embodiment, the method includes an RTA on an off-wafer reference image of the wafer being inspected. RTA to off-wafer images is a scanning inspection technique from wafer "self-referencing" approach such as die-die comparison and cell-cell comparison to inter-wafer inspection to detect defects on patterned wafers. An image alignment approach that can be used to enable extension of the. For example, the RTA may include electro-mechanically aligning the previously acquired image and the acquired live image to obtain sub-pixel precision positioning prior to digitizing the signal generated by one or more detectors of the inspection system. have. Examples of how RTA can be performed in the embodiments described herein are disclosed in US Pat. No. 7,061,625 to Hwang et al, which is incorporated herein by reference in its entirety.

One currently available approach that includes comparing the wafer image with the off-wafer image is the die-database inspection mode (NGR) used by Japan's "Nanogeometric Research". The die-database inspection approach involves "step and iterative" image acquisition and stitching followed by a complex series of edge-based image processing, process simulation, and detection algorithm steps. However, this method cannot be used to directly compare images of different wafers. In particular, the die-database inspection mode compares the wafer image with simulated criteria derived from the design layout database. The simulation steps of this approach must be carefully calibrated according to the specific manufacturing process used to fabricate the wafer under test. This calibration is an expensive and time consuming process. The correction is particularly complicated for multi-step integrated process flows. In addition, the "step and repeat" image acquisition inspection process is typically slower than the scanning based inspection process due to the practical limitations of stage inertia, stage vibration, static image acquisition, image stitching, and the like.

An alternative die-database inspection mode is a logical extension of the inspection mode using the "off-wafer" reference die described above. In this case, a "database" is a rendered image generated from design data and process simulation as described above. Thus, a "standard reference die" generated from an image (possibly a statistical augmentation that can be performed as described herein) from which wafer-to-wafer inspection has been obtained, and a "standard reference die generated mainly from design data and process modeling. Database-based checking can be considered as a logical extension of the "off-wafer" reference checking mode. Emphasizing the use of standard reference dies generated from design data and process modeling is the most complex wafer inspection mode to implement. Several attempts have been made to implement this inspection mode, but due to the computational intensity (modeling and detection), image acquisition speed, and image quality challenges of such applications, the current performance of the attempted implementation is not suitable. However, the method described herein is more practical because conventional absolute criteria (eg, design data) can be used to align the off-wafer criteria with inspection data for the wafer under test.

Thus, the methods described herein can be used to enable comparison of wafers to each other, which is a potentially very useful application. One motivation for defect inspection using wafer-wafer comparison is to search for "systematic defect mechanisms" that can result from the cumulative tolerances of the wafer fabrication process and the interaction of specific circuit layouts. This search process may include comparing wafers that have the same device design printed thereon but are processed differently. The most critical approach is to modularize process parameters in single or multivariate experiments (eg, using a systematic DOE approach). In one embodiment, the wafer and additional wafers (eg, two or more wafers) are processed using wafer level process parameter adjustments, which can be done as described above or in any other suitable manner. Process parameters can be adjusted to allow the measurable physical and / or electrical properties of the resulting wafer to approach its acceptable limits. The method may also include detecting defects on the wafer and additional wafers by comparing inspection data for the wafer and die on the additional wafer to conventional standard reference dies. Defect detection on the wafer in this manner can be performed as further described herein. In one such embodiment, the method may include determining whether structural differences occur between the wafers, as measured by detection of "defects." Such an approach may be referred to as an integrated PWQ (iPWQ). In this manner, the method described herein can be used to enable the implementation of iPWQ (eg, using a standard reference die approach to iPWQ). As such, the PWQ methodology may be extended to include comparison of die on other wafers with conventional standard reference dies and wafer level process parameter adjustments for the purpose of implementing the iPWQ methodology.

In contrast, the search for lithography induced “systemic defect mechanisms” is a method disclosed in US Pat. No. 6,902,855 (Peterson et al), incorporated herein by reference in its entirety and commercially available from KLA-Tencor. This can be done using PWQ products. PWQ influences the lithography tool's unique ability to adjust lithography exposure process variables at the reticle shot level using focus and exposure as variables to determine design-lithography interactions. Such applications are often used for OPC verification. However, the PWQ is limited to a direct comparison of the die on the printed wafer with the adjusted focus and / or exposure parameters. The influence of other process variables associated with process steps, such as etch, deposition, heat treatment, chemical-mechanical polishing (CMP), and the like, cannot be evaluated directly because these variables can only be adjusted at the wafer level. However, systematic defect mechanisms associated with or caused by these process variables cannot be explored using the methods described herein. In particular, the method described herein can be used to examine non-lithography process coordination in PWQ type applications by wafer-wafer comparison.

In scanning-based defect detection systems, die-die image subtraction is performed by "sub-pixel" image alignment to reduce differential image registration noise to enable better detection of defects. can do. Defects can be identified by detecting pixels in the differential image that exceed one or more thresholds. The scanning based image acquisition process includes a feedback mechanism, often referred to as RTA. This mechanism precisely aligns the image being acquired with the image often acquired from the same wafer prior to the current image. Depending on the configuration of the inspection system, the feedback mechanism may include a combination of an opto-mechanical approach, an electro-mechanical approach, and an electronic / algorithm approach.

In one embodiment, the method described herein includes an RTA that uses a stored image as a reference rather than an image acquired for a wafer under test. The stored image may be an “standard reference wafer” or an image of the reference wafer. Each die on the wafer under test can be compared to the corresponding die on a standard reference wafer. Although the embodiments described herein include comparison of two wafers or images of wafers, the embodiments can include comparing any data obtained by inspection of two or more wafers.

4 illustrates various embodiments of a computer implemented method for performing a wafer-wafer comparison. The steps shown in FIG. 4 are not essential to performing the method. One or more steps may be omitted from the method shown in FIG. 4, which may still be implemented within the scope of this embodiment.

As shown in step 220, the method includes a wafer-wafer comparison. In one embodiment, wafer-wafer comparison includes comparing a reference wafer image with a test wafer image as shown in step 222. For example, the reference wafer image used in the method described herein may be a stored image of the entire reference wafer. Comparison of the reference wafer image and the test wafer image can be performed as described herein. Alternatively, as shown in step 224, the wafer-wafer comparison may include comparing a standard reference die image with an image of all dies on a wafer (eg, reference or test wafer).

In one embodiment, the method detects defects on a wafer using a representation of wafer noise associated with inspection data, standard reference die, and standard reference die in a perturbation matrix for standard reference die based inspection. It includes a step. In this manner, the method may include using a relatively compact representation of wafer noise associated with a standard reference die in the form of a perturbation matrix. For example, an image of the reference die on the reference wafer can be stored in addition to the perturbation matrix, or other suitable data structure showing how the die pixels change from die to die on the reference wafer. Storing an image of the reference die in addition to the perturbation matrix instead of the entire reference wafer image allows a more compact representation of the reference wafer to be stored. In this manner, a perturbation matrix can be included in the representation of the reference wafer to reduce the reference wafer image size to a level that can be implemented in a practical and acceptable manner. As such, the method may include a standard reference die based inspection that includes using a perturbation matrix representation of the noise signature.

Generating the reference wafer image and the corresponding perturbation matrix may include standard reference die based inspection using standard reference die obtained from the reference wafer (ie, a kind of self reference). A single standard reference die image on the reference wafer is driven to reduce any effects of RTA performance on sensitivity, as well as baseline images perturbed with compressed differential data stored for each die on the reference wafer. Can be used as an RTA standard. Stored differential data can be reduced through a compression algorithm, as well as a limitation on the total attention region size per die swath. In operation, a perturbation matrix of differential image data can be loaded for the entire reference wafer with swaths for each corresponding standard reference die swath loaded. The perturbation matrix data volume for the entire wafer may be on the order of about 1 Gb to about 3 Gb, and the data volume for the standard reference die may be on the order of 1 Gb. All other methods described herein, including standard reference die comparisons, can use the perturbation matrix as described above.

The perturbation matrix is defined as P ₁ (x, y), D _x (1, 2), D _y (1, 2) Diff _{1 , 2} (x, y) when there are m dies in a column; P ₂ (x, y), D _x (2, 3), D _y (2, 3) Diff _{2 , 3} (x, y); ... P _{m -1} (x, y), D _x (m-1, m), D _y (m-1, m) Diff _{m -1, m} (x, y), where P _i (x, y) is the pixel value at the i-th die at position (x, y), D _x (i, i + 1), D _y (i, i + 1) is the die (i + 1) Is the offset at x and y of die i, respectively, and Diff _{i , i + 1} (x, y) is the x and y offset for die i + 1 to align it with the frame of die i. After being shifted, it is the differential gray level of die i + 1 relative to die i at positions x, y. However, within the interpolation error boundary, P ₂ (x, y) is derived from P ₁ (x, y), D _x (1, 2), D _y (1, 2) and Diff _{1 , 2} (x, y). Can be reconstructed. In addition, P _i (x, y) can be reconstructed for any other die by applying these steps successively for each die. Of course, this can mix interpolation errors and gradual blur of the image from the die to the die.

However, if the standard reference die is stored and all interpolation is performed for each die, the above-described transition error accumulation does not occur. Rather, the error is a simple interpolation error associated with reconstructing any die on the wafer from a standard reference die, given an offset and differential image. Thus, as shown in step 226, the method may include preserving differential images of each die with respect to the standard reference die.

5 shows one embodiment of a method of performing a wafer-wafer comparison using a differential image as a reference for comparison. For example, the reference wafer 250 may include a plurality of dies [(0,0), (0,1),... (4,2)], one of which is (eg, dies 2,2) designated as a standard reference die. The reference wafer 252 used for the comparison to the test wafer has a difference image for each die [Diff (0,0), Diff (0,1)... Diff (4, 2)] is generated by storing. The test wafer 256 can then be compared to the reference wafer 252. For example, as shown in FIG. 5, defect detection for the test dies 1, 3 is performed after adding the difference image Diff (1, 3) corresponding to the standard reference die image 254. Test dies 1, 3 may be subtracted to produce a difference 258 between (1,3) and reference dies 1,3.

Thus, the difference image between any die (under test) and the standard reference die can be represented in a compact manner. Lossy compression algorithms can be employed to achieve higher degrees of compression. The information that can be lost by such a compression technique depends on the technique itself. For example, as shown in step 228 of FIG. 4, the method may include performing lossy compression for non-essential regions of the difference image and lossless compression for important regions of the differential image. In this way, "intelligent" compression techniques can be used so that less critical device areas allow for greater loss than more important areas. Similar compression techniques can be used for the reference wafer image. For example, as shown in step 230, the method may include performing lossy compression on non-essential areas of the wafer image and lossless compression on critical areas of the wafer image.

Alternatively, the method may include preserving difference statistics per pixel for the standard reference die, as shown in step 232. For example, as shown in step 234, the method may include preserving statistics per die per context type. Each die may be separated into one or more context types, which may be performed as further described herein. In one such example, the method may include recording statistics for the difference at each (x, y) location in the standard reference die for another group of dies. As shown in step 236, the context may be a die area. Alternatively, as shown in step 238, the context may be of background type. Per pixel difference statistics can be determined in any suitable manner.

In another example, the wafer may be separated into N radial sectors and / or M annular rings. For example, as shown in FIG. 6, wafer 260 can be separated into annular rings 1, 2, and 3. Although the wafer 260 is shown as being separated into three annular rings, it should be understood that the wafer can be separated into any suitable number of annular rings. In addition (or alternatively), as shown in FIG. 7, wafer 260 may be divided into wafer sectors A, B, C, D, E, F, G, and H. As shown in FIG. Although wafer 260 is shown as being divided into eight sectors, it should be understood that the wafer can be divided into any suitable number of sectors. The method includes preserving statistics per pixel per wafer sector and / or annular ring, as shown in step 240 of FIG. In one such example, for each (N + M) partition, the mean and standard deviation of the difference for the standard reference die image at the (x, y) location can be recorded. The 8-bit average and 8-bit standard deviation include storing 2 × (N + M) bytes at each (x, y) location versus storing the difference bytes per die on the wafer. In this manner, if there are 100 dies on the wafer, using 8 sectors and 8 annular rings requires 32 bytes per (x, y) position versus 100 bytes per (x, y) position. In a further example, the method includes preserving wafer sector and / or annular statistics as described above per context type, as shown in step 242. The context type may be based on the die area, as shown in step 244. Alternatively, the context type may be based on the background type as shown in step 246. Statistics per context type and context type may be determined as described herein.

8 illustrates how such a technique is performed when statistics are stored for each (x, y) location on a standard reference die on a per ring annular basis. In particular, FIG. 8 illustrates one embodiment of a method for performing wafer-wafer comparison using differential statistics by annulus as a reference. For example, as shown in FIG. 8, the reference wafer 262 is divided into a plurality of dies [(0,0), (0,1)... (4,2)], one of which (eg, dies 2,2) is designated as a standard reference die. The reference wafer 264 used for comparison to the test wafer is the average difference in pixels (x, y) and the difference in pixels (x, y) for the standard reference die image 266 for each annulus. It is generated by determining the standard deviation. The test wafer 268 (shown in FIG. 8 with the annular overlay on the test wafer) may be compared to the reference wafer 264. For example, to produce the difference 270 between the test dies 1, 3 and the standard reference die image 266, the test dies 1, 3 are subtracted from the standard reference die image 266. As further shown in FIG. 8, the test dies 1, 3 are located inside the annular 1 and the annular 2. Thus, at step 272, difference image 270 is compared with statistics 274 (e.g., mean difference +/- k x standard deviation of difference) at each (x, y) location in the test die on an annular basis. . That is, the difference 270 for the portion of the test die located inside the annulus 1 is compared with the statistics for the annulus 1, and the difference 270 for the portion of the test die located inside the annulus 2 is The statistics for annulus 2 are compared.

More compact storage of standard reference die can be realized by storing standard reference die data on a statistical basis (eg, dividing the die into frames, dividing the frames into different structures (binning contexts), each frame / For context, the average / standard deviation of die-die differences is stored, for example, as shown in step 248 of Figure 4, the method includes preserving per die per frame per context statistics for a standard reference die. For example, as shown in Figure 9, an array of dies ((0, 0), (0, 1) ... (M, N)) 276 may be formed on the wafer 278. Also, as shown in Figure 10, die 276 may be separated into frame 280. Die may be separated into frame 280, and pixels of each frame may be separated based on context. (Not shown in Figure 10.) In each die The difference statistics for each other context of each frame can be determined as described herein.

11 illustrates a method of performing wafer-wafer comparison using differential frame statistics separated by context. As shown in Fig. 11, the reference wafer 282 has a plurality of dies [(0,0), (0,1) ... (4,2)], one of which is (eg, dies 2,2) designated as a standard reference die. The reference 284 used for comparison with the test wafer 286 includes a die 276 and a standard reference die image 288 separated by a frame 280. The frame 280 may be configured as described above. The reference 284 may be generated by determining statistics 290, such as the mean and standard deviation of the difference for each frame and each context within each frame for each die. In order to detect defects on the test wafer 286, the test wafer is compared to the reference 284. For example, to detect defects in the test dies 1, 3, the test dies 1, 3 are subtracted from the standard reference die image 288, creating a difference 292 between the test die and the standard reference die image. . In step 294, the difference 292 is a statistics 290 (eg, average and standard of difference for each frame and context) for the dies 1, 3 of the reference wafer 282 on a per frame basis per context. Deviation).

If the "standard reference die" is not known to be defect free, a single adjustment may be performed using the "polishing" technique (defect detection may be performed using a one-time comparison with a truly defect free reference die). have). Also, "polishing" may be performed to reflect the expected image variation across the wafer, due to "unique" or expected process variation. Thus, to create a "defect free" reference wafer, a standard reference die "polishing" may be performed on all dies on the reference wafer.

Table 1 shows the maximum die size of 40mm x 40mm, the smallest inspection pixel size of 90nm, the number of maximum size die on 44 wafers, the number of pixels in the maximum size die of 1.975E + 11, the frame size of 512x512 pixels, Frames per full size die of 7.535 + 0.5, bytes for storing average differences and standard deviations of two-byte differences, pixels per swath of full size dies of 0.91 G pixels, swaths per full size die of 217, and 2048 pixels Assuming a height swath, the approximate size of the reference data for the various wafer-wafer comparisons as described above is shown. The standard reference die assumes a 2K height sensor and includes 197 G pixels or 0.91 G pixels per swath. In addition, a differential image or some compressed form thereof for each die on the reference wafer must be stored.

Way Data size (Gbytes) Saved difference image (no compression) 8727.8 Difference image at 0.1% of total pixels 8.7 Per pixel sector-based stats: 8 sectors 3160.5 Per pixel ring based stats: 8 annular rings 3160.5 Per pixel sector + ring based statistics: 8 sectors, 8 rings 6321.0 Frame Based Statistics: 512 × 512 Frames 0.0666 Frames + context based statistics: 8 contexts / frames 0.5327

Table 1 shows that the data size for storing differential images is much larger than the data size for storing frames and context-based statistics per die. However, storing some difference pixels (e.g., 0.1%) with the maximum difference and those in the critical region reduces the data size requirement from 8727.7 gigabytes to 8.7 gigabytes.

The die on the test wafer may be scanned multiplely using a serpentine scan path to generate multiple swaths of inspection data. One embodiment of such a Spentine scan is shown in FIG. 12. As shown in Fig. 12, the test wafer 296 includes dies [(0,0), (0,1)]. (4,2)]. The test wafer 296 is scanned by the serpentine scan 298 and the serpentine scan 300. Although two serpentine scans are shown in FIG. 12, it should be understood that the test wafer can be scanned using any suitable number of times. Assuming 217 swaths per die and the same Serpentine scan in all die rows, the compression differentials for all dies can be loaded for the standard reference die swath, swath 1, swath 2, and the like. In this case, the memory requirement for storing reference data for the test wafer scan is (197 + 8.7) / 217 = 0.95 G pixels per swath.

One consideration in the implementation of standard reference die-die inspection is disk input / output (I / O) speed, which can affect throughput. Disk I / O traffic can be reduced by loading each swath of the "standard reference die" at once. Such loading can be used for serpentine scanning over the entire wafer, with die level steps (the serpentine pattern of the adjacent wafer scan) between wafer scans.

Of course, in all the inspection modes described herein, inspection can be performed using one image stored on the disk versus another image stored on the disk or an image in memory just acquired from the wafer in real time. All of the data described above may be stored as further described herein, and all the storage steps described herein may be performed in any manner described herein.

As mentioned above, the step of determining the location of the inspection data in the design data space may be performed subsequent to the inspection of the wafer. In one such embodiment, determining the location of the inspection data in the design data space is performed on the portion of inspection data corresponding to the defect detected on the wafer rather than the portion of inspection data that does not correspond to the data detected on the wafer. . In this way, the mapping transformation from pixel or wafer space to design data space is applied only to the location where the defect is found. That is, the method may include post-process mapping of the defects detected on the wafer into the design data space. Also, after defect detection is completed in the post-processing step, even if alignment (eg, alignment error measurement) can be performed, the alignment site within each die can be identified during inspection. The mapping is then applied to locate the defect in the design data space.

Regardless of when or how the positioning of inspection data in the design data space is performed, if one or more defects are present on the wafer, the inspection data includes data about the defect or defects on the wafer. Thus, the location of one or more defects in the design data space can be determined from the location of the inspection data in the design data space. In addition, the location of one or more defects in the design data space can be advantageously determined with substantially higher (eg, sub-pixel) precision equal to the location of inspection data in the design data space.

As further described herein, in some embodiments, inspection data is acquired within a swath by scanning a wafer. In one such embodiment, by aligning the alignment sites in each swath with the data for a given alignment site, each swath of inspection data can be individually aligned in the design data space, which can be performed as described above. Can be.

In another embodiment, determining the location of the inspection data includes determining a location of a swath of inspection data in the design data space based on the location of the alignment site in the design data space, and a location of the swath in the design data space. Determining a location of an additional swath of inspection data in the design data space based on the determination. In this manner, one swath of inspection data can be aligned in the design data space as described above (eg, by aligning data for a given alignment site with data for alignment sites on a wafer within a swath of inspection data). ), Additional swaths of inspection data can be aligned with those swaths of inspection data.

For example, as shown in FIG. 13, a swath (eg, swath # N + 1) may be aligned to a previous swath (eg, swath #N) using inter-swat image alignment. In particular, as shown in FIG. 13, swaths # N + 1 and #N partially overlap in the region 41 in the wafer space. Thus, both swaths may include inspection data for features formed within region 41. As such, inspection data for these features can be used to align one swath with another swath. In one such example, FIG. 14 shows features 41a and 41b formed in the inter-swap overlap region 41 in the wafer space where inspection data for two consecutive scans overlap. Features 41a and 41b can be used for swath- swath registration. Features 41a and 41b may be further configured as described herein for other alignment features.

In this manner, the first swath for the die column is aligned in the design data space by sorting the data for the alignment site (s) in the DAIL column to the provided image from the design database or other predetermined alignment site data described herein. Subsequent swaths of the die row can then be aligned using the techniques described herein. In particular, by using the position of the alignment feature within the swath and the swath #N relative to the design data space, the position of swath # N + 1 relative to the design data space can be determined. For example, determining the position of swath # N + 1 may include storing the alignment feature image acquired during the swath #N acquisition scan, and placing the alignment feature image on the image of the same feature acquired during acquisition of swath # N + 1. By sorting. By determining the misalignment offset between the two alignment feature images, one can determine the absolute position of swath # N + 1 with respect to the design data space.

During the setup of the inspection recipe, the wafer can be scanned with a relatively large overlap (eg, 50% overlap) between successive swaths to determine a suitable alignment site within the interswath overlap area. These site locations can be used to determine the location of each swath relative to the corresponding previous swath. Using the alignment site in the overlap area between the first and second swaths and the position of the first swath with respect to the design data space determined using the method described above to align the desired alignment site to the alignment site on the wafer. The shift of the second swath with respect to the determined can be used to determine the absolute position of the second swath with respect to the design data space. By repeating this procedure for each subsequent swath, pixels for the entire die can be mapped into the design data space.

A suitable alignment site can then be selected such that there is at least one site within each inspection swath (i.e., swath used during inspection where the overlap between swaths is the minimum overlap that ensures that the die is fully scanned). (Using the method described above). The location of these alignment sites in the design data space is stored in the inspection recipe along with the patch image of each alignment site. During inspection, for each swath, the corresponding alignment site is retrieved from the recipe, and its position is determined within the pixel stream acquired by the inspection system. Once the alignment site is located within the pixel stream, cross-correlation or other image matching techniques can also be used to determine the sub-pixel precision within the design data coordinate space by positioning the pixel within the inspection swath. One advantage of this method is that inspection swath can be obtained with a relatively small overlap (and thus speed up), but the swath “stitching” used to map the pixels for the entire die into the design data coordinate space. To perform and find the appropriate alignment site in the space that occurs within each test swath, the setup swath (used only for recipe setup) is obtained with a relatively large overlap. It should be understood that swath stitching techniques can be applied to field-by-field acquisition using other scanning patterns, such as area sensors. The fields can be stitched together in a manner similar to that described above.

Another advantage of the foregoing embodiments for each swath alignment for the design data space is that this technique requires that data for fewer alignment sites be rendered from the design data. In addition, rendering data from the design data to the alignment site is challenged due to the complexity of the model that can be used to predict how a given feature will be printed on the wafer, especially if the wafer has multiple layers formed thereon. Has However, as described above, data for a given alignment site can be obtained in a number of different ways, the manner of which is selected based on the layer being inspected, and thereby the predetermined alignment site regardless of the layer being inspected. Provide appropriate data for.

As mentioned above, swath stitching using “short swath” in coverage mode may be used to align the inspection data with the design data. However, in some embodiments, as shown in FIG. 14A, the alignment site 302 may be located on a wafer spaced apart (eg, away from) an area on the wafer corresponding to the first inspection swath 304a. have. This situation can only occur if a suitable alignment site is separated from the area of the wafer being scanned for the first inspection swath. The location of the first inspection swath can be determined from the attention area definition (eg, automatically defined or defined by the user). In such a situation, the method or system described herein may perform a series of “mini-scans” 306 on a wafer, with each die wide as shown in FIG. 14A. The swath obtained by mini-scan is used to "stitch" the swath containing the alignment site with the first inspection swath 304a using the above-described swath alignment method. Subsequent inspection swaths 304b and 304c may be aligned to the first inspection swath 304a as further described above.

The methods and systems described herein can obtain inspection swaths for wafers in a number of different ways. For example, as shown in FIG. 14B, the system can acquire an inspection swath 308 for the wafer in 100% inspection mode. In particular, the system scans the wafer back and forth to obtain an operating swath that can be used to inspect 100% of the area. In another example, as shown in FIG. 14C, the system can acquire an inspection swath 310 for the wafer in a standard coverage mode. In this coverage mode, the area on the wafer where swath is acquired can be from about 25% to about 50% of the die area. The swath shown in FIG. 14C corresponds to the 50% coverage mode in which alternate swaths are used for inspection. In another example, as shown in FIG. 14D, the system may acquire an inspection swath 312 for a “smart scanning” mode. In this mode, about 50% of the die area is scanned, and the scanned area can be selected based on information about the design or the expected interaction between the design and the process. In addition, the system described herein may be configured to perform any of the various scanning methods described above (eg, other scanning methods for other wafers). In addition, the method (or design analysis tool) described herein may include using knowledge of the inspection system (eg, scanning capacity) to determine the optimal "coverage" technique for the wafer.

In another embodiment, the method includes arranging inspection data to design data, and converting additional inspection data coordinates to design data space coordinates using the die corresponding design data space coordinates determined by this die alignment step. It may include. The transformation may be performed based on user input or by extracting relevant information from appropriate design files and / or process recipes (stepper recipes). Alternative approaches for determining the transformation without input from the user may include manually selecting an alignment site or aligning (eg, overlaying) the inspection data with the design data using an algorithmic overlay optimization approach. Can be. Note that this is a die alignment technique. If die correspondence coordinates are used (ie, the inspection system already knows where an alignment site exists for each die), wafer alignment techniques may not be used.

The method described herein may or may not include the step of performing inspection of the wafer to obtain inspection data. That is, the method described herein may be performed by a system (system as further described herein) that does not include an optical or electronic inspection subsystem. Instead, the system can be configured as a “standalone” system configured to receive inspection data from the inspection system. In this manner, the independent system can obtain inspection data from the inspection system. The independent system may acquire the inspection data in any manner known in the art (eg, via a transmission medium that may include the “wired” and / or “wireless” portion). Alternatively, the method may be performed by a system including an inspection system. In this manner, the inspection system can form part of the system, and inspection data can be obtained by the system by performing inspection of the wafer. Further, regardless of how the inspection data is obtained, the method described herein may be performed using any type of inspection data known in the art in any format known in the art. The inspection data may include data for detected bonds on the wafer. In another example, in one embodiment, inspection data is obtained for a PWQ described further herein.

The method described herein can advantageously be used to correlate test spaces to design data spaces with relatively high precision, and such correlations can be used in multiple steps as further described herein. For example, the location of inspection data within the design data space can be advantageously used to determine whether the inspection data corresponds to an attention region or a non-attention region on the wafer, and the inspection process is a type of region corresponding to the inspection data or other portion of the inspection data. Can be performed on the basis of For example, by moving the new image data relative to the inspection attention region such that the attention region is aligned substantially accurately to a predetermined feature in the design or CAD database for every point across the die, the method and system described herein provides a CMP pattern. Non-critical areas, such as filled areas, create a substantially accurate attention area so that inspection can be performed only on critical locations on the die, such as via locations. These critical locations, or areas to be "inspected", can be entered in recipe setup and performed using the results of CAD DRC, DFM analysis such as design scan and / or PWQ analysis, electrical test, FA, or some combination thereof. Can be determined by a "hot spot" analysis.

For example, in some embodiments, the methods described herein may provide design information and design data to inspection systems, such as attention areas, stored in standard EDA layout formats (eg, GDSII, OASIS, etc.) generated from layout analysis software tools. Converting to a format usable by. In this manner, the method may include transferring the attention area information from the design tool to the inspection system. For example, a transformation module (not shown) may be configured to generate inspection protection regions from standard design formats such as GDS or OASIS. Thus, the file in such a design format contains the resulting polygons from the design analysis performed by the EDA tool, not the design. Thus, the conversion module allows for efficient conversion between two spaces (ie, design and inspection).

In another embodiment, the method includes determining a location of a detected defect on a wafer in a design data space based on the location of inspection data in the design data space, which may be performed as described herein, and design data. Determining a value for at least one attribute of the design data corresponding to the location of the defect using a data structure in which the predetermined value for at least one attribute of is stored as a position function in the design data space. In this way, the value for the design data attribute corresponding to the defect location is based on the structure of the design, for example by determining a value for one or more attributes from the polygon in the structure (eg, as a function of structural drive on the polygon). Can be determined from previously calculated attributes. In this way, the design is processed at the polygon level, and any attribute at the polygon level that can be determined can be stored in the data structure. As such, it may include a "superset" of data for the value of one or more attributes of the design data stored in the data structure. Certain values for one or more attributes of the design data as a function of position in the design data space can be generated using an EDA layout analysis tool or any other method or system known in the art. In this manner, the design can be preprocessed to determine one or more attribute values of the design data as a function of position across the design data space, and the values for the one or more attributes are " actuated " using defect locations within the design data space. Medium "can be determined on a defect-by-defect basis by querying the values of one or more attributes in the data structure. The data structure in which the predetermined value is stored as a function of the design data space location may include any suitable data structure known in the art. In a similar manner, a data structure may be defined for one or more properties of a design layout for a design, one or more properties of a top view of the design, one or more properties of a cell in the design, any other information about the design, or any combination thereof. Can be included as a function of position in the design data space.

In one embodiment, the method may include determining sensitivity to detect a defect on another portion of the wafer, as shown in step 18 of FIG. 1. In one such embodiment, the method includes determining a sensitivity to detect a defect on another portion of the wafer based on a location of inspection data in the design data space and one or more attributes of the design data in the design data space. do. In one such embodiment, the method may include performing design based inspection by passing the attention area information from the design tool to the inspection system. For example, the attention area information can be used to identify other areas on the wafer and the sensitivity used to detect defects in those other areas. As such, one or more attributes of the design data may include attention zone information. However, one or more attributes of the design data may also include (or alternatively) any attributes of the design data described herein.

The data preparation step can include generating or obtaining data for one or more attributes of the design data. One or more attributes of the design data used to determine the sensitivity to detect defects on other portions of the wafer may include process or yield information associated with the design data. For example, in one embodiment, one or more attributes of the design data may be applied to design data, other design data, or some combination thereof, relative to the process layer, other process layer, or some combination thereof, from which inspection data for the wafer is obtained. Is selected based on one or more attributes of inspection data previously acquired for a wafer, another wafer, or some combination thereof. In this manner, one or more attributes of the design data in the design data space used to determine the sensitivity for detecting defects on other portions of the wafer are the same or different wafers for the same or different designs on the same or different process layers. Can be selected based on a correlation with attributes of previously collected inspection data from. The previously collected inspection data may be stored in a data structure such as a fab database or any other suitable database, file, or the like, or may be included in a knowledge base that may be configured as described herein. In this manner, in this embodiment one or more attributes of the design data may be selected based on cumulative learning, historical data, or a training set of data.

In other embodiments, one or more attributes of the design data are selected based on the yield threshold of defects previously detected at other sites, the probability of error of defects previously detected at that site, or some combination thereof. In this manner, the sensitivity to detect the defect may be based at least in part on one or more attributes of the selected design data based on the yield threshold and / or error probability of the defect detected at the other site. Process or yield threshold information may include, for example, a critical defect determined by the PWQ, the location of a defect of interest (DOI) based on the hot spot (e.g., determined from the inspection), hot spot information determined from the logic bitmap, a defect detected in the hot spot. KP value determined from the test results for, any other process or yield information described herein, or some combination thereof. KP values may be determined as described further herein. In addition, the error probability may be determined in a manner similar to that described herein to determine the KP value for the defect. The yield threshold may be determined in a similar manner as described further herein to determine the yield relevance of the defect.

Data for one or more attributes of the design data may include one or more attributes (eg, contact area or dummy filling area, information of "place to inspect" or "attention area", "critical" area where process errors are possible, or some combination thereof. And "context" data that defines a structural area within the device design that has a different value of type of feature within the area, such as. The term context data is used interchangeably with the terms "context information" and "context map". Contextual information may be obtained from various sources, including simulation, modeling, and / or analysis software products available from KLA-Tencor, other software, such as DRC software, or some combination thereof. In addition, additional context data may be determined and combined with data about attributes of the design data. Data structures such as databases or files containing design data and / or context data may have any suitable format known in the art.

As described above, the determining of the sensitivity may be performed such that defects detected at different portions of the wafer corresponding to the design data having different values of one or more attributes of the design data are detected with different sensitivity. In this manner, the method may also include determining, identifying, and / or selecting other sites based on values of one or more design data attributes as a function of design data space location. The dimensions of all or some of the other sites may be different and may vary depending on the resolution at which the value of the attribute of the design data is available or obtained. For example, if context maps are used to determine the sensitivity for other sites as described further herein, the dimensions of the other sites may vary depending on the resolution of the context map.

In one such embodiment, the sensitivity is determined based on the location of the inspection data within the context map and the design data space, and as described further herein, values for one or more attributes of the design data across the design data space. It may include. For example, the method may include using a context map to define a relatively high sensitivity area within the die on the wafer relative to the variable sensitivity area and the critical area based on the threshold of the context. In one example, segments of design data may be defined to isolate dense arrays and logic, open regions, and grainy metal. Combinations of image gray levels and contexts may also be used to define one or more segments in the design data. For example, pixels with intermediate gray levels can be combined into one segment. The image gray level can be determined using an image acquired by an inspection system or other image acquisition system or a simulated image.

In some embodiments, determining the sensitivity to detect defects on other portions of the wafer based on the location of the inspection data in the context map and design data space may be performed by the inspection system during inspection of the wafer. For example, the context map can be used by an inspection system as described herein in the inspection of a wafer. In another embodiment, determining the sensitivity to detect a defect on another portion of the wafer based on the location of the inspection data in the context map and design data space may be determined by the inspection system after acquisition of inspection data for the wafer is completed. Is performed. For example, the context map can be used by the inspection system as described above after the inspection data is made available offline. In both of these embodiments, the method can automatically define a dummy area (non-test area) of the die on the wafer and use a context map to define the rough area of the die where other sensitivity thresholds are used. For example, a context map (eg, a context map defining a dummy fill area) can be used to automatically define non-caution areas that do not require inspection, and therefore are excluded for defect detection purposes. Such regions are typically less controlled and thus produce a relatively large amount of noise (compared to die-die). Thus, the exclusion of such regions can increase the overall S / N of the inspection.

In one embodiment, determining the sensitivity to detect a defect on another portion of the wafer based on the location of the inspection data in the context map and design data space includes: Determining a sensitivity threshold to be used together. In this way, one or more thresholds used for defect detection can be changed from the area-area, which is similar to the segmented automatic threshold (SAT) method. For example, low threshold (high sensitivity) detection can be used for critical areas and high threshold (low sensitivity) detection can be used for non-critical areas. Based on one or more attributes of the design data, the overall sensitivity of the inspection process can be increased by segmenting the design data and changing the thresholds used for defect detection. Thus, the methods and systems described herein provide improved defect detection.

The method may also include using the context map described above to perform a plurality of other steps. For example, a context map (whether or not a die-die inspection mode, a standard reference die-die inspection mode, etc. is used for defect detection) may be used to determine the sensitivity, filter the Nuson's defects, classify the defects, It can be used to perform various steps, such as generating a review sample for a step, an online or offline review, and is not limited to such a step. In order to use design or contextual information as described further herein, the absolute position of other inspection data or image pixels acquired during the inspection process (eg, by scanning the wafer) is within the design data space (eg, design database coordinates). Is determined. The mapping of inspection data to design data within half of the inspection pixel size can be achieved by substantially accurate setting of inspection thresholds (substantially precisely separating critical areas from non-critical areas), filtering of neusons defects from actual defects, and arbitrary Other steps of may be allowed and can be performed as described further herein.

In addition, relatively high bandwidth, pixel-level context information can be used for a substantially very accurate mapping of inspection space to design space coordinates for a wide range of applications. For example, a relatively high resolution context map can be used to automatically define pixel-level regions that can be examined with different sensitivity. The relatively high resolution context as described herein is relatively rough (approximately 50 μm × 50 μm) and inaccurate user defined region based multi-threshold (RBMT) due to ambiguity (e.g., spread over about 5 μm) at the attention area boundary. Generally more accurate than

In one embodiment, the context map may be used at the pixel level to control the detection sensitivity at each pixel. However, a simpler approach (from a system complexity point of view) uses a context map only for post-processing of detected defects using a detection method that does not detect defects using contextual information. In this way, inspection into the design data space or mapping of wafer space can be applied only to inspection data corresponding to the detected defect. As discussed above for the die-die and standard reference die-die inspection, the location of the defect is determined within the design data space. Thus, a patch image of the design data at the location of the defect in the design data space can be obtained, and this patch image can be used to determine the design context corresponding to the defect. Alternatively, the context map aligned with the design data can be used to determine the design data context corresponding to the defect based on the location of the defect in the design data space.

For a standard reference die-die inspection, determining the context of each pixel in the inspection data may include determining the context of each standard reference die pixel. Since a standard reference die image is acquired during the recipe setup step, the method includes aligning data for an alignment site (selected as described above) in the standard reference die image with data for a given alignment site, and design data space. And performing a mapping transform to determine the location of each standard reference die pixel within. These steps can be performed during the recipe setup step. In addition, the standard reference die can be mapped to the context data based on the mapping of the standard reference die to the design data space, the standard reference die pixels are stored offline with the context corresponding to each pixel, and the inspection system during inspection It may be provided or obtained by it. This process can be performed off-line and only once during the recipe setup phase.

In one such embodiment, each standard reference die pixel may be associated (tag) with context information. In this manner, the context information may be "added" to the standard reference die pixel. In one example, if there are 16 different possible contexts, a 4 bit tag may be added to each pixel. Alternatively, the context data may be compressed using any suitable compression algorithm or method, or the context data may be represented in polygonal form. In this manner, during inspection, mapped (transformed) context data associated with standard reference die pixel data and standard reference die pixel data may be provided to or obtained by an image computer or other process of the inspection system. Thus, the context corresponding to the inspection data pixel can be determined based on the context information of the corresponding pixel in the standard reference die image. As such, contextual information corresponding to the inspection data pixels may be available to defect detection and classification (and / or binning) applications, which may be performed as described further herein.

In another embodiment, the method may use a context map at any resolution to assist in wafer inspection. For example, wafer variable resolution context maps can be used for wafer inspection and assistance in binning of defects. The resolution of the context map can vary depending on the accuracy with which the live pixel stream can be aligned to the design data and the accuracy requirements of the application. Context maps at different resolutions can be represented in a number of different ways. For example, an absolute representation (i.e., several decimal places of microns) of polygonal context maps may be given to the inspection system at an appropriate pixel size to produce a pixel level context map. In addition (or alternatively), the rough context map may include a context for a relatively rough area having, for example, a lateral dimension of about 1 μm × about 1 μm. Rough areas may be in the form of "tiles" that separate design data. Context data, such as feature type (eg, dummy feature, contact, line end), feature attribute (eg, minimum line width / space between structures, etc.), or some combination thereof, may be associated with each tile.

In one embodiment, the method generates a relatively high resolution context map using attribute information and locations for the design that can be obtained from any software program that can be used to analyze possible design rule violations and designs for critical areas. It includes a step. Such context maps are some attributes (or labels) of each location that can be converted into a commercially available analysis software (eg, design scan) from KLA-Tencor, or a format for use by an inspection, metrology, or review system. And other software such as DRC software to generate a list of locations.

In another embodiment, the method includes extracting feature vectors from the CAD layout and using a non-managed clustering to define equivalent context groups, creating a coarse context map of relatively low resolution. For example, a method for generating a relatively coarse context map (eg, about 1 μm × about 1 μm) may include processing a CAD layout file, rendering or analyzing tiles, and specific attribute or feature vectors for each tile. It may include the step of extracting. For each region, multiple features can be extracted from a predefined feature set. The value of each feature is its feature vector. The feature vectors for each region can be combined into a series of feature vectors that can be used to determine cluster similarity by evaluating clustering within the feature space. These feature vectors (one or more vectors per tile) can be used within the feature space using any non-directed clustering algorithm and / or methods known in the art that can be used to find clusters of vectors (ie tiles with similar properties). Can be clustered. Examples of such algorithms and methods that can be used in the methods described herein are disclosed in US Pat. No. 6,104,835 (Han), which is incorporated by reference as if fully set forth herein. Each such cluster may be assigned a unique context or identity. The map of the die where each tile is represented by this code or identity can be used by the inspection system as further described herein.

In another embodiment, the method renders the CAD layout patch image and cross-correlates the CAD layout patch image to identify equivalent groups of contexts (which may be used for binning as further described herein). Generating a rough context map with a relatively low resolution. Another method for generating a context map (eg, a relatively coarse context map) renders the CAD layout file into a patch image, separates design data into patch images, identifies image cross-correlations between patch images, Allowing patch images with high cross-correlation to be binned into groups of patch images corresponding to the same text type.

In some embodiments, the context data used in the methods used herein may include context data for one or more layers that may be present or formed on the wafer. For example, some defects may not be located in the critical area in the layer where the defect was detected. However, if the defect is located in an area on the wafer where the critical area in the overlapping layer can be formed on the wafer, such non-critical defect can be significant. The context map used in any of the steps described herein may be a context map for multiple layers on the wafer.

In another embodiment, the method includes a sensitivity diagram for detecting defects on other portions of the wafer based on the location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. Determining may also include. The attributes of the design data used in this step may include any of the attributes described herein. In such embodiments, if a defect is detected at another site, the one or more attributes of the inspection data include one or more image noise attributes or some combination thereof. In this manner, one or more attributes of the inspection data used in this embodiment may include detection or non-detection of image noise attributes and / or defects in other areas of the inspection data. The attributes of the inspection data used in this step may include any other attributes of the inspection data described herein. Determining the sensitivity in this embodiment may be performed for PBMT setup for the inspection process based on image noise correlated to the design data. Determining the sensitivity in the present embodiment may be performed as further described herein.

In another embodiment, the method may include one or more properties of schematic data about the design of the device being manufactured on a wafer, one or more properties of expected electrical behavior of the physical layout for the device, or some combination thereof. Changing one or more parameters for detecting a defect on the wafer based on the change. In this way, the design schematic data attributes and other electrical descriptions of the expected behavior of other physical designs (layouts) can be used to change one or more parameters for detecting defects or any other parameters of the inspection process. have. For example, such other information about critical and non-critical paths, active and non-active structures, and expected electrical behavior or schematic data of the physical design (layout) may change the sensitivity to detect defects, and Determine where in the defect to detect defects (e.g., attention area and non-attention area), determine which part of the inspection data to use to detect the defect (e.g. Association), one or more other parameters of the inspection process.

In another example, data capture rate and electrical behavior monitoring can be performed based on design / image context. For example, electrical behavior can be monitored using an electrical test, FA, or any other test or analysis known in the art, or using the results of such a test or analysis. The results of an electrical test, FA, or other test or analysis can be correlated to the contextual information regarding the schematic data and the physical layout of the device. Monitored defect capture rates and electrical behavior can be correlated to the design / image context to determine information about detection defects on the wafer, information about the inspection process used to detect the defect, and information about the design. have. For example, defect capture rate and electrical behavior monitoring results may be used to determine which type of defects are detected on the wafer, which defects should be detected (eg, in an online inspection process), but which defects are not detected, and the weak point in the design. Can be used for Such information can be used to modify the inspection process as further described herein.

In a further embodiment, the method includes changing one or more parameters for detecting data on the wafer using inspection data based on one or more parameters of an electrical test process performed on the wafer. For example, one or more parameters for detecting defects on the wafer or any other parameters of the inspection process may change based on electrical test rules associated with the corresponding (physical) design data space. In this way, the inspection process can change based on how the electrical test is performed. In such an example, the area on the wafer to be analyzed by the electrical test process can be determined based on one or more parameters of the electrical test process, and the one or more parameters for detecting defects or any other parameter of the inspection process Defects in areas on the wafer that will not be analyzed in the electrical test process can be altered to check for proper sensitivity.

In addition, one or more parameters of the electrical test process and the location of the defects in the design data space or wafer space may be used to identify defects that will not be tested (or “exclude electrical test”) by the electrical test process. In one such example, the area on the wafer and the location of the defect on the wafer to be tested in the electrical test process can be used to determine which defect to test by the electrical test process. In another example, the area in the design to be tested in the electrical test process and the location of the defect in the design data space can be used to determine which defect will not be detected by the electrical test process. In a similar manner, one or more parameters of the electrical test process and the location of the defects in the design data space or wafer space may be used to separate or bin the defects into different groups depending on whether the defects will be tested by the electrical test process or not. Can be.

In wafer space, information about hot spots (eg, information from a hot spot database) and attributes of design data can be used to set up inspection recipes in the monitoring phase. For example, the attention area can be automatically defined within the wafer space at the monitoring stage. Automatically defined areas may include macro and micro protected areas. Automatically defined protected areas may also include non-protected areas. In addition, inspection recipes automatically change the sensitivity, filter out Newsons defects, enhance the capture of known systematic defects (e.g., enhance the sensitivity to hot spots or hot spot areas), and cold spots. ) Can be set up to suppress the defect signal or data corresponding to the region. In addition, information about hot spots and attributes of the design data include design data based binning using GDS (i.e.GDS pattern grouping) and / or GDS pattern grouping pareto to set up more inspection recipes. Can be used for classification and binning of possible defects and sample defects.

In a further embodiment, the method may include periodically changing one or more parameters of the inspection process performed by the inspection system based on the results of one or more steps of the method using a feedback control technique. In another embodiment, the method may include using a feedback control technique to automatically change one or more parameters of the inspection process performed by the inspection system based on the results of the one or more steps of the method. In addition, the monitoring step may include an automatic process control (APC) for the inspection process that includes changing inspection recipes or parameters based on previous measurements in combination with previous knowledge of process area differences. APC for the metrology process can be performed based on systematic defects that can be identified in accordance with any of the embodiments described herein to determine where measurements are to be performed in addition to the measurements to be performed in subsequent metrology. The APC for the test process can be performed based on systematic defects that can be identified in accordance with any of the embodiments described herein to determine the electrical parameters to be tested in the subsequent electrical test and where the test is to be performed. .

In a further embodiment, the method includes generating a knowledge base using the results of one or more steps of the method, and generating a test process performed by the inspection system using the knowledge base. The knowledge base can be created by storing one or more image attributes and / or one or more attributes of the design data in a suitable data structure. In addition, the knowledge base can include cumulative learning acquired by an inspection system that can be used to create an inspection process. For example, in the inspection process, a knowledge base can be used to determine cumulative results of the inspection, such as the frequency of defect detection and the percentage of detection defects that are Newson's defects, which cumulative results can be added to additional factors such as the probability that the defect is a Newsons defect. Can be used to determine information.

Such knowledge base can be used to create an inspection process as described further herein. In this way, the knowledge base can be used to create new test recipes. In addition, the knowledge base can be used to create inspection processes for recipe setup and / or wafer-less recipe setup. Generating the inspection process may include selecting any one or more parameters of the inspection process. In addition, the knowledge base can be used to modify the inspection process by recipe optimization and automatic recipe optimization. For example, the method may comprise using a feedback mechanism for training the knowledge base for periodic or automatic optimization of one or more parameters of the existing inspection process. Changing the inspection process may include changing any one or more parameters of the inspection process.

In another embodiment, the method includes optimizing the wafer inspection process to determine the printability of the reticle defect on the wafer using the context map and the location of the inspection data in the design data space. In this manner, the method may include optimization of the wafer inspection process for the purpose of determining the printability of the defects detected on the reticle using the CBI in combination with the context map. Optimizing the wafer inspection process may include changing any one or more parameters of the wafer inspection process, which may include any parameters of any wafer inspection process described herein. In general, determining the printability of the reticle defect on the wafer may include inspecting the wafer to detect a defect on the wafer that may correspond to a defect on the reticle. In this manner, optimizing the wafer inspection process to determine the printability of the reticle defect may include optimizing the wafer inspection process to determine a defect on the wafer that may correspond to a defect on the reticle.

In one example, the method includes the location of inspection data acquired for a wafer in a design data space, which may be determined as described herein, to identify a location of inspection data that may be used to determine the printability of the reticle defect. , Using the location of one or more reticle defects in the design data space. In this manner, the inspection data acquired for the wafer and the design data space location of the reticle defect can be used to determine the site of inspection data that can be used to detect defects on the wafer that may correspond to the reticle defect. Any attribute of the design data included in the context map can be used to select one or more parameters of the wafer inspection process to determine the printability of the reticle defect. For example, the context map can be used to determine one or more attributes of the design data corresponding to the portions of the inspection data identified as described above. In this manner, one or more parameters of the wafer inspection process used for other portions of the inspection data identified as described above may be selected based on one or more attributes of the design data corresponding to those other portions. As such, other portions of the inspection data identified as described above, corresponding to design data having different values of one or more attributes, are processed by one or more other parameters to detect wafer defects that may correspond to reticle defects. can do. In one such example, the text map can be used to determine a threshold of design data corresponding to another portion of the inspection data acquired for the identified wafer as described above, the threshold being used to detect a defect within another portion of the inspection data. It can be used to determine risk sensitivity. In that particular example, different parameters of the wafer inspection process can be selected for different areas of the inspection data, such that the printability of one or more reticle defects is higher in the critical areas of the design data than in the non-critical areas of the design data. Can be determined.

One or more parameters of the wafer inspection process may be changed and / or optimized based on the location of the inspection data in the design data space, the context map, and any other information described herein. For example, one or more attributes of another portion of the design data where one or more reticle defects are detected may be determined using a context map, and wafer inspection of other portions of the inspection data corresponding to other portions of the design data where the reticle defects are detected. In order to select process parameters, one or more design data attributes of the other site may be used in combination with one or more attributes of the reticle inspection data (eg, attributes of one or more reticle defects). In such an example, one or more parameters of the wafer inspection process may be such that the printability of other types of reticle defects located at the site of the design data having substantially the same properties may be determined by one or more other parameters of the wafer inspection process. You can choose. In another example, one or more parameters of the wafer inspection process may be selected such that the printability of the reticle defects of the same type located in the site with different values of attributes may be determined by one or more other parameters of the wafer inspection process.

The context map used in the embodiment as described above to optimize the wafer inspection process to determine the printability of the reticle defects is configured as described herein and may include any context map described herein. . In addition, any information included in the context map may be used in the embodiments described above to change one or more parameters of the wafer inspection process.

In some embodiments, the method includes changing one or more parameters of an electrical test process performed on the wafer based on defects detected on the wafer using inspection data. For example, in a test space, the monitoring step may include using systematic defects identified in accordance with any of the embodiments described herein to define or modify test patterns and / or other test parameters. In addition, defects detected on the wafer using inspection data determine whether one or more defects are not tested by an electrical test process (or “electrical test avoidance”), and the electrical test such that one or more defects are tested by an electrical test process. It can be used to change one or more parameters that define the area on the wafer on which the process is performed. In this manner, the results of the inspection process can be fed to the electrical test process to reduce a plurality of defects that have not been tested in the electrical test process. In addition, one or more parameters of the electrical test process may be determined in such a manner that defects detected on the wafer using inspection data, design data spaces or positions of defects within the wafer space that can be determined as described herein, One or more properties of the defects that may include any of the properties of the defects described herein, one or more properties of the design data that may include any of the design data properties described herein, determined in any manner described herein, Changes may be made based on any other information described herein, or some combination thereof. For example, the location of the bond, the nature of the defect, and the nature of the design data can be used to determine the error probability value for one or more of the defects described herein. If a defect that will not be tested by an existing electrical test process has a relatively low error probability value, one or more parameters of the electrical test process may not be changed by the method. In contrast, if a defect that will not be tested by an existing electrical test process has a relatively high error probability value, one or more parameters of the electrical test process are changed such that a defect with a relatively high error probability value is tested by the electrical test process. Can be. In a similar manner, one or more parameters of the metrology process, such as sampling of the metrology process, can be selected, determined, or changed as described above.

Alignment of inspection data to design data allows inspection of "hot spots" on the wafer. A "hot spot" can generally be defined as a location in the design data printed on the wafer where a killer defect may be present. In contrast, a "cold spot" can generally be defined as a location in the design data printed on a wafer where there may be a Newsons defect. One example of the Newson's defect is a variation in the critical dimension (CD) of the feature that does not substantially affect the yield of the device formed on the wafer, but causes the inspection system to indicate that there is a defect at that location. Some defects may be killer defects only under certain circumstances, such as when the defects are contacted by device structures formed in other layers of the wafer. Thus, the location where such a defect may exist in the design data printed on the wafer may be generally referred to as an "adjustable hot spot."

In a further embodiment, as shown in step 20 of FIG. 1, the method includes determining whether the defect detected on the wafer is a Newson's defect. Whether the defect is a Newsons defect is determined based on the location of the inspection data in the design data space and one or more attributes of the design data. For example, in some embodiments, the method includes determining a location of a defect in the design data space based on a location of inspection data in the design data space, and a location of the defect in the design data space and one of the design data in the design data space. And determining whether the defect is a Newsons defect based on the above attributes. At this stage, one or more attributes of the design data used to identify the Newsons defect may include any of the attributes described herein. For example, one or more attributes of the design data may be defined in the context map. In this manner, the method may include, but is not limited to, applying a context map to the defect data to filter out defects (eg, Newson's defects) that are considered insignificant in an application such as, for example, PWQ. As such, the areas of the tongue that approach the limit of the capacity of the manufacturing process are separated into important and non-essential areas based on the context. In another example, the attributes of the design data used to identify the Newson's defects at this stage include hot spot information for the design data. In this manner, the location and hot spot information of the defects in the design data space can be used to identify defects detected at cold spots in the design data as Newson's defects.

The PWQ application for lithography exposes the die on the wafer at different exposure and focus offsets (ie, adjusted dosage and focus), and systematic defects within the die that can be used to determine the design vulnerability area and determine the process window. Identifying generally includes. An example of a PWQ application for lithography is disclosed in commonly assigned US patent application Ser. No. 11 / 005,658, filed Dec. 7, 2004; Wu et al., Which is incorporated herein by reference in its entirety. Included. Several artifacts of focus and exposure adjustment can be represented as defects (die-standard reference die differentials), but are actually Newson's defects. Examples of such artificial elements may include CD fluctuations and line-end pullbacks or shortening of areas where such artificial elements do not affect or reduce the yield or performance of the device. However, the location of the defect can be determined substantially accurately with respect to the design layout using the method described herein. In addition, the method described herein can be used to determine the protection area with a relatively high accuracy as described above. The “micro” protection areas can be concentrated in known hot spots and inspected at relatively high sensitivity, or can be concentrated in cold spots (systemic sensations) known as non-cautionary or relatively low sensitivity regions.

Thus, as discussed above, the method may include determining whether the defect is a Newsons defect based on the location of the defect relative to the design data space and whether the location is within the attention area. Defects can be filtered according to context, size, redundancy, PWQ "rules", or some combination thereof. For example, in the process space, PWQ analysis and DOE analysis can be performed using hot spots in the monitoring phase. In addition, the method described here can be used to extend PWQ applications up to 65nm design rules, where current noise filters fail due to limited resolution. Thus, one advantage of the method described herein is that the method can be used to extend BF inspection to detect systematic defects and DFM defects. In particular, as described herein, the CBI may enable additional functionality for BF inspection systems such as systematic defect inspection and / or DFM applications below 65 nm design rules. The method may provide or support a relatively quick determination of the root cause of DFM systematic defects. Determination of the root cause can be performed as further described herein.

In another embodiment, as shown in step 22, the method is based on one or more attributes of the design data in the design data space (which may be defined in the context map as described above), or lists the location of the defect or database. And comparing the location of the hot spots that may be stored in a data structure, such as determining whether a defect that is not determined to be a Newson's defect is a systematic or random defect. Also, not all defects of interest may not be Newson's defects. For example, systematic defects with relatively low or no impact on yield may be defects that are of no interest, not Newson's defects. Such defects may appear on the active pattern or in the device region of the wafer. The method described herein may include identifying such a defect. Such defects, or defects located in cold spots, may be associated with design context (eg redundancy vias), modeling (eg design scans), PWQ, inspection and review, and test and defect correlation (eg, relatively low stacked electrical error locations). Relatively high stacking fault density at the location). In addition, monitoring of these defects can be performed by comparing the positions of the defects with the positions of the hot and cold spots. If the patterns in which these defects are located are common, they can be binned separately from other systematic defects using the design data-based grouping method described herein. In addition, the search for systematic defects may be performed by correlating a plurality of input sources from the design, modeled results, inspection results, metrology results, and test and FA results.

The systematic DOI may include all pattern dependent defect types. Identifying systematic defects is advantageous as the effects of the defects on the device can be analyzed. The random DOI may include statistical samples of significant types of random defects. Analyzing random defects is beneficial because it is possible to analyze important types of random defects to determine the effect that defects have on the device. In addition, by analyzing the random defects, one or more inspection process parameters can be changed to suppress the detection of random defects that can be considered as Newson's defects. In addition, the inspection process parameters can be changed to distinguish Newson's defects from systematic causes (cold spots).

Determination of whether a defect is a Newsons defect, a systematic defect, or a random defect is advantageous because the yield can be predicted more accurately based on the type of defect detected on the wafer and the relevance to the yield of other types of defects. In addition, possibly in combination with yield prediction, the results of the methods described herein can be used to make one or more decisions regarding design data and manufacturing processes. For example, the results of the methods described herein can be used to verify IC design. In another example, the results of the methods described herein can be fed back to the IC design process such that the IC design generated by the process can be sensitive to fewer systematic defects and / or fewer types of systematic defects. In one such example, the results of the methods described herein can be used to modify the design and / or optical rules used in the IC design process. In another example, the method described herein can be used to change one or more parameters of the process used to fabricate the wafer level being inspected. Preferably, one or more parameters of the process such that less systematic defects and / or fewer types of systematic defects, and possibly fewer significant random defects and / or fewer types of significant random defects, are caused by the process. Is changed.

In some embodiments, as shown in step 24, the method includes classifying the one or more defects based on the location of the inspection data in the design data space and the one or more attributes of the design data in the design data space. For example, the location of a defect in a design data space can be determined from the location of inspection data in the design data space. In addition, one or more attributes of the design data associated with the position of the defect within the design data space may be determined from the context map or in any other manner described herein, and one or more attributes associated with the position of the defect may be used to classify the defect. have. In another embodiment, the method may include a location of a portion of inspection data corresponding to a defect in a design data space and values for one or more attributes of the design data across the design data space, as described further herein. Based on the context map, which may be, classifying the detected defects in other portions of the wafer may include. In this manner, the method may use a context map to classify the defects by context. Classifying the defects in this step can be performed in any of the other ways described herein.

In one such example, defect classification is performed by an inspection system during inspection of the wafer. For example, the context map can be used by the inspection system to classify defects as described herein during wafer inspection. In another such embodiment, defect classification is performed after inspection data acquisition for the wafer is completed. For example, after inspection data is available offline, the context map can be used by the inspection system to classify defects, as described below herein. In this manner, the method can be used to classify defects online in a second pass high resolution defect classification (HRDC) (eg using an inspection system) or offline in an HRDC (eg using an SEM review station). It may include using a context map. Typically, whether performed online by an inspection system or offline in a review system (optical or SEM), the second pass defect classification includes redetection and classification of defects. Both redetection and classification can be performed manually or automatically (ie, automatic defect classification; ADC) by the user. As design rules shrink, the probability of identifying a faulty object as a defect in the review process increases. Design data and context maps can be useful for both redetection and classification.

In redetection, the context map provides local background information near the defect that allows the user or system to locate the corrected defect in the field of view of the review system. For example, the local image of the wafer generated by the review system can be aligned to the design data, thereby allowing the location of the defects in the design data space to be identified substantially accurately within the aligned local image. In addition, a simulated image of the design data (eg, a gray scale image) can be used by the review system for alignment to the local image, and the location of the defect in the design data space can be used to determine the location of the defect in the local image. Can be. Such simulated images can be used for fine alignment and redetection of defects in the review process. Examples of such simulations are disclosed in US Pat. No. 6,581,193 (McGhee et al.), Incorporated by reference as if fully set forth herein. The method disclosed herein may include any step of the method disclosed in such a patent document. Thus, the methods and systems disclosed herein can be used to perform relatively high accuracy defect detection.

In the classification, the context map can provide additional information (along with data obtained by review) that can be used to determine the class to which the defect belongs. The review can also be performed using the context map, data obtained by the review, and inspection data. For example, a patch image acquired by a time delay integrated (TDI) camera of the inspection system, and / or a patch image acquired by the inspection system may be sent to the review along with the defect sample. Patch images can be used in combination with optical or SEM context maps for review and classification. In this manner, the coordinate precision at which the defect location can be determined as described above allows the system to classify the defect substantially accurately based on the design context and / or DRC error code.

One or more of the above steps may be performed in a monitoring step in which systematic defects are identified and classified (or binned) using the test results and any other results described herein. The monitoring phase may include deviation monitoring and baseline enhancement. The monitoring step can be performed during product lamps and manufacturing. In multiple source spaces (which may include correlations between design, wafer, reticle, test, and any of the process spaces), identifying and classifying systematic defects detected by inspection are steps described herein. Any combination of these may be used. In addition, one or more multiple source space steps may be used to verify systematic defect identification in any combination thereof.

In addition, the location of the defects in the design data space can be used in combination with inspection data, design data, or classification data to identify systematic defects (eg, defects located at hot or cold spots) in the monitoring phase. The identified hot spot can also be used to determine the design context for an inspection result where there is a "hit" at the hot spot location, which is on-tool in post-processing, or off Can be done with the tool The yield (or KP value) associated with the design data space can be used as an attribute to monitor systematic defects. In addition, one or more defect attributes can be used to estimate the association for a hot spot when there are a plurality of hot spot candidates.

In the reticle space, the monitoring step may include generating information about hot spots (eg, generating a hot spot list) that can be compared with the defect results to separate known systematic defects from random defects. In addition, one or more hot spot attributes, such as contextual information about a hot spot, may be used to determine whether a hot spot can be shared across multiple technologies, layers, devices, and in which case, which technology, layer, or device. Can be. In addition, systematic defects identified by inspection can be used to define or correct one or more parameters of the metrology process, such as metrology site locations, measurements or other parameters.

In some embodiments, the method includes determining an error probability value for one or more defects detected on the wafer based on the location of inspection data in the design data space and one or more attributes of the design data in the design data space. . Further, the method may include determining an error probability attribute value of a defect detected on another position of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. . As further described herein, an error probability value for a defect may be determined based on the design data space location of the inspection data corresponding to the defect and one or more attributes of the design data in the design data space.

In another embodiment, the method includes determining position coordinates of a defect detected on a wafer in the design data space based on a position of inspection data in the design data space, and determining the position coordinates of the defect based on a plan view for the design data. Converting to design cell coordinates. In one such embodiment, the method uses overlay tolerance to determine another area around the defect and uses the area to perform defect repeater analysis on one or more cell types, thereby providing one or more cells. Determining whether the type is a systematically defective cell type, and determining one or more locations of the one or more systematically defective structures within the systematically defective cell type. In this manner, the method may include using cell-based coordinates for repeater analysis. In particular, defect repeater analysis is performed for each cell type using overlay tolerances (e.g., two-dimensional areas around each defect) to systematically determine the presence of the defective cell type and the systematically defective structure within that cell. The location can be determined. The method may also include cell-based binning of defects based on cell context. Such binning can be performed as further described herein. In one such embodiment, the method is based on one or more attributes, structures, or some combination thereof, of design data for a cell located systematically close to the defective cell type. Determining if it occurs. In this way, the design context (peripheral cell or structure) of a spatially systematic defective cell can be used as an attribute to further specify the appearance of a spatially systematic defect.

In another embodiment, as shown in step 26, the method identifies defects (eg, all or part of the defects) based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Binning into groups. For example, the location of a defect in the design data space can be determined from the location of inspection data in the design space as described herein. One or more attributes of the design data used to bin the defect may be determined based on the location of the defect in the design data space. One or more attributes of the design data used in this embodiment are associated with the design data (eg, yield impact), in combination with other inspection results (eg, integrated defect organizer (iDO) results and integrated automatic defect classification (iADC) results). It can include any attribute of the design data described herein, such as a value. In addition, one or more attributes of the design data associated with the location of the defect in the design data may be determined from the context map. In this manner, the method may include applying a context map to the defects detected during wafer inspection to classify the defects into contexts.

Thus, the method described herein may include context-based background binning for wafer inspection. For example, as described above, the method may use a context map to bin defects by context. In one such example, defects remaining after Newsons filtering may be classified by context or other information described herein to identify defects that are systematic defects rather than random defects. Context can be used in conjunction with other image-derived attributes associated with defects to perform binning and classification.

In addition, defects may be binned based on expected electrical parameters of the defect and / or expected electrical parameters of the device feature close to the defect location in the design data space. The expected electrical parameters of the defects and device features can be determined based on previous electrical tests, simulations of electrical parameters of the defects, review of the defects, or some combination of them. In addition, fault simulation of one or more defects may be based on the group of defects binned and / or the location of the defect in the design data space.

In some embodiments, the method is based on a location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the reticle inspection data required for the reticle to which the design data is printed. Binning into groups. In this manner, the reticle inspection data can be used as binning attributes. In particular, the reticle inspection data attribute can be used to bin the defects detected on the wafer. In this embodiment, one or more attributes of the design data may include any attribute of the design data described herein. One or more attributes of the reticle inspection data may include a defect detected on the reticle, the location of the defect detected on the reticle within the reticle space, one or more attributes detected on the reticle, one or more attributes of the design data printed on the reticle, or some combination thereof. It may include any attribute of the reticle inspection data, such as. One or more attributes of the defect detected on the reticle may include any of the defect attributes described herein. In addition, one or more attributes of the design data printed on the reticle may include any of the design data attributes described herein.

The attributes of the reticle inspection data can be determined in any suitable manner by the method and system embodiments described herein (eg, using the output of the reticle inspection system). Alternatively, or in addition, the attributes of the reticle inspection data may be obtained by the method and system described herein from the storage medium on which the attributes are stored and / or the reticle inspection system that determined the attributes.

Binning the defect based at least in part on the one or more attributes of the reticle inspection data may be characterized by one or more attributes of the reticle that caused the defect on the reticle, the defect on the wafer, and the defect on the wafer. It can be used to isolate defects based on whether they are caused by one or more attributes of printed design data. As such, binning of the results may provide additional information about the cause of the defect and / or how the reticle affects the defect and / or design data printed on the wafer. Such binning results may include one or more parameters of the reticle manufacturing process, one or more parameters of the reticle inspection process, one or more parameters of any other reticle-related or design-related process, one or more of any other process described herein. It is useful to use to change parameters, or some combination thereof. The binning of the defects in this embodiment is performed based on the location of inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the reticle inspection data, and any other information described herein. can do.

In another embodiment, the method may include binning the defects into groups based on a location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. . In this manner, one or more attributes derived from the inspection data can be used for binning operations. In this embodiment, one or more attributes of the design data may include any attribute of the design data described herein. In addition, one or more attributes of the inspection data used for binning may include any of the attributes of the inspection data described herein. Defects can be binned in this embodiment using any other information described herein. Binning in this embodiment can be performed as further described herein.

In a further embodiment, the method comprises a reticle required for the location of inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, and a reticle on which the design data is printed. Binning the defects into groups based on one or more attributes of the inspection data. In this manner, the reticle inspection data can be used as binning attributes. In particular, the reticle inspection data attribute can be used for defect binning on the wafer. One or more attributes of the design data in the design data space used for binning in this embodiment may include any attribute of the design data described herein. One or more attributes of the inspection data used for binning in this embodiment may include any attribute of the inspection data described herein. One or more attributes of the reticle inspection data used for binning in this embodiment may include any attribute of the reticle inspection data described herein. Binning in this embodiment can be performed as further described herein. In addition, the binning results of this embodiment can be used to perform any step of any of the methods described herein.

In some embodiments, the method includes a location of inspection data in a design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, and a process hierarchy from which inspection data has been acquired for the wafer, another process. Grouping defects in a hierarchy or some combination thereof, based on one or more attributes of inspection data previously acquired for a wafer, another wafer, or some combination thereof, for design data, other design data, or some combination thereof. Binning. In this manner, attributes determined from previously collected inspection data for the same or different wafers, the same or different designs, and the same or different process layers may be included in the binning operation. Test data previously collected may be stored in a data structure or included in a knowledge base that may be configured as further described herein. In this manner, one or more attributes of previously acquired test data may be determined from cumulative learning data, historical data, or a training set of data. In this embodiment, one or more attributes of the design data may include any attribute of the design data described herein. In addition, one or more attributes of the inspection data used for binning may include any of the attributes of the inspection data described herein. Defects can be binned in this embodiment using any other information described herein. Binning in this embodiment can be performed as further described herein.

In any of the embodiments described above, binning can be performed on-tool, off-tool, or any combination thereof.

In a further embodiment, as shown in step 28, the method combines the location of the design data within the design data space and other inspection results (eg, iDO results and iADC results) to design a design such as a yield impact associated with the design data. Based on one or more attributes of the design data in the data space, the method may include selecting at least a portion of the defect for review. One or more attributes of the design data used to select the defect for review may include any of the attributes of the design data described herein. In addition, the position of the inspection data in the design data space can be used for positioning the defect in the design data space as described herein, which can be used for the attribute determination of the design data corresponding to the defect as described herein. . In some such embodiments, the Newson's defect can be filtered from other defects as described herein, and the DOI (or non-Newson's defect) can be maintained for review or further analysis. In another embodiment, the defect list and the identified hot spots, classification of defects and hot spots, and design context can be used to improve review sampling (which may include sub-sampling) in the monitoring phase, which is an on-tool Or off-tool during post-processing.

In another embodiment, defect selection for review is performed as a function of binning results. For example, defects in some groups may be selected for review while defects in other groups may not be selected for review. In another example, some groups of defects may be sampled more heavily than other groups (ie, more defects from some groups may be selected for review). The group of sampled defects and the degree to which the groups are sampled may be determined, for example, based on one or more attributes of the design associated with each group or any other information described herein associated with the group of defects. The selection of defects for review can be performed as a function of yield relevance associated with defects or defect bins. For example, a population of defects may be divided into random defects and systematic defects, and different sample plans may be used for each different defect type. In this way, sampling strategies for other types of defects can be very different.

In some embodiments, the method further comprises selecting at least a portion of the defect for review, including at least one defect located within each portion of the design data in the design data space having another value of one or more attributes of the design data. It may include. In this manner, defects in each other portion of the design data can be sampled for review. For example, the context of each defect may be used to classify the defects for review (eg, by threshold of context) to produce a review sample that ensures that all contexts in which the defect was detected are represented by a review sample. .

In a further embodiment, as shown in step 30, the method includes determining a sequence in which defects are reviewed based on the location of inspection data in the design data space and one or more attributes of the design data in the design data space. Include. For example, the method may include using a context map to classify defects based on priorities for offline review (eg, optical or SEM review). The context of each defect may classify the defects for review so that systematic and potential systematic defects are given a higher priority than other defect types (eg, by the context's threshold).

In order to provide sub-pixel alignment of inspection data at all points on the wafer, aligning the inspection data stream at a given alignment site at a sample point across the die on the wafer provides several advantages. For example, because the raw data stream is aligned substantially precisely with the design data, the defect location within the design data space can be determined with sub-pixel accuracy (eg, less than 100 nm accuracy versus 1000 nm accuracy currently achievable). Substantially high accuracy of defect location can greatly improve the precision of any subsequent review process and the speed at which defects can be located, imaged and analyzed in the SEM or FIB system. In addition, the contextual information related to the defect can be used in an HRDC step that can be performed in the inspection system in the second pass review or in an off-line SEM or optical review station. Such information may be provided to or obtained by another system, such as an automatic defect location (ADL), in addition to other local context information about the defect that may help to locate the defect automatically or manually. In addition, the review system may use such information to generate logic for the appropriate physical coordinate transformations for the wafer and the system under measurement parameters.

In some embodiments, the method comprises one of the outputs from one or more detectors of the inspection system, acquired for other portions of the wafer, based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. And extracting the above predetermined attribute. In this manner, the method includes a predetermined signal or image for an inspection data area (eg, a particular subset of the area being inspected) based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. And extracting the attribute. The extraction attribute of the output from one or more detectors may include, for example, the luminance or standard deviation of the signal or image relative to the pixel at other sites. The wafer may also be a patterned wafer with a pattern corresponding to the design data printed thereon. Thus, the attributes of the output can be extracted based on the information about the output corresponding to the pattern formed on the wafer. In addition, information about the structure in the pattern formed on the wafer can be extracted from the output from one or more detectors.

The extracted attribute of the output from the detector can be used to generate an image of the attribute across different portions of the wafer. In this manner, the method may include generating a "design aware image" of the surface of the wafer. The image can be used to determine one or more properties of the wafer, such as properties of the wafer that can be determined by metrology. In this way, the inspection system can be used similarly to metrology tools by extracting the attributes of the output from one or more detectors at substantially precisely defined locations based on the design data or the layout for the design data. Thus, other portions of the wafer can be treated essentially as metrology sites in this embodiment. In addition, one or more extracted predetermined attributes of the output from one or more detectors of the inspection system may be prepared by the steps described in co-owned US patent application Ser. No. 60 / 772,418 (Kirk et al., Filed Feb. 9, 2006). The same may be used to perform one or more steps, the patent documents of which are incorporated by reference as if fully set forth herein.

One or more attributes of the design data used in this embodiment may include any attribute of the design data described herein. In one such embodiment, one or more attributes of the design data may be applied to the design data, other design data, or some combination thereof, in the process layer, other process layer, or some combination thereof from which the inspection data for the wafer was obtained. Is selected based on one or more attributes of previously acquired inspection data for a wafer, another wafer, or a combination thereof. In this manner, one or more attributes of the design data in the design data space used in this embodiment may differ from attributes of previously collected inspection data from the same wafer or another wafer for the same or different designs for the same or different process layers. You can choose based on the correlation. Previously collected design data may be stored in a data structure or included in a knowledge base that may be configured as described herein. In this manner, one or more attributes of the design data may be selected in this embodiment based on cumulative learning, historical data, or training set of data.

In another embodiment, the method further comprises one of the inspection system acquired for another portion of the wafer based on the location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. Extracting at least one predetermined attribute of the output from the at least detector. One or more attributes of the design data used in this embodiment may include any attribute of the design data described herein. In addition, one or more attributes of the inspection data may include any attribute of the inspection data described herein. For example, in one embodiment, the one or more attributes of the inspection data include one or more image noise attributes, whether one or more defects were detected at other sites, or some combination thereof. In this manner, one or more attributes of the inspection data may include, but are not limited to, detection / non-detection of image noise features and / or defects in the inspection data area. Extracting one or more predetermined attributes of the output may be performed as further described herein. In addition, the extracted attributes of the output can be used as described further herein.

Each embodiment of the method described herein may include any other step of any of the methods described herein. In addition, each embodiment of the method described above may be performed by any other system described herein.

15 illustrates another embodiment of a computer-implemented method for determining the location of inspection data in a design data space. It should be noted that the steps shown in FIG. 15 are not essential to the embodiment of the method. One or more steps may be excluded from the method shown in FIG. 15, and the method may still be implemented within the scope of this embodiment.

The method shown in FIG. 15 can be used generally for CBI. In this embodiment, data preparation step 42 includes creating a database 44. Database 44 includes a CAD layout for design data and a context hierarchy for design data. Database 44 may have any suitable configuration known in the art and may include any other data or information described herein. In addition, the data in database 44 may be stored in any other suitable data structure. The database 44 may be created by the software 46 using the GDSII file 48 and the context layer 50 as input. The software 46 may include any suitable software known in the art. In general, software may use program instructions (shown in FIG. 15) that may be executed on a processor (not shown in FIG. 15, but may be configured as described further herein) to create a database using a GDSII file and context hierarchy. Not shown). Context layer 50 may be acquired or generated in any manner known in the art, and may include any context information or data described herein. In addition, the GDSII file 48 may be replaced with any other suitable data structure in which design data is stored.

The method shown in FIG. 15 also includes a recipe setup step 52. Recipe setup step 52 includes step 54, which may be performed to determine alignment information 56. Step 54 may include scanning a die on a wafer, which may be performed by an inspection system configured as further described herein. Step 54 may also include selecting an alignment site on the wafer using the information obtained by scanning the wafer. The alignment site on the wafer is selected as described herein. In addition, the alignment site on the wafer can be selected based on the inspection swath layout information 58 and any other suitable information as described further herein. The inspection swath layout information may include any swath information described herein and may be determined as described herein. The selection of alignment sites on the wafer can be performed automatically, semi-automatically (or user-assisted) or manually as described further herein.

Step 54 may include rendering an image or obtaining other suitable data corresponding to the alignment site on the wafer from the CAD layout information in the database 44. For example, step 54 may correspond to a CAD corresponding to the selected alignment site on the wafer to render the appropriate data or image, or to compute a value of a structural feature attribute, such as the center of a particular feature that may be aligned to the alignment site on the wafer. It may include using the patch 60. Step 54 may also include calculating an (x, y) mapping from the CAD layout information of the alignment site on the wafer to the information obtained. Alignment information 56 includes the data for a given alignment site and the (x, y) location of the given alignment site in the design data space.

The method shown in FIG. 15 may include a wafer inspection step 62. Wafer inspection step 62 may include an initialization step 64 and a drive step 66. As shown in step 68, during the initialization step 64, the method includes alignment information 56 including information about the given alignment site and the (x, y) location of the given alignment site in the design data space. It may include the step of preloading (preloading). As shown in step 70, the initializing step may also include preloading the context layer 72 from the database 44. The initialization step may also optionally include rendering data for a given alignment site from polygon to pixel, as shown in step 74, which may be performed as described herein. Context layer 72 may include any context information described herein.

During the driving step 66, as shown in step 76, the method includes performing alignment and mapping of inspection data into the design data space. This step can be performed during inspection of the wafer. Alignment and mapping may be performed as described further herein. The driving step may also include applying a mapping to the context map as shown in step 78. Context data may be mapped as described further herein. The driving step may include applying a context map to the inspection data during the inspection, as shown in step 80, which may be performed as described herein. The driving step may also include mapping the defect coordinates to the context map, as shown at step 82, which may be performed as described herein. The act of driving includes an additional step 84 which may include filtering detection data by context, classifying defects, generating a review sample, other steps described herein, or some combination thereof. It may include. Each additional step 84 may be performed as further described herein. Each embodiment of the method shown in FIG. 15 may include any other steps described herein. In addition, each embodiment of the method shown in FIG. 15 may be performed by any of the systems described herein.

Program instructions implementing methods such as those described herein may be transmitted over or stored on a carrier medium. The carrier medium may be a storage medium such as a ROM, RAM, magnetic or optical disk, or magnetic tape.

16 illustrates various embodiments of a system configured to determine the location of inspection data within a design data space. In one embodiment, the system includes a storage medium 86 that includes design data (not shown in FIG. 16). Storage medium 86 may also include any other data and information described herein. Storage media may include the storage media described above or any other suitable storage media known in the art. In this embodiment, the system also includes a processor 88 that is faulty to the storage medium 86. Processor 88 may be coupled to storage media in any manner known in the art. In this embodiment, the system may be configured as an independent system that does not form part of a process, inspection, instrumentation, review, or other tool. In such embodiments, the processor 88 may be configured to receive and / or obtain data from another system by a transmission medium that may include "wired" and / or "wireless" portions. In this manner, the transmission medium can act as a data link between the processor and another system. In addition, the processor 88 may transmit data to another system via a transmission medium. Such data may include, for example, design data, context data, the results of the methods described herein, inspection recipes or other recipes, or some combination thereof.

Processor 88 may take various forms, including a personal computer system, mainframe computer system, workstation, image computer, parallel processor, or any other device known in the art. In general, the term “computer system” may be broadly defined to include any device having one or more processors that execute instructions from a memory medium.

However, in other embodiments, the system includes an inspection system 90. The inspection system 90 is configured to acquire data for alignment sites on the wafer 92 and inspection data for the wafer. In an embodiment of a system that includes an inspection system, processor 88 may be coupled to the inspection system in any manner known in the art. For example, the processor 88 may be coupled to the detector 94 of the inspection system 90 such that the processor may receive inspection data generated by the detector and data at the alignment site on the wafer. In addition, the processor may receive any other output of the detector, such as image data and signals. In addition, when the inspection system includes an anomaly detector, the processor may be coupled to each detector as described above.

The processor 88 is configured to align the data obtained by the inspection system with respect to the alignment site on the wafer to the data for the predetermined alignment site. The processor may be configured to sort the data according to any of the embodiments described herein. The processor 88 is also configured to determine the position of the alignment site on the wafer within the design data space based on the position of the predetermined alignment site in the design data space. The processor may be configured to determine the location of the alignment site on the wafer within the design data space in accordance with any of the embodiments described herein. The processor 88 is also configured to determine the position of the inspection data acquired for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. The processor may be configured to determine the location of inspection data within the design data space in accordance with any of the embodiments described herein. The processor may be configured to perform other steps of any method embodiment described herein.

In one embodiment, the inspection system 90 includes a light source 96. The light source 96 may include any suitable light source known in the art. Light source 96 may be configured to direct light to beam splitter 98. Beam splitter 98 may be configured to direct light from light source 96 to wafer 92 at a substantially perpendicular angle of incidence. Beam splitter 98 may include any suitable optical element known in the art. Light reflected from the wafer 92 passes through the beam splitter 98 and proceeds to the detector 94. Detector 94 may include any suitable detector known in the art. The output generated by the detector 94 can be used to detect defects on the wafer 92. For example, processor 88 may be configured to detect defects on wafer 92 using the output generated by the detector. The processor may use any method and / or algorithm known in the art to detect defects on the wafer. During the inspection, the wafer 92 is placed over the stage 100. Stage 100 may comprise a suitable mechanical and / or robotic assembly known in the art. The inspection system shown in FIG. 16 may include any other suitable element (not shown) known in the art.

As shown in FIG. 16, the inspection system is configured to detect mirror reflected light from the wafer. In this manner, the inspection system shown in FIG. 16 is configured as a BF inspection system. However, the inspection system may be replaced with an inspection system configured as a DF inspection system, an EC inspection system, an aperture mode inspection system, or any other optical inspection system known in the art. In addition, the inspection system shown in FIG. 16 may be configured to perform DF inspection by changing the angle of incidence of light directed to the wafer and / or the angle at which light is collected from the wafer. In another example, the inspection system may include one or more optical elements (not shown) such as apertures within the illumination path and collection path, such that the inspection system may perform an EC mode inspection and / or aperture mode of inspection. It can be configured to be.

In addition, the optical inspection system shown in FIG. 16 may include commercially available inspection systems such as 2360, 2365, 2371 and 23xx available from KLA-Tencor. In another embodiment, the optical inspection system shown in FIG. 16 may be replaced with an electron beam inspection system. Examples of commercially available electron beam inspection systems that may be included in the system shown in FIG. 16 include the eS25, eS30 and eS31 systems from KLA-Tencor. The embodiment of the system shown in FIG. 16 can be further configured as described herein. In addition, the system may be configured to perform any other step of any method embodiment described herein. The embodiment of the system shown in FIG. 16 has all the advantages of the method embodiments described above.

The methods and systems described above generally perform alignment of inspection data and design data by aligning data (e.g., BF patch images) acquired for alignment sites on a wafer with data for a given alignment site (e.g., GDSII files). do. Additional methods and systems described herein generally perform alignment between inspection data and design data, and use techniques such as statistical techniques (eg, no patch image or SEM image) to provide similarity between different defects. Decide

Embodiments described herein may be used for context-based setup, inspection, binning, review, measurement, test, analysis, or some combination thereof. The context data used in the embodiments may be a design database or file (eg, GDS file, OASIS file, open access file, net-list, etc.); Process simulation results; Electrical simulation results; Pattern of interest (POI); Hot spot information (eg, OPC, electrical test results, inspection results); It may include design data or information about the design stored in a data structure, such as process tool data (work in progress) or some combination thereof. Predicting a yield impact of one or more defects and / or one or more groups of defects based on the results produced by the step of predicting the yield impact may be performed as further described herein. In addition, the embodiments described herein may be advantageously used to provide relatively fast, executable, yield related information.

The information described here can be used to group defects detected by inspection systems that inaccurately determine defect location coordinates (ie, actual defects may be located near the reported coordinates but not exactly at the reported coordinates). Can be. For example, the methods and systems described herein can be used to search for patterns that are at least similar to those reported near the reported defect locations by attempting to align the patterns with respect to each other, whereby the defect coordinates reported by the inspection system are perfect. This allows for improved grouping of defects even when they are not accurate. In another example, the acquired review image (eg, SEM image) or inspection image close to the reported defect location is a design close to the defect and the actual location of the defect within the wafer space (as opposed to the location of the defect reported by the inspection). To determine the exact representation of the data, it can be compared to or overlaid with the design data. At least all instances of a similar pattern are identified in the design data (including rotated, flipped, or otherwise tilted instances of the pattern) and binned into a group of patterns. The actual defect locations in the wafer space determined as described above are compared with the positions for the pattern group, and the defects located at the positions for the pattern group within a predetermined tolerance are binned into groups. Such grouping of defects can be performed on-tool or off-tool and can improve the performance of the method described herein (e.g., if there are coordinate inaccuracies in the defect location coordinates reported by the inspection) In particular, in coordinate inaccuracy, the source pattern determined based on the reported inspection coordinates is an approximate source pattern (as long as the pattern is isolated or the coordinates of the defect are not substantially accurate). Of course, the embodiments described herein can be used as inspection results generated by high precision inspection systems.

One embodiment relates to a computer-implemented method of binning detected defects on a wafer. In general, in the method described herein, a population of defects selects a source defect and design data close to the location of the source defect in the design data space (“source design data”) is close to the location in the design data space of the target defect. Design data by comparing it to design data (“target design data”) (eg, all or part of a defect population) and assigning target defects to target design data when there is a match or at least similarity between the compared design data (Eg, GDS design data). The comparison can be based on a direct comparison of the source and target design data. The comparison can also be performed after minor coordinate inaccuracies between the source defect and the location of the target defect in the design data space have been corrected. The comparison may also include retrieving source design data within the target design data to account for coordinate inaccuracies at the source and target defect locations. Alignment and retrieval can be improved by using a sub-pixel alignment technique that can be performed as described herein. Further, comparison of the source and target design data may be performed to determine if there is an exact match between the source and target design data, or a similar but inaccurate match between the source and target design data. Each of the steps described above may be further performed as described herein.

After the target defect population has been tested for source defects, the following source defects can be selected. Defects not yet grouped are selected as the next source defect. The above steps may be repeated until all the defects are grouped (or at least tested). The defect population used in the methods described herein may include all defects detected on a wafer and include all defects detected on a plurality of wafers, or a subset of defects detected on one or more wafers (eg, on one or more wafers). Defects detected and identified as being close to the hot spot. In addition, the methods described herein may be performed on the entire defect population or on a subset of defects within the entire defect population (which may be selected based on design functional blocks such as logic, memory, etc.). Binning can be performed with automatic single-pass or multi-pass grouping.

The method includes comparing a portion of design data close to the location of a defect in the design data space. For example, as shown in FIG. 17, the method replaces a portion 102 of the design data (not shown) close to the position of the defect 104 in the design data space 106. And comparing the portion 108 of the design data (not shown) close to the location of the < RTI ID = 0.0 > Defect 104 is referred to herein as a "source defect" and defect 110 is referred to herein as a "target defect". Design data close to the location of a defect in the design data space defines background pattern data or background information about the defect.

As shown in FIG. 17, the portion 102 is larger than the defect 104. The dimensions (in the x and y directions) of the portion 102 can be selected by the user. Also, portion 108 is larger than defect 110. The dimensions of the portion 108 can also be selected by the user. The dimensions of the portion 108 are typically larger than the dimensions of the portion 102 as further described herein. Alternatively, the dimensions of the portions can be selected (eg, automatically) by the computer-implemented method described herein.

In one embodiment, the dimension of the portion (in the x and y directions) detects a defect, one or more attributes of the inspection system, one or more attributes of the design data, a defect size, a defect size error of the inspection system, or some combination thereof. Based at least in part on the location of the defect reported by the inspection system used to do so. For example, the method may include defining a portion of defect data (ie, a "pattern window") centered on the reported defect location. The pattern window may have a width and height greater than the dimension of the defect and is selected to account for errors in the defect location due to coordinate uncertainty. For example, if the coordinates of the defect location reported by the inspection system are accurate to about +/- 3 μm, then the pattern window is taken from the x and y coordinates of the reported defect location for an overall minimum size of about 6 μm × about 6 μm. It may be specified to include at least 3 μm in all directions. In this way, the better the coordinate accuracy of the inspection system, the smaller the pattern window can be, which results in faster and more accurate grouping. The dimensions of the pattern window may be selected such that the pattern window contains a sufficient amount of background pattern data, such as a sufficient number of features in the design data. In addition, if the design data in the pattern window is compared to the clip, the pattern window dimensions may be selected to include the entire polygon that is only partially included in the clip.

The portion of design data used in the methods described herein may include a clip of the design taken around the location of the defect in the design data space. The term "clip" is generally defined as an area in the design data around the defect and can be considered as a vicinity of the defect. Polygons define a pattern within a clip, but polygons may extend partially beyond the clip. Clips used in the methods described herein for some of the defects may have one or more other dimensions. However, the portion of the design data used in the methods described herein may include design data in an extended bounding box EBB around the range of portions where the defect may be located. The EBB can be selected based on the coordinate accuracy of the inspection system used to detect the defect and the defect size (and the defect size error of the inspection system). For example, as the coordinate accuracy of the inspection increases, the dimensions of the EBB may decrease. Since the location of defects in smaller EBBs can be more accurately determined than in larger EBBs, smaller EBBs are preferred, and one or more attributes of the defects (eg, the location of defects relative to polygons in the design, classification for defects, and More accurate defect locations within the EBB can be used to determine the root cause. In addition, one or more dimensions of the EBB used for at least some of the defects may be different. EBB is generally smaller than the clip, indicating which defects can be placed).

In other embodiments, the dimensions of at least some of the portions are different. For example, as shown in FIG. 17, the difference between the dimensions of the portion 108 and the defect 110 is greater than the difference between the dimensions of the portion 102 and the defect 104. That is, the area of the target portion around the target defect is larger than the area of the source portion around the source defect. In this manner, the target portion may include more design data than the source portion.

The source portion of the design data can be compared with other areas of the target portion of the design data. In this manner, the method may include searching for a source portion of design data within the target portion. For example, as shown in overlay 112 of the source portion and the target portion, the source portion of the design data may be compared with one area of the target portion. After this comparison, the position of the source portion relative to the target portion may be changed such that design data in another area of the target portion can be compared to the source portion of the design data. In this manner, the method may include “sliding” the source portion of the design data around the target portion until a match is identified or until all regions of the target portion are compared with the source portion.

Comparing portions of the design data can be performed with any information available for the comparison step. For example, the portion of design data that is compared may be the portion of design data included in a data structure such as a GDS file. In addition, comparing the portions of the design data may include comparing the polygons in the portions. In another embodiment, the method includes converting a portion of the design data close to the location of the defect in the design data space into a bitmap prior to the comparing step. For example, polygons within portions of design data can be converted into bitmaps for rapid processing. Portions of the design data can be converted to bitmaps using any suitable manner known in the art. For example, it can be converted to a bitmap using the methods and systems disclosed in US Patent No. 7,030,997 (Neureuther et al.), Incorporated herein by reference in its entirety. In one such embodiment, comparing the portions of the design data includes comparing the bitmaps with each other. Comparing the bitmaps to each other may be performed using any suitable manner. Also, comparing portions of design data may include comparing one or more attributes of design data within that portion. One or more attributes to be compared can include any attribute of the design data described herein.

The method also includes determining, based on the results of the comparing step, whether the design data in the portion is at least similar (similar or exactly the same). Once one or more attributes of the design data in the portion are determined, the grouping may be based on common pattern similarity, common attribute similarity, common attribute similarity in the feature space, or some combination thereof. For example, in one embodiment, determining whether design data in the portion is at least similar includes determining whether a common pattern in the design data in the portion is at least similar, as further described herein. Can be. In another embodiment, determining whether the design data in the portion is at least similar includes determining whether the common attributes of the design data in the portion are at least similar, which may be performed as described further herein. have. In a further embodiment, determining whether the design data in the portion is at least similar comprises determining whether the common attributes in the feature space of the design data in the portion are at least similar, as further described herein. As can be performed. The method may also include determining how similar other regions exist within that portion. In addition, even if the design data in the portion is slightly offset from each other or includes slightly different design structures, the portions can be determined to be similar to each other when the portions have a significant common structure. The method compares the design data close to the location of each defect in the design data space with the design data close to the location of all the defects in the design data space to determine which defects are similar to each other based on the "background" pattern. It may include the step.

Determining whether the design data in that portion is at least similar is preferably not performed based on whether the defect is located at the same location in the design data. That is, defects binned into groups based on their "background" by the methods described herein may not need to be located at the same location relative to the pattern, feature, polygon, or structure in the design data. Without relying on the matching of the location of the defects to the design data, the method can provide more accurate defect binning. For example, two defects may be present in the same type of pattern, but may be located at different locations within the pattern. In addition, systematic defects in the POI may be localized, but may also not be localized. However, such a defect can be caused by or related to the same pattern based issue. Thus, defect binning that does not rely on similarities between actual defect locations in the design data can allow for more accurate binning, which can be used for control and prediction of yield based on these systematic issues and for more accurate demonstration of systematic issues. Can be. Determining whether portions of design data are at least similar may be performed using any suitable algorithm. Thus, the method can be used as a "similar checker". Since the target portion can be larger than the source portion compared to the target portion, the similarity checker can be advantageously used when there is coordinate inaccuracy at the actual defect location in the design data.

In the embodiment shown in FIG. 17, the entire source portion is compared with other regions of the target portion. In some embodiments, the method includes comparing all of the design data in at least a portion of the portion to design data in another portion. The method may also include comparing the entirety of the source portion of the design data to another area of the target portion of the design data. As such, the method may include searching for a target portion for design data that is at least similar to the entire source portion of the design data.

The method further includes binning the defects into groups such that portions of design data close to the location of the defects in each group are at least similar. In this manner, the method includes binning the defects into groups based on the context of the design data and / or the design data close to the location of the defect in the design data space. For example, to bin defects into groups in a non-supervised manner, polygons in portions of at least similar or matching design data may be used. In addition, the binning step may include binning the at least two defects into at least one group such that design data close to the location of the at least two defects in the at least one group is at least similar. Further, in the rare instance where there is no part of the design data close to the location of the defect in the design data space that is determined to be at least similar, the method does not bin the defect into groups.

The method also includes storing the results of the binning step in a storage medium. The result of the binning step may include any result described herein. The storing step may also include storing the result of the binning step in addition to any other results of any of the steps of any of the method embodiments described herein. The results can be stored in any other way known in the art. In addition, the storage medium may include any storage medium described herein or any other suitable storage medium known in the art. After the results are stored, the results can be accessed and used within the storage medium by any method or system embodiment described herein. The result can also be stored "permanently", "semi-permanently", temporarily or for some period of time. For example, the storage medium may be RAM, and the result of the binning step may not need to remain in the storage medium.

Determining whether portions of design data are at least similar may include comparing the result of the comparing step with a predetermined criterion for similarity. For example, the result of the comparing step can be compared with a threshold. If the design data in that portion is at least similar by at least such a threshold, the method may bin the defects into groups. In another example, the result of the comparing step can be compared to a "percent similar" value. If the design data in that portion is at least similar by at least that percentage, the method may bin the defects into groups.

In any case, the similarity check is performed between two or more portions of the design data (eg, a GDS pattern clip), and if a common pattern within the two or more portions is identified, the method includes binning the defects into groups. do. The result generated by determining whether the design data in the portion is at least similar may include an indication of whether the design data in the source portion was found in the target portion. In addition, the center point of the common structure can be considered to be close to the design data space location of the systematic defect. Thus, the (x, y) coordinates of the design data space locations of the defects in each group can be adjusted (moved) to the center point of the structure corresponding to each group. A coordinate correction vector (or error vector) may be determined for each binned defect based on the design data space coordinates of the defect and the center point of the common structure corresponding to the group in which the defect is binned. In order to determine the overall systematic uncertainty (design data space movement error + wafer space for errors in the reported coordinates) in the design data space coordinates of the defect location, the method uses a shift or error vector for a statistically significant number of defects. Determining the average of the. The method may also include determining a standard deviation of all error vectors and determining an average of the vector only within +/- 1 standard deviation or within +/- 3 standard deviations. In this way, outliers that can damage the mean value can be removed from the operation. The determined average value can be used as a global correction value. For example, this global correction value is applied to additional design data space coordinates of the defect location determined by wafer space in order to design the data movement so that a more accurate overlay can be determined in subsequent data processing steps.

The result of the determining step may also include an x and y offset between the target portion and the position of the source portion within the target portion where at least similar design data is found. The x and y offsets can be used to optimize the binning method. For example, upon initial comparison of the portions, the source portion may be positioned to align the center points of the two portions within the target portion. However, if it is determined that there is some predictable or repeatable offset (in the x and / or y direction) between the initial use position of the source portion within the target portion and at least the position of the source portion within the target portion where similar design data is found. This offset can then be used to adjust the overlay used in the comparison step of the binning method.

In some embodiments, the design data in the portion includes design data for one or more design layers. In this manner, the method checks one design layer for background similarity of the defect and bins the defect, or checks the set of design layers for the background similarity of the defect (ie, multi-layer background similarity). And binning. For example, during the inspection of the polysilicon layer (eg, gate electrode layer) on the wafer, the underlying diffusion layer may be visible to the inspection system, thus affecting the inspection results. As such, the design data included in that portion may include design data for the polysilicon layer and the diffusion layer to increase the accuracy of the background based binning. However, by using design data for one or more design layers, defects located at least similar but close to portions of design data located above non-like design data on the underlying layer can be binned into other groups.

Regardless of whether design data in the source portion is found in the target portion, the method may include comparing the source portion with another portion of the design data close to the location of another defect in the design data space. Since one or more target defects located at least similar to or close to the design data in the source portion can be detected on the wafer, comparing the design data in the source portion to the design data in the multiple target portions can be performed.

In one such example shown in FIG. 17, portion 102 may be compared to portion 114 of design data (not shown) close to the location of defect 116 in design data space 106. The dimensions of the portion 114 can be selected as described above. The source portion of the design data may be compared with the design data in other areas of the target portion as further described herein. The method may include determining whether the design data in the source portion is at least similar to at least a portion of the design data in the target portion, which may be performed as described above. Overlay 118 of the portions shows the location of the source portion within the target location where at least similar design data was found. Thus, the method includes binning defects 104 and 116 into one group because it is determined that the design data in portion 102 is at least similar to at least a portion of the design data in portion 114. Further, since it is determined that the design data in the source portion is at least similar to at least some of the design data in both target portions, the defects 102, 110, and 116 are binned into one group.

In another such example, portion 102 may be compared to portion 120 of design data (not shown) near the location of defect 122 in design data space 106. The dimension of the portion 120 may be selected as described above. The source portion of the design data may be compared with the design data in other areas of the portion 120 as described above. The method also includes determining, based on the comparison result, whether the design data in the portion 102 is at least similar to at least a portion of the design data in the portion 120, which may be performed as described above. Overlay 124 of portions 102 and 120 shows the location of portion 102 within portion 120 where at least similar design data is found. Thus, the method includes binning source defects and target defects 112 into one group. Further, since it is determined that the design data of the source portion is at least similar to at least a part of the design data of the three target portions, the source defects and the three target defects are binned into one group. The above steps may be performed until the background information for each defect detected on the wafer is compared with the background information for all other defects detected on the wafer.

As noted above, the method is based on the design data and / or the context of the design data located close to the location of the defect in the design data space, possibly in combination with other information, such as one or more attributes of the design data and / or design layout. Thereby binning the defect. In contrast to other methods of binning defects based on contextual information, the method described herein does not perform binning based on background information as printed on a wafer. Instead, the method described herein performs binning based on background information as defined in the design data. In this manner, the method described herein can perform background based binning regardless of how the design data is printed on the wafer or not.

Such independence from design data as printed on a wafer can be particularly beneficial for the PWQ method and the focus exposure matrix (FEM) method, in which design data as printed on the wafer is used for such a method. It may vary (sometimes dramatically) over process window parameters, thereby degrading the accuracy of the defect binning method based on the image of design data printed on the wafer. In one such application of an experimental technique such as PWQ, the method can provide improved background based binning by using an excerpt of defect data or a GDS clip at the location of the defect in the design data space. As such, binning can be performed by a common pattern. Bind defects can be classified individually or collectively as described further herein. For example, the method may include classifying the defects based on one or more attributes of the design data (eg, one or more attributes of the design data located proximate to the defect location in the design data space), which is further described herein. As can be done.

Since the defect detected on the wafer is binned by design data close to the design data space location of the defect, the location of the defect in the design data space can be determined before binning is performed. In one embodiment, the method includes acquiring (or determining a movement function) data for the x and y coordinates of the location of the detected defect in the design data space, which is performed as described herein. can do. In another embodiment, the method includes determining a location of a defect in the design data space by comparing the data obtained by the inspection system for the alignment site with data for a given alignment site. Acquiring data for the alignment site on the wafer may include using product layout data, optionally reticle frame data, and stepper data (or input to the stepper) to determine the appropriate wafer space location of the alignment site on the wafer; And acquiring data at the appropriate location. Such comparison and determination steps can be performed as described above. The method may also include determining the location of at least a portion of the defect in the design data space by comparing the data acquired by the inspection system with respect to the alignment site on the wafer and the data for the predetermined alignment site. The location determined for at least a portion of the defect can be used to determine the location of another defect in the design data space (eg, by creating and using a transform to move the reported defect location into the design data space). Determining the location of a defect in a design data space can be performed according to any of the embodiments described herein.

At times, all of the foregoing data may not be available, or the wafer may not be properly aligned in accordance with the design data. In such instances, it may be useful to experimentally determine some of the conversion information from the wafer during inspection or review. In one embodiment, the method determines the location of the defect in the design data space by comparing the data acquired by the inspection system during detection of the defect to the data acquired by the review system at a location in the design data space determined by the review. It includes. In this manner, the method may include aligning test results for one or more defects with review results obtained at a design data space location determined by the review. The method further includes determining the design data space position of at least a portion of the defect by comparing the data acquired by the inspection system during inspection of the defect to the data acquired by the review system at a position in the design data space determined by the review. It may include. The location determined for at least a portion of the defect can be used to determine the location of another defect in the design data space (eg, generating and using information to move the reported defect location to the defect location in the design data space). However, this approach provides a wafer scale offset that can be complicated by the coordinate inaccuracy of the inspection system. Thus, if there are coordinate inaccuracies within the reported location of the defect, it may be advantageous to base the transform function on a statistical sample of the measurement.

After the location of the defect in the design data space has been determined, a portion of the design data around the determined location can be extracted so that the extracted portion of the design data can be used to bin the defect and perform the other steps described herein. Further, before using the extracted portions of the design data for binning, each (or more than one) of the extracted portions is mirrored to produce a set of portions corresponding to and including each of the extracted portions, It can be rotated, scaled, moved (shifted), or some combination thereof. A set of portions can be used for binning to increase the accuracy of the binning method.

The method comprises some combination of dimensions (eg, width) in the x direction, dimensions (eg, length) in the y direction, and dimensions (eg, height) in the z direction, any of the attributes described herein, or the like. Determining one or more attributes of the same detection defect. One or more attributes may be organized and / or stored in any suitable structure, such as a table or list. In another embodiment, binning the defects bins the defects into groups such that portions of design data close to the design data space locations of the defects in each group are at least similar, and one or more attributes of the defects in each group are at least similar. It includes a step. In one such embodiment, the one or more attributes of the defect include one or more attributes, one or more inspection parameters, or some combination thereof, of the inspection results for which the defect was detected. One or more attributes of the inspection results may include, for example, optical modes and / or other inspection parameters such as polarization, acquisition angle, angle of incidence, etc., in which defects are preferentially detected. In addition (or alternatively), the one or more attributes may include any other attribute of the defects described herein. In this manner, binning can be performed to separate defects into design data and defect attributes. Such binning can be performed such that defects with different defect types or other attributes located within at least similar portions of the design data can be separated into different groups.

In some embodiments, binned defects as described herein are detected by optical or electron beam inspection. Optical and electron beam inspection can be performed by the inspection system described herein. In another embodiment, binned defects as described herein are detected in a PWQ or FEM method, which may be performed as described herein. The embodiments described herein may be particularly useful for defects detected in PWQ or FEM methods. For example, the methods described herein can be used to filter out defects detected in the PWQ and FEM methods, so that potential systematic issues can be more easily and accurately identified, which can be performed as further described herein. . In addition, the method embodiments described herein may be used to bin defects detected by the PWQ and FEM methods into useful groups, which may be performed as further described herein. In addition, the method embodiments described herein may be used to prioritize binned PWQ and FEM defects for review, measurement, or testing, which may be performed as further described herein. The method may also include binning inspection and / or electrical test defects into groups based at least on similar design / layout patterns.

In one embodiment, the inspection system used to detect binned defects in the embodiments described herein may be aligned to three or four alignment sites on the wafer. In addition, the alignment site may be selected as described further herein. In addition, one or more alignment features, patterns, and / or structures visible on the physical wafer or within the design data or layout may be selected for use in the methods described herein. After the inspection system is aligned at the alignment site, stage position accuracy, any rotational error, x and y movement error, magnification (scaling) error, or any combination thereof can be corrected. Such correction may occur during the inspection process or may be performed in a post-process (eg, performed after the inspection results are generated). The correction may be based at least in part on the comparison of the coordinates for the alignment sites reported by the inspection system and the reference coordinates for the same alignment site.

In some embodiments, the method may include obtaining coordinates for three or four alignment sites in multiple dies on the wafer, such as dies on the left, right, top, bottom, and center of the wafer. In another embodiment, the alignment sites on the wafer are located at three different sites on the wafer. One such embodiment is shown in FIG. 18. As shown in FIG. 18, the wafer includes a plurality of dies 128. Alignment site 130 may be located within dies 128a, 128b and 128c. While the measurement site is shown on only three dies, it should be understood that the alignment sites can be located on each die on the wafer. A subset of alignment sets in each die or alignment sites in a subset of dies can be used in the methods described herein.

The method may include identifying three common alignment sites (ie, alignment sites common to die and printed design data (eg, GDS layout) printed on a wafer) with a triangular distribution within the die. For example, as shown in FIG. 18, alignment sites 130 are arranged in a triangular distribution within dies 128a, 128b and 128c. In one such embodiment, three different dies may be distributed across the wafer in a predetermined arrangement (eg, triangle or other arrangement). For example, as shown in FIG. 18, dies 128a, 128b and 128c are positioned in a triangular arrangement 132 on wafer 126. In this manner, the method may include aligning the alignment image (eg, BF and / or DF image) acquired by the inspection system with respect to the alignment site on the wafer to the data for the given alignment site. The method may include mapping coordinates of inspection data obtained by the inspection system to design data coordinates (eg, GDS coordinates) and developing a transformation matrix. Is expressed as:

The coordinates of these alignment sites can be used to perform (eg, automatically perform) "tool matching" to eliminate coordinate differences between inspection systems. One advantage of such a method is that it can be determined individually and automatically for every test wafer, creating a set of correction factors per wafer. Another advantage of such a method is that the coordinates determined are coordinate drift in the inspection system or other inspection system across the wafer (e.g., errors caused by cumulative errors, stage shift errors, and mechanical, electrical and thermal noise) ( Otherwise it can be used to determine the accuracy of alignment of the inspection data with respect to the design data.

As noted above, comparing the design data in the portion may include comparing all of the design data in at least a portion of that portion to design data in another portion. In this manner, such comparison results can be used to determine whether all of the design data in the source portion is at least similar to at least some of the design data in the target portion. However, in alternative embodiments, comparing the design data in the portion may include comparing the design data in at least a portion of the portion with the design data in the other portion, as further described herein. Can be done. In addition, the design data in the plurality of regions of the source portion may be at least similar or identical to the design data in the region of the target portion, and the result of the comparison is a design in the source portion that is at least similar or identical to the pseudo-size region of the design data in the target portion. Can be used to identify the maximum area of data. In this manner, the method may include determining whether design data close to the location of the target defect and the source defect in the design data are “similar” or at least similar. Thus, this method may be more effective at certain design layers in the background based binning of defects as described herein.

One such embodiment of the method is shown in FIG. 19. For example, as shown in FIG. 19, the method may include defining a portion 134 of design data (not shown) close to the location of the defect 136 in the design data space 138. The defects 136 are referred to herein as "source defects. &Quot; Defining a portion 134 of design data may include selecting a dimension of the portion, which may be performed as described further herein. The method may also include separating, segmenting, or partitioning portions of design data into one or more other regions. For example, as shown in FIG. 19, portion 134 may be divided into four different regions 140, 142, 144, and 146. Another portion where portion 134 is separated inwardly may be referred to as a "source quadrant" in this example. Although portion 134 is shown as being divided into four source quadrants in FIG. 19, it should be understood that the portion may be divided into any suitable number of regions. All regions may have the same size, or all or some of the regions may have different sizes.

In this example, the method includes comparing design data in source quadrants 140, 142, 144, and 146 to design data (not shown) close to the location of defect 150 in design data space 138. do. The defect 150 is referred to herein as a "target defect". As shown in FIG. 19, portion 148 is larger than defect 150 and at least as large as portion 134. The dimension of the portion 148 may be selected as described above.

The design data in each source quadrant can be compared with the design data in other areas of the target portion. In this manner, the method may include searching for design data in each source quadrant in the target portion. In this example, the method includes determining whether the design data in the source quadrant is at least similar to the design data in the target portion based on the result of the comparing step. For example, the method may include determining how the design data in each source quadrant is similar to the design data in the target portion. As such, it may be determined that the design data in some or all of the source quadrants is at least similar to, or none of, the design data in the target portion. As shown by overlay 152, design data in three of the four source quadrants is in the area of portion 148 at the location of source quadrants 140, 144, and 146 shown within overlay 152. It is determined to be at least similar to the design data.

In this manner, the method may include comparing design data in the source quadrant to design data in the target portion to determine which defects may be binned into at least a group based on corresponding design data. have. The determination of whether the design data in each source quadrant and the target portion is at least similar includes an indication of how many and which of the source quadrants are determined to include at least similar design data in the design data in the target portion. can do. The result of the determining step may also include x and y offsets between the target portion and each source quadrant in the target portion where at least similar design data was found. Whether or not the source defects are binned together with the target defects determines how many and which of the source quadrants contain at least similar design data in the design data within the target portion, and at least the target portion where similar design data was found. Based on the offset between each source quadrant in the target and the target portion, it may be determined.

In some embodiments, the design data in each source quadrant and target portion includes design data for one or more design layers. In this manner, the method includes checking at least one design layer for at least similar design data to bin the defects or at least checking a set of design layers (eg, multi-layers) for similar design data to bin the defects. It may include a step.

Regardless of whether the design data in the source quadrant is at least similar to the design data in the target portion, the method includes comparing each source quadrant with another portion of the design data close to a location in the design data space of the other defect. It may also include.

In one such example, design data in source quadrants 140, 142, 144, and 146 may be compared to portion 154 of design data (not shown) near the location of defect 156 in design data space 138. Can be. Design data in the source quadrant and portion 154 can be compared as described above. The method also includes determining whether the design data in each source quadrant is at least similar to the design data in the portion 154, which may be performed as described above. As shown in overlay 158, two of the quadrants (eg, quadrants 144 and 146) have at least similar design data to those in portion 154 at the positions of the quadrants shown in overlay 158. Is determined to include. Thus, the method may determine whether design data close to the location of defects 136 and 156 in the design data space is less similar to defects 136 and 150. It can be determined as described above whether the design data close to the locations of the defects 136 and 156 in the design data space are similar enough to bin the defects 136 and 156 into the same group.

In another such example, design data in source quadrants 140, 142, 144, and 146 may be compared to portion 160 of design data (not shown) close to the location of defect 162 in design data space 138. Can be. Design data in the source quadrant and portion 160 may be compared as described above. The method also includes determining whether the design data in each source quadrant is at least similar to the design data in the portion 160, which may be performed as described above. As shown in overlay 164, two of the four quadrants (eg, quadrants 142 and 144) are at least partially aligned with portion 160 of design data at the location of the source quadrant shown within overlay 164. It is determined to include similar design data. Thus, the method may determine whether design data close to the position of defects 136 and 162 in the design data space are less similar than design data close to the position of defects 136 and 150 in the design data space. Whether the design data close to the locations of the defects 136 and 162 in the design data space are sufficiently similar to bin the defects 136 and 162 into the same group can be performed as described above.

The quadrant information determined as described above may be stored and / or displayed. This information can be used for setup, verification, and repair of errors.

The method dynamically compiles a table, list or other data structure of a unique pattern in the design data and replaces a portion of the design data close to the location of a defect in the design data space with the pattern in the table, list or other data structure. By comparison, it includes on-tool classification of systematic defects and Newson's defects (eg, defects with or without actual interest). Dynamically generated pattern sets (or static pattern sets) may be stored in a data structure, such as a library, with a design based classification (DBC) associated with each pattern. In this manner, the DBC may define a group in which defects can be binned, and the unique pattern may include a POI design example. As such, design data close to the design data space defect location is compared to the unique pattern in the dynamically generated pattern set, rather than design data close to the other design data space defect locations. For example, one embodiment that may utilize such data structures (which may or may not be generated dynamically) is a computer-implemented method for assigning categories to defects detected on a wafer, which is described below.

In addition, in some embodiments, the computer-implemented method is performed by an inspection system used to detect a defect. In this manner, binning the defect can be performed "on-tool." One advantage of the method is that the time for the result can be quick. The method may be performed on-tool at any time after a defect has been detected (eg, during or after other defects are being detected, during analysis of test results, during review, etc.). In addition, the location (hot spot) of potential systematic defects or systematic defects and the data used for binning are stored in a data structure (eg, hot spot database) and can be used for inspection comparison (monitoring). Thus, binning can be performed during inspection to provide better sorting (binning, filtering or monitoring for search).

In alternative embodiments, the computer implemented method is performed by a system other than the inspection system used to detect the defect. In this manner, the method embodiments described herein may be performed with an "off-tool". Systems that perform the method off-tool are, for example, in the art that can be configured to perform the method, such as a microscope (optical or electron beam), a review system, a system without a wafer (eg, an independent computer system), or a method. And any other suitable system known. For example, the method may be performed after defect detection during a second pass of the wafer where a microscope is used to acquire an image of at least a portion of the detected defect. Such image acquisition can be performed using an optical microscope since the electron beam microscope cannot capture some defects (eg, defects that are not visible to the electron beam microscope, such as defects located below the top surface of the wafer). Image acquisition is performed off-line and can be used to provide better sampling of defects for review. Binning of defects can be used to analyze and sample the defects as described further herein.

In some embodiments, the method includes identifying hot spots in the design data based on the results of the binning step. In this way, design based binning can be used for the search for hot spots. In addition, searching for hot spots can be performed on-tool. The method may include generating a data structure that includes the hot spots found and one or more attributes of the hot spots, such as location, design data close to the location of the hot spots, and the like. Data structures can include lists, databases, files, and the like. Hot spots can be used for hot spot management (possibly on-tool). Hot spot management may include searching for hot spots, which may be performed as further described herein. In addition, hot spots searched by design-based binning can be used as inputs for design scans, PWQ, DOE, and reviews. Alternatively, hot spots used in the methods described herein may be searched using any other method and system known in the art, such as a reticle inspection system.

FIG. 20 illustrates one embodiment of input to and output from module 166 configured to perform a computer-implemented method for binning detected defects on a wafer in accordance with an embodiment described herein. Module 166 may be configured to function as a GDS pattern checker (the location of design data close to the design data space location of any two defects or the accuracy checker of the design data) and / or the similarity checker (non-accuracy checkers). The module is configured to perform one or more steps described herein on- or off-tool. For example, the module may be configured to perform one or more steps described herein in an on-tool post-process (eg, on-tool, post-defect detection). In addition, the module can be configured to perform one or more steps described herein during fault detection. If a module is configured to perform one or more steps described herein on-tool, the module can be configured to perform other functions described herein, such as defect organization.

Input to module 166 includes a defect list 168. In one embodiment, the defect list 168 may include defect information, such as information included in a KLARF file or other standard file that may be generated by the inspection system. The input to the module may also include coordinate transformation information and design data, which may be determined as described above. In such embodiments, the module 166 may be configured to convert the location of the defect in the defect last 168 as reported by the inspection system to the location of the defect in the design data space.

Alternatively, module 166 may be configured to perform functions in wafer space by accessing transformed design data space coordinates provided through other software modules (software modules configured to perform the transform function). In another alternative, the defect list 168 may include the location of a defect in the design data space. In such embodiments, the defect locations reported by the inspection system may be converted to defect locations in the design data space by other software modules. Such defect information may be entered into module 166 via program means or in a suitable data file format on the same computing hardware or between a set of networked computing hardware, via in-process or inter-process communication. In this manner, defect information may be provided to module 166 by another system via a transmission medium that couples the module to another system. The transmission medium may include any suitable transmission medium known in the art, and may include a "wired" or "wireless" transmission medium or some combination thereof.

Additional input (not shown in FIG. 20) may be provided to module 166 that may be used by the module to perform one or more steps of one or more embodiments described herein. Additional inputs include electrical inspection data, defect information for one or more wafers, hot spot or weak spot information ("weak spot" is not limited to model-based simulations such as post-OPC verification software, and not limited to PWQ). Generally defined as the location of a potential weak point in the design identified by an experimental method such as, search box size (e.g., dimensions of the design data portion close to the location of source and target defects in the design data space as described above). Or any other defect and / or design data information available, such as source defect magnification and target defect magnification dimensions), some predetermined criteria for similarity (eg, similarity threshold), or some combination thereof. .

In addition, hot spots can be grouped in advance based on design data. For example, hot spots located at least close to similar design data are correlated with one another, and the method and system embodiments described herein may perform such correlation of hot spots. The correlated hot spots can be used to bin defects as described further herein. In one such embodiment, module 166 may be configured to bin defects into groups such that the defects in each group have locations in the design data space that are at least similar to only those in the hot spots that are correlated with each other. In this manner, the module can be configured to bin defects without using design data. In addition, one or more attributes of the correlated hot spots may be determined for use in later analysis (eg, yield information such as KP may be determined for the correlated hot spots). In this manner, when a defect is binned into a group corresponding to a correlated hot spot, the module may report the expected yield impact determined for the correlated hot spot for the defect group.

Module 166 may be configured to function as a GDS pattern checker by binning defects in defect list 168 by "checking" whether design data close to the location of another defect in the design data space matches. In this manner, module 166 may be configured to bin defects into groups such that defects within each group are located in a design data space close to the matching design data. Further (or alternatively), module 166 may be configured to function as a similarity checker by checking the similarity of design data close to the location of other defects in the design data space and binning the defects in defect list 168. .

The output of module 166 may include output 170. The output 170 includes the x and y coordinates of the defect location as reported by the inspection system, the x and y coordinates of the defect location in the design data space, and the identity of the group where the defects are binned into the same group (eg, 1, 2). , 3, a, b, c, etc.) (eg, if the defects are binned into the same group, their identities may be the same), and design data that matches or at least is similar to the design data in the center and source portions of the target portion Includes, but is not limited to, a shift or offset in the x and / or y directions between the centers of the regions in the target portion where is located. The output may include one or more data structures having any suitable format known in the art (eg, a simple text file format). In addition, the output can be stored in any suitable storage medium known in the art such that the output can later be accessed and / or analyzed. The output can be stored and used as described further herein.

In addition (or alternatively), as shown in FIG. 21, the output of module 166 is designed such that design data close to the location of each defect in the design data space is close to the location of each other defect in the design data space. A table may be included that indicates how similar to the data (eg,% similar). In the example shown in FIG. 21, the portion of the design data close to the position of the defects 1 and 2 in the design data space is 40% similar, but the position of the design data close to the position of the defects 1 and 3 in the design data space. Is 95% similar. In this manner, the method may use the output shown in FIG. 21 to determine which defects to bin into the same group. For example, if a portion of design data close to the location of a defect in the design data space is more than 90% similar, the defects can be binned into the same group. In addition, as shown in FIG. 21, the portion of the design data close to the position of the defect 1 in the design data space is 90% to the portion of the design data close to the position of both defects 3 and 4 in the design data space. The above is similar. In this way, the defects 1, 3 and 4 can be binned into the same group.

In another example, as shown in FIG. 22, the output of module 166 may include a graph (eg, a bar graph) indicating the number of defects (eg, defect count or frequency) as a function of a different group. Each different group includes defects located at design data space locations close to the same or at least similar design data as described above. In this way, the output shown in FIG. 22 provides information as to which pattern in the design is more defective. The chart may provide the error pattern type by various design contexts (eg, background pattern context by functional blocks). The information in the chart may be further divided into annular or angular regions, as described further herein, to provide information regarding the spatial distribution of defects located in the design data space close to the common design pattern. Such information and similar or other information may be used to perform one or more steps of the methods described herein (eg, defect sampling based on background pattern context). Additional information regarding defects binned into each group may be determined using any step of any of the methods described herein.

Module 166 may provide output in only one format shown in FIGS. 20-22. However, the module may provide one or more outputs of the format shown in FIGS. 20-22.

Additional examples of other inputs and outputs of module 166 are shown in FIG. As shown in FIG. 23, one input to module 166 may include a wafer map 172 that indicates the location of a detection defect on the wafer. The wafer map can be generated by the inspection system. The wafer map may indicate the location of the defect on the wafer but does not represent any other information about the defect. For example, bar graph 174 corresponding to wafer map 172 shows all of the detection defects within a single group corresponding to the layer of wafer inspected.

The output of module 166 may include a wafer map 176 that indicates the location of detected defects on the wafer, and defects binned into the same group may have the same characteristics (eg, different colors or different colors for different groups) within the wafer map. Symbol). Defects can be binned as described further herein (eg, automatic grouping of defects by a common GDS layout). In this manner, wafer map 176 indicates the location of individual defects on the wafer and the group of individual defects binned. The output may be sent and used by a spatial signature analysis (SSA) tool such as KLARITY DEFECT SSA, commercially available from KLA-Tencor, to enhance monitoring and root cause determination.

The output of the module may include a stacked die map, a stacked reticle map, or a stacked wafer map, where defects are indicated to represent a group of patterns. Stacked maps can be used to describe how systematic defects tend to occur statistically across multiple dies, reticles, or wafers, and are useful for identifying spatial signatures. In addition, any output of the modules described herein may also include one or more GDS clips, one or more SEM images, one or more optical images, or some combination thereof. The output of the module may be displayed by the same user interface in the user interface embodiments described further herein.

Bar graph 178 corresponding to wafer map 176 represents the number of defects binned into each group. In addition, the layout pattern signature corresponding to each group of defects is the same as that of the bar graph. In this manner, the bar graph shows the pattern in the design that shows (or causes) the most defects. For example, a relatively large number of defects binned into the group of layout pattern signatures 2 indicate a potential pattern dependent error mechanism corresponding to the layout pattern signature. This information can be used to perform one or more steps of the method described herein (eg, defect sampling based on design background context). Additional information about the defects binned into groups can be determined using any step of any of the methods described herein. Module 166 may generate an output that includes wafer map 176 and bar graph 178. The output of the module may be displayed by a user interface such as one of the user interface embodiments described further herein.

One example of how the output of module 166 may be used in the methods described herein is the correlation of different defects with different density regions within the device layout. For example, the device layout can be partitioned into different regions. Different regions can be determined based on the design pattern density of different regions of the device, as shown in FIG. In one example, the main cell blocks within the device may be partitioned into different regions. In another example, the device layout can be automatically partitioned based on the density of various device structures (eg, contacts, vias, metal lines, etc.) over the device layout. In one embodiment, a method embodiment described herein includes determining a defect density for another portion of the design data. For example, the method described herein may use information regarding the partitioning of the device layout to determine the defect density of other parts of the cell in the design data. In one such example, the number of defects detected in each area within the design data can be determined. Such information may be plotted in a bar graph or any other suitable output format.

In another example, module 166 divides the design data into “functional blocks” or “cell blocks”. Cell blocks are defined within the design data and identify the boundaries of major and less major sub-cells of the design, such as input / output (I / O) blocks, digital signal processor (DSP) blocks, and the like. The module determines the frequency of defects in each cell block. In this way, it can be determined whether the major or less major cells in the design are somewhat sensitive to yield issues.

Embodiments described herein may use a statistical approach to determine the design cell in which a defect is located. For example, in some embodiments, the method includes determining if the defect is a systematic defect, determining whether two or more systematic defects are located in one or more portions of the design data, and a correlation exists between the systematic defects and the likelihood. Determining whether or not. In particular, as described further herein, design data (ie, hierarchical design data) may be used in combination with the location of a defect in a design data space to determine a hierarchy of defects in the design data, such as cells in the design data. have. As further described herein, the hierarchy within the design data can be used to determine which portion of the design data can or should be used for yield improvement. One difficulty in determining the hierarchy of defects is that as the cell becomes smaller, the size of the cell becomes smaller than the coordinate accuracy of the inspection system, thereby degrading the accuracy with which the cell in which the defect is located can be determined. To overcome this difficulty, statistics can be used to determine the probability of a defect being placed in various parts of the design data (the probability that each defect is located in a different cell). In this way, for systematic defects, statistics can be used to determine whether there is a correlation between the probability of the defect being located within various parts of the design data and the systematic coupling.

In another embodiment, the input provided to module 166 may include design data (eg, GDS layout), inspection data (eg, physical defect data), and optionally memory bitmap and / or logic bitmap. The module may use some or all of the input to perform one or more additional steps, such as but not limited to search, characterization, monitoring, and disposition (eg, making one or more viable decisions). The module may be configured to perform the aforementioned steps in addition to one or more of the steps described below: generating hot spot / weak spot data structures, defects using design data (e.g., defects detected by optical or electron beam inspection systems) And / or grouping of defects detected by electrical inspection represented by bitmaps, creating a review sample plan, optimizing inspection recipes, changing review recipes (e.g., determining to review), optimizing review recipes Change defect analysis recipes (e.g., by design context in combination with any other information described herein where possible to analyze during in-line FIB processes and / or FA processes), optimize defect analysis recipes, Create sampling recipes for FIB processes, EDX processes, or other defect analysis processes, create sampling recipes for metrology processes, DOI and possibly one or more attributes of the DOI such as type and location. In addition, any sampling plan or sampling recipe described above may be dynamically determined based on the results of binning. In such an example, the module may be configured to analyze the design data or obtain analysis results of the design data, such as results from the DRC, to predict potential DOIs that may be detected in the inline defect data and the bitmap data. .

As mentioned above, module 166 may be configured to generate a data structure, such as a database. For example, in some embodiments, the method includes creating a data structure that includes the location of systematic and potential systematic defects within the design data space, and one or more attributes of the systematic and potential systematic defects. Such a database may be generally referred to as a "hot spot" database. The database may include information about weak spots, adjustable hot spots, and cold spots (non-critical areas of design data (eg, dummy structures, dummy filling areas, etc.) that have no yield impact or produce small systematic defects). . The database may include the location of potential defects and actual systematic defects and other attributes (eg, design context, KP, other yield characteristics, etc.).

Data in the hot spot database can be obtained from various sources. For example, the database may be configured as a flexible database that includes data about systematic issues from all (or at least some) possible sources. For example, some of the input to the module can be included in the database. In one such example, check results (eg, PWQ results, defects detected by BF and / or DF checks, memory bitmaps, logic bitmaps, etc.) may be included in the database. In some embodiments, the database may include design rules for one or more semiconductor manufacturing processes, such as lithography and CMP. In other embodiments, the database may include simulations performed on design data, such as the results of OPC simulations. In this way, multi-source correlation can be used to identify hot spots and systematic defects.

As mentioned above, the method includes binning the defects based on design data. In one such embodiment, the method described herein includes determining whether a defect is a Newsons defect based on one or more attributes of the design data. In this manner, the Newsons defect can be identified based on the context information. In some embodiments, the method includes removing a portion of the defect from the result of the inspection process in which the defect was detected, based on design data close to the location of the defect, to increase the S / N of the inspection process result. . In this way, information about the design located close to the location of the defect in the design data space can be used to reduce noise in the test results, thereby increasing the S / N of the test results. For example, defects in non-functional areas of the design can be binned into groups and filtered as Newsons from the test results before the test results are used for subsequent analysis. In another example, the defects may be separated based on whether the defects are located in the attentional or non-attentional regions of the wafer. In a further example, defects that are systematic but located in portions of the design where Newson's defects (eg, non-DOIs) are known to occur may be removed from the inspection results to increase the S / N of the results for the DOI. One or more portions of the design in which the Newsons defect is known to occur may be determined by the user and stored in a data structure such as a design library. For example, the portion of the design in which Newson's defects are known to occur may include polygons that the user has chosen to use for directed binning. Also, if the POI is defined prior to performing the binning method, the binning method may perform supervised binning using the prescribed POI. Alternatively, the POI can be determined by a method as further described herein. The method described herein may include performing supervised binning on an inspection system and excluding the Newsons defect from the inspection results.

As described above, removing some of the defects to increase the S / N of the inspection results may be advantageous for post-treatment of the inspection results. For example, removing some of the defects (eg, defects that do not affect yield) may be performed prior to binning the defects and may increase the S / N of the binning results for the defects of the type of interest. In addition, if the S / N of the result is high and contains less noise, the analysis of the test result of the method described herein can be faster and more accurate. In one particularly advantageous example, in the PWQ method, the main source of noise is line end shortening (LES) which is detected as a defect. However, LES generally does not have a significant impact on yield. Thus, the user does not pay attention to the LES, and since the LES may appear in a relatively large number, the detected LES may overwhelm other defects that are more related to yield. As such, removing the detected LES from the test results as described herein is particularly beneficial for further processing of the test results. Defects can include defects detected by optical or electron beam inspection systems. In addition, as further described herein, inspection recipes may be generated based on design contexts to distinguish between these defects during inspection. In this manner, the methods and systems described herein can be used to generate test recipes that can detect many DOIs, suppress many Nuson's defects, and classify systematic and random defects and patterns based on the binning of systematic defects. Can be.

In another embodiment, the method reviews at least a portion of the defects in the one or more groups and retrieves one or more groups corresponding to the Newsons defects from the results of the inspection process in which the defect was detected to increase the S / N of the inspection process results. Removing, determining whether the one or more defects correspond to the Newsons defect. Reviewing at least some of the defects can be performed as described herein or in any other suitable manner known in the art. Determination of whether one or more defect groups correspond to Newson's defects can be performed using any review result in any suitable manner. If one or more defect groups correspond to Newson's defects, one or more groups may be removed (filtered) from the test results to increase the S / N of the DOI in the test results.

As noted above, the embodiments described herein can advantageously use design data and defect locations within design data to bin defects in contrast to background information and / or defect information as printed on a wafer. However, design data in the design data space can be used in combination with other information to bin defects (eg, for better separation between defects binned into different groups). For example, in one embodiment, binning the defects may be performed such that the location of the design data close to the location of the defects in each group of design data spaces is at least similar, and one or more attributes of the defects in each group are at least similar. Binning into groups. The nature of the defect may include any of the properties described herein. In addition, the defect attribute may include any defect attribute that may be determined from the inspection result. As such, the binning step can be performed using a combination of design and one or more attributes. In this manner, the method may separate the defects into groups based on the design data and the defect attributes. Thus, it is possible to isolate different types of defects located in design data spaces at least in part in similar portions of design data. Such binning steps can advantageously be used to identify different defect mechanisms within the design data area and the speed at which the different defect mechanisms occur. In another embodiment, the portion of design data close to the location of the defect may include the design data where the defect is located. That is, the portion of the design data compared for binning may include defect "back" design data. In this manner, binning can include structure binning by use of the structure in the design data where the defect is located. Such binning can perform binning on defects whose defect locations are reported with relatively high coordinate precision, so that the probability of the correct structure being used for binning is relatively high. Since the design data used in this embodiment is not the design data as printed on the wafer, it is possible in the embodiments described herein to use defect "backward" design data. In contrast, a defect on a wafer may obscure design data printed at the same location on the wafer or in an area around the defect, which further degrades the accuracy of the method for defect binning based on design data as printed on the wafer. can do. In another embodiment, the portion of the design data close to the location of the defect used in the embodiments described herein includes design data around the location of the defect. In addition, binning can be performed using a structure in which the defect is located and a structure around or near the position of the defect in the design data.

As mentioned above, binning can be performed without consideration of the location of the defect within the portion of the design data. Such binning is particularly beneficial for defects detected by inspection systems that report defect locations with relatively low accuracy. Such binning can also produce substantially high accuracy binning results while providing important information such as which portions of the design data exhibit particularly high defects and / or particularly high defect rates. However, in further embodiments, the binning of the defects bins the defects into groups such that portions of the design data close to the position of the defects in each group are at least similar and positions of the defects in each group relative to polygons within the portion are at least similar. It includes a step. In this manner, binning can be performed using a combination of the portion of design data close to the position of the defect in the design data space and the position of the defect in the portion of the design data. As such, binning may be performed based in part on the location of the defect in the structure. That is, binning can be performed based on the inter-part location of the defect in combination with design data close to the inter-part location. Such binning is preferably performed on defects whose position is reported with relatively high coordinate accuracy such that a substantially accurate inter-part position of the defect is used for binning. In this way, defects that are located in the same part of the design data but that affect the device in different ways can be separated because of the different inter-part locations. For example, using such binning, a defect located between two features in a portion of the design data, and a relatively high probability of causing an open in the device are located entirely inside one of the two features and thus open to the device. It can be separated from defects that are much less likely to cause. Thus, such binning can advantageously be used to identify the rate at which different yield impact defects occur and the yield impact on a region of design data that differs.

In some embodiments, binning the defects into groups such that portions of design data close to the position of the defects in each group are at least similar, and hot spot information for portions of the design data close to the position of the defects in each group is at least similar. It includes. The hot spot information can include any hot spot information described herein or any other hot spot information known in the art. Hot spot information may be determined for different portions of the design data, as described further herein. In this manner, the method may perform binning using a combination of design data and hot spot information. In one such example, before the method is performed, hot spots in the design data with similar impact on yield may be binned as described above. Thus, defects can be binned based on design data similarity, and the resulting group of defects from this binning can be separated into sub-groups of defects with similar yield effects. In such an example, for example, if some of the locations are located above or below dissimilar design data, at least not all parts of the similar design data may be associated with the same hot spot information. As such, defects located close to at least similar portions of the design data may be separated based on hot spot information for each portion of the design data. In this way, the overall yield of the process used to manufacture the wafer can be evaluated quickly and accurately. In addition, hot spot information can be used for binning to check or verify that the similarity of portions of design data has been accurately determined. For example, if at least a portion of the design data determined to be similar is not associated with at least similar hot spot information, defects corresponding to the portion of the design data may not be binned into the same group.

In another embodiment, the method is based on one or more attributes of the design data, one or more attributes of the defect, or some combination thereof, close to the location of the defect in the design data space, such that the defects in the one or more groups are systematic defects or random defects. Determining the recognition. In this manner, the method may include classifying the defects collectively into groups. For example, systematic defects can be classified into a group as Newson's defects or defects of no interest. However, such classification can be done for individual defects. Attributes of defects that can be used to determine whether a defect is a systematic defect or a random defect include, for example, whether the defect is at approximately the same location in at least one die, whether the defect in at least one die has approximately the same attributes, and It may include whether the distribution of one or more defects is ordered and / or dense. In one example, defects that appear only in one die on the wafer may be classified as random defects, and defects that appear in multiple dies at nearly the same location may be classified as systematic defects. Thus, the method described herein can be used to determine the cause of a defect detected on a wafer by an inspection process (inline inspection process and / or electrical inspection process) using information about the defect.

In some embodiments, the method includes classifying the defects of one or more groups based on a review of at least some defects in one or more groups, one or more attributes of the design data, one or more attributes of the defects, or some combination thereof. Include. Reviews of at least some of the defects in one or more groups can be performed as described herein or in any suitable manner known in the art. One or more attributes of the design data or one or more attributes of the defect may include any of the attributes described herein. In this way, defects can be grouped collectively as a group based on the actual amount of information, thereby providing a relatively fast and relatively accurate defect classification.

In another embodiment, the method includes determining whether the group in which the defect is binned comprises a systematic defect or a potential systematic defect as described herein. In this way, defects can be grouped collectively as systematic or potential systematic defects. However, defects can be classified separately as systematic or potential systematic defects. For example, defects can be classified in this embodiment based on the position of the defect with respect to the polygon in the design and whether hot spots, cold spots, etc. are located at approximately the same position. Thus, the methods described herein can be used to determine the cause of defects detected on a wafer by an inspection process (inline inspection process and / or electrical inspection process) using information such as design data.

In some embodiments, the method includes monitoring systemic defects, potential systematic defects, or some combination thereof over time using the results of the binning step. For example, the results of the binning step can be used to identify systematic issues in the design data, and the identified systematic issues can be monitored for reappearance across the wafer and / or over time. Monitoring for systematic defects and / or potential systematic defects may be performed using any result of any of the methods described herein.

In addition, the step of monitoring systematic defects and / or potential systematic defects may be performed in a manner similar to the statistical process control (SPC) method. For example, monitoring for systematic defects, potential systematic defects, random defects, or some combination thereof may be used for yield-based SPC where different SPC methods and / or algorithms are used for different types of defects. In one such example, the SPC parameters can be used to monitor different types of defects, and the SPC parameters can be determined or selected based on the potential yield impact of the different types of defects that can be determined as described herein. In this way, different types of defects are monitored simultaneously for SPC in different SPC parameters. In another embodiment, only a subset of the defects detected by the inspection can be used for SPC. For example, only non-Newsons systematic defects and / or potential systematic defects may be monitored for SPC purposes so that processes can be monitored for design based process margins. In a further example, only systematic defects determined to have a potentially significant impact on the yield can be monitored for SPC so that changes in the yield of the manufacturing process caused by the change in the defects can be accurately detected relatively early. have. In addition, using other methods to estimate the yield impact of systematic defect groups and random defects can advantageously provide more accurate prediction, monitoring, and control of yield related issues. In this way, the method can be used to monitor and improve the manufacturing yield of information that can be used for manufacturing (eg, an increase in systematic defects over time, a decrease in systematic defects over time, a systematic defect over time). Change in, etc.).

In one embodiment, the method may include determining the cause of a pattern based defect (eg, a systematic defect). For example, if one or more pattern based defect groups are dominant, the method may include obtaining inline inspection data and / or electrical inspection data for multiple different wafers for the same layer and the same device. For example, inline inspection data and / or electrical inspection data can be obtained for about 100 to about 1000 other wafers. Such data can be obtained from storage media such as a defect database or a fab database. If such data is not available, the method may include inspecting the wafer after generating such information by inspecting a wafer that has already been processed in a process performed on a wafer for which a systematic defect was detected.

The method may include performing pattern-based binning of the detected defects on an additional wafer, which may be performed as described herein. The method may include determining whether one or more pattern based defect groups are dominant for additional wafers. If the additional wafer exhibits commonality of dominant pattern based defects, such a method may include determining whether the wafer has been processed through common equipment (or process tools). In this way, the method may perform equipment commonality analysis. The method is characterized in that the dominant pattern-based defect group is a particular piece of equipment, a particular chamber (eg, a piece of equipment or a chamber whose parameters drift for some reason). Or determining whether it relates to a particular route-step (eg, integration issue between the equipment and two or more steps). If the dominant pattern based defect group is associated with a particular piece of equipment or a specific chamber, the cause of the pattern based defect group is isolated and possibly identified. The method may include stacking data to determine if there is a spatial signature for the group of interest. Spatial signatures can be useful for limiting or determining the cause of process issues, OPC issues, or design-related systematic issues, or a combination thereof.

If the dominant pattern substrate defect group cannot be associated with a particular equipment or a specific chamber, the method may include performing data mining to attempt to correlate the defect with other process factors. Data mining can be performed in any suitable manner known in the art based on any information about defects and design data, and any information generated during device manufacturing that can be stored on one or more storage media, such as a fab database. Can be. If a relatively strong correlation is identified between the defect and one or more other process factors, the process factor associated with the defect may be identified as the cause of the defect. If a relatively strong association between one or more process factors and defects cannot be identified, the method may include performing an arbitrary pattern search of the design for potential POIs and a new inline hot spot so that the cause of the pattern dependent defects can be determined. And cleaning up the monitor. However, if process conditions are excluded, the process itself or the design itself must be evaluated and, if necessary, adjusted to reduce or eliminate problems. In addition, by comparing the attributes of systematic defects to the results of process window mapping, one can infer for possible sources and / or root causes.

The method may use information regarding systematic defects and / or potential systematic defects to perform data cleansing. For example, there may be 50,000 to 200,000 or more hot spots generated by a full-die pattern based search for a single POI or from experimental techniques such as electrical functional tests and lithographic PWQ results. Thus, to process and analyze this data in a meaningful and timely manner, data processing techniques may be performed on that data. In one such example, for a pattern based hot spot, the method may include binning the hot spots into a “like” group. For example, each group may include hot spots located close to at least similar patterns in the design data and / or close to design data having at least one or more similar one or more attributes (eg, hot spots located in a relatively low pattern density region of the design). Can be binned into one group). As such, the method may include binning hot spots based on design context and / or design attributes. In a further example, in an experimental technique such as PWQ, the method may include removing defects near the location (cold spot) of the design with little or no yield impact from the defect population where review sampling was performed. By performing the data cleanup as described above, the cleansed data can be used to generate better (eg, more yield-related) review samples as further described herein.

The methods and systems described herein can include CBI in combination with design-based and yield-based post processing (performed on- or off-tool). For example, after Newsons defects, systematic defects, and random defects are identified, the defects can be organized in some way (eg, using a defect organizer (DO) or an inline defect organizer (iDO)). In one example, the results are stored in a data structure such as a database. In another example, as described above, after a defect is binned based on the position of the design data close to the position of the defect in the design data space, the defect in the group is one or more attributes of the design data close to the position of the defect in the design data space. , May be further separated based on one or more attributes of the defect, or some combination thereof. Defects may be separated using iDO based on one or more attributes of the design data and / or one or more attributes of the defect. In this manner, design based binning can be used in combination with iDO in the embodiments described herein. In particular, the output of design-based binning can be input to iDO.

One or more attributes of the design data, used to further separate the defects binned into groups of defects based on the design data, include one or more attributes of the pattern or structure in the design data close to the position of the defect in the design data space, the design data. Pattern density close to the location of the defect in the space, the functional block in which the defect is located, and one or more attributes of the device (eg, n-MOS or p-MOS). One or more attributes of the defect used to further separate the binned defect include, without limitation, size, shape, brightness, contrast, polarity and texture.

The results of design-based binning and iDO can be shown in a bar graph. The bar graph may show the total number of defects versus the number of defects in the sub-group as a function of the pattern and pattern in the design data in which the defect was detected. Using design-based binning in combination with iDO, as described above, separates random and systematic defects, prioritizes groups of binned defects, and / or identifies and enables changes to be made to the design data. Can be used to prioritize (eg, using the potential yield impact of a group of defects, which can be determined as described further herein). In particular, the value provided by design-based binning for separation for systematic and random defects can be increased using iDO for further separation of systematic (and possibly random) defects. In addition, the value that design-based binning provides for separation of systematic and random defects can be increased by using yield relevance, possibly in combination with iDO, for separation of systematic (and possibly random) defects.

In this manner, systematic defect populations and random defect populations can be processed independently (eg, systematic defect populations and random defect populations can be sampled separately). To generate separate results for systematic and random defects, different populations or other information about systematic and random defects may be used. For example, systematic defects and random defects may be shown in different bar graphs, or in different graphs or textual representations, which may be automatically processed and / or used by a user. After defect sampling for review, some of the systematic defects, and optionally some of the random defects, can be reviewed using a suitable review system (eg, a relatively high magnification optical review system or SEM). The defect review results can be used to normalize the defect density of both systematic and random defects. The methods and systems described herein provide several benefits to the user. For example, the methods and systems provide sufficient baseline yield improvement, better excursion detection, improved review system efficiency, more effective root cause detection, and improved knowledge retention. In addition, the results of the embodiments described herein may include various other types of information useful to the consumer of the results (eg, the customer of the device manufacturer). Such other types of information may include information such as process tool owners, designers, integration engineers, and the like.

In addition, it is estimated that more than 50% of the yield loss in the 90nm design rule is caused by systematic issues. As such, systematic yield issues are prominent in 90 nm design rules, and dominate in design rules below 90 nm. Thus, separating systematic defects from Newson's defects and random defects as described herein allows for better evaluation, analysis, and control of systematic issues. In addition, the location of the systematic defects can be compared to the location of the functional blocks in the design data. In this way, systematic defects are correlated to one or more functional blocks, and this information can be used to improve S / N. In particular, the method may include separating the defects based on the functional blocks in which the defects are located to improve S / N. In a similar manner, the method may include separating defects based on hierarchical cells in which design data is organized by design. Thus, to improve S / N, defects grouped into bins and / or DBC-assigned defects can be separated based on the functional block (or any hierarchical level) where the defect is located (eg, memory or logic). have. Portions of design data used in the embodiments described herein may correspond to any cell structure or hierarchy of cells.

The percentage of defects per functional block can be determined by the method described herein. In this manner, functional blocks containing design issues may be identified based on the percentage of defects detected in each functional block and / or binned into groups corresponding to the functional blocks. Additional information about defects located in functional blocks can be used to identify design issues within each block. The information can be used to select and / or prioritize design issues for correction based on how many defects can be eliminated by the correction. For example, if it is determined that about 70% of the defects are caused by four design issues in four different functional blocks of the design, only these four design issues may be selected for correction, or these four design issues may be any Others may be selected for correction prior to correction (eg, prioritizing design issues based on the number or percentage of defects caused by the design issue). The user (eg, chip designer) can select a cell design to use, and can select a cell design that shows historically less systematic defects, and such information about the cell design can be generated using the embodiments described herein. Can be.

In another embodiment, the method includes prioritizing one or more POIs in the design data and optimizing at least one of the one or more POIs based on the result of the prioritizing step. In one such embodiment, the POI may be prioritized based on the number of defects detected in the POI. The number of defects detected in each POI, for example, compares the POI or one or more attributes of the POI to a design data portion corresponding to the group, and at least a portion of the design data (or a portion of the design data) that is at least similar to the POI (or attributes of the POI). Can be determined from the result of the binning step by assigning to the POI the number of defects in the group corresponding to one or more attributes). In this manner, the highest priority is assigned to the POI with the highest number of defects detected and the next highest priority is assigned to the next highest number of POIs with detected defects.

In other embodiments, the method may include prioritizing one or more systematic defect types for yield optimization (eg, by changing process parameters, designs, OPCs, or the like). In one such embodiment, systematic defect types may be classified as POIs or POI groups, and POIs may be prioritized based on the number of defects detected on or near the POI. To rank, it can be further enhanced using the threshold of systematic defects detected in the POI, the frequency of POIs in the design, and the sensitivity of the POI to process variations.

In addition, (or alternatively), the POI may be prioritized based on any other result of any step of any method described herein, or any combination thereof. For example, prioritizing the POI may include determining a defect threshold index (DCI) for one or more defects detected in the POI, and prioritizing the POI based on the DCI for the one or more defects. have. DCI can be determined in this example as further described herein. In another example, prioritizing the POI includes determining a KP value for one or more defects detected within the POI and prioritizing the POI based on the KP value for the one or more defects. . In another example, the POI may be prioritized based on the number of defects detected in or near the POI and the DCI for one or more defects detected in or near the POI. In this manner, prioritizing the POI may include prioritizing the POI based on the defect indicated by the POI such that a high priority is assigned to the POI having a high defect.

In addition, the POI may be identified and / or prioritized based on one or more attributes of the POI, possibly in combination with other results described herein. One or more attributes of a POI may include, for example, the dimensions of the feature within the POI, the density of the feature within the POI, the type of feature included in the POI, the location of the POI within the design, the sensitivity of the yield impact of the POI to defects, or some combination thereof. It may include. In one such example, POIs that are more susceptible to yield effects due to defects may be assigned higher priority than POIs that are less sensitive to the effects of defects on yield.

In addition, the POI may be prioritized based on one or more attributes of the design, possibly in combination with one or more attributes of the POI and / or other results described herein. One or more attributes of the design may include redundancy, electrical connectivity, electrical attributes, and the like, or some combination thereof. In particular, a cell in design data may have a context beyond a pattern contained within the cell. Such context may include, for example, the hierarchy of cells, redundancy, and the like. Thus, one or more attributes used in the embodiments described herein may include the context of the cell in which the POI is located, which may be determined based on the location of the POI in the design data space and / or the design data of the POI ( Design data is specific to cells within the design data). In such an example, non-redundant POIs (non-arrays) in the design data may be assigned a higher priority than redundant POIs (eg, arrays). POIs may be prioritized based on connectivity redundancy between cells (eg, routing or redundancy beer). Such context of the design may be obtained and / or determined in any manner known in the art.

Optimizing at least one of the POIs based on the result of the prioritizing step includes changing any one or more attributes, such as the dimensions of the features of the POI, the density of the features of the POI, or any combination thereof. It may include. One or more attributes of the POI can be changed by changing the design data corresponding to the POI. Preferably, the POI is adapted to modify one or more attributes of the defects detected in the POI (eg, DCI, KP, etc.) to reduce defects in the POI (eg, the number of defects detected within the POI), and And / or change to increase the yield of the device in which the POI is included. Also, prior to the POI having a lower priority as determined by the prioritization step, the POI having a higher priority as determined by the prioritization step may be changed and optimized. In this manner, the defects with the highest defects and / or the greatest impact on yield can be modified and / or optimized before the defects with the lowest defects and / or the smallest impact on yield. As such, the results of the optimization step indicate which POIs can be changed and / or optimized to show the greatest improvement in yield, and the POIs can be changed and / or optimized before other POIs.

Thus, without timely guidance as to which POI has the greatest impact on yield, changes made to the design data and / or manufacturing process are delayed, resulting in slower improvements in yield and increased time to market. This embodiment is advantageous over the methods and systems used. Also, even if the modified POI at this stage includes only the POI included in the design printed on the wafer prior to detection of binned defects in the embodiments described herein, the modified POI is included in one or more designs to optimize the POI. May include a POI. For example, if one or more design data includes a POI based on prioritization and / or any other result of the methods described herein, the POIs in other designs may be altered and optimized to produce each different design. Increase the yield of the device.

In a further embodiment, the method includes prioritizing one or more POIs in the design data and optimizing one or more RET features of the one or more POIs based on the results of the prioritization step. The POI prioritization step in this embodiment may be performed as described above. The optimized RET feature at this stage may include any RET feature (eg, OPC feature) included in the design. Optimizing the one or more RET features of the one or more POIs based on the result of the prioritizing step may include one or more attributes of the RET (eg, the dimensions of the RET feature, the shape of the RET feature, the location of the RET feature relative to the feature within the POI, etc.). ) May be included. At least one attribute of the RET feature that is changed in this step preferably includes any attribute of the RET feature that will reduce defects in the POI and / or increase yield.

In addition, the step of optimizing one or more RET features based on the result of the prioritizing step in the present embodiment prior to optimizing the RET features for other POIs, determines the RET features for the POIs determined to have the highest priority. Optimizing. In this manner, the RET feature of the POI with the highest priority may be changed before the RET feature of the POI with the lower priority is changed. In this manner, the RET characteristics of POIs that exhibit the greatest defects and / or defects that have the greatest impact on yield may be altered and / or optimized prior to the RET features of POIs that exhibit low defects and / or minor impact on yield. Can be. As such, the results of the prioritization step indicate which POIs can be changed and / or optimized to exhibit the greatest improvement in yield, the RET feature of the POIs being changed and / or before the RET feature of the other POIs. Can be optimized.

Thus, without timely guidance as to which POI has the greatest impact on yield, changes to the design are delayed, resulting in slower improvements in yield and increased time to market than previously used methods and systems. This embodiment is advantageous. Furthermore, even if the RET feature of the POI changed at this stage includes only the RET feature of the POI included in the design printed on the wafer prior to detection of binned defects in the embodiments described herein, the modified and / or optimized POI The RET feature of may include the RET feature of the POI included in one or more designs. For example, if one or more design data includes POIs having the same RET characteristics based on prioritization and / or any other result of the methods described herein, the RET characteristics of the POIs in other designs may be altered and optimized. Thereby increasing the yield of devices made with each different design.

In some embodiments, the method includes modeling electrical characteristics of a device manufactured using design data relating to the defect location, and determining parameter association of the defect at the defect location based on the modeling result. do. In this way, the results of the modeling step can be used to determine the parameter relevance of the defect. For example, the results of the modeling step can be used to determine how defects change one or more electrical parameters of the device being manufactured using the design. As described above, the defect in which the parameter relevance is determined may be a systematic defect. Parameter association can be used at any stage of the method described herein. For example, possibly in combination with other information described herein (e.g., one or more defect attributes, one or more attributes of design data, etc.), the parameter relevance determines the DCI of the defect, as described above, and prioritizes the POI. It can be used for painting.

Modeling the electrical characteristics of the device in this embodiment may be performed using any suitable method known in the art. The electrical characteristics of the modeled device may include any one or more electrical features of the device. The parameter association of a fault can be determined using modeled electrical features and designed electrical features. For example, the modeled electrical features can be compared with the designed electrical features to determine the extent to which the defect changes the electrical features. Parameter relevance may be determined based on the degree to which the defect changes the electrical characteristics (eg, defects that change the electrical characteristics to a greater extent are more parametrically related than defects that change the electrical characteristics to a lesser extent). Parameter relevance can be determined in a similar manner using a range of modeled electrical features and suitable electrical features of the device. For example, the modeled electrical features can be compared to that range, and whether the modeled electrical features are within or outside of that range can be used to determine parameter relevance. In such an example, when the modeled electrical feature is near or outside the acceptable range, it may be determined that the defect is more parametrically related than when the modeled feature is within the acceptable range. Parameter relevance may be determined based at least in part on information from a plurality of different sources including but not limited to simulations, optical inspection lodges, defect review results, electrical test results, or some combination thereof.

In one embodiment, the method includes assigning priorities to systematic defects or potential systematic defects based on parameter associations determined or related to systematic defects and potential systematic defects. For example, the priority or emphasis of hot spots can be ranked based on parameter relevance. Parameter relevance may define how or how many defects in the hot spot will affect the electrical parameters of the device.

Parameter relevance can be used to isolate or prioritize defects that are more likely to cause parameter issues (eg, yield loss) for the device. For example, using electrical test results or other information about the electrical properties of the device, such as resistance, capacitance, timing, etc., in combination with one or more attributes of the design data and / or one or more attributes of the defects close to the location of the defects in the design data space. In addition, it is possible to determine which defects affect the electrical properties of the device and which defects will not. Electrical test results or other information regarding electrical properties may be determined using the method (eg, using simulation) or obtained from other sources (eg, net list information). In this manner, defects that are more likely to cause parameter issues can be separated from defects that are less likely to cause parameter issues. As such, defects affecting only the structural configuration or material properties of the device can be separated from defects affecting whether the device can operate according to its intended purpose. In addition, in combination with one or more properties of the design data and / or one or more properties of the defects, electrical test results or other information regarding the electrical properties of the device may be associated with a major parameter defect (e.g., the electrical properties of the device). Electrical defects that can affect) and minor parametric defects (eg, electrical defects that do not significantly affect the electrical properties of the device).

In some embodiments, the method includes determining a DCI for a defect (eg, one or more defects). The DCI may be determined based on one or more attributes of the design data, one or more attributes of the defects, or some combination thereof that is close to the location of the defect in the design data space. For example, one or more attributes of the design data, one or more attributes of the defect, or some combination thereof, close to the location of the defect in the design data space can be used to determine the design based potential yield impact, thereby increasing the value of the defect data. You can. In one particular example, the DCI can be determined using the location of the defect and the defect size in the design data to determine the likelihood that the defect is likely to cause an electrical error. DCI can be used to indicate the yield relevance of a defect. In particular, the defect size can be used to determine the likelihood that the defect will break the die or change one or more attributes of the device being manufactured on the wafer. For example, as defect size and pattern complexity increase, the likelihood of a defect breaking a die or changing one or more electrical properties of the device also increases. Thus, the relationship describing the probability of a defect breaking a die or changing one or more electrical properties of the device in terms of defect size and pattern complexity can be used to determine the relative risk of each defect on the wafer. The relative risk of each defect can be determined immediately after the inspection, allowing better decisions to be made based on the relative risk.

Alternatively, the DCI may be used to determine the DCI for a different defect size and possibly for different types of defects (possibly across the entire die), or the defect may break the die, or one or more electrical Decisions can be made using a statistical method that includes determining the likelihood of changing an attribute. For example, in one embodiment, the method is reported by one or more attributes of the design data close to the location of the defect in the design data space, one or more attributes of the defect (eg, defect size), by the inspection system used to detect the defect. Based on the location of the defect that was detected, the coordinate inaccuracy of the inspection system, or some combination thereof, one or more defects in the device manufactured for the design data will cause one or more electrical errors (or alter one or more electrical properties of the device). Determining a parametric electrical issue) probability and determining a DCI for one or more defects based on the probability. The probability can be determined in this way using any suitable statistical method known in the art.

The DCI for a defect can be determined in a number of ways in the embodiments described herein, such as sampling to select a defect for review. In particular, for each defect category or group of defects, the DCI is configured to sample defects having the same category or binned into the same group, instead of performing random sampling of commonly classified defects or commonly binned defects. Can be used. By using DCI for sampling, the distribution of DCI can be used to determine which defects are more likely to break a die or change one or more electrical properties, and to detect defects that are more likely to break a die or change one or more electrical properties. You can sample more intensively. As such, defects that are more likely to affect yield can be sampled more intensively for review, thus generating defect review results that are particularly useful for identifying and classifying defects that are more likely to affect yield. Can be. DCI can be used to sample random defects as well as potentially systematic and systematic defects.

In some embodiments, the method includes determining a high density area on the electrical error density map. The error density map can be generated by generating a "logic bitmap" or physical transformation of an error test chain or error flip-flop (detected by a structural test, a scan based test type). All error lines or regions found by the scan based test are shown as in the graphical rendering of the die under test (DUT). The terms "logic bitmap" and "bitmap" are used interchangeably herein. Logical bitmaps for different dies of the same layer and design are stacked (ie, overlayed) to indicate the number of errors at each point of the die, thereby generating an error density map. Defects that appear in the error density map with a frequency greater than a predetermined value may be considered systematic defects. Defects found close to hot spots within the die coordinate space can be considered to be yield impact systematic defects or systematic candidates.

In some embodiments, the results of the electrical inspection process (eg, bitmap) can be analyzed using information from the inline inspection results to determine whether the cause of the electrical defect can be determined from the inline inspection results. In order to correlate the inline test results with the electrical test results, different test results may be aligned with one another as described herein. Also, different test results can be first aligned with the design data, and then the test results can be aligned with each other. In either case, the bitmap result can be overlaid on the inline check result.

The method may include determining the cause of an electrical defect in the bitmap based on the inline inspection data and the design data. In addition, different error types and their candidate locations or paths can be analyzed to determine how many electrical errors overlap with physical defects. In this manner, the hit ratio for the error type can be determined as the number of errors of the type corresponding to the reported physical defect divided by the number of errors of that type. The hit ratio can be evaluated to determine if the error type tends to be associated with the reported physical defect. In addition, in-line test results and hit ratios of physical defects can be used to determine how many of the same type of defects are caused by electrical errors. In this way, the number of defects of the same type that caused the electrical error can be used to determine a statistical prediction of the yield importance of the defect.

Additional information about the physical fault can be used to determine the cause of the bit error. Such information may include, but is not limited to, an image of a physical defect corresponding to the location of the bit error, a classification result of the physical defect, a binning result for the physical defect, or some combination thereof, that is, of the entire die where the bit error is located. Detailed information about the bitmap image, an image showing a stack (i.e., overlay) of bitmap images of multiple dies (e.g., to show repeatability of electrical errors across the dies), bitmap Pareto diagrams, and bitmap results ( For example, data in a table or list).

In some embodiments, the method may include using a defect transition table (DTT) method to identify hot spots where no defects were detected, or non-destructive or non-conspicuous defects were detected. In general, rows of DTT contain test results for different defects, and other columns of DTT contain test results generated by tests performed at different times. The test results can be arranged in chronological order across the rows. In this way, the table shows which defects are redetected in different layers during the semiconductor manufacturing process. The table may include or provide access (eg, a link) to additional information about the defect detected at the different layers. In this way, additional information, such as an image of the defect, can be used to determine whether or how the defect is changing in different layers.

In a further embodiment, the method includes determining a KP value for the one or more defects based on one or more attributes of the design data, one or more attributes of the defects, or some combination thereof. In a similar manner, the method may determine a KP value for a defect of at least one group of defects based on at least one attribute of design data corresponding to at least one group, at least one attribute of a defect in at least one group, or some combination thereof. Determining may include. KP values for systematic defects can be used to determine additional attributes of systematic defects such as yield ratios. KP values can also be used to perform the additional steps described herein. For example, the KP value for systematic defects can be used to determine which defects will be selected for review. In particular, systematic defects with relatively high KP values can be selected for review. The method may also include monitoring the KP value for systematic defects and generating an output signal if the KP value exceeds a predetermined KP value. The output signal can be an automatic report, a visible output signal, an audible output signal, or some other output signal that can be used to alert the user of potential problems with the process. In this way, the output signal can be a warning signal.

As further described herein, one advantage of the methods and systems described herein is that information from a plurality of different sources can be correlated, stored, displayed and / or processed with each other. Such information may include information in a GDS file, information about the process performed on the wafer (commonly referred to as WIP data, which may be obtained from a source such as a fab manufacturing execution system (MES) database), inline inspection results, In-line metrology or measurement results, electrical test results, and end-of-line yield information may be included without limitation. Such information can be used to determine yield-related information for systematic deficiencies. In addition, yield ratios or other yield related information determined for systematic defects may be used to assign yield related contexts to systematic defects. Both yield related context information and design context information can be assigned to systematic defects. In one embodiment, instead of classifying defects based on design context, systematic defects may be classified based on yield limiting context.

As further described herein, hot spot based inspection for systematic defects may generate inspection results that include systematic defects and design contexts corresponding to the systematic defects. In this manner, margin features in the design data can be identified and used for SPC applications. For example, SPC can be performed by monitoring the position of margin features in the design data, because if the process drifts from process limits, the features tend to be error first. Thus, the SPC can be performed more quickly by monitoring a subset of all features in the design, including the most important features in the design instead of all the features in the design, and the features in the design that are most sensitive to changes in the process are monitored during the SPC. This allows for faster detection of drift in the process. In a similar manner, margin feature information can be used to generate a recipe for a metrology process, such as a CD measurement process. The CD measurement process can include any suitable CD measurement process known in the art (eg, CDSEM, scatterometry CD measurement, etc.). Generating a recipe for the CD measurement process may include determining a location on the wafer (eg, a margin feature to be printed) during which the CD measurement is to be performed. In addition, inspection results of a wafer, such as a BF image acquired at a location on the wafer where a CD measurement is to be performed, can be provided to the metrology system so that the results can be used in a recipe or by a metrology system moving to a location on the wafer for measurement. have.

However, with the addition of test data, the design portion corresponding to the systematic defect can be associated with the yield probability of the semiconductor manufacturing process and the KP of the systematic defect. In one such embodiment, an inspection system or any other system described herein can produce yield results for systematic defects, such as the probability that each individual die produces and which defects most affect yield. have. KP of systematic defects can be used for SPC applications. For example, each individual die calculates, and the probability of which defect most affects yield can be used to improve SPC monitoring applications and review sampling. In this manner, SPC may perform based on context based yield. In addition, improved SPC monitoring and review sampling can improve root cause analysis and baseline reduction.

In a further embodiment, the method includes monitoring the KP value for a group of defects over time and determining the importance of the group of defects based on the results of the inspection. For example, over time, as the KP value continues to be updated, hot spots with low KP values may be removed or downgraded to adjustable hot spots, weak spots, or cold spots. In this way, the identified potential hot spots can be assigned low or zero KP values (ie, cold spots). In another embodiment, the method includes determining a KP value for a group of defects based on the electrical error density associated with the design data. In this manner, hot spots determined not to overlay on a relatively high error density area on the electrical error density map may be downgraded at KP and optionally removed from the hot spot database and / or its associated inspection recipe. .

In one embodiment, the method includes monitoring KP values for one or more POIs in the design data, and if the portion of the design data is close to the location of a defect binned into one or more groups corresponding to the one or more POIs, Assigning a KP value for the POI to at least one group. For example, monitoring the KP value for one or more POIs in the design data may include electrical error, electrical error density, any other property of electrical error, or any combination thereof determined for one or more POIs over time. , Based on the test results obtained for one or more POIs over time. Electrical errors, electrical error densities and any other properties of electrical errors can be determined using any suitable method or system known in the art. The test result can be acquired as described here. Although the checking of the KP value is performed by the method in this embodiment, the step of monitoring the KP value may be performed by another method or system, and the above-mentioned assignment step may be performed by the method. In addition, monitoring the KP value may be performed during the setup phase prior to performing the binning step, thereby reducing the time between inspection and assigning the KP value to one or more groups of defects. Assigning a KP value for one or more POIs to one or more groups comprises comparing a portion of design data close to the location of at least some defects binned into one or more groups to a portion of design data corresponding to one or more POIs. It may include. If the portion of the design data close to the location of at least some defects in the group is at least similar to the portion of the design data corresponding to the POI that can be determined based on the result of the comparing step, then the KP value corresponding to the POI is equal to the defect in the group (e.g., , All defects).

The method described herein may include generating information about one or more diagnostic or repair processes that are sensitive to a hot spot (eg, having a high signal and low noise for the hot spot). The information can be used to automate or optimize one or more diagnostic or repair processes for hot spots. One or more processes can be used for hot spot verification and analysis, capturing new learning, optimizing non-cautionary areas and Newsons defect filtering, reporting, and differentiating between design and process margins. In this way, the method includes wafer inspection, reticle inspection, optical inspection, macro-defect inspection, electron beam inspection, optical defect review, SEM defect review, ellipsometry and CDSEM. It can be used to generate recipes for metrology processes, defect analysis processes, FIB and other FA processes, and diagnostic and repair processes such as defect repair processes.

In some embodiments, the method includes prioritizing one or more POIs in the design data and optimizing one or more processes performed on the wafer to which the design data is to be printed based on the prioritizing step. . Prioritizing one or more POIs may be performed as described herein. Optimizing one or more processes in this embodiment may include focusing, dosage, exposure tool, resist, post expose bake time, PEB temperature, etch time, etch gas composition, etch tool, deposition tool. Changing one or more parameters of one or more processes, such as deposition time, and the like. Preferably, the parameters of the process change the one or more attributes of the defects detected in the POI (eg, DCI, KP, etc.) to reduce the defects of the POI (eg, the number of defects detected within the POI). And / or to increase the yield of the device in which the POI is included.

In addition, one or more parameters of one or more processes may be optimized only for POIs having the highest priority as determined by the prioritization step or POIs having a relatively high priority as determined at the prioritization step. In this manner, one or more parameters of one or more processes may be altered and / or optimized based on the POI showing the largest defect and / or the defect with the greatest impact on yield. As such, the result of the prioritization step indicates which POI should be used to change and / or optimize one or more parameters of one or more processes to indicate the greatest yield improvement.

Thus, without guidance as to which POI has the greatest impact on yield, beneficial opportunities for optimizing the process for yield and stability may not be identified or made in a timely manner, increasing time to market and optimizing the process. This embodiment is advantageous over previously used methods and systems, which reduce the

In addition, even if the modified and / or optimized process at this stage includes only the process used to print the POI in the design data on the wafer prior to the detection of binned defects in the embodiments described herein, the modified and / or optimized The one or more processes that are included may include any process used to print other design data including the POI. For example, if one or more design data includes a POI based on prioritization and / or any other result of the methods described herein, one or more processes used to print one or more designs may be modified and optimized so that Increasing the yield of devices manufactured with each different design.

In other embodiments, the method may be performed on or based on the results of the binning step and / or any other result of any other step of any of the methods described herein. Changing the variable. The process may include any process known in the art, such as CMP, deposition (electro-chemical deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition), lithography, etch, ion implantation, and cleaning. One or more parameters may be changed based on the results of binning so that defects binned into one or more groups can be reduced for a wafer after subsequent processing of the wafer, or for another wafer after processing of another wafer.

For example, if an etch process is performed on a wafer prior to inspection, the at least one parameter of the etch process is preferably a lower number of other wafers in the at least one group than the other wafers processed in the etch process with the changed parameters. It can be altered using feedback control techniques to indicate defects, fewer defects with relatively high DCI, fewer defects with relatively high KP values, or some combination thereof. Such changes of parameters may be made based on prioritization of defect groups or other information described herein, such as DCI and KP values. In this way, the process can be changed based on the group of defects that have the greatest impact on yield.

In another example, if an etch process is performed on the wafer prior to inspection, the one or more parameters of the post-etch process to be performed on the wafer are preferably performed by the post-etch process on the wafer with the changed parameters. Thereafter, the wafer feeds forward to show fewer defects in one or more groups, fewer defects with relatively high DCI, fewer defects with relatively high KP values, or some combination thereof. Can be changed using control techniques. The parameters of the post-etch process or other process can be changed as described above.

As described above, changing one or more parameters of the process includes determining how one or more parameters should be changed, and changing the value of one or more parameters in the recipe to be used to perform the process. Can be. Such changes can be performed by methods and systems described herein, for example, by accessing recipes in a fab database or in a storage medium coupled to a process tool that will perform the process and making direct changes to the recipe.

Alternatively, changing one or more parameters of the process as described above may be used to determine how one or more parameters should be changed and to change the value of one or more parameters in the recipe to be used to perform the process. And transmitting one or more parameter values to another method or system (eg, a fab database or processor coupled to a process tool to perform the process). One or more parameter values to be changed may be transmitted along with other information such as recipe entities, process tool identities, instructions to change one or more parameters, and so on, so that the process may be changed by other methods or systems.

In one embodiment, the method includes changing a process for inspecting a wafer based on the results of the binning step. The process for wafer inspection can be altered based on any binning results described herein. Also, any parameter of the process for inspecting the wafer can be changed in this embodiment. For example, one or more parameters of the wafer inspection process, which may be changed based on the results of the binning step, may include attention areas (or alternatively non-attention areas), sensitivity, in-line binning process, inspection areas, May be examined, or some combination thereof without limitation. In one particular example, the result of binning may include the number of defects included in one or more groups, and the area of interest corresponds to a location on the wafer that corresponds to a location in the design data space of the defect in the group that includes a relatively large number of defects. It may be changed to include. In another example, the wafer inspection process can be modified to inspect more or differently based on the results of the binning step. The process for wafer inspection can be modified based on any result of any step of the method described herein.

As described herein, defects can be detected by an inspection process. In one embodiment, the method includes the steps of reviewing a location on a wafer on which one or more POIs in the design data are printed, determining whether a defect has been inspected at the location of one or more POIs based on the results of the reviewing step; Modifying the inspection process to improve one or more defect capture rates. The location review step in this embodiment can be performed using any method or system known in the art. In this manner, reviewing the location on the wafer may be performed at the location of the POI to determine whether a defect was detected at the location of the POI. In one such embodiment, the method may include any pattern retrieval step for identifying a location of one or more POIs in the design data and determining the location of the one or more POIs from the location of the one or more POIs in the design data. have. Determining the location of the POI in this manner may be performed as further described herein.

Further, in some embodiments, the method may include indicating the location of the POI with a hit and the POI without the hit during the review step. As such, the results of the review can be used to determine where a defect has occurred but has not been captured by the inspection system. The POI can be reviewed to find missing defects (or uncaptured defects) to know where to perform changes or optimizations of the inspection process.

Based on such information in addition to the review results (e.g., one or more properties of the defect, one or more properties of the design data, etc.), optical mode, collection, preferably to be captured at the location of the POI at a higher rate than in subsequent inspections. One or more parameters of the inspection process may be changed, such as angle, angle of incidence, and the like. In this manner, the method may include a setup adjustment step based on the analysis of the defect capture rate in the POI. One or more parameters of the inspection process to be changed can be determined in any suitable manner, such as using a rules database. One or more defect capture rates that can be improved in this embodiment include defect capture rates for one or more defect types in one or more POIs. In a similar manner, the foregoing embodiments for improving one or more defect capture rates can be performed by reviewing locations on the wafer that correspond to the locations of one or more hot spots in the design instead of reviewing the locations on the wafer where one or more POIs are printed. Can be performed.

In addition, the method described above is performed for one or more POIs, the POIs may be prioritized as further described herein, and the inspection process may determine the rate of defect capture for the POIs having the highest priority or the highest priority. Can be changed to improve. In this manner, the inspection process may be optimized for the highest priority POI or the high priority POI (although such optimization may also result in the optimization of the inspection process for low priority POIs).

In another embodiment, the method includes changing a process for inspecting a wafer during inspection based on inspection results. In this manner, the method may include modifying the inspection process using in-situ process control techniques. The test results used to modify the test process can include any of the results described herein. In addition, changing the inspection process in the present embodiment may include changing any one or more parameters of the inspection process.

As further described above, the method may include optimizing the inspection recipe. Inspection recipes that are optimized may include inline inspection recipes and / or electrical inspection recipes. In one embodiment, the method may include changing the process for wafer inspection based on hot spot information. In another embodiment, the method includes creating a process for wafer inspection based on hot spot information and design data. The method may also include modifying or creating a process for wafer inspection based on hot spot information and / or predicted POI. For example, the inspection recipe may be configured such that only the locations of the hot spots and POIs are inspected and / or the locations of systematic nucleus defects are not inspected, or data obtained at such locations is otherwise suppressed. In another example, as described above, the method embodiments described herein can include identifying hot spots in the design (eg, based on systematic defects). In this manner, the method embodiment can be a source of hot spots, and the location of the hot spots in the design can be used to change the inspection process using feedforward control techniques.

The method may include changing the process for wafer inspection based on any other available information. In such an example, the method may include modifying the inspection recipe based on the hot spot information in addition to the design data, the inspection result, and the one or more bitmaps. In this way, any information available to the method may detect the defects that do not affect the yield, while reducing the sensitivity of the inspection recipe, while detecting the defects that may affect the yield. Can be optimized Generation and optimization of test recipes can be performed as described further herein (eg, based on testability for DOI).

In some embodiments, the method may include determining a sensitivity for detecting a defect on a wafer based on design data. In some such embodiments, they are different in at least two different portions on the wafer corresponding to at least two portions of the design data. The method may also include identifying a "region of interest" (or "region to inspect") on the wafer. The inspection result may not be acquired in the non-attention area, and defect detection may not be performed for the inspection result acquired in the non-attention area. However, if data acquisition and defect detection are performed in the non-attention area before additional processing of inspection results such as binning is performed, the method determines whether the detected defect is present in the attention area or the non-attention area. It may include. If the defect is located in the non-caution area, no further processing may be performed on the defect. In this manner, pattern based binning can be limited to sensitive areas in the design data to optimize the throughput of the binning process. In other embodiments, after the defects are grouped by common design data (eg, pattern grouping or other context data), the grouping information is added here for improved counting, binning, monitoring, analysis, sampling, review, testing, etc. Can be used as described.

The method embodiment may or may not utilize hot spot information. For example, based on knowledge of design data, the method may include identifying a portion of design data that is more critical to yield and / or more sensitive to yield-lowering defects. In this manner, the sensitivity for detecting a defect in that portion of the design data may be higher than the sensitivity for detecting a defect in another portion of the design data. As such, during inspection data acquisition, the method may include aligning the inspection data with the design data, which may be performed as described further herein. The sensitivity of the inspection process can change based on the location of the inspection data in the design data space. In such embodiments, the sensitivity of the inspection process may change in real time. Further examples of design-based inspection or measurement recipes are disclosed in U.S. Patent 6,886,153 (Bevis) and U.S. Patent Application Serial No. 10 / 082,593 published by Hamamatsu et al. In US Patent Application Publication No. US2003 / 0022401 (February 22, 2002). Applications, which are incorporated by reference as if fully set forth herein. The method described herein may comprise any of the steps disclosed in the patents and patent applications.

In one embodiment, the method includes selecting at least some defects for review based on the results of the binning step. For example, the results of the binning step can be used to determine which defects are most important as described herein (eg, by determining the DCI for a defect), and most significant defects can be selected for review. In another example, the binning results can be used to determine which defects are systematic defects, as further described herein. In this manner, the method may include review sampling from the portion of design data for which DOI tends to occur. In addition, information about which defects are systematic, as well as whether systematic defects are visible to a review system such as SEM, and / or whether systematic defects are yield-related can be used to select at least some defects for review. (Eg, only defects visible in the SEM are selected for review). Defect selection in this manner is particularly advantageous because re-location of the defects during the review is relatively difficult and can be relatively time consuming, especially if the review system spends a lot of time looking for actual invisible defects in the review system. The defect selection result for review may include the location of the selection defect on the wafer and other results of any step of the method described herein.

In another embodiment, the method includes generating a process of sampling a defect for review based on the results of the binning step. Thus, instead of or in addition to the selection of a defect for review, the method may be used to sample a defect for review (eg, the method, another method, a system configured to perform the method, or another system). By) creating the process. Such a process may be used for sampling of defects detected on a plurality of wafers for review and / or sampling of defects for review performed by the plurality of review systems. The process for sampling includes a portion of the design data in which the detected defects in the portion of the design data corresponding to the binned defect group containing the relatively large number of defects correspond to the group of binned defects containing the relatively small number of defects. It can be generated based on the results of the binning step so that it can be sampled more intensively than the defects detected therein. The process for sampling the defect for review may be generated based on the result of the binning step in combination with any other result of any step of any method described herein, such as the DCI for the defect, the KP value for the defect, and the like. Can be.

In another embodiment, the method includes creating a process for selecting a defect for review based on hot spot information. The process of selecting defects for review can be generated based on hot spot information as well as any other information available for the method. For example, the process of selecting a defect for review may be generated based on design data, one or more attributes of the defect, one or more bitmaps, and hot spot information. Preferably, the process of selecting defects for review selects certain types of defects, such as defects detected in hot spots or systematic defects, for defects and coldson detected defects in cold spots for review. Is not created. In this manner, the method described herein produces a defect sample that includes a large number of defects that can affect the yield while increasing the throughput of the review process by excluding most defects from the review sample that will not affect yield. can do.

In another embodiment, after the defects are binned by at least similar design data as described above, the method aims to generate one or more "" review samples for CDSEM, optical or other forms of physical defect review and classification or verification. Using the binning result may include. In one such embodiment, the method includes generating a pattern group pareto as described above that represents the pattern group identity on the x-axis and indicates the number of defects detected in each pattern group on the y-axis. In this way, the chart shows the number of defects detected in other patterns. However, other data indicating the number of defects detected in other patterns may be used in the method steps described herein. Embodiments described herein may include generating electrical, systematic, and / or random Pareto charts.

The method may include analyzing data for one or more different patterns shown in this chart to determine one or more physical defect types detected in each pattern type. One or more defect types may be detected in one pattern group. The method may also include analyzing data for one or more other spatial signatures shown in such charts to determine one or more attributes of the defects binned into one or more groups corresponding to the one or more different signatures. . Defect attributes may include, but are not limited to size, die location (or die identity), and any other attributes known in the art. The die position indicates whether the pattern has a high frequency of occurrence at a particular position, zone, or region of the wafer, such as the edge, center, three o'clock position, and the like.

The defect sampling plan can be determined from the results of the above analysis steps. For example, the method may include determining whether a strong signal arises from the analysis step described above. This strong signal indicates which defects (eg, which patterns determined by the analysis step and which defect types and / or attributes) should be sampled at high or low rates. The sampling plan described above is useful for increasing the throughput of relatively slow review systems such as electron beam based review systems and atomic force microscopes or other scanning probe microscope based review systems.

The method described here can be used to optimize review recipes. For example, in one embodiment, the method includes modifying the process of reviewing defects on a wafer based on hot spot information and optionally any other information available for the method. The parameters of the review recipe changed or selected based on this information may include any data acquisition parameters, and any data processing parameters of the review process. The method includes selecting the type of review system to use to review the defect (eg, optical or electron beam) and additional parameters of the review process, such as the make and model of the review system used to review the defect. It may include.

The method can include providing the review system with information that can be used to assist in determining a location on the wafer where the review is to be performed. For example, the location of the defect to be reviewed may be reported to the review system as design data space, die space, and / or wafer space. In addition, other information regarding defects and / or defect locations may be provided to the review system. For example, an image or overlay of a defect generated by inline inspection can be provided to the review system in addition to the portion of design data corresponding to the defect location. In this manner, the review system may use some or all of its information to locate the selected defects on the wafer during review. In addition, the results of one or more steps of the one or more methods described herein can be provided to the review system so that the review system can use the results to perform automatic defect locating (ADL) based on edge placement errors. The method may also include determining where to measure or test for review based on test results and systematic identity (perhaps with yield relevance and / or process window mapping). The review is published in commonly assigned U.S. Patent Application Serial No. 11 / 249,144, filed Oct. 14, 2005; Teh et al., Published as U.S. Patent Application Publication No. 2006/0082763 (April 20, 2006). User-assisted reviews that can be performed using methods and systems such as those disclosed, which are incorporated by reference as if fully set forth herein. Thus, user cases for binning methods (and how to assign categories to defects described further herein) include systematic search and user-assisted reviews.

In one embodiment, the method includes changing the metrology process for the wafer based on the results of the binning step. For example, the metrology process can be modified so that most major defects as determined from the results of the binning step are measured during the metrology process. Thus, changing the metrology process may include changing the position on the wafer where the measurement is performed during the metrology process. In addition, the results of inspections and / or reviews, such as BF images and / or SEM images of defects selected for measurement, are provided to the metrology system, and the results can be used to determine where the measurements will be performed. For example, the metrology process may include generating an image of the proper location of the defect on the wafer, and if necessary, the metrology system may correct the location on the wafer such that the measurement is performed at the correct wafer location, and thus for the correct defect. As such, the image can be compared with the results of inspection and / or review for defects. In this manner, the measurement can be performed at a substantially accurate position on the wafer. Changing the metrology process may also include changing any other one or more parameters of the metrology process, such as the type of measurement being performed, the angle at which the measurement is performed, or the like, or some combination thereof. The metrology process may include any suitable metrology process known in the art, such as a CD metrology metrology process.

In another embodiment, the method includes changing the sampling plan for the metrology process of the wafer based on the results of the binning step. Thus, the method may include adaptive sampling. For example, the sampling plan for the metrology process can be modified so that the majority of the most significant defects as determined from the results of the binning step are measured during the metrology process. In this way, the most important defects can be sampled more intensively during the metrology process, thereby advantageously generating large amounts of information about the most important defects. The metrology process can include any metrology process known in the art. The metrology process may also be performed by any suitable metrology system known in the art, such as SEM. In addition, the metrology process may include performing any suitable measurement known in the art of any suitable attribute of a feature or defect formed on the wafer, such as a profile, thickness, CD, and the like.

In a similar manner, the method includes modifying a process for analyzing (eg, metrology or configuration analysis) or repairing defects on a wafer based on hot spot information and optionally any other information available to the method. can do. For example, the method may include modifying a process, such as electron scattering x-ray spectroscopy (EDS or EDX) to analyze the composition of the defect or repair of the defect or an FIB process for FA. The process for analyzing or repairing a defect can be changed as described herein for changing other processes. For example, a defect or repair process may be modified such that analysis and / or repair is performed only at the location of the selected defect, and such selection may be made as described herein. In addition, one or more parameters of the analysis or repair process may be selected and changed based on the results of any of the steps of the methods described herein. Such results may include, for example, defect category, defect root cause, defect size, defect criticality (which may indicate the accuracy with which analysis and / or repair should be performed), yield impact, one or more attributes of the design data close to the defect (eg, features). , Dimensions, density of features, hierarchy, redundancy, etc. (which may indicate whether analysis and / or repair should be performed, and the accuracy with which the analysis and / or repair should be performed, etc.). Additional examples of methods and systems for generating recipes for metrology tools are disclosed in US Pat. No. 6,581,193 to MaGhee et al., Which is incorporated by reference as if fully set forth herein. The methods and systems described herein may be configured to perform any additional steps disclosed in the patent.

In some embodiments, the method includes determining the root cause of the defect based on one or more attributes of the design data. In another embodiment, the method includes determining the root cause of at least one group of defects binned. For example, in one embodiment, the method is the result of at least some defects in one or more groups, one or more attributes of the design data, one or more attributes of the defects, or some combination thereof, the root cause of the one or more groups of defects. Determining a step. In this manner, the method may include determining the root cause of the defect individually or collectively as a group. The root cause of a defect or group defect can be determined based on an analysis result from a diagnostic system such as an EDS system that can be used to analyze the defect, for example by measuring the composition of the defect. An example of an EDS system is disclosed in US Pat. No. 6,777,676 to Wang et al., Which is incorporated by reference as if fully set forth herein.

The root cause step can include identifying a source, cause, and / or correction for systematic defects. Root cause steps can be performed in multiple source spaces using the correlation between any design, wafer, reticle, test and process space. For example, in one embodiment, the method includes determining the root cause of the one or more group defects by mapping at least some of the defects in the one or more groups to experimental process window results. The experimental process window results may be generated by a system other than the method, another method, a system configured to perform the method, or a system configured to perform the method. In addition, the experimental process window results can be used to detect defects on the wafer after the PWQ method or other experiments using the PWQ method or any other suitable experiment (eg, by performing an etch process on a different wafer at one or more different parameters). It can acquire by making it. The experimental process window results may include any results obtained by inspection and / or review of defects detected on the wafer. For example, the experimental process window result may be an image of a defect, a portion of design data close to the location of a defect in the design data space, the location of a defect in the design data space that may be determined as described herein, or any other described herein. Inspection and / or defect review results.

Mapping at least some of the defects to the experimental process window results may be performed using the results of the inspection process. For example, if the experimental process window results include portions of design data close to the location of the defects in the design data space and an image of the defects on the wafer, then mapping the defects to the experimental process window results may include binning defects into one or more groups. Comparing the image of the image with the image in the experimental process window results for the detected defect at least near the design data to the design data close to the location of the binned defect in the design data space. In another example, if the experimental process window results include the location of a defect in the design data space, the mapping of binned defects to the experimental process window results in this embodiment may result in the occurrence of defects in the design data space in the experimental process window results. And comparing the location to the location of the binned defect in the design data space.

In this manner, the result of the mapping step may indicate where in the process window space a process performed on the wafer is performed prior to defect detection. In particular, when the mapping result indicates that the defects and bound defects included in the experimental process window results are at least similar and are located at least close to similar design data, One or more parameter values may be correlated to binned defects and may be determined as the root cause of binned defects or may be used to determine the root cause of binned defects.

In another embodiment, the method includes determining the root cause of the one or more group defects by mapping at least some of the defects in the one or more groups to simulated process window results. The simulated process window results may include similar results to the experimental process window results described above. However, the simulated process window results are obtained by simulating images describing how design data is printed on the wafer at the values of one or more various parameters of the process, rather than by performing experiments on physical wafers. The process can include any process involved in the manufacture of a device corresponding to the design data. For example, this embodiment may include modeling a patterning process (eg, lithography or etch) with respect to systematic defect locations, and the results of such modeling can be used to determine the root cause of systematic defects. The simulated process window results can be generated by any suitable method or system known in the art. For example, simulated process window results can be generated by PROLITH software commercially available from KLA-Tencor. In addition, the simulated process window results may be generated by a system other than the method, another method, a system configured to perform the method, or a system configured to perform the method. Determining the root cause in this embodiment can be performed as taught for the experimental process window results.

The root cause step can include determining a source and / or correction for the systematic defect. One possible source for systematic defects is process window shift. In addition, knowledge of hot spot signatures can provide information about where a process operates within a process window. The root cause step may also include determining the most significant opportunity for process improvement to expand the process window. The root cause step may also include determining the most important systematic issues to improve the reticle design. The root cause step may further include determining the most important systematic issues for improving and / or implementing next generation technology.

In some embodiments, the method includes determining a percentage of the die formed on the wafer affected by the at least one group of defects. For example, the percentage may be determined by determining the number of inspection dies on the wafer where defects in the group have been detected at least once, and dividing the number of inspection dies that have detected at least one defect in the group by the total number of inspection dies. The number of inspection dies on the wafer at which defects in the group were detected at least once may be determined based on information about the design data space location of the defects, the design space location of the die printed on the wafer, and the inspection process used to detect the defects. have. The result of these steps is multiplied by 100 to reach the percentage. In one particular example, if there are 300 defects binned into one group, and the defects within that group are located on five dies on the wafer, and there are 6,000 dies on the wafer, the percentage is [(5) ( 100)] / (6000) or 0.083%. The percentage thus reflects the die impact margin for the group of defects. Such percentages can be determined for one or more groups of defects, and each (or at least some) percentage can be represented by a chart such as a bar chart that can be generated by the method. Thus, the chart shows die impact margin as a function of the group of defect bins. Such charts may be presented in a user interface that may be configured as further described herein. The method may also include prioritizing one or more groups of defects based on the percentage determined in this embodiment. Such steps of prioritization may be performed as further described herein, and the results of such prioritization may be used as described further herein.

In another embodiment, the method includes determining at least one POI in design data corresponding to at least one group, and defects binned into at least one group corresponding to at least one POI for the number of one or more locations on a wafer. Determining the ratio of the number of. One or more POIs in the design data corresponding to the at least one group may be determined as described further herein. If all examples of one or more POIs are not inspected during the inspection process used to detect defects, the number of locations of one or more POIs on the wafer used in this embodiment may be the number of inspected locations of one or more POIs on the wafer. In this way, the method performs margin analysis by determining the percentage or percentage of POIs detected on the wafer for defects on the number of locations of POIs printed on the wafer (or the number of inspected locations of POIs on the wafer). It may include a step. In such embodiments, the number of locations of POIs on the wafer can be identified by any pattern search. The number of inspected positions of the POI on the wafer can be performed using information about the inspection process and the results of any pattern search to determine the number of inspected positions of the POI on the wafer, by any pattern search. . In addition, the method described herein may include any pattern search to identify the location of the POI on the wafer and determine the area of the POI. The area of POI on the wafer and the number of locations of POI (or the number of inspected locations of POI on the wafer) can be used to determine the defect density by POI. The method may also include prioritizing one or more POIs based on the rate determined in this embodiment. Such prioritization may be performed as further described herein, and such prioritization results may be used as described herein.

In a further embodiment, the method includes determining one or more POIs in the design data corresponding to the at least one group, and the number of one or more POI locations in the design data (or all locations of one or more POIs in the design data are defective). Determining the ratio of the number of binned defects in at least one group corresponding to one or more POIs to the number of inspected locations of one or more POIs in the design data, if not inspected during the inspection process used to detect Include. In this manner, the method includes performing a margin analysis by determining the ratio or percentage of the number of defects in the group corresponding to the POI to the number of locations of the POIs in the design (or the number of inspected locations of the POIs in the design). It may include. In such an embodiment, the number of locations of POIs in the design data may be performed by any pattern search. In addition, the number of inspected locations of POIs in the design can be determined as described above. One or more POIs corresponding to the at least one group may be determined as described further herein. This method may also include prioritizing one or more POIs based on the rate determined in this embodiment. Such prioritization may be performed as further described herein, and such prioritization results may be used as described herein.

In a further embodiment, the method includes determining a POI in design data corresponding to at least one group, determining a percentage of a die formed on the wafer at which defects binned into the at least one group are located; Assigning a priority to the POI based on the percentage. In this manner, the method may include performing a margin analysis based on the percentage of die affected by the defect. For example, the number of defects binned into groups can be divided by the number of design instances of the POI on the reticle used to print the design data on the wafer and the number of times the reticle is printed on the wafer. The result of this step is multiplied by 100 to reach a percentage. In one particular example, if there are 300 defects binned into a group and 2000 design instances of the POI corresponding to the group on the reticle, and the reticle is printed 1000 times on the wafer, the binned defects into the group are located. The percentage of die formed on the wafer is [(300) (100)] / [(2000) (1000)] or 0.015%, which is essentially a wafer based margin for a group of defects.

In this manner, the method may include prioritizing systematic defects by the number of inspection dies on the wafer at which defects are detected at least once. For example, if a systematic defect emerges as 10% of the design instance of the POI in the die for 1% of the design instance of the POI in the die, a higher priority may be assigned to the POI. In another example, a group of defects detected on multiple dies on a wafer may be assigned a higher priority than a group of defects detected on a few dies on a wafer. The method may also include generating a chart, such as a bar chart, representing the percentage of die formed on the wafer where the defects binned into different groups are located. Thus, the chart graphically shows die based margins for different defect groups. Such charts may be displayed in a user interface that may be configured as described herein. The result of such prioritization can be used as described herein.

In another embodiment, the method includes prioritizing the one or more groups by the number of total design instances on the wafer for which defects in the one or more groups are detected. The number of design instances on the wafer used in this embodiment may be the total number of inspected design instances on the wafer if all design instances on the wafer were not inspected during the inspection process used to detect the defect. In this manner, the method may include prioritizing systematic defects known as the total number of design instances on the wafer (or the total number of design instances inspected). As such, the method may include prioritizing known systematic defects based on wafer based margins. For example, a group of defects detected in a large number of design instances on a wafer may be assigned a higher priority than a group of defects detected in a small number of design instances on a wafer. Such prioritization can be performed based on the percentage of the location of the design instance (or inspected design instance) on the wafer where the defect is detected. For example, the number of defects detected and binned into a group can be divided by the total number of design instances on the wafer (or the total number of design instances inspected). The result of this step can be multiplied by 100 to reach the percentage mentioned above. The method may also include generating a chart, such as a bar chart, indicating the number of design instances (or the number of design instances inspected) on the wafer where different groups of defects were detected. Such charts can be displayed in a user interface that can be configured as described herein. Such prioritization can be further performed as described herein, and the result of the prioritization can be used as described herein.

In some embodiments, the method includes prioritizing the one or more groups by the number of design instances on the reticle used to print design data on the wafer at which defects in the one or more groups are detected at least once. The number of design instances on the reticle used in this embodiment may be the number of design instances inspected. In this manner, the method may include prioritizing a systematic defect known by the number of design instances on the reticle where the defect is found at least once. For example, a group of defects detected in a large number of design instances on a reticle may be assigned a higher priority than a group of defects detected in a small number of design instances on a reticle. The method may also include generating a chart, such as a bar chart, indicating the number of design instances on the reticle for which different groups of defects were detected. Such charts can be displayed in a user interface that can be configured as described herein. Such prioritization can be further performed as described herein, and the result of the prioritization can be used as described herein.

In another embodiment, the method includes design data printed on a reticle that is at least similar to the number of locations on the reticle where defects binned into one or more groups are detected, and portions of design data close to the locations of defects binned into one or more groups. Determining a reticle based margin for the one or more groups based on the total number of portions of. The number of locations on the reticle used in this embodiment may include the number of locations examined. For example, the reticle-based margin can be determined by dividing the number of locations in the stacked reticle map where at least one defect in a group was detected by the entire design instance on the reticle. The result of this step may be multiplied by 100 to reach a percentage of the location of the design instance, corresponding to the group in which the defect was detected. In one particular example, where there are 2000 design instances for a POI corresponding to a group on 300 reticles, binned into a group of 300 defects, and defects binned into the group are detected at 50 different locations within the reticle ( Can be determined from a stacked reticle map), the reticle based margin in this group of defects can be [(50) (100)] / (2000) or 2.5%. The method may also include generating a chart, such as a bar chart, representing the percentage or reticle based margin of the location where the different group of defects were detected. Such charts can be displayed in a user interface that can be configured as described herein. The method may also include prioritizing the defects of one or more groups based on the reticle based margin determined for the one or more groups. For example, a group representing a relatively high reticle-based margin may be assigned a higher priority than a group of defects representing a relatively low reticle-based margin. Such prioritization can be further performed as described herein, and the results of such prioritization can be used as described herein.

The steps of the foregoing embodiments can be performed for individual defects binned into groups or groups of defects as described above.

Each embodiment of the foregoing method may include any other step of any of the methods described herein. In addition, each of the foregoing method embodiments may be performed by any of the systems described herein.

As mentioned in detail above, a method embodiment for binning a defect may include determining a DCI. In addition, some methods may include determining a DCI for one or more defects detected on the wafer, and may or may not include binning the detected defects on the wafer. For example, one embodiment of a computer-implemented method of determining DCI for a defect detected on a wafer is based on an apparatus that is close to the location of a defect in a design data space, based on one or more attributes of the design data, such that the defect is on the wafer. Determining the probability of changing one or more electrical properties of the device being manufactured. The probability that a defect will change one or more electrical properties of the device may be the probability that the defect will change one or more electrical parameters of the device and / or break the die for the device. One or more attributes of the design data may include any of the design data attributes described herein. The probability may be determined based on one or more attributes of the design data in combination with one or more attributes of the defect (eg, defect size). In addition, the probability may be determined based on one or more attributes of the design data in combination with one or more attributes of the defect, the location of the defect reported by the inspection system used to detect the defect, and the coordinate accuracy of the inspection system.

In one particular example, determining the probability may include determining one or more attributes of the design data, such as the major area, for a defect in the design data. In this manner, the major area, reported defect size, and reported defect location can be used to determine the probability that the defect will change one or more electrical properties of the device. For example, as the defect size increases and the pattern complexity increases, the probability that the defect will change one or more attributes of the device also increases. Thus, a relationship describing the possibility of damage or alteration within one or more electrical properties of the device as a function of defect size and pattern complexity can be used to determine the relative risk of each defect on each wafer.

In another example, the probability is a defect size as entered into the model to determine whether the design data close to the location of the defect in the design data space, the probability of the location of the defect in the design data, and whether the defect will change one or more electrical properties of the stationary. Can be determined using. In this manner, the probability is the probability of changing one or more electrical properties of the device when the defect is located at a particular spot in the design layout.

The method also includes determining a DCI for the defect based on the probability that the defect will change one or more attributes of the device. For example, the DCI may be an index that is at least approximately correlated to the probability. In one example, a high DCI can be determined for a defect for which a relatively high probability is determined. That is, DCI is high for defects with a relatively high probability of changing one or more electrical properties of the device. The DCI can be determined from the probability using any suitable method, algorithm, data structure, etc., or some combination thereof, describing the relationship between the DCI and the probability. The methods described herein can be performed using experimental results (eg, inspection, metrology, review, test, or some combination thereof), simulation results, experimental data, design information, historical data, or some combination thereof. Generating such methods, algorithms, data structures, rules, and the like. In addition, the DCI may have any suitable format (number, alphabet, string, etc.). The DCI can be expressed in a way that the user can easily understand the value of the DCI. For example, a DCI is assigned a value between 1 and 10, with 10 being the highest DCI and 1 being the lowest DCI. The DCI may be expressed in such a way that a method or system, such as one or more embodiments described herein, may use the DCI to perform one or more steps described herein.

The method further includes storing the DCI in a storage medium. In addition, the storing step may include storing the DCI in addition to any other results of any of the method embodiments described herein. DCI can be stored in any manner known in the art. In addition, the storage medium may include any storage medium described herein or any suitable storage medium known in the art. After the DCI is stored, the DCI can be accessed and used within the storage medium by any method or system described herein. In addition, DCI may be stored "permanently", "semi-permanently", or temporarily for any period of time. In addition, storing the DCI may be performed in any other manner described herein.

In one embodiment, the defect for which DCI is determined includes a random defect. In another embodiment, the defect for which DCI is determined includes a systematic defect. In this manner, DCI can be determined for both random and systematic defects. Defects can be determined as random defects or systematic defects, as further described herein. Furthermore, while an embodiment of the method has been described as including determining a DCI for a defect, the method may include determining a DCI for one defect, some defect, or all defects detected on a wafer. have. The defect whose DCI is determined in this way can be selected by the user. Alternatively, a defect whose DCI is determined in this manner may be selected by the method (eg, one or more attributes of the defect, one or more attributes of the design data close to the position of the defect in the design data space, the defect described herein). And / or based on any other information of the design data, or some combination thereof).

In some embodiments, the one or more electrical properties include the functionality of the device. In this manner, the DCI can be determined based on the probability of a fault that can cause the device to fail or not function. In another embodiment, the one or more electrical properties of the device includes one or more electrical parameters of the device. In this manner, the DCI can be determined based on the probability that the defect will change one or more electrical parameters of the device. As such, the probability may be a probability that a defect may cause an electrical parameter issue. The electrical parameter issue is not qualified as an electrical defect in the electrical test and can initiate a defect that alters the electrical performance of the device and causes electrical defects over time on other wafers if the defect persists. It may be an instruction. The electrical parameters may include any electrical parameters known in the art such as speed, drive current, signal integration, and power dissipation of the device.

In one embodiment, the one or more attributes of the design data include redundancy, net list, or some combination thereof. In another example, the one or more attributes of the design data include the dimensions of the features in the design data, the density of the features in the design data, or some combination thereof. Such attributes can be used to determine probabilities as described above. In additional embodiments, the one or more attributes of the design data include one or more attributes of the design data for one or more design layers of the device. In this manner, the probability can be determined based on multi-layer context information about the defect, which is one or more design layers as the defect propagates through the device and because the device formed on the wafer is typically formed of multiple layers. It is beneficial if it affects. Thus, defects can change design data printed on one or more layers of the device, and changes to any layer, some layers, or all layers can change one or more attributes of the device. As such, by using one or more attributes of the design data to determine the probability, the probability can be determined based on how it affects one or more layers of the device, thereby possibly determining the probability and from it. DCI can further dictate potential parameter issues and make them more yield-related.

In some embodiments, determining the probability comprises determining a probability using a correlation between electrical test results for the design data and one or more attributes of the design data. For example, the method may include performing data mining to determine whether a correlation exists between one or more attributes of the design data and the electrical test results. In particular, one or more attributes of the design data, such as line width, spacing, etc., printed on the wafer may be measured, and electrical test results for the wafer may be used to determine the correlation between the attributes of the design data and the design data test results. . The electrical test results may include measurements of one or more attributes of one or more devices formed on the wafer, or may be used to determine one or more electrical properties of the device. Thus, the correlation may be determined as an correlation between one or more attributes and one or more electrical attributes of the design data. The electrical test results may use any suitable electrical test results generated using any method or system known in the art. Defects may be identified as random defects in accordance with any of the embodiments described herein. Such correlation can be used to determine probabilities for both systematic and random defects. Using such a correlation to determine the probability is advantageous because one or more attributes of the design data located close to the correlation and the location of the defect in the design data space can be used to determine the probability relatively quickly.

In another embodiment, determining the probabilities may include determining the probability of the location of the defect in the design data space, the location of the defect reported by the inspection system used to detect the defect, the coordinate accuracy of the inspection system, the size of the defect, the inspection system. Determining the probability based on one or more attributes of the design data in combination with a defect size error, or some combination thereof. In one such embodiment, the defect includes a random defect. In this manner, the defect size, the location of the defect reported by the inspection system, and the coordinate accuracy of the inspection system can be used to determine the DCI for the random defect. Using the defect size, defect size error, reported defect location and coordinate accuracy to determine the DCI as described above is beneficial because the size and location of the random defect are relatively unpredictable. Thus, using such information to determine the DCI may increase the accuracy of the DCI.

In a further embodiment, determining the probability includes determining the probability based on one or more attributes of the design data in combination with one or more attributes of the defect. In one such embodiment, the defect includes a systematic defect. In this way, systematic defect attributes can be used to determine the DCI for systematic defects. Defects may be identified as systematic defects in accordance with any of the embodiments described herein. Since systematic defects in the design data can be determined with relatively high accuracy in the embodiments described herein, one or more attributes of the systematic defects can be used to determine the DCI for the defect.

In one embodiment, determining the DCI includes determining a DCI for the defect based on the probability in combination with the category assigned to the defect. For example, the DCI may be determined based on the probability and the DCI may be modified based on the defect category to improve that DCI. In such an example, if the defect category indicates that the defect is a bridging defect, the DCI for the defect may be changed such that the changed DCI indicates a higher threshold for the defect than the originally determined DCI. In another example, if the defect category indicates that the defect is a partial bridging defect, the DCI determined for the defect may be changed such that the changed DCI indicates a lower threshold for the defect than the originally determined DCI. The category of defects used in this embodiment may be determined or assigned to the defects according to any of the embodiments described herein or using any other method or system for classifying defects known in the art. In addition, the DCI may be modified using any other result (eg, KP value for a defect) or any other available information (eg, hot spot information) of any step of any of the methods described herein.

In some embodiments, the method includes determining the location of inspection data in the design data space to determine design data close to the location of the defect in the design data space. In another embodiment, the method includes determining design data close to the location of the defect in the design data space by defect alignment, which may be performed as described herein. In a further embodiment, the method includes the location of a defect reported by the inspection system used to detect the defect, the coordinate accuracy of the inspection system, one or more attributes of the design data, a defect size error of the inspection system, or some combination thereof. And determining design data close to the location of the defect based at least in part on. In this manner, design data close to the location of the defect in the design data space may be determined based at least in part on the reported location of the defect and where the defect may be located within the coordinate accuracy of the inspection system. The design data beyond where the defect can be located can be determined in a similar manner.

In one embodiment, the method includes modifying the DCI based on the sensitivity of the yield of design data for a defect. In this manner, the DCI can be modified based on the sensitivity of the yield impact within the area of the design (eg, cell or functional block). For example, the method may include determining a location of a defect in a design data space that may be performed as described herein, wherein the defect is located at a location and / or a defect in the design data close to that location. Yield sensitivity due to can be determined. Such yield sensitivity can be determined using any of the embodiments described herein. For example, the method may be manufactured using design data relating to a location in the design data space for one or more different values of design data, which may be selected based on how one or more attributes may be changed by the defect. Modeling electrical characteristics of the device. Such modeling can be performed as described herein, and the modeled electrical properties can be used to determine how the yield changes as the value of one or more attributes of the design data changes, which is located at that location. It can be used to determine the yield sensitivity of design data for defects and / or defects in design data close to that location. In this manner, the location of a defect in the design data space can be used to determine the yield sensitivity of the design data for the defect. If the yield sensitivity of the design data for a defect is relatively high, the DCI for the defect may be modified such that the modified DCI indicates a higher threshold than the originally determined DCI. Similarly, if the yield sensitivity of the design data for a defect is relatively low, the DCI for the defect may be modified such that the modified DCI indicates a lower threshold than the originally determined DCI.

As mentioned above, DCI can be used in a number of ways in the embodiments described herein. For example, in one embodiment, the method includes changing the process performed on the wafer based on the DCI determined for the defect. In one such embodiment, the process may be a metrology process or may include one or more measurements on the wafer. In this manner, the method may include adopting a measurement process based at least in part on the DCI. In another example, the process is a defect review process. As such, the method may include adopting a defect review process based at least in part on the DCI. As described above, changing the process may include changing any one or more parameters of the process. In addition, such changes may be made as further described herein.

In another embodiment, the method may include changing the process used to detect the defect based on the DCI determined for the defect. Changing the process used to detect the defect may include changing any one or more parameters of the process as described further herein. In addition, changing the process used to detect a defect based on the DCI can be performed using a feedback control technique. In one such example, if the DCI for a defect indicates that the defect is relatively important, the process used to detect the defect may include one or more locations on the wafer where the defect corresponding to the defect for which the DCI was determined could potentially be located. May be altered such that it can be checked with a higher sensitivity than previously used to check these positions. Other parameters of the process can be changed in a similar manner.

In some embodiments, the method includes generating a process for inspection of an additional wafer on which the device is to be manufactured based on the DCI determined for the defect. In this way, instead of changing the previously used process in which a defect is detected, the method can create an entirely new inspection process. A new inspection process can be created for any one or more layers of additional wafers. For example, a process may be created for the layer in which a defect whose DCI is determined is detected. However, such inspection processes may be created for one or more other layers of additional wafers. For example, if the DCI for a defect indicates that the defect is relatively important, the process for inspecting a layer that is subsequently formed on the wafer may potentially locate a defect that may be caused by the defect in which the DCI was determined. It may be generated by selecting one or more parameters of the inspection process so that one or more locations on the subsequent formed layer in which they can be examined with a relatively high sensitivity. Other parameters of the process can be selected in a similar manner. Creating a process for inspecting additional wafers may be performed as described further herein.

In one embodiment, the computer-implemented method for determining DCI is performed by an inspection system used to detect a defect. In this way, the method can be performed on-tool. In another embodiment, the computer-implemented method for determining DCI is performed by a system other than the inspection system used to detect the defect. As such, the method can be performed off-tool. The system used to perform the method off-tool may be configured as further described herein.

DCI for defects can be used in a number of ways in the embodiments described herein, such as in sampling where defects for review are selected. For example, for each group of defects binned, DCI may be used for sampling instead of performing random sampling of grouped defects. In addition, the DCI determined for each defect can be used to determine which defect has a high probability of changing one or more electrical properties of the device, and defects with a high probability of changing one or more electrical properties are sampled more intensively. . DCI can be used to sample systematic defects as well as random defects.

Each embodiment of the method for determining the aforementioned DCI may include any other step of any of the methods described herein. In addition, each embodiment of the method for determining the above-described DCI may be performed by any system embodiment described herein.

Another embodiment is directed to a computer-implemented method for determining a memory repair index (MRI) for a memory bank formed on a wafer. The memory die includes a memory bank (often several memory banks). Each memory bank includes an array block region (or raw region) and a redundant region. The redundant area includes a number of columns and a number of rows and is used to repair the memory bank. The number of columns and rows included in the memory bank is user-specific. Array blocks may generally be rectangular or rectangular in shape. The redundant column may be formed along one side of the array block region, and the redundant row may be formed along the other side. The memory bank may also include a column decoder adjacent to the redundant column, a row decoder adjacent to the redundant row, and a sense amplifier adjacent to the row decoder. The method may also include detecting positions of redundant columns and rows, sense amplifiers, and decoders for each array block region. Such location may be determined using any method or system known in the art.

The method includes determining a plurality of redundant columns and a plurality of redundant rows needed to repair a memory bank based on a defect located in an array block area of the memory bank. For example, in some embodiments, the method determines which of the defects located within the array block area can cause a bit in the memory bank to fail, and based on the location of the defect that can cause the bit to fail. Determining the location of the bit to fail. Alternatively, the method may include determining which fault in the array block area may cause a bit in the memory bank to fail, and which bits may fail based on the location of the fault that may cause the bit to fail. Determining the position of the. Determining which fault in the array block area may or may cause the bit to fail may be performed using one or more attributes of the fault, which attribute may be any defect attribute described herein, and / Or the results of one or more other steps of any of the methods described herein. For example, a reported defect location, a defect, in combination with a DCI for a defect that can possibly be determined as described herein, and possibly further in combination with an electrical test result for an associated test and / or memory bank. The coordinate accuracy, defect size, and defect size inaccuracy of the inspection system used to detect the error can be used to determine whether or not the defect will cause a bit failure.

In one such embodiment, determining the number of redundant columns and redundant rows required to repair the memory bank is performed using the location of the bit to fail. This step may alternatively be performed using the location of the bits that may fail. For example, individual fault bits need not be replaced on a one-to-one basis with redundant columns and rows. Instead, if individual fault bits are "adjacent" to each other along the same logical column or row, the entire column or row becomes a candidate for replacement by the redundant column or row. Thus, the location of the faulty or faulty bits can be used to determine which faulty bits are "adjacent" to each other along the same logical column or row, and to determine the number of redundant columns and rows needed to repair the memory bank. Can be used. In this manner, the method may include predictive bit failure estimation, which may be used to determine and / or monitor the amount of redundancy that may be consumed by a failed bit.

Also, although two memory bits may be physically adjacent to each other in the layout, they may belong to different logical columns or rows. That is, physical proximity may not be associated with logical or electrical proximity. For example, if logical column 1 contains 256 bits, the 256 bits do not need to touch each other within the physical layout of the bank or segment. As such, the physical (or topology) address may be translated into a logical (or electrical) address through a mapping function that may be different for each device. Such mapping can be performed using any suitable method or system known in the art. For example, Klarity Bitmap, commercially available from KLA-Tencor, provides a graphical or easy way to generate topological-to-electrical mapping. Thus, using such a mapping function in the present method may allow the determination of the MRI to reflect the repairability of the memory bank.

Defects located within the array block area can be identified from the location of the memory bank. For example, the inspection can detect defects in both the array block area and the redundant area (or across the entire memory bank), which defects can be separated into defects in the array block area and defects in the redundant area based on the location of the defect. This may be determined in accordance with any of the embodiments described herein. Separating defects into array block regions, redundant regions, decoder regions, and sense amplifier regions provides improved values for inspection results because such separation can be used to separate repairable defects from non-repairable defects. . In addition, separation of defects into defects in the raw, redundant, decoder, and sense amplifier regions can be rule based or region based.

The method includes comparing the number of redundant rows needed to repair the memory banks to the number of available redundant columns for the memory banks. The method also includes comparing the number of redundant rows required to repair the memory banks to the available redundant rows for the memory banks. In some embodiments, comparing the number of redundant columns is performed independently for each bank of memory dies, and comparing the number of redundant rows is performed independently for each bank of memory dies. Comparing the number of redundant columns and comparing the number of redundant rows can be performed in any suitable manner.

In another embodiment, the method includes determining the amount of reserved redundant rows and aromas of the available redundant columns based on defects located within the redundant rows and redundant rows of the memory bank. Defects located within redundant columns and rows can be identified as described above. Since a memory bank failure may occur if the redundancy is sufficiently defective, it may be beneficial to determine the amount of available redundancy as described above. In addition, when the redundancy is spatially defective, the amount of redundancy available for repair of the memory bank is reduced, and when the number of failures exceeds the non-defective redundancy, the memory bank is not repairable. As noted, the amount of available redundancy is determined by the individual memory banks within the die, because each bank has its own set of redundant columns and rows, and the fault bits in each bank can only be replaced by the available redundant columns or rows in the same bank. Can be determined for.

The amount of available redundancy can be determined based on one or more attributes of a defect located in the redundant area and a defect located in the redundant area. One or more attributes used in this step may include one or more attributes described herein. Determining the available redundancy can also be performed (or alternatively) using any result of any of the steps of any of the methods described herein. For example, the reported defect size of a defect in the redundant area, the coordinate accuracy of the inspection system used to detect the defect, and the category assigned to the defect can be used to determine if the defect can cause a failure in the redundant area. It can be used to determine the amount of available redundancy.

The method further includes determining an MRI for the memory bank based on the results of comparing the number of redundant columns and comparing the number of redundant rows. The MRI indicates whether the memory bank is repairable. For example, if the number of redundant columns and / or rows required to repair the fault bit is greater than the number of redundant redundant columns and / or rows, the memory bank is not repairable and the die is not repairable. The MRI may be determined based on the compared comparison and may be assigned a value indicating whether the memory bank is repairable. For example, if the memory bank is repairable, the MRI may be assigned a first value, and if the memory bank is not repairable, the MRI may be assigned a second value. Different values for the MRI may be represented in any suitable format (eg, such values are readily understood by the user and / or the values may be used by the method embodiments described herein). Suitable formats can include, but are not limited to numbers, alphabets, strings, and the like.

The method also includes storing the MRI in a storage medium. The storing step may include storing the MRI in addition to any other results of any of the method embodiments described herein. In addition, the storage medium may include any storage medium described herein, or any other suitable storage medium known in the art. After the MRI is stored, the MRI can be accessed and used within the storage medium by any of the method or system embodiments described herein. In addition, the MRI may be stored "permanently", "semi-permanently", or temporarily for any period of time. Also (or alternatively) storing the MRI may be performed as described herein.

Thus, a handful of method embodiments can be used for the initial detection of memory loss using MRI, which is beneficial for a number of reasons and can be used in a number of ways. For example, in one embodiment, the method includes determining an MRI for one or more memory banks formed in the die and predicting a repair yield for the die based on the MRI for the one or more memory banks. Since each bank or segment of the die has a corresponding set of redundant columns and rows available for repair, estimating repair yield for the die is advantageous based on the MRI determined for the memory banks within the die. Only fault bits in a particular bank or segment may be replaced by the corresponding redundant redundant column or row. Thus, it is possible to "run out" redundancy for one bank while another bank in the die has available redundancy. In this case, since at least one bank or segment is not repairable, the die is no longer fully repairable. As such, based on the MRI for memory banks in the die, the method may determine the yield of a repair process performed on the die. In addition, an MRI indicating whether the die is repairable may be determined for the die based on the MRI determined for the memory bank in the die. For example, if the MRI for a memory bank indicates that any memory bank is not repairable, the MRI may be determined to be a value indicating that the memory die is not repairable.

In another embodiment, the method includes determining an MRI for each memory bank in at least one die on a wafer, and determining a memory yield for at least one die based on the MRI for each memory bank. do. These steps can be performed as described above. This embodiment of the method can be used to determine die-die memory yield. In addition, memory yield for one or more dies may be used to determine memory yield for a wafer.

In another embodiment, the method includes combining the memory yield prediction with the out of memory yield to determine the overall yield prediction.

In a further embodiment, the method includes performing a wafer placement based at least in part on one or more memory yields for one or more die on the wafer. For example, the methods described herein can be used to perform in-line placement of wafers, thereby allowing for better (eg, more effective) WIP planning and reduction of manufacturing costs. For example, the number of dies having a memory yield below some predetermined threshold may be determined and used to determine whether repair should be performed on the wafer, whether the wafer should be rewritten, the wafer should be scraped, and the like. In such an example, the number of dies having a memory yield below a predetermined threshold can be compared to another predetermined threshold, with both thresholds representing the minimum wafer based yield required to determine whether repair should be performed on the wafer. Can be selected. For example, the threshold is selected such that the estimated value of the wafer corresponds to a minimum memory yield that does not exceed the cost of completing the wafer (eg, by the user or by one or more embodiments described herein). In another embodiment, the method may include determining a memory yield for the wafer based on the memory yield for one or more dies on the wafer. Thus, if a memory repair process is performed for one or more dies on a wafer, the memory yield may be the yield after that memory repair process. Memory yield for the wafer may be used to place the wafer as described above. For example, the value of the wafer after the memory repair process can be determined based at least in part on the memory yield, and the value can be compared to the cost of completing the wafer to determine if the wafer should be scrapped.

In one embodiment, comparing the number of redundant rows includes determining a fraction of redundant rows needed to repair the memory banks, and comparing the number of redundant rows comprises determining the fraction of redundant rows required to repair the memory banks. Determining the MRI for the memory bank, and determining the MRI based on the fraction of redundant columns and the fraction of redundant rows.

The method comprising determining the MRI based on the fraction as described above may include any of the other steps described herein. For example, in one such embodiment, the method includes determining an MRI for each memory bank in at least one die on a wafer, and determining a memory yield for at least one die based on the MRI for each memory bank. Include. The steps of this embodiment may be performed as further described herein. In another example, in such another embodiment, the method includes determining an MRI for each memory bank in at least one die on a wafer, and determining memory yield for at least one die based on the MRI for each memory bank. Determining and determining the memory yield for the wafer based on the memory yield for each one or more dies. The steps of this embodiment may be performed as further described herein. In this manner, the method may include using MRI to predict memory yield on a wafer to wafer basis. In a similar manner, MRI can be determined for each die on a wafer, and MRI for each die can be used to determine wafer-based memory yield. For example, wafer-based memory yield can be divided by the sum of the MRI for each die on the wafer by the number of die on the wafer to determine the fraction of die on the wafer that is good or repairable for the memory. The fraction of die on a good or repairable wafer can possibly be used in combination with information about the repair process, such as historical yield or success rate.

In some embodiments, the MRI may also indicate the probability that the memory bank cannot be repaired. In this manner, the MRI may indicate whether a memory bank is repairable and how that memory bank is not repairable. The probability that a memory bank is unrepairable is determined by comparing the number of available redundant columns to the number of redundant columns required for repair and the number of available redundant rows to repair, which may be performed as described above. Based on one or more attributes of the defect, one or more attributes of the memory design, and possibly one or more attributes of the repair process. Such an attribute may include, for example, the historical success rate of a repair process performed in another memory bank whose design is at least similar for the memory bank whose probability is being determined. The MRI can be expressed in two values: one indicating whether or not the memory bank is repairable and the other indicating the probability that the memory bank is not repairable. Alternatively, the MRI may be represented by a single value that indicates whether the memory bank is repairable and whether the memory bank is repairable. The two values and the single value can be expressed in any of the formats described herein. In one such embodiment, the method includes determining an MRI for each memory bank in at least one die on a wafer, and determining an MRI for at least one die based on the MRI for each memory bank in at least one die. It includes a step. These steps can be performed as described herein. In one such embodiment, the MRI for one or more dies indicates the probability that one or more dies may not be repairable (the MRI for each memory bank indicates the probability that the memory banks may not be repairable, and the repair of the dies). Since the possibility relates to the repairability of the memory bank as described further here). In one such embodiment, the method includes determining wafer based memory yield based on a threshold of MRI for one or more dies on a wafer. Wafer based memory yield prediction may be performed as described above, but the yield of the wafer may not be the yield of a repair process as described above.

In some embodiments, the method includes identifying an uncorrectable defect in a memory bank based on one or more defects located within a decoder region of a memory bank, one or more defects located within an amplifier region of a memory bank, or some combination thereof. do. For example, inspection of the memory bank may be performed to detect defects in all regions (including logic periphery, decoder region, and sense amplifier region) within the memory bank, and may be determined according to any of the embodiments described herein. The location of a defect in a memory bank in which it is located may be used to determine in which region of the memory bank each or more than one defect is located. The number of non-repairable defects in the memory bank may be determined at least in part by the number of defects detected and located in the decoder region and the sense amplifier region. The method may also include estimating a memory yield based at least in part on an unrepairable defect in the memory bank, which is advantageous because the unrepairable defect can damage the die.

In one embodiment, the method includes changing one or more parameters of the electrical test process based on MRI using a feed forward control technique. In another embodiment, the method uses feed forward technology to change one or more parameters of the electrical test process based on MRI such that if the memory bank is unrepairable, the die on which the memory bank is located is not tested during the electrical test process. It includes a step. For example, the memory test takes a relatively long time. Thus, based on the prediction that the memory bank or memory die is unrepairable, which can be determined as described above, the information is sent to a probe or other memory test system such that the affected unrepairable die is skipped during the memory test. Can be supplied. In this way, the test amount can be reduced, thereby reducing the cost of the memory test. Memory tests may also include open / short tests, functional tests, and electrical parameter tests. If such a test can be eliminated using the method described herein to determine which die can be repaired, the memory test process can be performed in a much shorter period of time. Alternatively, the electrical test process can be modified to collect more relevant test data for additional FAs on the die that cannot be repaired, and the test can be based on specific locations based on the predicted impact of various possible failure mechanisms. Can be focused on. In addition, memory repair may include laser or electrical means to blow a fuse, thereby re-routing the decoder to redundant columns and / or rows. The memory test can be performed after the memory repair to verify the repair and run additional tests such as stress tests. Thus, by determining which die can be repaired as described herein, memory repair and additional memory tests can only be performed on the repairable die, thus saving much time.

In some embodiments, the method includes changing one or more parameters of the repair process based on one or more attributes of the defect, MRI, or some combination thereof located within the array block of the memory bank. For example, the memory repair process may be modified such that repair is not attempted for a memory die that includes memory determined to be unrepairable. In addition, the memory repair process can be modified to increase the probability that the repair will be successful. In one embodiment, one or more parameters of the repair process modified may include any of the parameters of the repair process.

In some embodiments, the defect includes a defect detected in the gate layer of the memory bank. In another embodiment, the defect includes a defect detected in the metal layer of the memory bank. For example, in memory fabrication, the inspection can be performed on the gate layer and the metal layer. The method described herein can be performed on defects detected in one or more of these layers. In addition, although most memory fabrication involves inspection in the gate and metal layers, and inspection results generated in the gate and metal layers are sufficient to predict yield, the inspection can also be performed in the capacitor layer for bit repair. Thus, the test results generated at the gates, metals, and capacitors can also be used to predict the yield. In addition, the embodiments described herein may be performed for defects detected in the capacitor layer.

In one embodiment, the method includes predicting the bit error mode of the defect based on the location of the defect in the memory bank. In this way, the location of the defect can be used to predict the bit error mode. Such information may be valid for determining the amount of redundancy needed to repair the memory bank. For example, a defect in the n-MOS region of the memory bank can cause a sense amplifier error, thereby consuming more redundancy than a defect in the n-MOS region. One or more attributes of the design data close to the defect and / or one or more attributes (eg, size) of the defect may be used to improve prediction of the bit error mode. In addition to supporting the prediction of redundancy needed for repair, the prediction of error mode will result in a faster or better identification of the fault causing the bit error. All predictions can allow the DOI to be identified and reviewed, which would be impossible without FA if no bit error was detected in the test. It is possible to identify and review the defects responsible for the potential failure of the device and use available redundancy to reduce the potential error rate. In this manner, defects may be mapped to regions of memory (eg, sense amplifiers), and defects and / or design attributes may be used in combination with rules for predicting bit error modes.

In some embodiments, the method includes determining, based on the MRI, whether the amount of available redundant rows in the memory bank, the amount of available redundant columns, or some combination thereof is to be evaluated by the memory bank designer. In this manner, the method may include performing a "redundancy analysis" to suggest to the designer whether adding more columns or rows in the redundant area must be performed in a particular memory bank. The method described herein is particularly beneficial for providing feedback regarding the design of the die, since the method described herein can be used for early detection of critical wafers and allow for rapid yield learning.

In another embodiment, the method includes determining a DCI for one or more defects located within the array block area. DCI for one or more defects can be determined as described herein. In one such embodiment, determining the number of redundant columns required for repair of the memory bank and determining the number of redundant rows are performed using DCI for one or more defects. In another embodiment, determining the number of redundant rows required for repair of the memory bank, and determining the number of redundant columns, determining the DCI for each defect located within the array block area of the memory bank; Comparing the DCI with a predetermined threshold and determining the number of redundant columns and redundant rows required to repair all defects having a DCI above the predetermined threshold. For example, DCI may be determined for all defects located within the array block area. DCI may perform on defects located within the array block as described further herein. The method may also include predicting the number of column or row errors caused by the defect using DCI. For example, if the number of defects with a DCI greater than a predetermined value that can be user specified is greater than the number of columns or rows in the redundant area, the MRI (in this example, Defined as a ratio) can be determined to be greater than one (failure). In contrast, if the number of defects having a DCI smaller than the second predetermined value that can be user defined and different from the first predetermined value is less than the number of columns or rows in the redundant area, the MRI is determined to be less than one. (Passed, perhaps with some repairs). The method may also include determining a maximum count or percentage of available redundant columns and / or rows that may be needed to repair the memory bank if all defects with a DCI above a threshold require repair.

Since the actual yield impact of an individual defect may vary depending on the pattern error caused by the defect, the location of the defect (e.g., the top of the layer, buried in the layer, etc.), one or more attributes such as the defect size, etc. It is beneficial to use DCI to determine if it is repairable. DCI can be determined based on such variations in defects as described herein, thereby reflecting how different defects affect the actual yield. In addition, since systematic defects have more actual yield impact, the method described herein includes determining which defects detected within a memory bank are systematic defects, and based on the criticality of the systematic defects as described herein. As well as determining the MRI. Systematic defects may be identified in accordance with any of the embodiments described herein.

In some embodiments, the method includes determining an MRI for an error in the memory bank due to a defect located within the array block area of the memory bank. In this manner, the method may include determining an index for segment errors due to defects detected within the non-redundant region of the memory bank. In a similar manner, the method may include determining an index for segment error due to a defect detected within a redundant area of the memory bank.

In another embodiment, the method includes determining an MRI for an error in the memory bank due to a defect located in the redundant column and redundant row of the memory bank. In this manner, the method may include determining an index for logical columns and / or row errors. Such an index can be used to change one or more parameters of the test process as described above.

In some embodiments, the method includes generating a stacked map of the pseudo memory bank design indicative of the spatial correlation between defects detected within the memory bank. In this manner, the method may include generating a stacked map representing spatial correlation. Such a stacked map can be generated in any suitable manner known in the art.

In one embodiment, the method includes determining an MRI on a die basis. In a similar manner, the method may include determining an MRI based on a wafer substrate and / or lot. Determining the MRI on a die basis, wafer basis, and / or lot basis may be performed as described herein.

In another embodiment, the method includes determining an index or memory yield prediction that indicates whether a die on the wafer will fail due to a defect located in an array block area. In this manner, the method may include determining an index or probability that the die will fail due to a bad memory bank. This index can be determined as described further herein.

In a further embodiment, the method includes determining an MRI for a memory bank in a die on a wafer, and generating a stacked map of the die representing a spatial correlation between two or more memory banks indicated by the MRI as non-repairable. It includes. Determining the MRI for a memory bank in the die may be performed as described herein. In addition, the stacked map can be generated in any suitable manner known in the art.

In a further embodiment, the method includes determining an MRI for a memory bank in a die on the wafer and forming a memory bank on the wafer that exhibits a spatial correlation between two or more memory banks indicated by the MIR as non-repairable. Generating a stack map of used reticles. In addition, the stacked map can be generated in any suitable manner known in the art.

In some embodiments, the method includes identifying a memory bank of a die affected by a defect detected in the die, and ranking the memory bank based on the impact of the defect on the memory bank. . In this manner, the method may include ranking the affected memory bank list. The impact of a defect on a memory bank can be determined based on any of the information described herein (eg, one or more attributes of the defect, one or more attributes of the design data for the memory bank, etc.). The effect of the defect on the memory bank, used to rank the memory bank, may include any effect that the defect has on the memory bank (eg, any adverse effect). Memory banks are ranked in such a way that the highest rank is assigned to the memory bank most affected by the fault and the lowest rank is assigned to the memory bank least affected by the fault. Such a class of memory bank can be used, for example, to determine the relationship between the location of the memory bank within the die and the extent to which the defect affects the memory bank. In addition, such a relationship can be used to predict the cause of at least some of the defects, which can be used to reduce defects on additional wafers and / or reduce defects with less impact on the memory bank (e.g., 1 above). By using the above change steps, one can first reduce the number of defects that have the most impact on the memory bank (e.g., change the process performed on the memory bank prior to detection of the fault). Can be used).

In another embodiment, the method includes determining a percentage of the memory bank formed on the wafer affected by a defect in the non-repairable area of the memory bank. The memory banks affected by the defects in the unrepairable areas of the memory banks can be determined as described herein. The percentage can be determined based on the number of such memory banks and the total number of memories formed on the wafer. The method may also include determining the percentage of die affected by possible redundancy errors and / or affected by unrepairable errors. Possible redundancy errors and uncorrectable errors can be identified as described herein. In addition, die affected by possible redundancy errors and / or unrepairable errors may be identified as described herein. The number of dies affected and the total number of dies formed on the wafer can be used to determine the percentage of dies affected by possible redundancy errors and / or unrepairable errors.

In some embodiments, the method includes generating a stacked wafer map of possible errors in a memory bank formed on a wafer that exhibits a spatial correlation between possible errors. In this manner, the method may include generating a stacked wafer map of binned exsex (for spatial correlation) or possible errors. Possible errors can be identified as described herein, and the stacked wafer map can be generated in any suitable manner. The stacked map may alternatively indicate or overlay the probability that the die will have a memory error by a method such as a color coding probability bin.

In another embodiment, the method includes determining an MRI for at least one die formed on the wafer and ranking the at least one die based on the MRI. In this manner, the method may include generating a ranked list of affected die on the wafer. MRI for one or more dies can be determined as described herein. In addition, grading one or more dies based on the MRI may be performed as described herein, and such ratings may be used as described herein.

The method of determining the MRI described above may include any other step of any of the methods described herein. In addition, each embodiment of the method for determining the MRI described above may be performed by any of the system embodiments described herein.

Another embodiment relates to another method of binning detected defects on a wafer. This method includes comparing a location of a defect in the design data with a location of a hot spot of the design data. Hot spots located at least close to similar design data are correlated with each other. Hot spots are correlated by any other method or system. Alternatively, hot spots may be correlated with one another by one embodiment of the method. For example, in one embodiment, the method includes correlating hot spots by identifying locations of POIs in design data associated with systematic defects, and correlating POIs with similar patterns in design data. Correlating the position of the POI with the position of a similar pattern in the design data as the position of the hot spot. In one such embodiment, systematic defects may be included in a data structure such as a list, a database, or a file of systematic defects for design data, which may be generated by other methods or systems. In another such embodiment, the method includes identifying a systematic defect and / or determining a POI in the design data for the systematic defect. For example, systematic defects may be identified by binning the detected defects on the wafer based on the portion of the design data close to the position of the defect in the design data space, which may be performed as described above. POIs can be determined by extracting a pattern in a portion of the design data corresponding to a group of binned defects, and hot spots can be correlated with each other using design background grouping, which will be performed as further described herein. Can be. In addition, hot spots may be correlated with one another by binning the hot spots, which may be performed as further described herein. Correlating the hot spots together may be performed on-tool. The location of the correlated hot spots can be stored in a "hot spot list" or any other suitable data structure, where the data structure provides some indication of which hot spots are associated with each other, the identity of the hot spots in the list, and Contains the location of the hot spot in the list. This list can be used essentially as reference data in the binning method.

The method also includes associating the defect with a hot spot having at least a similar location. In particular, hot spots and defects having at least similar locations in the design data space can be determined based on the results of the foregoing comparison step. Hot spots and defects with locations in the design data space are related to each other in any suitable manner. The method also includes binning the defects into groups such that the defects in each group are only associated with hot spots associated with each other. In this way, each group of defects may correspond to a correlated group.

The method further includes storing the result of the binning step on a storage medium. The storing step may include storing the results of the binning step in addition to any other results of any of the method embodiments described herein. The result of the binning step can be stored in any manner known in the art. In addition, the storage medium may include any storage medium described herein or any other suitable medium known in the art. After the results of the binning step have been stored, the results of the binning step can be accessed and used by any method or system as described herein. In addition, the results of the binning step may be stored "permanently", "semi-permanently", or temporarily for any period of time. Storing the results of the binning step may be further performed in accordance with any other embodiment described herein.

In one embodiment, the method includes assigning a DBC to at least one group. Assigning a DBC to one or more groups may be performed according to any of the embodiments described herein. In another embodiment, the method includes determining a DCI for one or more defects. Determining the DCI for one or more defects in this embodiment may be performed according to any of the embodiments described herein.

In another embodiment, the computer-implemented method is performed by an inspection system used to detect defects on the wafer. In this manner, computer-implemented methods can be performed on-tool. The method may also include performing hot spot management on-tool. Hot spot management may include, for example, hot spot search, hot spot monitoring, hot spot revision, or some combination thereof, each of which may be performed as further described herein. For example, in some embodiments, hot spots are identified by the inspection system used to detect defects on the wafer. In this manner, hot spots can be identified or searched on-tool. Such identification or searching of hot spots may be performed as described herein (eg, by performing design background based grouping of detected defects on the wafer).

In another embodiment, the method includes monitoring hot spots using inspection results of one or more wafers on which design data is printed. Monitoring the hot spots based on the test results may be performed as described herein. Such monitoring of hot spots can be performed on-tool. Monitoring of hot spots may be performed as a result of the above-described inspection, as a result of one or more binning methods described herein, or as a result of assigning one or more DBCs to one or more defects, which may be performed as described herein, It may also be performed (or alternatively) using any other result of the method, or some combination thereof.

In another embodiment, the method includes inspecting the wafer based on the correlation between hot spots. For example, the locations on the wafer corresponding to different groups of correlated hot spots can be examined differently. Wafer inspection based on correlation between hot spots may also be performed based on one or more attributes and correlations of design data corresponding to a group of correlated hot spots. For example, the location of a group of correlated hot spots corresponding to design data with particularly high yield sensitivity to defects can be used to determine the location on the wafer to be inspected with a higher sensitivity than conventional. One or more attributes of the design data used in this embodiment may include one or more design data attributes described herein. In addition, one or more parameters of the inspection process may be modified such that the locations on the wafer corresponding to different groups of correlated hot spots can be inspected differently. One or more parameters of the test may include one or more parameters described herein.

In some embodiments, the method includes monitoring systemic defects, potential systematic defects, or some combination thereof over time using the results of the binning step, in accordance with any of the embodiments described herein. Can be performed. In another embodiment, the method includes identifying systematic and potential systematic defects in the design data based on the results of the binning step, and monitoring the occurrence of systematic and potential systematic defects over time. . The steps of this method embodiment can be performed as described herein.

In another embodiment, the method includes performing a review of the defect based on the result of the binning step. For example, the review of the defects may be performed such that the defect groups corresponding to different groups of correlated hot spots are reviewed differently (eg, using at least one different value of one or more parameters of the review process). Wafer review based on the results of the binning step may be performed based on the binning results and one or more attributes of the design data corresponding to the group of hot spots correlated with each other. In this manner, review of defects based on the results of the binning step can be performed as described above for inspecting the wafer based on the correlation between hot spots.

In a further embodiment, the method includes creating a process for selecting a defect for review based on the results of the binning step. Creating a process for selecting a defect for review in this embodiment may be performed according to any of the embodiments described herein. In addition, the process for selecting defects for review may be combined with information about correlated hot spots associated with a group of defects, possibly resulting from any other step of any method described herein and described herein. It may be generated based on the results of the binning step in combination with any other information (eg, one or more attributes of the design data, one or more attributes of the defect, etc.). In addition, creating a process for selecting a defect may include selecting a value for any one or more parameters of the process used to select the defect.

In another embodiment, the method includes creating a process for inspecting a wafer on which design data is printed based on the results of the bitmap step. Creating a process for inspecting the wafer in this embodiment may be performed according to any of the embodiments described herein. In addition, the process for inspecting a wafer may be combined with information about correlated hot spots associated with a group of defects, possibly resulting in any other step of any method described herein (eg, 1 of design data). In combination with the above attributes, one or more attributes of the defects, etc.). In addition, creating a process for inspecting the wafer may include selecting a value for any one or more parameters of the process used to inspect the wafer.

In a further embodiment, the method includes changing a process for inspecting a wafer on which design data has been printed based on the results of the binning step. Changing the process for inspecting the wafer in this embodiment may be performed according to any of the embodiments described herein. In addition, the process for inspecting a wafer may, in combination with information about correlated hot spots associated with a group of defects, possibly result from any other step of any of the methods described herein (eg, design data). In combination with one or more attributes, one or more attributes of the defect, etc.). In addition, changing the process for inspecting the wafer may include selecting a value for one or more parameters of the change process used to inspect the wafer.

In some embodiments, the method includes determining a percentage of the die formed on the wafer affected by the at least one group of defects. In such embodiments, the percentage of die may be determined in accordance with any of the embodiments described herein.

In another embodiment, the method includes determining a percentage of the die formed on the wafer where the defects binned into the at least one group are located, and assigning a priority to the at least one group based on the percentage. do. Determination and assignment of priorities may be performed in accordance with any of the embodiments described herein.

In a further embodiment, the method includes prioritizing the one or more groups by the total number of hot spots correlated with the hot spots associated with the defects in the one or more groups and the number of defects in the one or more groups. For example, the number of hot spots in a correlated hot spot group may be compared to the number of defects in the group corresponding to the hot spot group. As such, a defect degree of a group of correlated hot spots may be determined (eg, in determining the fraction of correlated hot spots in which a defect is detected and / or in determining the percentage of correlated hot spots in which a defect is detected. due to). Thus, groups of defects can be prioritized by the degree of defects of the correlated hot spots. For example, a large percentage of defects, large fractions, or corresponding hot spots in a large number of detected groups may be assigned a higher priority than a small group of small number of detected defects, or a small percentage of corresponding hot spots. have. Thus, groups of defects can be prioritized according to the hot spot defect degree across the wafer.

In a further embodiment, the method prioritizes one or more groups by a number corresponding to a hot spot location on the reticle used to print design data on a wafer where defects in one or more groups are detected at least once. It includes. For example, a defect group corresponding to a plurality of hot spot locations on the reticle may be assigned a higher priority than a defect group corresponding to a few hot spot locations on the reticle. Thus, groups of defects can be prioritized based on the potential degree of defects across the wafer. In addition, when the number of times a reticle is to be printed on a wafer is known or determined, the potential defect degree of the group across the reticle can be used to determine or estimate the potential defect degree of one or more groups across the wafer. The result of the prioritization step can be used to perform one or more of the steps described herein.

In some embodiments, the method is based on the number of locations on the reticle where defects binned into one or more groups were detected, and the total number of hot spot locations on the reticle correlated with hot spots associated with defects in one or more groups, Determining a reticle-based margin for one or more groups. For example, the number of locations in which a defect in a group of correlated hot spots on a reticle is detected may be compared to the number of locations in which a defect in a group corresponding to a group of correlated hot spots is detected. Thus, the reticle based margin may be based on such a comparison and may be a measure of defect degree over the location of correlated hot spots across the reticle. Such reticle-based margins can be used in one or more steps as described herein.

Each of the method embodiments for binning defects as described above may include any other step of any of the methods described herein. In addition, each of the method embodiments for binning defects as described above may be performed by any of the system embodiments described herein.

Another embodiment relates to another method for binning detected defects on a wafer. In this embodiment, the method includes comparing one or more attributes of the design data close to the location of the defect in the design data space. In one embodiment, the one or more attributes include pattern density. In another embodiment, the one or more attributes include one or more attributes in the feature space. The feature space may include one or more features derived from design data. Unlike design spaces, feature spaces have the ability to effectively account for multiple attributes that can be useful for grouping defects in a supervised manner (e.g., closest binning technique) or non-supervised (e.g., natural grouping technique). Has One or more attributes of the design data used in this step may also include (or alternatively) any other attributes of the design data, defect data, hot spots, or POIs described herein.

The method also includes determining based on the results of the comparing step whether one or more attributes of the design data close to the location of the defect are at least similar. Determination of whether at least one attribute is at least similar may be performed in a similar manner to other steps for determining similarity described herein. The method also includes binning the defects into groups such that at least one attribute of the design data close to the location of the defects in each group is at least similar. The binning step can be performed in a similar manner to the other binning steps described herein. The method further includes storing the results of the binning step in a storage medium, which may be performed as described herein.

In some embodiments, the method includes using an attribute to determine whether the defect is a random or systematic defect. In addition, attributes can be used directly for random or systematic defects. One or more attributes may be used to determine whether binned and / or non binned defects are random or systematic defects. In order to determine whether a defect is a random defect or a systematic defect, one or more attributes of the design data may include any other result described herein and / or any other information described herein (eg, hot spot information and one or more of the defects). Property). In one example of the foregoing embodiments, one or more attributes of the design data used to determine whether the defect is systematic or random may include one or more attributes of the feature of the design data at the location of the defect relative to the feature. For example, if one or more attributes of the design data close to the location of the defects in the design data space have a relatively high pattern density, relatively small feature dimensions, and the design data having such attributes is susceptible to systematic defects (which is experimentally , Simulation, or any other suitable method or system), the defect is determined to be a systematic defect.

In another embodiment, the method includes ranking one or more groups using the attribute. The one or more attributes used to grade the defects in the binned one or more groups may include any of the attributes described herein. In one example, a group of binned defects is more likely to have a group of defects associated with a higher pattern density than a group of defects associated with a lower pattern density because defects located in the high pattern density region of the design may have a greater detrimental effect on yield. It can be graded based on the pattern density so that it is graded high. Such ranking results may be used as described herein (eg, the results may be used in place of prioritization results at the step of including the prioritization results).

Attributes can also be used to grade defects within a group. For example, in a further embodiment, the method includes ranking defects into at least one group using one or more attributes. The attributes of the design data used to grade the defects in groups may be any of those described herein. In addition, the attributes used to bin the defects may or may not be the same as the attributes used to rank the defects in the group. The binning and grading steps in this embodiment can advantageously provide for fine separation of defects into groups and grades, which can provide more information about the effect of defects on yield. Grading the defects in the group can be performed as described herein. In addition, defects in one or more groups can be graded individually within its group. The grading of the defects in the group can be used in one or more of the steps described herein.

Attributes can also be used to bin defects within a group. For example, in a further embodiment, the method includes binning the defects in the at least one group into sub-groups using one or more attributes. The attributes of the design data used to bin the defects within a group into sub-groups may include any of the attributes described herein. Also, the attribute used to bin defects into groups may or may not be the same as the attribute used to bin defects into sub-groups. In this embodiment binning the defects into groups and sub-groups can advantageously provide a finer separation of the defects into groups and sub-groups, which can provide more information about the effect of the defects on yield. Can be. Binning the defects in one group into sub-groups may be performed as described herein. In addition, defects in one or more groups may be binned individually into one or more subgroups. The results of binning defects into the above groups and sub-groups can be used in one or more steps described herein.

In some embodiments, the method comprises analyzing defects in at least one group using one or more attributes. In this way, attributes can be used to analyze defects within a group. DCI determination is an example of this type analysis. For example, in a further embodiment, the method includes assigning DCI to one or more defects using attributes. The attributes of the design data used to analyze the defect may include any of the attributes described herein. The analysis may also include (or alternatively) any other analysis described herein.

In another embodiment, the method includes determining yield relevance of one or more defects using one or more attributes. In this way, attributes can be used to estimate the yield relevance of individual defects. One or more attributes used to determine yield relevance may include any of the attributes described herein. In one such example, a defect located closer to design data with a relatively high pattern density may be determined to be more yield related than a defect located closer to design data with a relatively low pattern density. In addition, yield relevance may be determined based on one or more attributes of the design data and how defects affect yield based on such one or more attributes. The defects for which yield relevance has been determined may or may not include binned defects.

In a further embodiment, the method includes using the attribute to determine the overall yield relevance of one or more groups. Thus, the attribute can be used to estimate the overall yield relevance. The overall yield relevance can be determined as described above.

In some embodiments, the method includes separating design data close to the location of the defect into design data in the area around the defect and design data in the area in which the defect is located, which may be performed as described herein. . The attribute can also be used to distinguish near the bond from the area where the defect will be located.

In another embodiment, the method includes identifying a structure in the design data for binning or filtering using rules and attributes. For example, the method may include identifying a structure such as a LES-sensitive structure, a large poly block, etc. using one or more attributes and rules of the design data, where defects located close to the structure are grouped. It can be binned and / or filtered from the results. The rules may be generated by the methods described herein using experimental results and / or simulation results or any suitable method.

In another embodiment, the method includes determining a location on a wafer on which a review, measurement, test, or some combination thereof is to be performed, based on a test result generated during detection of a defect and a defect identified as a systematic defect. This can be done according to any of the embodiments described herein. In some embodiments, the method determines the location on the wafer where a review, measurement, test, or some combination thereof is to be performed, based on inspection results generated during detection of the defect, defects identified as systematic defects, and yield relevance of the defects. Determining, which may be performed as described herein. In a further embodiment, the method determines a location on the wafer on which a review, measurement, test, or some combination thereof is to be performed, based on inspection results generated during detection of the defect, defects identified as systematic defects, and process window mapping. Which may be performed as described herein.

In some embodiments, the method includes performing a systematic search using the results of the binning step and the user-assisted review. For example, the results of the binning step can be used to assist the user in the review (eg, to determine where to review, review method, and the like). The review may comprise generating a review result (eg, a high magnification image) for at least one defect in one or more groups, and reviewing the result so that the user can identify one or more defects or defects in one or more groups as systematic defects. It may include the step of displaying to.

In another embodiment, the method includes, prior to the comparing step, separating the defects based on the functional blocks in which the defects are located to improve S / N at the result of the binning step. The functional block in which the defect is located can be determined as described herein. By separating the defects by the functional block prior to the comparing step, the defects in some (eg non-yield related) functional blocks can be removed from use at other stages of the method, which results in S / N in binning results. Will increase. In addition, binning can be performed based on one or more attributes of the design data, in combination with the functional block in which the defect is located, thereby providing better separation and higher S / N in the binning results. In addition, binning can be performed individually for each functional block or for one or more different functional blocks, thereby increasing the S / N for the binning result.

In another embodiment, the design data is organized into hierarchical cells, and the method further comprises, prior to the comparing step, separating the defects based on the hierarchical cell in which the defects are located to improve S / N at the result of the binning step. It includes. Design data may be organized into hierarchical cells as further described herein. Separating the defect based on the layer cell may be performed as described above for functional block based separation. Separating the defect based on the layer cell can be used to improve the S / N of the result of the binning step as described above.

In a further embodiment, the design data is organized into hierarchical cells by design, and if the defects can be located in one or more hierarchical cells, the method may be based on a region of the hierarchical cell, a defect location probability, or some combination thereof. Correlating defects to each layer cell based on the probability of being located within each layer cell. In this manner, if a defect can be located in multiple cells, the defect is correlated to that cell based on the probability that the defect is located in a different cell, which can be determined based on the area of the defect location probability. The probability can be determined in any manner known in the art.

In some embodiments, a defect is detected by an inspection process, the method comprising reviewing a location on a wafer where one or more POIs in the design data are printed, and reviewing whether a defect should have been detected at a location of one or more POIs. Determining based on the results and altering the inspection process to improve one or more defect capture rates, which may be performed as further described herein.

Each embodiment of the method for binning the above-described defects may include any other step of any of the methods described herein. In addition, each embodiment of the method for binning the above-described defects may be performed by any system embodiment described herein.

As noted above, the location of the design data close to the location of the defect may be compared to the design data (eg, POI design example) corresponding to different DBCs (eg, DBC bin definitions) stored in a library or other data structure. One embodiment in which such a library or data structure can be used is a computer-implemented method for assigning categories to defects detected on a wafer. This method includes comparing a portion of design data close to the location of a defect in the design data space to design data corresponding to different DBCs. Comparing portions of design data (or “source portions” of design data) to design data (or “target portions” or “reference patterns” of design data) corresponding to different DBCs may be performed as described herein. Can be. In some embodiments, the method includes comparing one or more attributes of the portion of the design data to one or more attributes of the design data corresponding to different DBCs. Comparing one or more attributes of the design data within that portion, and one or more attributes of the design data corresponding to the different DBCs being compared in this step, may include any of the attributes described herein. In addition, the one or more attributes used in the comparing step may include one or more attributes in the feature space. The comparing step may also include comparing a portion of the design data to a reference pattern to determine if there is an exact match or similarity between the source and the reference pattern. Further, the comparing step may include using any of the rules described herein or a rule based on any method for performing the comparing steps described herein. Further, the comparing step may include comparing the location of the defect in the design data space to the location of the hot spot in the design data space, which may be performed as described herein.

The dimensions of at least some of the portions are different in some embodiments, and the dimensions can be selected and / or determined as further described herein. In another embodiment, the design data in that portion includes design data for one or more design layers. Such portions of design data may be constructed and used in a method as further described herein. The design data in that portion may include any other design data described herein. For example, design data close to the location of the defect includes design data in which the defect is located in one embodiment. In this manner, the design data used in the method may include design data below or behind the defect, or design data where the defect will be located. In another embodiment, the design data close to the location of the design data includes design data around the location of the defect.

In a further embodiment, the method further comprises, prior to the comparing step, converting a portion of the design data close to the location of the defect into a first bitmap, which may be performed as described herein, and before the comparing step. And converting the design data corresponding to the DBC into a second bitmap, which may be performed as described herein. In one such embodiment, the comparing step includes comparing the first bitmap and the second bitmap. Such comparison step can be performed as further described herein. Embodiments of a method of assigning a category to a defect may include determining a location of the defect within a design data space in accordance with any of the embodiments described herein.

In one embodiment, the DBC identifies one or more polygons in the design data where the defect is located or near the defect. In this manner, one or more polygons in which the defect is located or one or more polygons located near the defect can be identified by the DBC assigned to the defect. As such, one or more polygons may be determined that may or may not be affected by the defect. In addition, one or more polygons in which the defect is located or one or more polygons located near the defect can be identified and information about these polygons can be used to determine the location of the defect with respect to the polygon in the design data. In some embodiments, the DBC identifies the location of a defect in one or more polygons in the design data. Thus, the method may include determining a location at or near the defect in the polygon based on the DBC assigned to the defect.

In another embodiment, the method includes separating design data near the portion of the defect into design data in the region around the defect and design data in the region in which the defect is located. In this manner, the method may include distinguishing the perimeter around the defect from the area where the defect will be located. Such separation can be performed as further described herein. Such separation may also be used in a computer implemented method for assigning a category to a defect as described further herein.

Design data corresponding to different DBCs and their different DBCs are stored in a data structure. In addition, design data corresponding to different DBCs and their different DBCs may be stored in a data structure as described above. In particular, design data corresponding to different DBCs and their different DBCs may be stored as DBC library files within the data structure. In addition, in one embodiment, the data structure may be a library containing examples of design data organized by description, process, or some combination thereof. In this manner, the data structure can include a set of POI design examples that can be used to classify defects on-tool, and the POI design examples can be organized by description, process steps, or any other suitable information. The data structure may include any suitable data structure known in the art, and may be stored in a storage medium such as one storage medium described herein or any other suitable storage medium known in the art.

The method also includes determining, based on the result of the comparing step, whether the design data in the portion is at least similar to the design data corresponding to the different DBCs. This determination step may be performed in accordance with any of the embodiments described herein. In some embodiments, the determining step includes determining whether the design data in the portion is at least similar to the design data corresponding to the different DBC, and based on the comparing step, the design data in the portion corresponding to the DBC in which the design data in the portion corresponds to the different DBC. Determining whether it is at least similar to at least one attribute. One or more attributes may include any of the attributes described herein. For example, one or more attributes may be associated with defects and / or information about the inspection system used to detect the defect (e.g., inspection system type, one or more parameters of the inspection system operating at the time the defect is detected, etc.) and / or defects. For attributes (eg, size, rough bin, polarity, etc.).

The method also includes assigning a defect to the DBC corresponding to the design data at least similar to the design data in the portion. The assignment step can be performed in any suitable manner. In some embodiments, the assigning step comprises assigning a defect to the DBC corresponding to the design data having at least one attribute that is at least similar to the design data in the portion and at least similar to the at least one attribute of the design data in the portion. . In one embodiment, the one or more attributes may include one or more attributes of the inspection result for which a defect was detected, one or more attributes of the inspection, and some combination thereof. One or more attributes may also include (or alternatively) any other attribute described herein.

The method further includes storing the result of the assigning step in a storage medium. The result can be stored in a storage medium in any suitable manner or as described herein. The storage medium may include any storage medium described herein or any other suitable storage medium known in the art.

The computer-implemented method described above is performed by an inspection system used to detect a defect in one embodiment. In this manner, assigning a category to a defect as described herein may be performed on-tool. In another embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect the defect. In this manner, assigning a category to a defect as described herein can be performed off-tool.

In one embodiment, the method includes binning the defects assigned to one or more DBCs into groups such that the position of the defects in each group relative to the polygon in the portion of the design data close to the position of the defects is at least similar. In this manner, the method may include separating the defects into groups based on the location of the defects within the DBC and the portion. The location of the defect relative to the polygon can be determined as described herein. In addition, such binning can be further performed as described herein.

In some embodiments, the method includes monitoring hot spots in design data based on the assigning step. For example, design data corresponding to a DBC or different DBCs may be associated with hot spots in the design data. Hot spots can be identified in the design data as described herein. As described above, monitoring the hot spot in the design data may include determining whether the number of defects corresponding to the DBC associated with the hot spot or a different DBC and assigned to the design data associated with the hot spot changes over time. . In addition, monitoring hot spots in the design data based on the results of the assigning step is based on the results of the assigning step, in combination with any other data described herein, such as one or more attributes of the defects to which different DBCs are assigned. Can be performed. The method may also include monitoring hot spots based on location (eg, near location). In another embodiment, the method may include binning the hot spots based on design data corresponding to the DBC. Such binning of hot spots can be performed as described herein. Binning the hot spots may include generating one or more data structures (eg, lists, databases, files, etc.) of the hot spots that include the location of the hot spots and indicate which hot spots are at least similar. . Such binning steps of hot spots can be performed on-tool.

In another embodiment, the method includes monitoring, over time, a systematic fault, a potential systematic fault, or some combination thereof using the results of the allocation step. For example, the results of the allocation step can be used to identify systematic issues in the design data, and the identified systematic issues can be monitored across the wafer and / or over time. Systematic issues may be determined based on the results of the allocation steps as further described herein. In addition, systematic defects, potential systematic defects, or some combination thereof may be further performed as described herein.

In one embodiment, design data corresponding to different DBCs is identified by grouping the detected defects on one or more other wafers based on the portion of the design data close to the location of the detected defects on one or more other wafers in the design data space. Such grouping of defects can be performed as described herein. The result of the grouping can be used to identify design data corresponding to different DBCs. For example, design data corresponding to each group of defects may be identified as design data corresponding to different DBCs. In addition, different DBCs corresponding to the design data may include classification of defects into groups that may be performed as described herein, one or more attributes of the design data, one or more attributes of the defects, any other information described herein, or May be determined by some combination thereof.

In another embodiment, the method includes determining whether the defect is a Nuson's defect based on a DBC assigned to the defect and from the result of the inspection process in which the defect was detected to increase the S / N of the inspection process result. Removing the slack defect. In this manner, the method may include Newsons filtering. Defects that are determined to be Newson's defects are those assigned to them by a Newsons DBC (eg, LES's DBC); It may be an assigned defect. Increasing the S / N of a test result is particularly advantageous when the test result is used to perform one or more other steps to increase the S / N of that other step result.

In some embodiments, the method includes determining one or more POIs in the design data by identifying one or more features in the design data indicating pattern dependent defects. In this manner, the method may include identifying a POI in the design data. One or more features in the design data indicating pattern dependent defects are determined based on experimental results, simulation results, binning results, other results described herein, or some combination thereof. Such results can be generated as described herein. One or more POIs may be determined using the identified features to perform any pattern search of the design data. Patterns in the design data determined by any pattern search, at least similar to the identified features, may be identified as POIs. One or more POIs may be determined in this manner for one or more pattern dependent defects.

In the manner described here, defects assigned a DBC are detected within the inspection process. In one embodiment, the method includes the steps of reviewing a location on a wafer on which one or more POIs in the design data are printed, and determining, based on the results of the reviewing step, whether a defect should have been detected at the location of one or more POIs. And modifying the inspection process to improve one or more defect capture rates. Each step of this embodiment may be performed as described herein.

In another embodiment, the method includes determining a KP value for one or more defects. In a further embodiment, the method includes determining a KP value for at least one DBC based on at least one attribute of the design data corresponding to the DBC. In a further embodiment, the method includes determining a KP value for one or more defects based on one or more attributes of the design data corresponding to the DBC assigned to the one or more defects. Each of these steps can be performed as described herein. In some embodiments, the method includes monitoring KP values for one or more DBCs and assigning the KP values for the DBCs assigned to the defects to the defects. KP values for one or more DBCs can be monitored as described herein. In this manner, the KP value for one or more DBCs may be modified over time, and / or at the time the defect is detected, the KP value for the DBC assigned to the defect may be assigned to the defect with relatively high accuracy. . The step of assigning the KP value to the defect based on the DBC assigned to the defect may be further performed as described herein.

In some embodiments, the method includes selecting at least some defects for review based on the results of the assigning step. For example, the results of the allocation step can be used to determine which defects are most important as described herein (eg, based on one or more attributes of the DBC assigned to the defects) and the most important defect is selected for review. Can be.

In another example, the assignment result can be used to determine which fault is a systematic fault as described herein. In this manner, the method may include review sampling from an area within the design data where DOI tends to occur.

In one embodiment, the method includes determining whether a DBC assigned to a defect corresponds to a systematic defect visible to the review system, and selecting only defects visible to the review system for review to sample the defect for review. Include. DBCs corresponding to systematic defects that are visible or invisible to the review system may be determined in any manner known in the art. The DBC corresponding to a systematic defect visible to the review system may be determined prior to the method, and the DBC may be assigned some identity indicating whether the DBC corresponds to a visible or non-visible defect. In this way, defects can be selected for review based on this identity. Selecting only defects visible to the review system may be performed such that defects not visible to the review system, such as the SEM, are not selected for review. Defect selection in this manner is particularly advantageous because re-location of the defects during the review is relatively difficult and can be relatively time consuming, especially if the review system spends a lot of time looking for actual invisible defects in the review system. The defect selection result for review may include the location of the selection defect for review on the wafer and other results of any step of the method described herein.

The method may include adopting a process, measurement or test based on the results of the assigning step. For example, in another embodiment, the method includes generating a process of sampling a defect for review based on the results of the assigning step. Thus, instead of or in addition to the selection of a defect for review, the method may employ a method, another method, a system configured to perform the method, or a process that may be used by another system to sample the defect for review. It may comprise the step of generating. Such a process may be used for sampling of defects detected on a plurality of wafers for review and / or sampling of defects for review performed by the plurality of review systems. The process for sampling may be generated based on the result of the allocation step such that a relatively large number of defects assigned the same DBC can be sampled more intensively than a relatively small number of defects assigned the same DBC. The process for sampling the defect for review is generated based on the result of the assignment step in combination with any other result of any step of any method described herein, such as the DCI for the defect, the KP value for the defect, and the like. can do.

In a further embodiment, the method includes changing the process for wafer inspection based on the results of the allocation step. Any parameter of the wafer inspection process can be changed in this embodiment. For example, one or more parameters of the process for wafer inspection, which may be changed based on the result of the allocation step, include: attention region (or alternatively, non-attention region), surveillance, in-line binning process, inspection region, The wafer may be inspected, or may include without limitation some combination thereof. In one particular example, the result of the allocation step may indicate the number of defects to which different DBCs have been assigned, and the attention area may also include design data corresponding to the DBCs to which a relatively large number of defects are assigned. It can be changed to include a location on the wafer that corresponds to the additional location. In another example, the wafer inspection process may be modified to inspect more or differently based on the results of the allocation step. The process for wafer inspection can be modified based on any result of any step of the method described herein.

In some embodiments, the method includes changing a process for inspecting a wafer during inspection based on the inspection results. Changing the inspection process in this embodiment may be performed as further described herein.

In a further embodiment, the method includes changing the metrology process for the wafer based on the result of the assigning step. For example, the metrology process may be modified such that the most significant defect as determined from the result of the assignment step is measured during the metrology process. Thus, changing the metrology process may include changing the position on the wafer where the measurement is performed during the metrology process. In addition, the results of the inspection and / or review, such as the BF image and / or SEM image selected for the measurement, are supplied to the metrology process, and the result can be used to determine where the measurement will be performed. For example, the metrology process may include generating an image of a near position of the defect on the wafer, and if necessary, the metrology system may correct the position of the wafer so that the metrology is performed at the correct wafer position and therefore for the correct defect. Such an image may be compared to the results of inspection and / or review for defects. In this way, the measurement can be performed at a substantially accurate position on the wafer. Changing the metrology process also includes changing any other one or more parameters of the metrology process, such as the type of measurement performed, the wavelength at which the measurement is performed, the angle at which the measurement is performed, or some combination thereof. can do. The metrology process may include any suitable metrology process known in the art, such as a CD metrology metrology process.

In some embodiments, the method includes changing the sampling plan for the metrology process based on the result of the assigning step. Thus, the method may include adaptive sampling. For example, the sampling plan for the metrology process can be modified so that the majority of the most significant defects as determined from the results of the binning step are measured during the metrology process. In this way, the most important defects can be sampled more intensively during the metrology process, thereby advantageously generating large amounts of information about the most important defects. The metrology process can include any metrology process known in the art. The metrology process may also be performed by any suitable metrology system known in the art, such as SEM. In addition, the metrology process may include performing any suitable measurement known in the art of any suitable attribute of a feature or defect formed on the wafer, such as a profile, thickness, CD, and the like.

In another embodiment, the method prioritizes one or more DBCs (e.g., DBCs assigned to defects), and based on the results of the prioritization step, one or more DBs to be performed on the wafer on which the design data will be printed. Optimizing the process. In one such embodiment, the DBC may be prioritized based on the number of defects to which the DBC has been assigned. The number of defects assigned to the DBC can be determined from the result of the allocation step. In such an example, the DBC assigned to the maximum number of defects may be assigned the highest priority, and the DBC assigned to the next highest number of defects may be assigned the next highest priority.

In addition (or alternatively), the DBC may be prioritized based on any combination of any other result of any step of any method described herein and any step result of any method described herein. Can be. For example, DBC prioritization may include determining a DCI for one or more defects to which the DBC is assigned and prioritizing the DBC based on the DCI for one or more defects. DCI may be determined as described further herein in this embodiment. In another example, prioritizing the DBC may include determining a KP value for the one or more defects to which the DBC has been assigned, and prioritizing the DBC based on the KP value for the one or more defects. Can be. In another example, a DBC may be prioritized based on a combination of the number of defects assigned that DBC and the DCI for one or more defects assigned the DBC. In this manner, prioritizing the DBC prioritizes the DBC based on the defect degree detected in the design data corresponding to the DBC such that the highest priority is assigned to the DBC corresponding to the highest defect degree. It may include the step.

In addition, a DBC may be prioritized based on one or more attributes of design data corresponding to that DBC, possibly in combination with other results described herein. One or more attributes of the design data may include, for example, the dimensions of the features in the design data, the density of the features in the design data, the types of features included in the design data, the location of the design data corresponding to the DBC in the design, and the yield of the design data for defects. Sensitivity of influence, or the like, or some combination thereof. In one such example, a DBC corresponding to design data that is more sensitive to yield effects due to defects may be assigned a higher priority than DBCs corresponding to design data that are less sensitive to impact of yield.

In addition, a DBC may be prioritized based on one or more attributes of the design, possibly in combination with one or more attributes of the design data corresponding to that DBC and / or other results described herein. One or more attributes of the design may include, for example, redundancy, netlist, and the like, or some combination thereof. In particular, the POI in the design data may have a context beyond the pattern included in the POI. Such context may include, for example, the label of a cell containing a POI, the hierarchy of cells above the cell containing the POI, the effect of redundancy of systematic defects on the POI, and the like. Thus, one or more attributes used in the embodiments described herein may include the context of the POI where the design data corresponding to the DBC is located, which may be the location of the design data corresponding to the DBC in the design data space and / or the DBC. Can be determined based on the design data corresponding to the (if the design data corresponding to the DBC is specific to a cell in the design data). In one such example, a DBC corresponding to design data that does not have redundancy and corresponding to design data where systematic defects may have a significant yield impact may correspond to design data that has redundancy so that systematic defects may not have a yield impact within the design. May be assigned a lower priority. Such context of the cell may be obtained and / or determined in any manner known in the art.

Optimizing one or more processes in this embodiment includes focusing, dose, exposure tool, resist, PEB time, PEB temperature, etch time, etch gas composition, etch tool, deposition tool, deposition time, CMP tool, CMP process. Altering any one or more parameters of one or more processes, such as one or more parameters and the like. Preferably, the parameter of the process is a defect selected in the design data corresponding to the DBC to lower the degree of defects in the design data corresponding to the DBC (eg, the number of defects detected in the design data corresponding to the DBC). To change one or more attributes of (e.g., DCI, KP, etc.), and / or to increase the yield of devices in which design data corresponding to the DBC is included.

In addition, one or more parameters of one or more processes may be optimized only for DBCs having the highest priority as determined by the prioritization step or DBCs having a relatively high priority as determined by the prioritization step. . In this manner, one or more parameters of the one or more processes may be modified and / or optimized based on design data corresponding to the DBC representing the defect degree with the maximum defect degree and / or the maximum yield impact. As such, the result of the prioritization step indicates which DBC should be used to change and / or optimize one or more parameters of one or more processes to indicate maximum improvement in yield.

Thus, this embodiment allows several changes to be made to the process without significant or any improvement in yield, without guidance of which DBC has the greatest impact on yield, thereby reducing the change time and cost for process optimization. This embodiment is advantageous over previously used methods and systems for modifying and / or optimizing the increasing process.

Furthermore, although the process to be changed and / or optimized at this stage includes only the process used to print the design data corresponding to the DBC on the wafer prior to detection of the defects assigned by the DBC in the embodiments described herein, the modification and One or more optimized processes may include any process used to print another design that includes design data corresponding to the DBC. For example, if one or more designs include design data corresponding to a DBC based on prioritization and / or any other result of the methods described herein, the one or more processes used to print one or more designs may be modified and It can be optimized, increasing the yield of devices manufactured with each different design.

In a further embodiment, the method includes determining the root cause of the defect based on the DBC assigned to the defect. For example, the root cause can be determined based on one or more attributes of the design data corresponding to the DBC assigned to the defect. The attributes of the design data used to determine the root cause may include any of the design data attributes described herein. In addition, any other information and / or the result of any step of any method described herein can be used to determine the root cause of the defect in combination with the attributes of the design data.

In a further embodiment, the method includes mapping at least a portion of the defect to an experimental process window result to determine the root cause of at least a portion of the defect, which may be performed as described herein.

In another embodiment, the method includes determining a root cause corresponding to one or more DBCs and assigning a root cause to the defect based on the root cause corresponding to the DBC assigned to the defect. For example, the root cause of a defect previously detected in design data corresponding to the DBC may be associated with the DBC. The root cause of a previously detected defect can be determined in any manner described herein or in any other suitable manner known in the art. In this manner, the root cause of the defect may be the root cause associated with the DBC assigned to the defect.

In a further embodiment, the method includes determining the percentage of die formed on a wafer that is affected by a defect to which one or more DBCs are assigned. For example, the percentage can be determined by the number of dies across the wafer where defects assigned the same DBC are detected at least once. Such percentage can be determined by dividing the number of dies for which at least one defect to which the same DBC is assigned is detected by the total number of dies inspected. The result of such a step is multiplied by 100 to reach a percentage. Thus, the percentage reflects the die impact margin of defects assigned the same DBC. Such percentage can be determined for one or more DBCs assigned to the defect, and each or at least a portion of the percentage can be represented by a chart, such as a bar chart, which can be generated by the method. Thus, the chart shows the die impact margin as a function of the DBC assigned to the defect. Such charts can be presented in a user interface that can be configured as further described herein. The method may also include prioritizing defects assigned one or more DBCs based on the percentage determined in this embodiment.

In some embodiments, the method includes determining a POI in design data corresponding to at least one DBC, and determining a ratio of the number of defects assigned at least one DBC to the number of locations on the wafer. do. In this manner, the method may include performing a margin analysis by determining a ratio or percentage of the number assigned by the DBC to the number of positions of the POI corresponding to the DBC printed on the wafer. In such an embodiment, the location of the POI on the wafer can be identified by any pattern search. Further, the method described herein may include any pattern retrieval step for identifying the location of the POI within the inspection area of the design, and determining the cumulative area of the POI within the inspection area of the design. The ratio of the number of defects allocated to the DBC to the cumulative area of the POI in the inspection area of the design can be used to determine the defect density of the DBC corresponding to the POI. The method may also include prioritizing the one or more DBCs determined in this embodiment.

In another embodiment, the method includes determining at least one POI in the design data corresponding to the at least one DBC, and determining the number of at least one defect assigned a DBC for the number of locations of the at least one POI in the design data. Determining the ratio. In this manner, the method includes performing a margin analysis by determining the ratio or percentage of the number of defects assigned to the DBC corresponding to the POI found on the wafer to the number of positions of the POI in the design over the inspection area of the wafer. It may include. In such an embodiment, the location of the POI on the wafer can be identified by any pattern search. Such a method may also include prioritizing one or more DBCs based on the rate determined in this embodiment.

In a further embodiment, the method includes determining a POI in design data corresponding to at least one DBC, determining a percentage of the die formed on the wafer where the defect to which the at least one DBC is assigned is located, and the percentage of the die; Assigning a priority to the POI based on the. In this manner, the method may include performing a margin analysis based on the percentage of die affected by the defect. For example, the number of defects assigned the same DBC can be divided by the number of design instances of the POI in the reticle used to print the design data in the inspection area on the wafer and the number of times the reticle is printed and inspected on the wafer. The result of this step is multiplied by 100 to reach a percentage. In this manner, the method may include prioritizing known systematic defects by the number of dies across the wafer at which defects are detected at least once. For example, high priority may be assigned to POIs where systematic defects are detected when POIs appear in 10% of dies relative to 1% of dies. In another example, defects assigned the same DBC, detected on a large number of dies on a wafer, may be assigned higher priority than defects assigned on different DBCs, detected on a smaller number of dies on a wafer. The method may also include generating a chart, such as a bar chart, indicating the percentage of die formed on the wafer on which the defect to which the different DBC is assigned is located. Thus, such charts graphically represent die based margins for different DBCs. Such charts may be displayed in a user interface that may be configured as described herein.

In a further embodiment, the method includes prioritizing the one or more DBCs by the number of defects to which one or more DBCs are assigned. In this manner, the method may include prioritizing a systematic defect known by the total number of defects of which the DBC is assigned. As such, the method may include prioritizing known systematic defects based on wafer-based margins. For example, a DBC assigned to a defect detected in a large number of design instances on a wafer is assigned a higher priority than a DBC assigned to a defect detected in a small number of design instances on a wafer. Such prioritization may be performed based on the percentage of the location of the design instance across the wafer where the defect was detected. For example, the number of defects detected and assigned to the DBC may be divided by the total inspected design instance corresponding to the DBC across the wafer. The result of this step is multiplied by 100 to generate the percentage mentioned above. The method may also include generating a chart, such as a bar chart, indicating a number of design instances across a reticle to which different DBCs have been assigned. Such charts can be displayed in a user interface that can be configured as described herein.

In some embodiments, the method includes prioritizing the one or more DBCs by the number of design instances on the reticle used to print the design data on the wafer at which one or more DBCs assigned defects are detected at least once. In this manner, the method includes prioritizing systematic defects known by the number of design instances across the reticle in which the defect is found at least once. For example, a DBC assigned to a defect detected in a large number of design instances on a reticle may be assigned a higher priority than a DBC assigned to a defect detected in a small number of design instances on a reticle. The method may also include generating a chart, such as a bar chart, indicating the number of design instances across the reticle for which defects assigned different DBCs are detected. Such charts can be displayed in a user interface that can be configured as described herein.

In another embodiment, the method includes design data printed on a reticle that is at least similar to the number of places on the reticle where a defect assigned one or more DBCs is detected, and a portion of design data close to the location of the defects assigned one or more DBCs. Determining a reticle-based margin for the one or more DBCs based on the total number of portions of. For example, the reticle-based margin can be determined by dividing the number of places in the stacked reticle map where the DBC has been assigned at least one defect detected by the entire inspection design instance across the reticle. The result of this step is multiplied by 100, so that the DBC generates a percentage of the place of the design instance corresponding to the detected DBC. The method may also include generating a chart, such as a bar chart, indicating a percentage or reticle-based margin of where a defect to which a different DBC is assigned is detected. Such charts may be displayed in a user interface, which may be configured as further described herein. The method may include prioritizing one or more DBCs based on a reticle-based margin determined for one or more DBCs. For example, a DBC showing a relatively high reticle-based margin may be assigned a higher priority than a DBC showing a low reticle-based margin. The steps of the embodiments described herein may be performed for a group of defects assigned the same DBC or for individual defects assigned a DBC.

Each embodiment of a method for assigning a category to a defect as described above may include any method embodiment described herein. In addition, each embodiment of a method for assigning a category to a fault described above may be performed by any of the system embodiments described herein.

Another embodiment is directed to a method of modifying an inspection process for a wafer. This method includes reviewing a location on the wafer where one or more POIs in the design data are printed. The method also includes determining, based on the results of the reviewing step, whether a defect should have been detected at the location of one or more POIs. The method also includes modifying the inspection process to improve S / N for one or more defect capture rates and / or defects located in at least a portion of the at least one POI. Each of these steps can be performed as further described herein. For example, one or more parameters of the inspection process may be changed based on prioritization of the POI, which may be determined as described herein.

One use case for the method is a light sensitivity application. For example, in one embodiment, changing the inspection process includes changing the optical mode of the inspection system used to perform the inspection process. In this manner, the optical mode used for the inspection can be changed to improve the S / N for detecting one or more defects corresponding to at least a portion of the one or more POIs. The optical mode can include any optical mode known in the art.

In another embodiment, the method includes determining an optical mode of the inspection system used to perform the inspection process based on the results of the step of determining whether a defect should have been detected at the location of one or more POIs. In this way, the optical mode with the highest S / N for defects that should have been detected can be determined. The optical mode can include any optical mode known in the art. In addition, the determined optical mode and / or defects that should have been detected may be used to select other parameters of the changed inspection process, such as the type of inspection system used to perform the inspection process.

In some embodiments, modifying the inspection process includes modifying the inspection process to increase the capture of DOIs associated with one or more POIs. Changing the inspection process to increase the capture may include changing any one or more parameters of the inspection process. Enhanced detection by changing the parameters of the inspection process may include detection of DOIs associated with POIs in the inspection results (eg, increasing defect counts for yield deterministic systematic DOI, etc.). One or more parameters changed to increase the capture are based on any result of the inspection process and / or any result of the review step (eg, not only the result of reviewing a place on the wafer where one or more POIs are printed). Can be selected.

In some embodiments, changing the inspection process includes modifying the inspection process to suppress noise in the results of the inspection process. Changing the inspection process to suppress noise may include changing any one or more parameters of the inspection process. Noise suppressed by changing the parameters of the inspection process may include any noise in the inspection result (eg, background noise, Newson's defect, etc.). The one or more parameters that are changed to suppress noise are dependent on any result of the inspection process and / or any result of the review step (e.g., not just the result of reviewing a place on the wafer where one or more POIs are printed). You can choose based on that.

In a further embodiment, the inspection process includes modifying the inspection process to reduce detection of defects of no interest and to improve binning of defects of no interest. Changing the inspection process to reduce detection of defects of no interest may include changing any one or more parameters of the inspection process. Uninterested defects that are less examined by changing the parameters of the inspection process may include any uninterested defects (eg, non-yield related systematic defects, defects in cold spots, etc.). The one or more parameters changed to reduce the detection of defects of no interest are not the result of any result of the inspection process and / or any result of the review step (eg, reviewing a place on the wafer where one or more POIs are printed). Can be selected based on

Changing the inspection process to improve one or more defect capture rates may include changing any one or more parameters of the inspection process. For example, in one embodiment, changing the inspection process includes changing the algorithm used in the inspection process. The algorithm to be modified may be a defect detection algorithm or any other algorithm used in the inspection process. The modified algorithm may include any suitable algorithm known in the art. In addition, changing the inspection process may include changing one or more algorithms used in the inspection process.

In a further embodiment, changing the inspection process includes changing one or more parameters of an algorithm used in the inspection process. Algorithms with one or more parameters changed may include a defect detection algorithm or any other algorithm used in the inspection process. In addition, changing the inspection process may include changing one or more parameters of one or more algorithms used in the inspection process. One or more parameters in the algorithm may include any parameter of the algorithm, preferably a parameter that affects the defect capture rate.

Each embodiment of a method for modifying an inspection process for a wafer described above may include any other step of any method embodiment described herein. In addition, each embodiment of the method for modifying the inspection process for the wafer described above may be performed by any of the system embodiments described herein.

Further embodiments relate to a system configured to display and analyze design and defect data. One embodiment of such a system is shown in FIG. 25. As shown in FIG. 25, the system includes a user interface 182. User interface 182 displays one or more design layouts 184 for the semiconductor device, inline inspection data 186 acquired for the wafer on which at least a portion of the semiconductor device is formed, and electrical test data 188 obtained for the wafer. It is configured to. In one embodiment, the electrical test data includes logic bitmap data. Design, inspection (or metrology), test, and overlay data is represented in the design, device, reticle, or wafer space. The user interface may be configured to display modeled data for the semiconductor device and / or FA data for the wafer. In addition, the user interface may be configured to display information about a particular hot spot or DOI based on input from the user (eg, selection of a hot spot or DOI by the user). In this manner, the user interface may be configured to display information about different hot spots or DOIs at different times. However, the user interface may be configured to simultaneously display information about different hot spots or DOIs using one or more different markers (eg, colors, symbols, etc.) to indicate different hot spots or DOIs (eg, wafer map or Bar graph). Using the display of information in the hot spot database, a user can generate one or more hot spot lists by selecting a subset of hot spots of interest by a given analysis or inspection recipe. The user interface may be displayed on the display device 190. Display device 190 may include any suitable display device known in the art.

The system also includes a processor 192. The processor 192 is configured to analyze one or more design layouts, inline inspection data, and electrical test data upon receiving a command from the user to perform an analysis through the user interface. The processor may be configured to analyze the modeled data and / or FA data as described above. For example, user interface 182 may be configured to display one or more icons 194. Each icon may correspond to another function that may be performed by the processor. In this manner, five icons are shown in FIG. 25, but the user interface may be configured to display any number of icons corresponding to the number of possible functions. The user may instruct the processor to perform one or more functions by selecting (eg, clicking) one or more icons. In addition, the user interface may display various functions that are made available to the user in any other manner known in the art (eg, drop-down menus). In this manner, the user interface may be configured as a single integrated user interface that combines design / layout visualization and analysis manipulation with inline process data visualization and analysis manipulation, and functional / structural electrical test data visualization and analysis manipulation.

The system can be configured to process data at increased resolution, which is commonly referred to as "drill down capabilities". For example, the system may be configured to use inputs such as wafer maps representing defects detected on the wafer to select two or more dies for stacking, select defects represented within the die stacking results, and perform some function on the defects. Can be. The system can be configured to use data from one or more domains together, which is commonly referred to as "drill across capabilities."

In one embodiment, the user interface is configured to display at least two overlays 196 of the design layout, inline inspection data, electrical test data, and any other information described herein. In one such embodiment, the electrical test data includes logic bitmap data. In such embodiments, the processor may be configured to overlay different data in accordance with any of the embodiments described herein. In this manner, the system can be configured to generate and display an overlay of data from two or more of three domains (eg, design, inspection, and electrical test). Such overlay of data is used to map physical locations of the defects to logical locations using mapping and electrical test results (eg, electrical errors) to identify defects (eg, causing electrical errors) that affect electrical test results. Can be used.

In one embodiment, the processor is further configured to determine a defect density in the design data space upon receipt of an instruction to perform a determination from the user via the user interface. In this manner, the system can be configured to perform error density calculations as described further herein. The user interface may be configured to display the result of the error density calculation.

In a further embodiment, the processor is configured to receive defect sampling from the user via the user interface to perform defect sampling for review. In a further embodiment, the processor is configured such that receiving instructions to perform grouping from the user via the user interface groups the defects based on the similarity of the design layout close to the position of the defect in the design data space. In this manner, the system can be configured to perform sampling and data reduction (eg, data reduction by pattern dependent binning) techniques. Such techniques may be performed as further described herein.

In some embodiments, the processor is configured to monitor the KP value of the defect group over time and determine the importance of the defect group based on the KP value over time. In this manner, the system can be configured for defect tracking (eg, using a DTT method and / or using an image). The user interface may be configured to display monitoring results of missed KP values and importance of defect groups over time. The processor and system shown in FIG. 25 may be configured as further described herein. For example, the processor and system may be configured to perform any other step of any other method described herein. In addition, the system shown in FIG. 25 may include other components described herein, such as an inspection system, which may be configured as further described above. The system shown in FIG. 25 has all the advantages of the method described herein.

Further embodiments relate to computer-implemented methods of determining the root cause of electrical defects detected on a wafer. In one such embodiment, the inspection result of the wafer for electrical defects may include a bitmap for the logic device. The method includes determining a location of an electrical fault within a design data space. The location of electrical faults in the design data space can be determined as described herein.

In some embodiments, the method includes correlating spatial signatures of defects, such as systematic defects, to process conditions. For example, after converting scan-based and structural test results into wafer space coordinates, certain spatial signatures may be correlated to one or more process conditions. Methods and systems for performing spatial signature analysis of defect data are disclosed in US Pat. Nos. 5,991,699 (Kulkarni et al.), 6,445,199 (Satya et al.), And 6,718,526 (Eldredge et al.). The patent document is incorporated by reference as if fully set forth herein. The methods and systems described herein may be configured to perform any step of any of the methods described in that patent document.

The method includes determining if the location of the electrical defect portion defines a spatial signature corresponding to one or more process conditions. This step can be performed by comparing the spatial signature of the electrical defect portion to the spatial signature set corresponding to the process conditions, applying a rule to the location of the electrical defect portion, or in any suitable manner. Further, if the location of the electrical defect portion defines a spatial signature corresponding to one or more process conditions, the method includes identifying the root cause of the electrical defect portion as one or more process conditions. In this manner, the above-described method may include performing spatial signature analysis on logic bitmap data. The method further includes storing the result of the identifying step in a storage medium. The results of the identification step can include any of the results described herein. In addition, the method may perform a storing step as further described herein. Storage media may include any of the storage media described herein.

Each embodiment of the method for determining the root cause of the aforementioned electrical defect may include any other step of any method embodiment described herein. In addition, each of the embodiments of the method for determining the root cause of the above-described electrical defects may be performed by any system embodiment described herein.

The root cause of other defects can also be determined in the methods described herein. For example, wafer-based or reticle-based spatial signatures (and combinations thereof) by groups of patterns mapped across process windows are particularly useful for determining correlations for assistance in root-cause decisions. In one example, at one edge of the process window, defects x and y are marginal and tend to be errors first from the outside of the wafer. At the other edge of the process window, defect z tends to be an error first at the edge of the wafer. Thus, the possible root cause can be determined by observing which systematic defects are the most frequent (and possibly for the outer annular ring) errors on the wafer.

Another embodiment relates to a computer-implemented method of selecting defects detected on a wafer for review, search for categories / investigations, and proof / root cause analysis, including on-tool, off-tool, and on-SEM. will be. The method includes identifying one or more regions of the wafer. One or more regions are associated with the location of one or more defect types on the wafer. One embodiment of one or more such areas is shown in FIG. 26. As shown in FIG. 26, region 198 on wafer 200 may be identified as associated with the location of one or more defect types on the wafer. For example, such regions may be associated with defect types caused by focus errors near the outer edges of the wafer during the lithography process or the etch change from the wafer center to the wafer edge.

The method includes selecting a detected defect in only one or more areas for review. For example, as shown in FIG. 26, wafer map 202 may overlap the layout of region 198. In this manner, the defects shown in the wafer map 202 may be selected for review based on the area where they are located and one or more defect types associated with that area. In one such example, if the region shown in FIG. 26 is associated with a defocus error near the outer edge of the wafer, the method may select a defect (only, preferentially, or mainly) in region 198. . Alternatively, the defect may be selected from an area on the wafer other than the area 198.

Although only one region is shown in FIG. 26, it should be understood that the wafer may be separated into any plurality of suitable regions. Further, the region can be defined on the wafer as an annular region, an angular region and a radial region, and a rectangular region as shown in FIG. However, the region may have an irregular (eg, polygonal) shape. In addition, all, some or nothing of the area may have the same characteristics, such as shape and / or size.

The method described above can be used to provide a defect sample so that the review results of the defect sample can be interpolated from the die to the wafer. In contrast, a typical review sample plan contains 100 to 200 defects for recipe optimization and 10 to 100 defects for monitoring spread across the entire wafer. However, tens of thousands of hot spots can exist on only one die. Hot spots can be reviewed for search. Systematic flaws can be reviewed for monitoring and verification. Thus, even after selecting 100 or 200 defects from this population, preferably not all of them are reviewed on the same die. Instead, the selected defect is preferably spread over a plurality of dies. The method described above uses region analysis results to identify correlations between specific defect types and specific regions on a wafer. As such, the method described herein can be used to identify wafer location-specific defects. In this manner, the method may include biasing the sampling plan into these regions to provide results suitable for use in die-wafer interpolation. The method further includes storing the result of the selection step in a storage medium. The result of the selection step may include any result described herein. In addition, the method may be performed as further described herein the storage step. Storage media may include any of the storage media described herein.

Each embodiment of a method for selecting a defect for the foregoing review may include any other step of any method embodiment described herein. In addition, each embodiment of the method for selecting a defect for the aforementioned review may be performed by any of the system embodiments described herein.

Another embodiment is directed to a computer-implemented method for evaluating one or more yield related processes for design data. One such embodiment is shown in FIG. 27. The steps shown in FIG. 27 are not essential to implementing such a method. One or more steps may be excluded from, or added to, the method shown in FIG. 27, and the method may still be practiced within the scope of this embodiment.

As shown in FIG. 27, the method includes identifying potential errors in design data using rule checking, as shown in step 204. Alternatively, potential errors in the design data can be identified using potential hot spots observed from repeater analysis or defect density maps. Potential errors identified at this stage may include one or more other types of DOI. In some embodiments, the potential errors identified in this step may include post-pattern potential errors (eg, post-etch potential errors). In addition, once a potential error is identified, it can be propagated throughout the design throughout the design, which can be detected by searching for common patterns within the design (eg, searching for any pattern). In some embodiments, the method includes any pattern searching step to identify the location of all similar POIs. Common patterns can be identified by searching for rotated or flipped patterns to find all potential errors. In addition, potential errors in design data may be identified at step 204 using any other suitable method (eg, modeling), software, and / or algorithm known in the art. In addition, potential errors can cause errors in the device being manufactured with respect to the design data, or areas or patterns within the design data that can change one or more electrical parameters of the device in an undesirable manner without actually causing the device to fail. It may include.

As shown in step 206, the method also includes determining one or more attributes of the potential error. The nature of the potential error determined may include, for example, the type. The nature of potential errors can be obtained by experimental tests, simulation results, design data, or any other method. Because the method includes identifying potential errors as described above, the method may include modifying the design data prior to manufacture to eliminate as many potential errors as possible. Such alteration of design data may be performed as described herein. However, it is contemplated that not all potential errors can be eliminated prior to manufacture. In addition, potential errors identified in the methods described herein may or may not actually produce errors during manufacturing, or may affect yield. Thus, some of the potential errors can be eliminated prior to manufacture (and hence inspection), but the method described here is a place where design checks should be performed so that if a potential error actually fails, it can be detected as soon as possible. It can provide important information about. In addition, the method described herein can be performed with inspection parameters where the portion of the design data contains potential errors in the design with the most appropriate inspection parameters, whereby the potential errors cause actual errors, In order to increase the probability of inspection by inspection, it can provide important information about how different areas of the design should be examined.

As shown in step 208, the method includes determining whether a potential error is detectable based on one or more attributes of the potential error. Whether a potential error is detectable can be determined based on the nature of the potential error in combination with the known capabilities of various inspection systems. As shown in step 210, the method determines which of a plurality of different inspection systems (eg, BF, DF, voltage contrast, EC, electron beam, etc.) is best suited for detecting potential errors based on one or more attributes. It includes a step.

In some embodiments, the method includes selecting one or more parameters of the inspection system determined to be most suitable, as shown in step 212. In one such embodiment, the parameter is selected based on one or more parameters of the potential defect. The parameter may be selected as further described herein. In addition, the parameters selected in this step can include any parameters of the inspection system that can be changed and / or controlled. One example of such a parameter is optical mode or inspection mode. Preferably, the parameters are selected to optimize the inspection of the wafer for potential errors (e.g., to increase the defect capture rate of defects at the location of potential errors, increase the sensitivity for defects in potential errors, etc.). do.

In some embodiments, the method, possibly in combination with any other information described herein (eg, the sensitivity of design data to a defect, the sensitivity of an electrical parameter corresponding to the design data to a defect, etc.), Prioritizing the one or more potential errors based on the one or more attributes of the design data close to the location of the potential errors. Such prioritization may be performed as further described herein. In addition, the most suitable inspection system and parameters of the inspection system may be selected based on the results of such prioritization as further described herein. For example, in such an embodiment, the most suitable inspection system and parameters of the inspection system may be selected to optimize the inspection for potential errors with the highest priority so that the most significant defect is detected in the inspection process. Determination of such a most suitable inspection system and selection of parameters may or may not lead to optimization of inspection for potential errors with the lowest priority.

In another embodiment, the method includes determining the effect of potential error on the yield of the device manufactured with the design data, as shown in step 214. In this way, the method can be used for recipe optimization and monitoring. In a further embodiment, the method may include determining the impact of a potential error that is not detectable but determined to affect yield. In this manner, the method may include determining a percentage of yield loss that is not detectable by the inspection. One example of a yield prediction method that can be used in the methods disclosed herein is disclosed in US Pat. No. 6,813,572 (Satya et al.), Incorporated by reference as if fully set forth herein.

Thus, the method described above can be used for fully automatic prediction, tracking, and validation of hot spots (after some initial manual setup is performed). The above method further comprises storing the result of the determination of which of the plurality of different inspection systems is suitable for detecting a potential error on a storage medium. The result of this step may be any result described herein. In addition, the method may perform a storage step as described further herein. Storage media may include any of the storage media described herein.

Each of the embodiments for evaluating one or more yield related processes described above may include any other step of any of the methods described herein. In addition, each embodiment for evaluating one or more yield related processes described above may be performed by any of the systems described herein.

The method and system embodiments described herein can be used to provide a total design. For example, as described above, the method may include separating the defects (detected by inline and / or electrical inspection) into systematic defects and random defects. The methods and systems described herein can be used to manage hot spots.

Defect-related parametric yield loss can be used as input to a simulation, such as a simulation that determines the electrical parameters of a device based on one parameter of a semiconductor manufacturing process. In this manner, defects related to parametric yield loss can be used in combination with information about the process performed on the wafer to adjust or optimize the simulation. In addition, the simulation results can be used to identify the parameters of the process performed on the wafer that can be altered to reduce defects associated with parametric yield loss. In addition, the results of the simulations and methods described herein can be used to identify which parameters of a process are important to reduce parametric yield loss.

Defects related to systematic patterning loss can be used to identify pattern defects related to the interaction between the design of the device and the process. In this way, information about the defect can be used to change the process, change the design, or change the process and the design to reduce the defect.

The above steps may be performed during the design feedback step used to improve future designs in view of the lessons learned. That is, the knowledge transfer and monitoring steps from the hot spot database may be provided to the design phase (eg, technology search and development, product design, EET design, etc.). This step can be performed within a multi-source space (eg, using correlation between any of the design, wafer, test, and process spaces). This step can include improving the design based on hot spots that have a strong correlation to the particular cell design. This step may also include improving the design using hot spots that have a strong correlation to the proposed design rule.

Information about random defects can be used to determine defect limited yield (ie, the maximum possible yield that can be achieved if all systematic and repeater defects are eliminated). Such information can be used for on-line and off-line monitoring in combination with simulations to determine the impact of random defects on the device to identify random defects that are higher yield impairments.

The method described herein can include monitoring the semiconductor manufacturing process using the results of the method. The results used to monitor the semiconductor manufacturing process may be any results described herein (eg, inline inspection data, systematic defect information, random defect information, error density maps, binning results, etc.) or any combination of the results described herein. It may include. The method described herein may also include changing one or more parameters of the one or more semiconductor fabrication processes based on the results of any of the methods described herein. Parameters of the semiconductor manufacturing process may be controlled using feedback techniques, feedforward techniques, in situ techniques, or some combination thereof. In this manner, the methods described herein and the results generated by the methods can be used for SPC applications.

As further described herein, the methods and systems described herein provide for on-tool yield prediction based on design data for improved binning, review sampling, inspection setup, and any other analysis described herein. Can be used. The methods and systems described herein have numerous advantages over the methods and systems currently used. For example, currently used methods and systems for KP analysis use historical yield data for overall random yield loss prediction by considering defect density by size distribution and / or category. One disadvantage of such methods and systems is that other defect groupings (eg, size bins, category beams, layers) are not taken into account when calculating the probability of one or more defects breaking a die. In addition, these methods and systems require statistically significant historical data for setup. In another example, currently used methods and systems for KP analysis use historical yield data and yield loss prediction per defect by considering the size and / or category within a region to better predict the KP of the detected defect. . One disadvantage of such methods and systems is that statistically significant historical data is required for setup. In a further example, currently used methods and systems for critical area analysis (CAA) determine yield loss prediction by defects, and overall by structure (line width, spacing) for various defect sizes. Relies on pre-calculation of key areas across the die. The approach is relatively computationally intensive, but once calculated, defects with areas larger than the main area based on location are predicted as breakers. One disadvantage of such methods and systems is that statistically significant historical data is required for setup. In addition, such methods and systems include computationally intensive pre-processing, and the accuracy of such methods and systems is limited by defect coordinate accuracy.

In contrast, the methods and systems described herein utilize very high coordinate precision, which results in improved yield prediction accuracy for the CAAs and methods described herein. The methods and systems described herein can be used for an active CAA. For example, instead of pre-processing the data to generate a lookup table across multiple sizes and locations, this approach calculates yield based on the improved location and size. This requires design data to be available to the inspection system and has a more computationally efficient potential. In addition, the methods and systems described herein include saving analysis of systematic defects or by pattern grouping, which can further improve computational efficiency. In addition, the methods and systems described herein can be used to predict the yield of on-tool results, which allows the results to be reviewed (eg, manual review for recipe optimization, high resolution while the wafer is on the chuck). Used to prioritize defects for image grabs, etc.).

Further variations and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art from the point of view of this description. For example, methods and systems are provided for utilizing design data in combination with inspection data. Accordingly, the description is to be regarded as illustrative only and as teaching the person skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments. As will be apparent to those skilled in the art after taking advantage of this embodiment of the present invention, the elements and materials may be replaced with those shown and described herein, the parts and processes may be reversed, and certain features of the present invention may be independently Can be utilized. Modifications may be made to the elements described herein without departing from the spirit and scope of the invention as described in the following claims.

Claims (58)

A computer-implemented method of using computer systems to determine the location of inspection data within a design data space,
Aligning the data obtained by the inspection system with respect to the alignment site on the wafer with the data for the predetermined alignment site;
Determining a location of the alignment site on the wafer in the design data space based on the location of the predetermined alignment site in the design data space;
Determining a location of inspection data acquired for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space; And
Sensing for detecting a defect on a different portion of the wafer based on a location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data Determining Sensitivity
Including,
Wherein the one or more attributes of the inspection data include one or more image noise attributes, or some combination of the image noise attributes, when one or more defects are detected in the different portions. Computer-implemented method of determining the number. The computer-implemented method of claim 1, wherein the location of the inspection data is determined with sub-pixel accuracy. The computer-implemented method of claim 1, wherein the data for the predetermined alignment site includes design data stored in a data structure. The method of claim 1, wherein the data for the predetermined alignment site includes one or more simulated images that indicate how the predetermined alignment site is to be printed on the wafer. Computer-implemented method of determining. The method of claim 1, wherein the data for the predetermined alignment site includes one or more attributes of the predetermined alignment site, the data for the alignment site on the wafer includes one or more attributes of the alignment site on the wafer, Wherein the aligning includes aligning one or more attributes of the predetermined alignment site to one or more attributes of the alignment site on the wafer. . 6. The method of claim 5, wherein at least one property of the predetermined alignment site comprises a centroid of the predetermined alignment site, and at least one property of the alignment site on the wafer comprises a center of the alignment site on the wafer. Computer-implemented method for determining the location of inspection data within a design data space. The computer of claim 1, wherein the data for the predetermined alignment site includes data obtained by an inspection system aligned with design data stored in a data structure. How to implement. The inspection data of claim 1, wherein the data for the predetermined alignment site comprises at least a portion of a standard reference die image aligned to design coordinates in the design data space. A computer-implemented method of determining the location of a. The method of claim 1, wherein the predetermined alignment site comprises at least one alignment feature or at least two alignment features having one or more attributes unique in the x and y directions, wherein the first of the at least two alignment features is selected. Wherein the first alignment characteristic has only one or more attributes in the x direction, and the second alignment characteristic of the at least two alignment characteristics has only one or more attributes in the y direction. Computer-implemented way. The computer-implemented method of claim 1, further comprising selecting the predetermined alignment site using the inspection system. 12. The method of claim 10, wherein the imaging mode of the inspection system used in the selecting step is different from the imaging mode of the inspection system used to acquire the inspection data. Computer-implemented method. The design data of claim 1, wherein determining a location of the alignment site on the wafer is performed prior to inspection of the wafer and determining the location of the inspection data is performed during inspection of the wafer. A computer-implemented method of determining the location of test data in a space. The method of claim 1, wherein determining the location of the inspection data is performed subsequent to the inspection of the wafer, and determining the location of the inspection data is a portion of the inspection data corresponding to the defect detected on the wafer. For a portion of inspection data that does not correspond to the defect, wherein the location of the inspection data within the design data space is determined. 2. The method of claim 1, wherein the data for the alignment site is within a swath of the inspection data, and determining the location of the inspection data comprises: swaying in the design data space based on the position of the alignment site. Determining the location of the swath of the inspection data in the design data space based on the position of the swath and determining the position of the additional swath of the inspection data in the design data space. Computer-implemented way. The method of claim 1, wherein the one or more attributes of the design data are, for different process layers or some combination thereof, for the process layer from which the inspection data for the wafer was obtained, for the design data, for the different design data, or A computer for determining the location of inspection data within the design data space, for some combination thereof, selected based on one or more attributes of inspection data previously acquired for a wafer, a different wafer, or some combination thereof. How to implement. The method of claim 1, wherein the one or more attributes of the design data comprise: yield criticality of defects previously detected in different portions, fault probability of defects previously detected in different portions, Or based on some combination thereof, computer-implemented method for determining the location of inspection data within a design data space. The method of claim 1, wherein determining the sensitivity comprises: detecting sensitivity on different portions of the wafer based on a context map and a location of the inspection data within the design data space. Determining a location of inspection data within a design data space, wherein the context map comprises a value for one or more attributes of the design data over the design data space. 18. The design data of claim 17, wherein determining the sensitivity further comprises determining a sensitivity threshold used with the inspection data to detect defects on different portions of the wafer. A computer-implemented method of determining the location of test data in a space. 18. The computer-implemented method of claim 17, wherein determining the sensitivity is performed by the inspection system during inspection of the wafer. 18. The computer-implemented method of claim 17, wherein determining the sensitivity is performed after acquisition of the inspection data for the wafer is complete. The method of claim 1, wherein one or more attributes of schematic data about the design of the device being manufactured on the wafer, and one or more attributes of the expected electrical behavior of the physical layout for the device. And based on some combination thereof, changing one or more parameters for detecting a defect on the wafer. The method of claim 1, further comprising changing one or more parameters for detecting defects on the wafer using the inspection data based on one or more parameters of an electrical test process to be performed on the wafer. Computer-implemented method of determining the location of inspection data within a design data space. The method of claim 1, further comprising changing one or more parameters of an electrical test process to be performed on the wafer based on defects detected on the wafer using the inspection data. Computer-implemented method of determining location. The method of claim 1, further comprising periodically changing one or more parameters of an inspection process performed by the inspection system, based on the results of one or more steps of the method, using a feedback control technique. Computer-implemented method for determining the location of inspection data within a design data space. The method of claim 1, further comprising automatically changing one or more parameters of an inspection process performed by the inspection system, based on the results of one or more steps of the method, using a feedback control technique. Computer-implemented method of determining the location of inspection data within a design data space. The method of claim 1, further comprising generating a knowledge base using the results of one or more steps of the method, and generating a test process performed by the inspection system using the knowledge base. Computer-implemented method for determining the location of inspection data within a design data space. The method of claim 1, further comprising classifying the detected defects on different portions of the wafer based on a location and a context map of portions of inspection data corresponding to the defect in the design data space. Is a value for one or more attributes of the design data over the design data space. 28. The computer-implemented method of claim 27, wherein the sorting is performed by the inspection system during inspection of the wafer. 28. The computer-implemented method of claim 27, wherein the classifying step is performed after the acquisition of the inspection data for the wafer is complete. The method of claim 1, wherein the inspection data includes data about defects on the wafer, and the method further comprises: determining a position of the defect in the design data space based on the position of the inspection data in the design data space. And determining, based on the location of the defect in the design data space and one or more attributes of the design data in the design data space, whether the defect is a nuisance defect. A computer-implemented method of determining the location of test data in a computer. 31. The method of claim 30, further comprising determining, based on one or more attributes of design data in the design data space, whether a defect that is not determined to be a Newson's defect is a systematic or random defect. , Computer-implemented method of determining the location of inspection data within a design data space. The computer-implemented method of claim 1, wherein the inspection data is acquired for process window qualification (PWQ). The method of claim 1, wherein the inspection data includes data about defects on the wafer, and the method is based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Classifying the defect further comprising: classifying the location of inspection data within a design data space. The method of claim 1, wherein the inspection data includes data about defects on the wafer, and the method is based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Binning the defects into groups, wherein the location of the inspection data within the design data space is determined. The method of claim 1, wherein the inspection data includes data about defects on the wafer, and wherein the method includes the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and the design. Binning the defects into groups based on one or more attributes of the reticle inspection data obtained for the reticle on which the data is printed above, wherein the location of the inspection data within the design data space is determined. Computer-implemented method. The method of claim 1, wherein the inspection data includes data about defects on the wafer, and wherein the method includes the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and the inspection. And based on one or more attributes of the data, binning the defects into groups. The method of claim 1, wherein the inspection data includes data about defects on the wafer, the method further comprising: the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, the inspection data And binning the defects into groups based on one or more attributes of and one or more attributes of the reticle inspection data obtained for the reticle on which the design data is printed. A computer-implemented method of determining the location of a. The method of claim 1, wherein the inspection data includes data about defects on the wafer, the method further comprising: the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, the inspection data For one or more attributes of, and for different process layers or some combination thereof, for a process layer from which inspection data for the wafer was obtained, for a design data, for different design data, or for some combination thereof, a wafer, a different wafer Or binning the defects into groups, based on one or more attributes of inspection data previously obtained for some combination thereof, computer-implemented to determine the location of inspection data within a design data space. Way. The method of claim 1, wherein the inspection data includes data about defects on the wafer, and the method is based on a location of the inspection data in the design data space and one or more attributes of design data in the design data space. And selecting at least a portion of the defect for review. The method of claim 1, wherein the inspection data includes data about defects on the wafer, and the method is based on a location of the inspection data in the design data space and one or more attributes of design data in the design data space. And determining a sequence in which the defect is reviewed. The method of claim 1, wherein the inspection data includes data about a defect on the wafer, and the method further comprises selecting at least a portion of the defect for review, wherein at least a portion of the defect is the design data. And at least one defect located within each portion of the design data in the design data space having different values of one or more attributes of the computer-implemented method. The system of claim 1, wherein one or more detectors of the inspection system are acquired for different portions of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Extracting one or more predetermined attributes of the output from the computer-implemented method for determining the location of inspection data within the design data space. 43. The method of claim 42, wherein the one or more attributes of the design data are, for different process layers or some combination thereof, for the process layer from which inspection data for the wafer is obtained, for the design data, for the different design data, or for its combination. And for some combinations, is selected based on one or more attributes previously obtained for the wafer, different wafers, or some combination thereof. The method of claim 1, wherein the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data are acquired for different portions of the wafer. Extracting one or more predetermined attributes of the output from the one or more detectors of the inspection system, wherein the location of the inspection data within the design data space is determined. The method of claim 1, wherein determining an error probability value for one or more defects detected on the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Further comprising a location of the inspection data within the design data space. The method of claim 1, further comprising: determining a position coordinate of a defect detected on the wafer in the design data space based on a position of the inspection data in the design data space, and determining the position of the defect based on a plan view of the design data. And translating the position coordinates into the design cell coordinates. 47. The method of claim 46, further comprising determining different areas around the defect using overlay tolerance, determining whether one or more cell types are systematically defective cell types, and determining the systematically defective cell type. Design data, further comprising performing defect repeater analysis for the one or more cell types, using the region to determine one or more locations of one or more systematically defective geometries within the design data. A computer-implemented method of determining the location of test data in a space. 48. The method of claim 47, wherein the spatially systematic defect is based on one or more attributes, structures, or some combination thereof, of design data for a cell located proximate to the systematically defective cell type. And determining the location of the inspection data within the design data space. The method of claim 1, further comprising: determining a location of a detected defect on the wafer in the design data space based on the location of the inspection data in the design data space, and determining a predetermined value for one or more attributes of the design data. Using a data structure in which a value is stored as a function of a location in the design data space, further comprising determining a value for one or more attributes of the design data corresponding to the location of the defect. Computer-implemented method of determining the location of data. The inspection in a design data space of claim 1, wherein an image of the reticle generated by the reticle inspection system is used as design data in the design data space, and the reticle is used to print the design data on the wafer. Computer-implemented method of determining the location of data. The computer-implemented method of claim 1, wherein a simulated image showing how a reticle image is to be printed on the wafer is used as design data in the design data space. . The method of claim 1, further comprising generating a context map for design data in the design data space based on the reticle inspection data obtained for the reticle used to print the design data on the wafer. Computer-implemented method of determining the location of inspection data within a design data space. The method of claim 1, further comprising optimizing a wafer inspection process to determine the printability of reticle defects on the wafer using a location map and a context map of inspection data within the design data space. Computer-implemented method of determining the location of test data. 2. The method of claim 1, further comprising detecting a defect on the wafer using a standard reference die for the inspection data and a standard reference die based inspection. Computer-implemented way. The method of claim 1, further comprising detecting defects on the wafer using a representation of wafer noise associated with a standard reference die in a perturbation matrix for the inspection data, a standard reference die, and a standard reference die based inspection. Further comprising the steps of: determining the location of inspection data within the design data space. The method of claim 1, wherein the wafer and additional wafers are processed using wafer level process parameter modulation, wherein the method compares inspection data for the die on the wafer and the additional wafers with a conventional standard reference die, And detecting defects on the wafer and additional wafers. A system configured to determine a location of inspection data within a design data space,
A storage medium containing design data; And
A processor coupled with the storage medium,
The processor comprising:
Align the data obtained by the inspection system for the alignment site on the wafer with the data for the predetermined alignment site,
Based on the location of the predetermined alignment site in the design data space, determine the location of the alignment site on the wafer in the design data space,
Based on the position of the alignment site on the wafer in the design data space, determine the position of inspection data acquired for the wafer by the inspection system in the design data space,
Sensing for detecting a defect on a different portion of the wafer based on a location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data Configured to determine sensitivity,
Wherein the one or more attributes of the inspection data include one or more image noise attributes, or some combination of the image noise attributes, when one or more defects are detected in the different portions. The system is configured to determine. A system configured to determine a location of inspection data within a design data space,
An inspection system configured to obtain data about alignment sites on a wafer and inspection data for the wafer;
A storage medium containing design data; And
A processor coupled to the inspection system and the storage medium,
The processor comprising:
Align the data for the alignment site on the wafer with the data for the predetermined alignment site,
Based on the location of the predetermined alignment site in the design data space, determine the location of the alignment site on the wafer in the design data space,
Based on the location of the alignment site on the wafer in the design data space, determine the location of inspection data in the design data space,
Sensing for detecting a defect on a different portion of the wafer based on a location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data Configured to determine sensitivity,
Wherein the one or more attributes of the inspection data include one or more image noise attributes, or some combination of the image noise attributes, when one or more defects are detected in the different portions. The system is configured to determine.

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