JP5465880B2 - Method and system for using design data in combination with inspection data - Google Patents

Description

Related applications

(Claiming priority)
This application is a US Provisional Application No. 60/737, entitled “Methods and Systems for Customizing Design Data in Combination with Inspection Data,” filed Nov. 18, 2005, which is incorporated herein by reference. No. 947 and US Provisional Application No. 60 / 738,290 entitled “Methods and Systems for Customizing Design Data in Combination with Inspection Data” filed on Nov. 18, 2005.

  The present invention generally relates to a method and system for using design data in combination with inspection data. Some embodiments relate to computer-implemented methods that determine the position of inspection data in the design data space and / or determine the position of the design space placement on the wafer substantially accurately during the execution of the inspection process.

  The following description and examples are not admitted to be prior art because they are included in this section.

  Integrated circuit (IC) design can be performed using methods or systems such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. Such a method and system can be used to generate a circuit pattern database from an IC design. The circuit pattern database includes data representing multiple layouts for various layers of the IC. The data in the circuit pattern database can be used to determine the layout for multiple reticles. A reticle layout typically includes a plurality of polygons that define a pattern of features on the reticle. Each reticle is used to fabricate one of the various layers of the IC. The IC layers include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on an electrode wiring layer.

  The term “design data” as used herein refers to the physical design (layout) of an IC and is derived from a physical design through complex simulations or simple geometric and Boolean operations. Refers to data.

  Semiconductor device designs are verified by various procedures prior to IC production. For example, the semiconductor device design is checked by software simulation that verifies that all features are printed correctly after lithography in the manufacturing process. Such check operations typically involve steps such as design rule check (DRC), optical rule check (ORC), more advanced software based on verification approaches including process simulation calibrated to a specific fab or process. including. The output of the physical design verification step can be used to locate critical points, sometimes referred to as “hot spots”, which are also potentially numerous in the design.

  Manufacturing semiconductor devices such as logic devices and memory devices typically uses a large number of semiconductor manufacturing processes to process substrates such as semiconductor wafers that form various features and multiple levels of semiconductor devices. Including doing. For example, lithography is a semiconductor manufacturing process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, ion implantation. The plurality of semiconductor devices are processed in an array on a single semiconductor wafer and then divided into individual semiconductor devices.

  The inspection process is used at various steps in the semiconductor manufacturing process to detect defects on the wafer, which promotes increased manufacturing process yield and increased revenue. Inspection has always been an important part of processing semiconductor devices such as ICs. However, as the size of a semiconductor device decreases, small defects can cause the device to fail, and inspection becomes even more important for successfully manufacturing a semiconductor device that meets specifications. For example, as the size of semiconductor devices decreases, it has become necessary to detect defects of small size because even relatively small defects can cause undesirable erratics in the semiconductor device.

  Another important part of manufacturing yield management is to identify the cause of defects on the wafer or reticle and correct the cause of the defects, thereby reducing the number of defects on other wafers or reticles. In many cases, locating the cause of a defect involves identifying the defect type and identifying other attributes of the defect such as size, shape, composition. Inspection typically only detects defects on the wafer or reticle and provides limited information about the defect such as placement on the wafer or reticle, number of defects on the wafer or reticle, and sometimes defect size. Since they are not included, defect reviews are often used to obtain information about individual defects beyond those determined from inspection results. For example, a defect review tool can be used to review defects detected on a wafer or reticle and to examine the defects further by some automatic or manual means.

  The defect review typically involves generating supplemental information about the defect with higher resolution using either high magnification optics or a scanning electron microscope (SEM). Higher resolution data for defects generated by defect review is more suitable for determining defect attributes such as profile, roughness, and more accurate size information. Defect analysis can also be performed using a system such as an electron dispersive x-ray spectroscopy (EDS) system. Such defect analysis is performed to find information such as the composition of the defect. By using defect attributes determined by inspection, review, analysis, or some combination thereof, the type of defect (ie, defect classification) can be identified and, in some cases, the root cause of the defect can be determined . This information can then be used to monitor and change one or more parameters of one or more semiconductor processing processes to reduce or eliminate defects.

  However, as design rules shrink, semiconductor manufacturing processes may be operating near the limits of their ability to execute. In addition, as design rules shrink, even small defects can affect device electrical parameters, requiring careful attention to inspection. Thus, as design rules shrink, the potential yield-related defect population detected by inspection expands dramatically, and the nuisance defect population detected by inspection also increases dramatically. Increase. Thus, more and more defects are detected on the wafer, and correcting the process to eliminate all defects can be a difficult task and can be expensive. In doing so, by identifying the defects that actually affect the electrical parameters and yield of the device, the process control method is focused on those defects, and the other defects are largely ignored. It is possible to Furthermore, with smaller design rules, process-induced failures tend to be systematic failures in some cases. That is, process-induced failures tend to occur in a predetermined design pattern that is often repeated many times in the design. The elimination of spatially statistical, electrically related defects is important because eliminating such defects has a significant overall impact on yield. Whether defects affect device parameters or yield can often not be determined from the inspection, review, and analysis processes described above, which means that these processes determine the location of defects with respect to electrical design. This is because it may not be possible to determine.

  Several methods and systems have been developed for aligning defect information with electrical designs. For example, a SEM review system can be used to determine more accurate coordinates of defect placement for a sample of defects, and defect coordinates reported by the SEM review system can be used to determine defects in electrical design. Can be determined. Another method involves aligning the area to be inspected (eg, the area of the device formed on the wafer on which the inspection is performed) with the physical arrangement of the pattern printed on the wafer. However, at present, the target area can be aligned with the pattern printed on the wafer with an accuracy of about 2 μm or less due to system errors and imperfections. For example, a bright field (BF) inspection system has a coordinate accuracy of about ± 1 μm. In addition, the area to be inspected in currently used methods is relatively wide and includes many non-critical features, but of course also includes desirable critical features. Even if the inspection system tries to maximize the sensitivity to capture subtle spatially systematic “manufacturable design” (DFM) defects that result from the interdependence of design and process, It can be overwhelmed by millions of events in non-critical areas such as areas. Detecting such nuisance defects is not beneficial for a number of reasons. For example, these nuisance defect events need to be removed from inspection results by post-processing of inspection data. In addition, nuisance event detection limits the ultimate achievable sensitivity of the inspection system for DFM applications. High rates of nuisance defect data can also overload the run-time data processing capabilities of the inspection system, thereby reducing throughput and / or causing data loss.

  Therefore, the grouping of pixels in defect detection algorithms or methods, reworking of detection sensitivity, nuisance defect filtering, defect classification, defect Sub-pixel accuracy for inspection data to perform one or more context-based functions such as grouping, sampling defects so that they can be reviewed by using the design context as part of the sampling scheme It would be beneficial to develop a method and system for aligning design data (where the pixel size can be a measure of the size of the geometry being examined).

  The following description of various embodiments of methods and systems should not be construed as limiting the subject matter of the appended claims in any way.

  One embodiment relates to a computer-implemented method for determining the location of inspection data in a design data space. The method includes aligning data captured by an inspection system for an alignment site on a wafer with data (eg, design data) for a predetermined alignment site. Data for a predetermined alignment site and data captured by the inspection system for the alignment site on the wafer are obtained separately. For example, data for a predetermined alignment site is not captured using a wafer on which the alignment site is printed. The method further includes determining the position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site in the design data space. Determining the position of the alignment site on the wafer in the design data space is further performed based on the design layout on the wafer and / or the orientation of the wafer during inspection. In addition, the method includes determining the position of inspection data captured for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. The location of the inspection data is stored and used as described further herein. In one implementation, the location of the inspection data is determined with sub-pixel accuracy.

  In other embodiments, the data for a given alignment site may be a graphic data stream (GDS) file, other standard machine readable files, other suitable files known in the art, design databases, etc. , Including design data stored in a data structure. A GDSII file is one of a class of files used to represent design layout data. Other examples of such files include GL1 files and OASIS files. Although some implementations are described herein with respect to GDS or GDSII files, these implementations apply to this entire class of files regardless of data structure organization, storage format, or storage mechanism. It should be understood that it is equally applicable. In different embodiments, the data for a given alignment site includes one or more simulated images that show how the given alignment site is printed on the wafer.

  In some embodiments, the data for the predetermined alignment site includes one or more attributes of the predetermined alignment site, and the data for the alignment site includes one or more attributes of the alignment site and are aligned. Includes aligning one or more attributes of the predetermined alignment site to one or more attributes of the alignment site. In one such embodiment, the one or more attributes of the predetermined alignment site include a centroid of the predetermined alignment site, and the one or more attributes of the alignment site include a centroid of the alignment site.

  In additional embodiments, data for a given alignment site includes data aligned with design data stored in a data structure, such as a GDSII file for design data, captured by an inspection system or other image acquisition system. . In yet another embodiment, the data for a given alignment site includes at least a portion of a standard reference die image aligned with design coordinates in the design data space. The standard reference die image may be a captured reference, a simulated or magnified reference image, or a combination of these.

  In some implementations, the predetermined alignment site includes at least one alignment feature having one or more attributes that are unique in the x and y directions. In other embodiments, the predetermined alignment site includes at least two alignment features. The first of the at least two alignment features has one or more attributes that are unique in the x direction. The second of the at least two alignment features has one or more attributes that are unique in the y direction.

  In an additional embodiment, the method includes selecting a predetermined alignment site using an inspection system. In one such embodiment, the imaging mode of the inspection system (or other image acquisition system) used to select the predetermined alignment site is one of the inspection systems used to capture inspection data. Or different from multiple imaging modes. In some implementations, determining the position of the alignment site is performed prior to inspection of the wafer, and determining the position of inspection data is performed during inspection of the wafer. In other embodiments, determining the location of the inspection data is performed subsequent to inspection of the wafer. In such an embodiment, determining the position of the inspection data is performed for the position of the inspection data corresponding to the defect detected on the wafer and not for the position of the inspection data not corresponding to the defect. As described above, the position of the inspection data in the design data space is determined only by the inspection data (for example, patch image) acquired by the defect arrangement on the wafer.

  In other embodiments, the data for the alignment site is in a swath of test data. In other such embodiments, determining the position of the inspection data may include determining a swath position in the design data space based on the position of the alignment site in the design data space, and based on the swath position. Determining the location of additional swaths of inspection data in the design data space.

  In one embodiment, the method includes determining sensitivity to detect defects in different portions of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. . In one such embodiment, the one or more attributes of the design data may include design data, different design data, or a process layer for which wafer inspection data was captured, a different process layer, or some combination thereof, or Some combination thereof is selected based on one or more attributes of inspection data already captured for the wafer, other wafers, or some combination thereof. In other such implementations, the one or more attributes of the design data may include the yield criticality of defects already detected in different parts, the failure probability of defects already detected in different parts, or their It is selected based on some combination.

  In another embodiment, the method detects defects in different portions of the wafer based on a context map that includes the location of inspection data in the design data space and values for one or more attributes of the design data across the design data space. Determining the sensitivity to perform. In one such implementation, determining the sensitivity includes determining a sensitivity threshold that is used with the inspection data to detect defects at different portions of the wafer. In other such embodiments, determining the sensitivity is performed by the inspection system when inspecting the wafer. In other such embodiments, determining sensitivity is performed after inspection data capture for the wafer is complete.

  In an additional embodiment, the method includes different portions of the wafer based on the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data. Determining the sensitivity of detecting defects. In one such implementation, the one or more attributes of the inspection data include one or more image noise attributes, or some combination thereof, when defects are detected in different portions.

  In some implementations, the method includes one or more attributes of schema data for a design of a device being processed on a wafer, one or more of the expected electrical behavior of a physical layout for the device. Changing one or more parameters that detect defects on the wafer based on the attributes, or some combination thereof. In other embodiments, the method includes one or more for detecting defects on the wafer using inspection data based on one or more parameters of an electrical test process to be performed on the wafer. Including changing the parameters. In other embodiments, the method includes altering one or more parameters of an electrical test process performed on the wafer based on defects detected on the wafer using inspection data.

  In another embodiment, the method periodically changes one or more parameters of an inspection process performed by the inspection system based on the results of one or more steps of the method using feedback control techniques. Including doing. In other embodiments, the method automatically alters one or more parameters of an inspection process performed by the inspection system based on the results of one or more steps of the method using feedback control techniques. Including doing. In yet another embodiment, the method uses the result of one or more steps of the method to generate a knowledge base and uses the knowledge base to generate an inspection process that is performed by the inspection system. Including.

  In another embodiment, the method includes the location of a portion of the inspection data corresponding to a defect in the design data space and a wafer map based on a context map that includes values for one or more attributes of the design data across the design data space. Including classifying defects detected in different parts. In one such embodiment, classifying the defects is performed by the inspection system when inspecting the wafer. In other such embodiments, classifying the defects is performed after inspection data capture for the wafer is complete.

  In other embodiments, the inspection data includes data for one or more defects on the wafer. In one such embodiment, the method determines the position of the defect in the design data space based on the position of the inspection data in the design data space, and the position of the defect in the design data space and the design data in the design data space. Determining whether the defect is a nuisance defect based on one or more attributes of In one such embodiment, the method determines whether a defect that is not determined to be a nuisance defect based on one or more attributes of the design data in the design data space is a systematic defect or a random defect. Determining. Determining whether the defect is a spatial systematic defect or a random defect is further combined with other information such as historical fab data or other data corresponding to hot spots in the design data. It can also be performed based on one or more attributes of design data in the design data space. In one such embodiment, the method further includes determining whether the defect is a systematic defect based on the location of the inspection data in the design data space and one or more statistically determined attributes of the inspection data. Or determining whether it is a random defect. In one embodiment, inspection data is captured for process window qualification. In another embodiment, the method includes classifying defects based on the location of inspection data in the design data space and one or more attributes of the design data in the design data space.

  In one embodiment, the method includes grouping defects according to bin ranges based on the location of inspection data in the design data space and one or more attributes of the design data in the design data space. In some embodiments, the method includes the location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one of the reticle inspection data captured for the reticle on which the design data is printed. Or grouping defects according to bin ranges based on a plurality of attributes. In an additional embodiment, the method is in accordance with a bin range based on the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data. Including grouping defects. In some embodiments, the method prints the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, the design data. Grouping defects according to bin ranges based on one or more attributes of reticle inspection data captured for the reticle. In other embodiments, the method may be based on the location of inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, and even on the wafer. For the process layer from which inspection data was captured, a different process layer, or some combination thereof, for the design data, different design data, or some combination thereof, to the wafer, other wafers, or some combination thereof Including grouping defects according to bin ranges based on one or more attributes of inspection data already captured.

  As described above, the inspection data includes data for one or more defects on the wafer. In one such embodiment, the method includes at least a portion of a defect for review based on the location of inspection data in the design data space and based on one or more attributes of the design data in the design data space. Including selecting. In such other embodiments, the method determines the order in which defects are reviewed based on the location of inspection data in the design data space and based on one or more attributes of the design data in the design data space. Including deciding. In yet other such embodiments, the method includes selecting at least a portion of the defect for review, wherein at least a portion of the defect has a different value of one or more attributes of the design data. At least one defect found in each portion of the design data in the design data space. Defect review sampling is additionally or alternatively performed based on one or more attributes of the group into which defects are separated according to bin ranges. Defects are divided according to bin ranges, as described further herein, and one or more attributes of those groups can be based on one or more attributes of the design data or as used herein. Determined by other methods described.

  In another embodiment, the method includes an inspection system captured for different portions of a wafer based on the location of inspection data in the design data space and based on one or more attributes of the design data in the design data space. Extracting one or more predetermined attributes of the output from the one or more detectors. In one such embodiment, the one or more attributes of the design data may include design data, different design data, or a process layer for which wafer inspection data was captured, a different process layer, or some combination thereof, or Some combination of them is selected based on one or more attributes of inspection data already captured for the wafer, other wafers, or some combination thereof.

  In other embodiments, the method may be used for different portions of a wafer based on the location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. Extracting one or more predetermined attributes of the output from one or more detectors of the captured inspection system. In one such embodiment, the one or more attributes of the inspection data may include one or more image noise attributes, or some combination thereof, if one or more defects are detected in different portions. including.

  In some embodiments, the method includes one or more detected on the wafer based on the location of the inspection data in the design data space and based on one or more attributes of the design data in the design data space. Determining a failure probability value for a given defect.

  In another embodiment, the method is based on determining a coordinate of a position of a defect detected on the wafer in the design data space based on the position of the inspection data in the design data space, and on a floor plan for the design data. And converting the coordinates of the position of the defect into design cell coordinates. In one such embodiment, the method uses overlay tolerances to determine different regions around the defect and performs defect repeater analysis using different regions for one or more cell types. Determining whether one or more cell types are systematic defect cell types, and determining one or more arrangements of one or more systematic defect geometries within the systematic defect cell types Determining. In one such embodiment, the method includes a spatial lineage based on one or more attributes of the design data for a cell, geometry, or some combination thereof that is located near the systematic defect cell type. Determining whether a physical defect occurs within the systematic defect cell type.

  In another embodiment, the method determines a position of a detected defect on the wafer in the design data space based on the position of the inspection data in the design data space, and for one or more attributes of the design data. Determining a value for one or more attributes of the design data corresponding to the position of the defect using a data structure stored as a function of position in the design data space.

  In another embodiment, an image of a reticle generated by a reticle inspection system is used as design data in a design data space. The reticle is used to print design data on the wafer. In other embodiments, a simulated image illustrating how the reticle image is printed on the wafer is used as design data in the design data space. In an additional embodiment, the method includes generating a context map for design data in the design data space based on reticle inspection data captured for the reticle used to print the design data on the wafer. .

  In one embodiment, the method includes optimizing a wafer inspection process that uses the location of the inspection data in the design data space and the context map to determine the printability of reticle defects on the wafer. In other embodiments, the method includes using the inspection data and the standard reference die for standard reference die based inspection to detect defects on the wafer. In another embodiment, the method uses a representation of wafer noise associated with the standard reference die in the inspection data, standard reference die, and perturbation matrix for standard reference die based inspection, and defects on the wafer. Detecting.

  In other embodiments, the wafer and the additional wafer are processed using wafer level process parameter modulation, and the method can pass inspection data for the die on the wafer and the additional wafer to a common standard reference die. Detecting defects on the wafer and additional wafers by comparing.

  Each of the above steps is an approximate location of inspection data in the design data space, one or more attributes of the design data in the design data space, historical fab data, or other data corresponding to hot spots in the design data. It is executed based on. In some embodiments, the method can include a defect, one or more attributes of a group in which the defect is separated according to a bin range, or any of the method embodiment (s) described herein. Performing statistical process control (SPC) based on other results. Each of the method embodiments described above includes other step (s) of the method (s) described herein. Each of the method embodiments described above may be performed by any of the system embodiments described herein.

  Another embodiment relates to a system configured to determine the location of inspection data in a design data space. The system includes a storage medium that stores design data. The system further includes a processor coupled to the storage medium. The processor is configured to align data captured by the inspection system for alignment sites on the wafer with data for a predetermined alignment site. The processor is further configured to determine the position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site in the design data space. In addition, the processor is configured to determine the position of inspection data captured for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. This embodiment of the system is further configured as described herein.

  An additional embodiment relates to a system configured to determine the location of inspection data in the design data space. The system includes an inspection system configured to capture data for alignment sites on the wafer and inspection data for the wafer. The system further includes a storage medium storing design data. In addition, the system also includes an inspection system and a processor coupled to the storage medium. The processor is configured to align data for alignment sites on the wafer with data for predetermined alignment sites. The processor is further configured to determine the position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site in the design data space. In addition, the processor is configured to determine the position of the inspection data in the design data space based on the position of the alignment site on the wafer in the design data space. This embodiment of the system is further configured as described herein.

  Additional embodiments may be examined at run time (eg, when performing an inspection process) target areas (eg, areas to be inspected, areas to be inspected with higher sensitivity, or with lower sensitivity) based on design data in the inspection space. Related to a system configured to determine the position of the area to be. In addition, the system is configured to substantially accurately assign the captured pixels to the correct area to be inspected when performing the inspection process. The size and frequency of such a region to be inspected approaches the size and frequency of the design geometry on the die. The system is further configured as described herein.

  Another embodiment relates to a computer-implemented method for separating defects detected on a wafer according to bin ranges. The method includes comparing portions of the design data that are proximate to the location of the defect in the design data space. The method further includes determining whether the design data in those portions is at least similar based on the result of the comparing step. Determining whether the design data in those portions is at least similar includes rotating and / or mirroring one or more of those portions. In addition, when the defects are grouped according to bin ranges, the method includes grouping such that portions of the design data that are proximate to the position of the defect in each of those groups are at least similar. The method further includes storing the result of the grouping step according to the bin range on a storage medium.

  In one embodiment, the dimensions of these portions are determined at least in part from the location of the defect reported by the inspection system used to detect the defect, inaccuracies in the coordinates of the inspection system, one of the design data. Or based on multiple attributes, inspection system defect size error, or some combination thereof. In other embodiments, the dimensions of at least some of these portions are different.

  In one implementation, the design data in these portions includes design data for multiple design layers. In this method, the design data used in the methods described herein is design data for one or more layers of the design. Using the design data for one or more layers of the design in the method described herein can detect defects using bright field (BF) inspection that can detect defects in multiple layers. This is useful in cases such as when detected and where the criticality of the placement can depend on what happens in the layers before or after the design. The method described above includes grouping a portion or front of the defect of interest together with at least similar design data according to bin ranges.

  In other embodiments, the comparing step includes comparing the entire design data in at least some of those portions with design data in other portions of the portions. In different embodiments, the comparing step includes comparing different regions of design data in at least some of those portions with design data in other portions of those portions.

  In one embodiment, the method includes determining the position of the defect in the design data space by comparing data captured by the inspection system for the alignment site on the wafer with data for a predetermined alignment site. In another embodiment, the method includes determining the position of the defect in the design data space by comparing the data captured by the inspection system upon detection of the defect with an arrangement in the design data determined by review.

  It should be noted that the alignment accuracy depends on both the design-to-wafer coordinate transformation and the inspection system coordinate accuracy. Preferably, therefore, the coordinates reported by the inspection system are substantially accurate. In addition, alignment site measurements are performed using logical test coordinates. The inspection system outputs logical wafer coordinates, while a defect review tool such as a scanning electron microscope (SEM) measures physical wafer coordinates. Thus, the physical coordinates on the wafer are corrected by the inspection system to account for reticle offset, scaling, and micro-rotation differences when compared to the expected wafer layout. In so doing, these corrections are further applied to SEM measurements to reduce errors between the two coordinate systems from reticle to reticle.

  In one embodiment, the step of binning according to bin ranges is such that when the defects are grouped according to bin ranges, portions of the design data that are proximate to the position of the defect in each of those groups are at least similar, and in each of those groups Grouping such that one or more attributes of the defects are at least similar. In one such implementation, the one or more attributes include one or more attributes of the result of the inspection in which the defect was detected, one or more parameters of the inspection, or some combination thereof.

  In some implementations, the portion of the design data proximate to the location of the defect includes design data where the defect is located. In other embodiments, the portion of the design data proximate to the defect location includes design data around the defect location.

  In another embodiment, the step of binning according to bin ranges is such that when defects are grouped according to bin ranges, portions of the design data proximate to the position of the defect in each of those groups are at least similar and relate to polygons within the portion. Grouping so that the positions of the defects in each of these groups are at least similar.

  In other embodiments, the method includes determining a defect criticality index (DCI) for one or more of the plurality of defects. In other embodiments, the method is used to detect one or more of the defects, one or more attributes of the design data proximate to the position of the defect, one or more attributes of the defect, defects. The probability of causing one or more electrical faults in the device processed for the design data based on the location of the defect reported by the inspected inspection system, inaccuracies in the coordinates of the inspection system, or some combination thereof Including deciding. In one such implementation, the method further includes determining a DCI for one or more of the defects based on the probability.

  In some implementations, the method includes identifying one or more hot spots in the design data based on the results of the step of dividing according to bin ranges. In other embodiments, the method includes selecting at least some of the defects to review based on the result of the step of dividing according to bin ranges. In an additional embodiment, the method includes generating a process for sampling defects to review based on the result of the step of dividing according to bin ranges. In other embodiments, the method includes modifying the process of inspecting the wafer based on the result of the step of dividing according to bin ranges. In some embodiments, the method includes changing the process of inspecting the wafer during inspection based on the results of the inspection. In yet another embodiment, the method includes changing the weighing process for the wafer based on the result of the step of dividing according to the bin range. In yet another embodiment, the method includes changing the sampling plan of the metrology process for the wafer based on the result of the step of dividing according to the bin range. In yet another embodiment, the method includes monitoring systematic defects, potential systematic defects, or some combination thereof over time using the results of the step of dividing according to bin ranges.

  In yet another embodiment, the defect has been detected by an inspection process, the method comprising: reviewing an arrangement on the wafer on which one or more patterns of interest (POI) in the design data are printed; Determining whether a defect has been detected at the location of the one or more POIs based on the results of the steps, and modifying the inspection process to improve one or more defect capture rates. Including.

  In some implementations, the method is performed on a wafer on which design data is printed based on the results of prioritizing one or more POIs in the design data and prioritizing steps. Optimizing one or more processes. In another embodiment, the method prioritizes one or more POIs in the design data and optimizes at least one of the one or more POIs based on the results of the prioritization step. Including. In an additional embodiment, the method prioritizes one or more POIs in the design data, and one or more resolutions of the one or more POIs based on the results of the prioritization step. Optimizing enhancement technology (RET) features.

  In one embodiment, the defect is detected by optical inspection. In some embodiments, the defect is detected by electron beam inspection. In other embodiments, defects are detected with a process window qualification (PWQ) method.

  In some implementations, the method reviews at least some of the defects in one or more of the group to increase the signal to noise ratio resulting from the inspection process, and the inspection in which the defects are detected. Determining whether one or more of the group of defects corresponds to the nuisance defect by removing one or more of the group corresponding to the nuisance defect from the result of the process. In other embodiments, the method may include as a result of at least some review of defects in one or more of the group, one or more attributes of the design data, one or more attributes of the defects, or Categorizing one or more of the group of defects based on some combination of. In an additional embodiment, the method includes the result of at least some review of defects in one or more of the group, one or more attributes of the design data, one or more attributes of the defects, or Locating one or more root causes of the group of defects based on some combination of.

  In one embodiment, the method includes locating one or more root causes of the group of defects by mapping at least some of the defects in one or more of the groups to the results of the experimental process window. In other embodiments, the method locates one or more root causes of a group of defects by mapping at least some of the defects in one or more of the groups to the result of a simulated process window. Including that.

  In some implementations, the method uses the design data regarding the defect placement to model the electrical characteristics of the device being processed and based on the results of the modeling step, the defect placement in the defect placement. Including determining parameter relevance. In other embodiments, the method includes monitoring one or more kill probability (KP) values of the defect based on one or more attributes of the design data. In an additional embodiment, the method monitors KP values for one or more POIs in the design data, and detects design data proximate to the location of the defect grouped into one or more groups according to the bin range. Assigning a KP value for one or more POIs to one or more of the groups if the portion corresponds to one or more POIs.

  In some embodiments, one or more of the method steps described herein may be separated by the inspection system (ie, “on-tool”) or physically separated from the inspection system, Probably implemented by a processor coupled to the inspection system using a transmission medium. For example, in one embodiment, the computer-implemented method is performed by an inspection system that is used to detect defects. In an alternative embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect the defect.

  In other embodiments, the determining step includes determining whether common patterns in the design data in the portion are at least similar. In an additional embodiment, the determining step includes determining whether the common attributes of the design data in the portion are at least similar. In another embodiment, the determining step includes determining whether common attributes in the feature space of the design data in the portion are at least similar.

  In one embodiment, the method includes determining a percentage of dies formed on the affected wafer (s) of the group of defects. In another embodiment, the method includes determining one or more POIs in the design data corresponding to at least one of the groups, and at least one of the groups corresponding to the one or more POIs according to the bin range. Determining the ratio of the number of defects divided into the number of one or more POI placements on the wafer. In an additional embodiment, the method includes determining one or more POIs in the design data corresponding to at least one of the groups and at least one of the groups corresponding to the one or more POIs according to the bin range. Determining the ratio of the number of defects divided into the number of placements of one or more POIs in the design data.

  In another embodiment, the method includes determining a POI in design data corresponding to at least one of the groups and forming on the wafer where the defects divided into at least one of the groups according to the bin range are located. Determining a percentage of the die that has been made and assigning a priority to the POI based on the percentage. In some implementations, the method includes prioritizing one or more of the groups by the number of total design instances on a wafer in which a defect included in one or more of the groups is detected. In another embodiment, the method includes grouping according to the number of design instances on the reticle that are used to print design data on a wafer in which defects in one or more of the groups are detected at least once. Prioritizing one or more of the. In an additional embodiment, the method includes the number of placements on the reticle in which a defect divided into one or more groups according to the bin range is detected, and the defect divided into one or more groups according to the bin range. Determining a reticle-based limit for one or more of the groups based on the total number of portions of the design data printed on the reticle that are at least similar to the portion of the design data proximate to the location of.

  In one implementation, the method includes converting a portion of the design data proximate to the location of the defect in the design data space to a bitmap prior to the comparing step. In one such implementation, the comparing step includes comparing the bitmaps.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system described herein.

  Another embodiment relates to a method for determining DCI for defects detected on a wafer. The method includes determining the probability that the defect will change one or more electrical attributes of the device being processed on the wafer, the one or more attributes of the design data for the device that are proximate to the position of the defect in the design data space. To make a decision based on The method further includes determining a DCI for the defect based on the probability that the defect changes one or more electrical attributes. In addition, the method includes storing the DCI on a storage medium.

  In one embodiment, the defect includes a random defect. In other embodiments, the defects include systematic defects. In additional embodiments, the one or more electrical attributes include device functionality. In other implementations, the one or more electrical attributes include one or more electrical parameters of the device.

  In one implementation, the one or more attributes of the design data include a redundancy, a net list, or some combination thereof. In other implementations, the one or more attributes of the design data include feature dimensions in the design data, feature densities in the design data, or some combination thereof.

  In one embodiment, determining the probability includes determining the probability using a correlation between an electrical test result for the design data and one or more attributes of the design data. In other embodiments, determining the probability is reported by an inspection system used to detect one or more attributes of the design data combined with the probability that the defect is located in the design data space, the defect. Determining the probability based on the location of the defect, the inaccuracy of the inspection system coordinates, the size of the defect, the defect size error of the inspection system, or some combination thereof. In one such embodiment, the defects include random defects.

  In some implementations, determining the probability includes determining the probability based on one or more attributes of the design data in combination with one or more attributes of the defect. In one such embodiment, the defect includes a systematic defect.

  In one embodiment, determining the DCI includes determining the DCI for the defect based on the probability in combination with the classification assigned to the defect. In other implementations, the one or more attributes of the design data include one or more attributes of the design data for multiple design layers of the device.

  In one embodiment, the method includes determining design data proximate to a defect location by determining the location of inspection data in the design data space. In other embodiments, the method includes determining design data proximate to a defect location by defect alignment. In some implementations, the method includes, at least in part, the location of the defect reported by the inspection system used to detect the defect, the inaccuracy of the inspection system coordinates, one of the design data or Determining design data proximate to the position of the defect based on a plurality of attributes, defect size, defect size error of the inspection system, or some combination thereof.

  In one embodiment, the method includes modifying the DCI based on design data yield sensitivity to defects. In other embodiments, the method includes altering a process performed on the defect based on the DCI determined for the defect. In additional embodiments, the method includes changing the process used to detect the defect based on the DCI determined for the defect. In other embodiments, the method includes generating a process for inspection of additional wafers on which the device is processed based on DCI for defects.

  In one embodiment, the computer-implemented method is performed by an inspection system that is used to detect defects. In other embodiments, the computer-implemented method is performed by a system other than an inspection system used to detect defects.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by any of the systems described herein.

  Another embodiment relates to a computer-implemented method for determining a memory repair index (MRI) of a memory bank formed on a wafer. The method includes determining the number of redundant rows and redundant columns required to repair the memory bank based on defects located in the array block area of the memory bank. The method further includes comparing the number of redundant rows required to repair the memory bank with the number of available redundant rows in the memory bank. In addition, the method includes comparing the number of redundant columns required to repair the memory bank with the number of available redundant columns in the memory bank. The method further includes determining the MRI of the memory bank based on the result of comparing the number of redundant rows and the result of comparing the number of redundant columns. MRI indicates whether the memory bank can be repaired. The method further includes storing the MRI on a storage medium.

  In one embodiment, the method determines which of the defects located in the array block area causes errors in the bits in the memory bank and causes errors in those bits. Determining the position of the bit causing the error based on the placement of the defect. In one such embodiment, determining the number of redundant rows and redundant columns needed to repair the memory bank is performed using the location of the bit causing the error.

  In other embodiments, the method includes changing one or more parameters of the electrical test process based on MRI using a feed forward control technique. In an additional embodiment, the method uses an MRI using a feed forward control technique so that if the memory bank is not repairable, the die in which the memory bank is located is not tested during the electrical test process. Changing one or more parameters of the electrical testing process based on In other embodiments, the method includes one or more of the repair process based on one or more attributes of defects located in the array block region of the memory bank, MRI, or some combination thereof. Including changing parameters.

  In one embodiment, the defects include defects detected at the gate layer of the memory bank. In other implementations, the defects include defects detected in the metal layer of the memory bank.

  In some implementations, the method includes predicting the bit error mode of the defect based on the placement of the defect in the memory bank. In other embodiments, the method includes determining DCI for one or more of the defects located in the array block region. In one such implementation, determining the number of redundant rows and redundant columns needed to repair the memory bank is performed using DCI for one or more of the defects.

  In one embodiment, comparing the number of redundant rows is performed separately for each bank of the memory die, and comparing the number of redundant columns is performed separately for each bank of the memory die. Executed. In some implementations, the method determines the number of redundant rows available and the number of available redundant columns based on the defects located in the redundant rows of the memory bank and the redundant columns of the memory bank. Including deciding.

  In one implementation, the method includes determining an MRI for a plurality of memory banks formed in the die and predicting a repair yield of the die based on the MRI for the plurality of memory banks. In other embodiments, the method is based on MRI and the number of available redundant columns in the memory bank, the number of available redundant rows, or some combination thereof is evaluated by the memory bank designer. Including deciding whether or not to do.

  In some implementations, the method includes determining an MRI for each memory bank of one or more dies on the wafer and determining the one or more dies based on the MRI for each memory bank. Determining the memory repair yield. In some such implementations, the method includes performing wafer placement based on one or more memory repair yields for one or more dies on the wafer.

  In one embodiment, comparing the number of redundant rows includes determining a portion of the redundant row necessary to repair the memory bank, and comparing the number of redundant columns includes: Determining a portion of redundant columns necessary to repair the memory, and determining an MRI for the memory bank includes determining an MRI based on a portion of the redundant row and a portion of the redundant column. . In some such implementations, the method includes determining an MRI for each memory bank of one or more dies on the wafer and one or more based on the MRI for each memory bank. Determining a memory repair yield of the plurality of dies. In additional such embodiments, the method includes determining a memory repair yield for the wafer based on the memory repair yield for each of the one or more dies.

  In one implementation, the MRI further indicates the probability that the memory repair bank will not be repairable. In one such embodiment, the method includes determining an MRI for each memory bank in one or more dies on the wafer and an MRI for each of the memory banks in the one or more dies. Determining an MRI for the one or more dies based on the MRI for the one or more dies indicates a probability that the one or more dies will not be repairable. In one such embodiment, the method includes determining wafer-based yield prediction based on MRI threshold settings for one or more dies on the wafer.

  In one embodiment, the method includes memory based on the number of defects located in the decoder area of the memory bank, the number of defects located in the sense amplifier area of the memory bank, or some combination thereof. Including determining the number of unrepairable defects in the bank.

  In some implementations, determining the number of redundant rows and the number of redundant columns includes determining DCI for each of the defects located in the array block region of the memory bank, Comparing to a threshold value and determining the number of redundant rows and redundant columns required to repair all defects having a DCI higher than a predetermined threshold value.

  In one embodiment, the method includes determining an MRI for failure of the memory bank due to a defect located in the array block area of the memory bank. In another embodiment, the method includes determining an MRI for failure of the memory bank due to defects located in the redundant row and redundant column of the memory bank.

  In some implementations, the method includes generating a stack map of similar memory bank designs that illustrate the spatial correlation between defects detected in the memory bank. In other embodiments, the method includes determining an MRI based on the die. In an additional embodiment, the method includes determining an indication that indicates when a die on the wafer is defective due to a defect located in the array block region.

  In one embodiment, the method determines an MRI for a memory bank in a die on the wafer and a spatial between two or more of the memory banks indicated by the MRI that it is not repairable. Generating a die stacking map illustrating the correlation. In another embodiment, the method determines the MRI for a memory bank in a die on the wafer and the space between two or more of the memory banks indicated by the MRI that it is not repairable. Generating a stacking map of reticles used to form a memory bank on the wafer illustrating the dynamic correlation.

  In some embodiments, the method identifies a memory bank of a die that is affected by a detected defect in the die and ranks the memory bank based on the effect of the defect on the memory bank. Including. In another embodiment, the method includes determining a percentage of the memory bank formed on the wafer that is affected by a defect in an unrepairable area of the memory bank. In an additional embodiment, the method includes a stacked wafer map of potential failures that may occur in a memory bank formed on a wafer that illustrates a spatial correlation between possible failures. Generating. In other embodiments, the method includes determining an MRI for a plurality of dies formed on the wafer and ranking the plurality of dies based on the MRI.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system described herein.

  Other embodiments relate to different computer-implemented methods that divide the defects detected on the wafer according to bin ranges. The method includes comparing a defect location in the design data space with a hot spot location in the design data. Hot spots located close to at least similar design data are correlated with each other. The method further includes associating a hot spot having a location that is at least similar to the defect. In addition, the method includes grouping defects by bin ranges so that defects in each of the groups are associated only with hot spots that correlate with each other. The method further includes storing the result of the grouping step according to the bin range on a storage medium.

  In one embodiment, the method correlates hot spots by identifying POI placement in design data associated with systematic defects and correlates POIs with similar patterns in design data. And correlating the POI arrangement and the arrangement of similar patterns in the design data as correlated hot spot positions.

  In some implementations, the method includes assigning a DBC to one or more of the groups. In other embodiments, the computer-implemented method is performed by an inspection system that is used to detect defects on the wafer. In other embodiments, the method includes monitoring hot spots using inspection results of one or more wafers on which design data is printed.

  In one embodiment, the method includes inspecting the wafer based on the correlation between hot spots. In other embodiments, the method includes monitoring systematic defects, potential systematic defects, or some combination thereof over time using the results of the step of dividing according to bin ranges. In an additional embodiment, the method includes performing a defect review based on the results of the step of dividing according to bin ranges. In other embodiments, the method includes generating a process for selecting defects to review based on the results of the step of dividing according to bin ranges.

  In one embodiment, the method identifies systematic and potential systematic defects in the design data based on the results of the step of binning according to bin ranges, and identifies systematic and potential systematic defects over time. Monitoring the occurrence. In another embodiment, the method includes generating a process for inspecting a wafer on which design data is printed based on the result of the step of dividing according to bin ranges. In an additional embodiment, the method includes modifying the process of inspecting the wafer on which the design data is printed based on the result of the step of dividing according to the bin range.

  In some embodiments, the method includes determining a percentage of dies formed on the affected wafer of one or more of the group of defects. In other embodiments, the method includes determining a DCI for one or more of the defects. In an additional embodiment, the method includes determining a percentage of dies formed on a wafer having at least one defect grouped therein according to the bin range, and based on the percentage of the group. Assigning priority to at least one.

  In one embodiment, the method depends on the number of total hot spots correlated with the hot spots associated with defects included in one or more of the groups and the number of defects included in one or more of the groups. Prioritizing one or more of the groups. In another embodiment, the method includes a corresponding hot spot arrangement on a reticle used to print design data on a wafer in which defects in one or more of the groups are detected at least once. Prioritizing one or more of the groups by number.

  In some embodiments, the method is associated with the number of placements on the reticle in which defects classified into one or more of the groups according to the bin range are detected, and the defects included in one or more of the groups. Determining a reticle-based limit for one or more of the groups based on the total number of hot spot placements on the reticle that correlate with the hot spots being detected.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system described herein.

  Other embodiments relate to different computer-implemented methods that divide the defects detected on the wafer according to bin ranges. The method includes comparing one or more attributes of design data proximate to a defect location in the design data space. The method further includes determining whether one or more attributes of the design data proximate to the defect location are at least similar based on the result of the comparing step. In addition, when the defect is grouped according to the bin range, the method groups so that one or more attributes of the design data close to the position of the defect in each of those groups are at least similar. Including doing. The method further includes storing the result of the grouping step according to the bin range on a storage medium.

  In one implementation, the one or more attributes include pattern density. In other embodiments, the method includes determining whether the defect is a random defect or a systematic defect using one or more attributes. In an additional embodiment, the method includes ranking one or more of the groups using one or more attributes. In other implementations, the method includes ranking defects included in at least one of the groups using one or more attributes. In some implementations, the one or more attributes include one or more attributes in the feature space.

  In one implementation, the method includes using one or more attributes to divide defects included in at least one of the groups into subgroups according to the bin range. In other embodiments, the method includes analyzing defects included in at least one of the groups using one or more attributes. In an additional embodiment, the method includes determining one or more yield relevances of the defect using one or more attributes. In other embodiments, the method includes determining one or more overall yield associations for the group using one or more attributes. In yet another embodiment, the method includes assigning a DCI to one or more of the defects using one or more attributes.

  In some implementations, the method includes dividing design data proximate to a defect location into design data in a region around the defect and design data in a region where the defect is located. In other embodiments, the method includes identifying structures in the design data for grouping or filtering according to bin ranges using rules and one or more attributes.

  In one embodiment, the method includes performing a review, measurement, test, or some combination thereof based on inspection results generated upon detection of defects and based on defects identified as systematic defects. Including determining the top placement. In other embodiments, the method includes review, measurement, testing, or some combination thereof based on inspection results generated upon detection of defects, defects identified as systematic defects, and defect yield relevance. Determining the placement on the wafer to be performed. In an additional embodiment, the method includes review, measurement, testing, or some of them based on inspection results generated upon detection of defects, defects identified as systematic defects, and process window mapping. Determining the placement on the wafer where the combination is performed.

  In one implementation, the method includes performing a systematic discovery using the results of the step of dividing according to bin ranges and the results of the user-assisted review. In another embodiment, the method isolates the defect based on the functional block in which the defect is located to improve the signal to noise ratio included in the result of the step of dividing according to the bin range prior to the comparing step. Including that.

  In some implementations, the design data is organized into hierarchical cells by design, and the method includes a defect to improve the signal to noise ratio included in the result of the step of dividing according to bin ranges prior to the step of comparing. Isolating defects based on the hierarchical cell in which is placed. In other embodiments, when the design data is organized into hierarchical cells by design and the defects are placed in multiple of the hierarchical cells, the method can be used to determine the area of the hierarchical cell, the probability of the defect location, or Correlating defects with each of the hierarchical cells based on the probability that the defect is placed in each of the hierarchical cells based on some combination of.

  In one embodiment, the defect has been detected by an inspection process, and the method is based on reviewing an arrangement on the wafer on which one or more POIs in the design data are printed and the result of the review step. Determining whether a defect has been detected at the location of the one or more POIs and modifying the inspection process to improve the one or more defect capture rates.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system described herein.

  Another embodiment relates to a computer-implemented method for assigning a classification to defects detected on a wafer. The method includes comparing portions of design data proximate to a defect location in a design data space corresponding to DBCs (eg, different DBC bin definitions) with different design data (eg, POI design examples). A DBC different from design data corresponding to a different DBC is stored in the data structure. The method further includes determining whether the design data in those portions is at least similar to design data corresponding to different DBCs based on the result of the comparing step. In addition, the method includes assigning to the defect a DBC corresponding to design data that is at least similar to the design data in those portions. The method further includes storing the result of the assigning step on a storage medium.

  In one embodiment, the computer-implemented method is performed by an inspection system that is used to detect defects. In other embodiments, the computer-implemented method is performed by a system other than an inspection system used to detect defects.

  In one embodiment, the method includes monitoring hot spots in the design data based on the result of the assigning step. In other embodiments, the design data corresponding to different DBCs may be one or more based on the location of the design data proximate to the location of defects detected on one or more other wafers in the design data space. The defects detected on other wafers are identified by grouping them.

  In some implementations, defects have been detected in the inspection process, and the method can include reviewing the placement on the wafer on which one or more POIs in the design data are printed and the result of the review step. Based on determining whether a defect has been detected at the location of the one or more POIs and modifying the inspection process to improve one or more defect capture rates.

  In one embodiment, the method detects a defect to determine whether the defect is a nuisance defect based on the DBC assigned to the defect and to increase the signal-to-noise ratio resulting from the inspection process. Removing nuisance defects from the results of the inspection process.

  In other embodiments, the method includes determining a KP value for one or more of the defects. In an additional embodiment, the method determines whether the DBC assigned to the defect corresponds to a systematic defect visible to the review system and selects only defects visible from the review system for review. Sampling defects for review. In other embodiments, the method includes determining one or more POIs in the design data by identifying one or more features in the design data that exhibit pattern dependent defects.

  In one implementation, the DBC identifies one or more polygons in the design data where the defect is located or in the design data located near the defect. In other implementations, the DBC identifies the placement of defects within one or more polygons in the design data. In additional implementations, the data structure includes a library that includes examples of design data (eg, POI design examples for DBC bin definitions) organized by technology, process, or some combination thereof.

  In some implementations, the method includes dividing design data proximate to a defect location into design data in a region around the defect and design data in a region where the defect is located. In other embodiments, the method includes monitoring systematic defects, potential systematic defects, or some combination thereof over time using the results of the assigning step. In additional embodiments, the method includes determining a KP value for one or more of the DBCs based on one or more attributes of design data corresponding to the DBC. The KP value is further determined based on one or more attributes of design data and electrical test data corresponding to the DBC. In another embodiment, the method comprises determining a KP value for one or more of the defects based on one or more attributes of the design data corresponding to the DBC assigned to the one or more of the defects. Including. In yet another embodiment, the method includes monitoring a KP value for one or more of the DBCs and assigning a KP value for the DBC assigned to the defect to the defect.

  In one embodiment, the dimensions of at least some of these portions are different. In other implementations, the design data in these portions includes design data for multiple design layers. In another embodiment, the method includes determining the position of the defect in the design data space by comparing data captured by the inspection system for the alignment site on the wafer with data for a predetermined alignment site. In an additional embodiment, the method includes determining the position of the defect in the design data space by comparing the data captured by the inspection system upon detection of the defect with an arrangement in the design data determined by review.

  In one embodiment, the assigning step corresponds to design data having one or more attributes that are at least similar to the design data in those portions and at least similar to one or more attributes of the design data in those portions. Assigning DBCs to defects. In one such implementation, the one or more attributes include one or more attributes of the inspection in which the defect was detected, one or more parameters of the inspection, or some combination thereof.

  In one embodiment, the design data proximate to the position of the defect includes design data where the defect is located. In other embodiments, the design data proximate to the defect location includes design data around the defect location. In an additional embodiment, the method includes groups of polygons included in a portion of the design data proximate to the location of the defect when grouping defects assigned to one or more of the DBCs according to the bin range. Grouping so that the positions of the defects in each of the are at least similar.

  In one embodiment, the method includes selecting at least some of the defects to review based on the result of the assigning step. In other embodiments, the method includes generating a process for sampling defects for review based on the result of the assigning step. In additional embodiments, the method includes changing the process of inspecting the wafer based on the result of the assigning step. In some embodiments, the method includes changing the process of inspecting the wafer during inspection based on the results of the inspection. In another embodiment, the method includes changing the wafer weighing process based on the result of the assigning step. In yet another embodiment, the method includes changing the sampling plan of the metrology process for the wafer based on the result of the assigning step. In addition, the method includes determining an arrangement on the wafer at which measurements, tests, reviews, or some combination thereof are performed at runtime based on the results of the assigning step.

  In other embodiments, the method prioritizes one or more of the DBCs, and the one or more performed on the wafer on which design data is printed based on the results of the prioritization step. Optimizing the process.

  In one embodiment, the method includes locating the root cause of the defect based on the DBC assigned to the defect. In another embodiment, the method includes locating at least some root causes of the plurality of defects by mapping at least some of the plurality of defects to the results of the experimental process window. In an additional embodiment, the method includes determining at least some root causes of the plurality of defects by mapping at least some of the plurality of defects to a simulated process window result. Including. In other embodiments, the method includes locating a root cause corresponding to one or more of the DBCs and assigning a root cause to the defect based on the root cause corresponding to the DBC assigned to the defect. .

  In one embodiment, the method includes determining the percentage of dies that are formed on the wafer to which one or more of the DBCs are affected by the assigned defect. In another embodiment, the method includes determining a POI in design data corresponding to at least one of the DBCs, the number of defects to which at least one of the DBCs is assigned, and the number of POI placements on the wafer. Determining the ratio of.

  In some implementations, the method includes determining one or more POIs in design data corresponding to at least one of the DBCs, and determining the number of defects to which at least one of the DBCs are assigned and the design data. Determining a ratio to the number of placements of the one or more POIs. In another embodiment, the method includes determining a POI in design data corresponding to at least one of the DBCs and a die formed on the wafer on which the defect to which at least one of the DBCs is assigned is located. And determining a priority for the POI based on the ratio.

  In one implementation, the method includes all design instances (eg, POIs from a DBC bin definition) on a wafer (eg, an inspected area of the wafer) in which defects to which one or more of the DBCs are assigned are detected. Including prioritizing one or more of the DBCs according to the number of design examples). In another embodiment, the method includes a reticle (e.g., inspecting a reticle) used to print design data on a wafer where a defect to which one or more of the DBCs are assigned is detected at least once. Prioritizing one or more of the DBCs according to the number of design instances on the region.

  In another embodiment, the method includes the number of placements on a reticle (eg, an inspection area of a reticle) in which a defect to which one or more of the DBCs are assigned is detected, and one or more of the DBCs are assigned. One of the DBCs based on the total number of portions of design data (eg, POI design examples from DBC bin definitions) printed on a reticle that is similar to the portion of the design data proximate to the location of the defect being marked Or determining a reticle-based limit for the plurality.

  In some implementations, the method includes converting a portion of design data proximate to a defect location to a first bitmap prior to the comparing step and a design corresponding to the DBC prior to the comparing step. Converting the data into a second bitmap. In one such implementation, the step of comparing includes comparing the first bitmap and the second bitmap.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system described herein.

  Another embodiment relates to a method for changing the inspection process for a wafer. The method includes reviewing an arrangement on the wafer where one or more POIs in the design data are printed. The method further includes determining based on the result of the step of reviewing whether the defect was to be detected at the placement of the one or more POIs. In addition, the method includes modifying the inspection process to improve one or more defect capture rates for defects located in at least some of the one or more POIs.

  In one embodiment, the changing step includes changing the optical mode of the inspection system used to perform the inspection process. In other embodiments, the step of changing includes determining an optical mode of the inspection system used to perform the inspection process based on the result of the determining step. In additional embodiments, the modifying step includes modifying the inspection process to suppress noise in the results of the inspection process. In other embodiments, the modifying step includes modifying the inspection process to reduce detection of defects that are not of interest. In yet another embodiment, the changing step includes changing an algorithm used in the inspection process. In still other embodiments, the step of changing includes changing one or more parameters of an algorithm used in the inspection process.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system described herein.

  Additional embodiments relate to a system configured to display and analyze design data and defect data. The system includes a user interface configured to display a semiconductor device design layout, in-line inspection data captured for a wafer on which at least a portion of the semiconductor device is formed, and electrical test data captured for the wafer. Prepare. The user interface is further configured to display semiconductor device modeled data and / or fault analysis data for the wafer. The system further comprises a processor configured to analyze one or more of the design layouts, in-line inspection data, electrical test data after receiving an analysis execution instruction from the user via the user interface. The processor is further configured to analyze the data modeled as described above and / or fault analysis data.

  In one embodiment, the electrical test data includes logical bitmap data. In other embodiments, the user interface displays at least two overlays of design layout, in-line inspection data, electrical test data, possibly in combination with other data described herein. Configured as follows. In one such embodiment, the electrical test data includes logical bitmap data. In some implementations, the processor is configured to determine the defect density in the design data space after receiving an instruction to perform the defect density determination from the user via the user interface. In additional embodiments, the processor is configured to perform defect sampling for review after receiving an instruction to perform defect sampling from a user via a user interface. In another embodiment, the processor groups the defects based on the similarity of the design layout close to the position of the defects in the design data space after receiving an instruction to perform the grouping from the user via the user interface. Configured to do. Each of the embodiments of the system described above are further configured as described herein.

  Another embodiment relates to a computer-implemented method for determining the root cause of electrical defects detected on a wafer. The method includes determining the location of electrical defects in the design data space. The method further includes determining whether the location of the portion of the electrical defect defines a spatial signature corresponding to the one or more process conditions. In addition, if the location of the portion of the electrical defect defines a spatial signature corresponding to the one or more process conditions, the method can identify the root cause of the portion of the electrical defect as one or more process conditions. Including identifying as. Thus, the method includes performing a spatial signature analysis on the electrical test results. The method further includes storing the result of the identifying step on a storage medium. Embodiments of the method described above include the other step (s) described herein. The method embodiments described above may be performed by any of the system embodiments described herein.

  Yet another embodiment relates to a computer-implemented method for selecting defects detected on a wafer for review. The method includes identifying one or more zones on the wafer. One or more zones are associated with the location of one or more defect types (eg, possible systematic defects) on the wafer. The method further includes selecting defects detected in only one or more zones to be reviewed. In addition, the method includes storing the result of the selected step on a storage medium. Implementations of this method include the other step (s) described herein. This method embodiment is performed by any of the system embodiments described herein.

  There are several review use cases that can use the method described above. For example, the method described above is used for systematic defect verification from a list of potential systematic defects performed in the discovery phase or during maintenance of the monitoring phase. In addition, the above-described method allows local patterns that are similar to known hot spots (identified by any pattern search performed in the discovery phase or during recipe setup) (ie, Used for systematic defect capture by reviewing known hot spots or locations using local design data. This method is further used for verification or classification of defects detected on or near the hot spot, performed in the monitoring phase.

  The above-described zone information not only samples defects from a particular zone, but also samples critical regions from all zones of the wafer in some reasonable way and / or extracts critical regions from the design. Used to correlate to specific zones of the wafer that are likely to find or locate a specific type of critical area as determined by design. The critical areas extracted from the design data may be for a single device, but the probability of finding actual inspection defects due to these critical areas may be more pronounced in certain wafer zones than in other zones. is there. Thus, the method includes extrapolation of defect information from die to wafer using the zone analysis described above. Implementations of this method include the other step (s) described herein.

  Yet another embodiment relates to a computer-implemented method for evaluating one or more yield-related processes for design data. The method includes identifying potential faults in the design data using rule checks, models, or other suitable steps or methods described herein. The method further includes determining one or more attributes of the potential failure. In addition, the method includes determining whether a potential fault is detectable based on one or more attributes. The method further includes determining which of a plurality of different inspection systems is best suited for detecting a potential failure based on the one or more attributes. In addition, the method includes storing a result of determining which of a plurality of different inspection systems is most suitable for detecting a potential failure stored on the storage medium.

  In one embodiment, the method includes selecting one or more parameters of the inspection system determined to be most suitable. These parameters are selected based on one or more attributes. Thus, the best inspection system type is estimated or selected based on the defect (s) attributes of interest. In other embodiments, the method includes determining the impact of a potential failure on the yield of devices fabricated using design data. Each of the above-described method embodiments includes other described step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system embodiments described herein.

  Another embodiment relates to a carrier medium containing program instructions executable on a processor to perform the computer implemented method (s) or the method (s) described herein. Additional embodiments relate to computer-implemented method (s) or systems configured to perform the method (s) described herein. The system can comprise a processor configured to execute program instructions for performing one or more of the computer-implemented methods or methods described herein. In one embodiment, the system is a stand-alone system. In other embodiments, the system may be part of an inspection system, such as a wafer inspection system, or coupled to the inspection system. In different embodiments, the system may be part of a defect review system or coupled to a defect review system. In yet other implementations, the system may be coupled to a fab database. The system is coupled to the inspection system, review system, and / or fab database by a transmission medium such as a wire, cable, wireless transmission line, and / or network. Transmission media can comprise “wired” and “wireless” portions.

  Other advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments and upon reference to the accompanying drawings.

  While the invention is subject to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described in detail herein. The drawings are not necessarily to scale. However, the drawings and detailed description thereof are not intended to limit the invention to the particular forms disclosed, but on the contrary, the invention is not limited to the invention as defined by the appended claims. All modifications, equivalents, and alternatives that do not depart from the spirit and scope are covered.

  As used herein, the term “wafer” refers to a substrate formed from a semiconductor or non-semiconductor material. Examples of such semiconductor or non-semiconductor materials include, but are not limited to, single crystal silicon, gallium arsenide, and indium phosphide. Such substrates are generally found and / or processed in semiconductor manufacturing facilities.

  The wafer comprises one or more layers formed on the substrate. For example, such layers include, but are not limited to, resists, dielectrics, and conductors. Many different types of such layers are known in the art, and the term wafer as used herein is intended to include wafers that include all types of such layers. Has been.

  The layer or layers formed on the wafer can be patterned or unpatterned. For example, a wafer includes a plurality of dies each having a repeatable patterned feature. By forming and processing such a material layer, a finished device is finally obtained. Many different types of devices, such as integrated circuits (ICs), are formed on a wafer, and the term wafer as used herein is a wafer on which devices of the type known in the art are formed. It is intended to include

  Although embodiments are described herein with reference to a wafer, it is understood that these embodiments can also be used for other samples, such as reticles, which are commonly referred to as masks or photomasks. I will. Many different types of reticles are known in the art, and the terms “reticle”, “mask”, and “photomask” as used herein are all known in the art. It is intended to include other types of reticles.

  The term “design data” as used herein generally refers to the physical design (layout) of an IC, data derived from a physical design through complex simulations or simple geometric and Boolean operations. Point to. In addition, the reticle image and / or its derivatives captured by the reticle inspection system are used as one or more “proxy” to the design data. Such a reticle image or derivative thereof can be used in place of the design layout in any of the embodiments described herein that use design data.

  For example, in one embodiment, an image of a reticle generated by a reticle inspection system is used as design data in the design data space. The reticle is used to print design data on the wafer. Thus, the reticle image generated by the reticle inspection system is used in place of the design data. The reticle image used in this embodiment includes a preferred image of the reticle generated in a suitable manner by a reticle inspection system known in the art. For example, the reticle image may be a high magnification optical or electron beam image of a reticle captured by a high magnification optical reticle inspection system or an electron beam based reticle inspection system, respectively. Alternatively, the reticle image may be a reticle aerial image captured by a spatial imaging reticle inspection system. The image of the reticle is used as a proxy for design data in the embodiments described herein that use design data to perform one or more steps.

  In additional embodiments, the method includes generating a context map for design data in the design data space based on reticle inspection data captured for the reticle used to print the design data on the wafer. . In this way, reticle inspection data is captured as input to the generation of the context map. The context map is configured as described further herein (eg, the context map includes values for one or more attributes of design data across the design data space). The reticle inspection data used to generate the context map includes suitable reticle inspection data known in the art, such as one or more of the above-described reticle images. Thus, in this embodiment, reticle inspection data is used to determine values for one or more attributes of design data printed on the reticle across the reticle, and these values are used in context maps. Are mapped in the design data space. Determining values for one or more attributes of design data printed on a reticle is performed as described herein or in any other suitable manner. The one or more attributes of the design data include the attribute (s) described herein. Mapping the values for one or more attributes from the reticle space to the design data space is further performed as described herein. Such a context map is used in any of the embodiments described herein that include performing one or more steps using the context map. In addition, such a context map is further generated as described herein and / or based on other information described herein.

  The image derived from the reticle image can further be used as a “proxy” of design data. For example, using a reticle image generated by a reticle inspection system or other suitable imaging system to generate a simulated image illustrating how the reticle image is printed on a wafer This can be used as a “proxy” for design data. In one embodiment, a simulated image that illustrates a method for printing a reticle image on a wafer is used as design data in the design data space. Thus, a simulation showing how the reticle image appears on the wafer surface can be further substituted for design data. The simulated image is generated in any manner using any suitable method or system known in the art. The simulated image is used as a proxy for design data in the embodiments described herein that use design data to perform one or more steps.

  In the embodiments described herein that use design data to at least partially perform one or more steps, the design data may comprise design data or a design data proxy as described above, or a combination thereof. Including.

  When referring to the figures, it should be noted that the figures are not to scale. In particular, the scale of some of the elements in the figure is greatly exaggerated to emphasize the characteristics of the elements. Note also that the figures are not drawn to the same scale. By using the same reference numerals, elements shown in several figures are shown which may have a similar configuration.

  FIG. 1 illustrates one embodiment of a computer-implemented method for determining the location of inspection data in the design data space. Note that not all steps shown in FIG. 1 are essential to the implementation of the method. One or more steps may be omitted from or added to the method illustrated in FIG. 1, or the method may be implemented as such within the scope of this embodiment.

  In general, the method includes a data preparation phase, a recipe setup phase (eg, wafer inspection recipe setup), and a wafer inspection phase itself. The method further includes a review phase and an analysis phase. The data preparation phase includes design data (eg, graphic data stream (GDS) file, GDSII file, or other that reflects the physical design layout of the device being processed on the wafer or to be processed on the wafer. Information obtained from data structures such as standard files or databases). Information from the GDS file, other files, or database describes the physical design layout pre-decoration (ie does not add optical proximity correction (OPC) features and other resolution enhancement technology (RET) features to the design. so).

  The method shown in FIG. 1 generally includes aligning a test data stream with design data with sub-pixel accuracy as further described herein. Thus, the methods described herein can generally be referred to as “aligning to design” methods for inspection (eg, wafer inspection). In this method, design data and, where appropriate, context data are used for wafer inspection. Thus, the methods described herein can also be referred to as “context-based inspection” (CBI) methods. Use device design data and context data to increase wafer inspection sensitivity, dramatically reduce nuisance event detection, increase defect classification accuracy, and inspection systems such as process window qualification (PWQ) The application functions can be enhanced. The context data is also used to advantageously utilize a defect review process or system as described further herein. In addition, an example of how to use design data and context data can be found in US Patent No. 6,886,153 to Bevis, incorporated by reference as if set forth in its entirety herein. And US Patent Application No. 10 / 883,372, filed July 1, 2004, published January 6, 2005, by Volk et al. As US Patent Application Publication No. 2005 / 6886,153. Has been. The methods described herein include the step (s) of any of the method (s) described in this patent and patent application.

  The method described herein includes a hot spot discovery phase. Hot spot discovery is performed in technology research and development, product design, RET design, reticle design and manufacturing, and product increase. The hot spot discovery phase includes identifying hot spots for reticle design improvement and defect monitoring and classification. The hot spot discovery phase further includes generating a data structure that stores information about the hot spot, such as a hot spot database. In some embodiments, hot spot discovery is performed using multiple sources. For example, hot spot discovery uses the correlation between design space hot spot discovery, wafer space hot spot discovery, reticle space hot spot discovery, test space hot spot discovery, process space hot spot discovery. Executed. In one such example, hot spot discovery is performed by correlating multiple input sources from design, modeling results, inspection results, metrology results, tests and fault analysis (FA) results. Any of the steps described herein are combined to find hot spots.

  In the design space, the results of the design rule check (DRC) are used to create a list of critical points in the design data, thereby identifying hot spots. DRC is typically performed for reticle layout data quality control (QC) prior to mask manufacture (before mask processing). Therefore, DRC may not generate hot spots. Instead, DRC results can be used to identify new critical hot spots that were in the design manual but are not part of the DRC rules or are newly discovered. In addition, computer designed automation (EDA) can be used to find hot spots. Thus, in the hot spot discovery phase, design rules (DRC used as a marginality checker) and / or EDA design tool can be used as a source of hot spots. In addition, hot spots can be discovered using computer aided design technology (TCAD) tools and proxies. The TCAD tool is available from Synopsis, Inc., Mountain View, California. It is commercially available from the company. In addition, or alternatively, DesignScan analysis software, optional pattern search, and design context (eg, functional blocks, design library elements, cells, and patterns redundantly available from KLA-Tenoror, San Jose, Calif.) Whether or not, pattern density, dummy / fill vs active, etc.) can be used as a source of hot spots. In another example, grouping based on defect design data (with or without Pareto analysis) can be used to find and group hot spots, which are described herein. It is executed as it is.

  In additional examples, in the design space, the hot spot discovery phase can be accomplished by aligning or overlaying a scanning electron microscope (SEM) image of design data printed on the wafer with the design data (as used herein). Performed as described), identifies the actual defect location in the design data space, performs an arbitrary pattern search based on the design data close to the location of the defect in the design data space, and Possible hot spots can be identified. A repeater analysis performed on the original inspection results for the wafer can then be used to identify systematic defects and their design groups in the design data, as further described herein. Executed. One advantage of this approach is that if the target defect is located substantially accurately in the design data space, the pattern search window used for any pattern search and / or systematic defect identification is adjusted for each defect. can do.

  Design to increase signal-to-noise ratio (S / N) for repeater analysis, systematic (eg process limit) defect zone / space signature analysis, systematic defect time signature analysis, and reticle / die space discovery in wafer space One of the stacked die (or reticle) results with overlay, and the yield (or critical probability (KP)) that correlates to the defect space as a defect attribute to further prioritize systematic defects or groups of systematic defects. Alternatively, a plurality can be used to find hot spots, each performed as further described herein.

  In reticle / die space, repeater analysis, defect density mapping, design pattern-based grouping analysis, filtering by design context (eg, functional block) for S / N ratio improvement, to find cold spots in the design One or more of the unidentified defect identifications from the other reticle inspections can be used to find hot spots, each performed as further described herein.

  In the test space, one or more of memory bit error to design mapping and logical bitmap density to design mapping can be used to find hot spots, both of which Can be combined with repeater analysis (performed in wafer space) or grouping of design data base (performed in reticle / die space) to identify defects of interest (or cold spots in the design) . Each of these steps is performed as described further herein.

  In process space, PWQ is used as a source of hot spots (using die-die, standard reference die, or die-database methods) and process design using process experiment design (DOE). By determining windows and critical design features as hot spots (using die-die, standard reference die, or die-database methods), hot spots can be found, respectively, As described in more detail in the book.

  In some embodiments, as shown in step 10 of FIG. 1, the method includes selecting a predetermined alignment site in the design data. Selecting a predetermined alignment site is performed using an inspection system. The predetermined alignment site is selected when setting up the inspection process recipe. A “recipe” is generally defined as a group of instructions that perform a process such as inspection. Setting up the wafer inspection recipe as described herein may be performed automatically, semi-automatically (eg, with user assistance), or manually.

  In one example, information about inspection system parameters such as wafer swath split information, inspection system model number, optical mode (s) used for inspection, pixel size, etc. during the setup of the inspection process performed by the inspection system Is used to select a predetermined alignment site in addition to the design data. The predetermined alignment site is further selected based on one or more attributes of the wafer being inspected. Data and / or images (or indexes that refer to this data) for a given alignment site are stored in a recipe for the inspection process. For example, information about a given alignment site for a layer on the wafer is stored as alignment data in an inspection process recipe for the layer on the wafer, and the alignment data is used by the inspection system to inspect the wafer for this particular device and layer. Used every time.

  Some embodiments are described herein as including "wafer scanning" or "scanning the wafer" to capture data and / or images for the wafer, but are known in the art. It should be understood that such data and / or images can be captured using appropriate techniques and / or systems that are known. For example, data and / or images for a wafer may be captured by the inspection system described herein or other inspection system configured to perform field-by-field image collection. Thus, instead of scanning across the wafer, the inspection system can capture data and / or images in a stepping manner. In other examples, data and / or images for a wafer can be captured by the inspection system described herein, or other inspection system configured to perform point-by-point inspection, This can generally be referred to as automated process inspection (API).

  Several methods can be used to select a given alignment site. In one embodiment, the method includes capturing design data corresponding to a predetermined alignment site. Data or images for a given alignment site used in the methods described herein are rendered GDS clips (the term “clip” as used herein is a relatively small design layout). Means an image generated by an inspection system rendered and aligned to a GDS clip. Simulating (or “rendering”) design data corresponding to a given alignment site can be used to generate an image that illustrates how the design data is printed on a wafer. The method further performs cross-correlation between the design data or GDS clip and the simulated ("rendered") image and determines the location of the simulated image in the design data space (i.e., the design data space). Recording (with the coordinates inside). Simulating an image illustrating how design data corresponding to a given alignment site is printed on a wafer as described above is commercially available from suitable methods, algorithms, or KLA-Tencor. It is implemented using software known in the art such as PROLITH.

  In addition, a simulated image is generated as described above that illustrates how a given alignment site is printed on the wafer after one or more processes have been performed on the wafer. . For example, the one or more processes include lithography, a combination of lithography and etching, different lithography processes, and the like. Thus, data for a given alignment site used in the methods described herein is selected or generated based on one or more processes performed on the wafer prior to inspection. Contains one or more simulated images. By using different data for a given alignment site for alignment of inspection data captured after different processes are performed on the wafer, the accuracy of the method described herein can be increased.

  Selecting a predetermined alignment site includes pre-processing design data (eg, GDS data) to select a predetermined alignment site that is compatible with the inspection process or system. For example, in some cases, a rendered GDS clip is less susceptible to changes caused by the wafer processing process (eg, color changes), so data for a given alignment site is described in the manner described herein. Convenient to use as However, an image of a predetermined alignment site captured by an inspection system aligned to a rendered GDS clip “offline” may be convenient to use with inspection data generated at a later stage of device processing. This is because these images may be more similar to the image of the alignment site on the wafer generated by the inspection system compared to the rendered GDS clip, which makes it more accurate. Alignment can be obtained. Thus, in some embodiments, the alignment data used in the methods described herein is a GDS that ensures that a suitable data match is found for the GDS clip and the alignment site on the wafer when the inspection is performed. Includes both images aligned to the clip. Separately, determine one or more attributes of a given alignment site in the design data, such as the center of gravity of the given alignment site, determine the corresponding center of gravity of the image of the alignment site captured by the inspection system, and It can be used to align inspection pixel data with design data.

  The number of predetermined alignment sites selected for each die varies greatly. For example, a relatively sparse collection of predetermined alignment sites is selected. In addition, a predetermined alignment site is selected on a single die with a predetermined frequency. Since the predetermined alignment site is contained within the die itself, the predetermined alignment site is selected to include device features within the die and / or features located within the device region of the die. . Thus, the predetermined alignment site is selected to include existing features of the design data. Such a predetermined selection site is beneficial. This is because it is not necessary to modify the design data to include alignment features, and alignment features do not need to increase the size of the die.

  The method further includes selecting a predetermined alignment site in the design data that is uniquely identifiable (within misalignment tolerances) in the image or data captured by the inspection system. For example, a predetermined alignment site can be selected to include alignment features (ie, targets) that are unique within a predetermined search range uncertainty. Thus, given a specific positional uncertainty in the alignment site placement on the wafer in the image or data, a correlation is performed on the alignment data and the image or data to produce a relatively strong match between the two alignment sites. It can be clearly identified.

  In one embodiment, the predetermined alignment site includes at least one alignment feature having one or more attributes that are unique in the x and y directions. One embodiment of one such predetermined alignment site is shown in FIG. As shown in FIG. 2, the predetermined alignment site 32 includes alignment features 34. The alignment feature 34 has one or more attributes that are unique in the x and y directions. For example, the corners of the alignment feature can make the alignment feature unique in the x and y directions adjacent to the alignment feature with respect to other features in the die. A given alignment site may further include a plurality of such alignment features configured in a similar or different manner. Thus, one or more alignment features can be unique in both the x and y directions.

  In an alternative embodiment, the predetermined alignment site includes at least two alignment features. The first of the two alignment features has one or more attributes that are unique in the x direction. The second of the two alignment features has one or more attributes that are unique in the y direction. One embodiment of one such predetermined alignment site is shown in FIG. As shown in FIG. 2, the predetermined alignment site 32 includes alignment features 38. The alignment feature 38 has one or more attributes that are unique in the x direction but do not provide information about the alignment in the y direction. For example, the vertical edge of the alignment feature 38 can make the alignment feature unique in the x direction adjacent to the alignment feature with respect to other features on the die. A given alignment site includes a plurality of such features.

  The predetermined alignment site 36 includes an alignment feature 40. The alignment feature 40 has one or more attributes that are unique in the y direction but do not provide information about the alignment in the x direction. For example, the horizontal edge of the alignment feature 40 makes this alignment feature unique in the y direction, close to the alignment feature with respect to other features on the die. A given alignment site includes a plurality of such features. Furthermore, a given alignment site includes more than two attributes that are unique in the x and / or y direction. In this way, the combination determines the absolute (x, y) offset between the “live” image or data (eg, the image or data captured by the inspection system during inspection) and the data for a given alignment site. The predetermined alignment site can be selected to include a set of alignment features, such as features 38, 40, that provide sufficient x and y alignment information.

  The selection of the predetermined alignment site is performed manually, automatically, or some combination of manual and automatic (ie, semi-automatic or user assistance). Regardless of whether it is performed manually, automatically, or both, a given alignment site selection can include design data, wafer optical or electron beam images, or both. Executed using. For user-assisted selection of a given alignment site, the user examines the computer-aided design (CAD) layout, the live or stored light or electron beam image of the wafer, or both to determine the uniqueness criteria described above. One or more predetermined alignment sites to satisfy can be determined.

  In automatic or semi-automatic selection of a predetermined alignment site, the method scans a row of dies on the wafer using an inspection system and performs each frame of the die (eg, executes an algorithm). Processing) and identifying unique alignment sites. The term “frame” is generally defined herein as inspection data or data or image for a portion of a die within a swath of an image that is captured when scanning a wafer. Processing the frame determines the x and y gradients of the features in the frame and determines one or more features that have a relatively strong gradient in the x and / or y direction to use at a given alignment site. Selecting. The method further performs a cross-correlation of the frame and the patch image containing such features to determine if only one relatively strong peak (s) of gradient is within a predetermined search range. Including determining. In this manner, unique alignment features within the pattern search window are identified and selected for a given alignment site. The method further includes accessing the design data, rendering one or more relatively small regions of the design data as one or more images, and identifying the preferred alignment site. Performing. The method further includes displaying one or more potential alignment sites identified by the method (eg, a light or electron beam and CAD image pair for the potential alignment sites) and allowing the user to Allowing selection of one or more suitable alignment sites distributed over the die at distance intervals.

  In other embodiments, the imaging mode of the inspection system or other image acquisition system used to select the predetermined alignment site is one or more imaging of the inspection system used to capture inspection data.・ Different from mode. Thus, the method includes using different imaging modes for alignment site selection and wafer inspection. The alignment site selection step is also performed based on the various imaging modes used to inspect the wafer. For example, the inspection system may include bright field (BF) mode, dark field (DF) mode, Edge Contrast (trademark of KLA-Tencor) mode, various aperture modes, and / or electron beam imaging modes, etc. Configured to use multiple optical imaging modes for inspection. Edge contrast (EC) inspection is typically performed using a circularly symmetric illumination aperture with a complementary imaging aperture. The best imaging mode for inspecting a particular layer on the wafer is the imaging mode that maximizes the defect S / N ratio, and the best imaging mode depends on the type of layer. In addition, the inspection system is configured to inspect the wafer using multiple imaging modes simultaneously or sequentially. Since alignment site image or data acquisition performed during wafer inspection uses the best imaging mode for wafer inspection, the alignment site selection preferably uses that mode to determine the proper alignment site and alignment features. Select.

  However, in order to accurately determine the position of the selected alignment site selected in the design data space, an optical patch image of the predetermined alignment site (on the wafer) is derived from the design data or GDSII clip as described above. Can be aligned to a simulated image. Acquiring a simulated image with a quality suitable for aligning the simulated image with the optical image may be difficult for any imaging mode. However, for a particular imaging mode (eg, BF mode), the best match between the simulated image and the optical image can be obtained. Thus, the method includes selecting a suitable predetermined alignment site by scanning the wafer using the best imaging mode for inspection. The method further revisits a selected predetermined alignment site on the wafer using an inspection system and uses an optical patch mode using a mode that results in the best match with the simulated image or GDSII clip. Including capturing images.

  The image obtained using the best mode that matches the simulated image or GDSII clip is aligned to the simulated image or GDSII clip of the corresponding alignment site in the design data. Use the (x, y) position of the selected alignment site in the design data space determined by aligning the captured image using the best mode that matches the simulated image or GDSII clip These x and y positions can then be associated with a patch image captured using the best mode for inspection. If there is some fixed offset between images collected for the same site in different modes (inspection mode and simulated image or best mode matching GDSII clip), use a suitable calibration target. This offset is measured and / or corrected at the start (or before) of the inspection.

  In one such embodiment, the method performs off-line alignment of CAD-simulated images or GDSII clips to optical or electron beam images of a given alignment site to determine the mapping (ie, design Determining the position of individual pixels of the optical or electron beam image in data space). For example, after selecting predetermined alignment sites and capturing images of those sites on the wafer using an imaging mode that can provide the best image that matches the simulated image, the predetermined alignment The design data corresponding to the site is captured (in a form such as a polygon representation) and then rendered as a simulated image with the appropriate pixel size using an appropriate transformation function. The optical (or electron beam) image and the simulated image are then aligned with each other using appropriate methods and / or algorithms known in the art. Aligning the optical (or electron beam) image and the simulated image with each other may cause the previous layer geometry to be excluded from the optical image or otherwise known in order to make a sufficiently accurate alignment. This is performed using other information about design data (eg, in a design database) such as previous layer geometry that can be a source of noise in the optical image.

  The result of the process of setting up the inspection recipe is that the alignment position, the respective position of the alignment area in the design data space (eg, x and y coordinates), and a substantially accurate alignment during subsequent wafer inspections. It includes one or more optical or electron beam patch images representing additional information used by the inspection system to perform.

  As shown in step 12 of FIG. 1, the method includes aligning data captured by an inspection system for an alignment site on the wafer with data for a predetermined alignment site. The data for the predetermined alignment site includes any of the data described above. For example, data for a given alignment site includes design data stored in a data structure such as a GDSII file or other standard machine readable file format. In other embodiments, the data for a predetermined alignment site includes one or more simulated images showing how the predetermined alignment site is printed on the wafer. The one or more simulated images can be used to determine the position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site in the design data space according to the further description herein. Maps to the design data space as further described in the specification.

  In additional embodiments, the data for the predetermined alignment site includes one or more attributes of the predetermined alignment site, the data for the alignment site on the wafer includes one or more attributes of the alignment site, and is aligned. The step of causing includes aligning one or more attributes of the predetermined alignment site to one or more attributes of the alignment site. The predetermined alignment site and one or more attributes of the alignment site on the wafer used in this embodiment include the attribute (s) described herein. For example, in one embodiment, the one or more attributes of the predetermined alignment site include a centroid of the predetermined alignment site, and the one or more attributes of the alignment site on the wafer include the centroid of the alignment site. The center of gravity of a given alignment site and the alignment site on the wafer is the center of gravity for one or more alignment features at those sites. Thus, the method includes aligning the alignment site on the wafer to the predetermined alignment site by matching the center of gravity of the predetermined alignment site and the alignment site on the wafer. At that time, the data for the predetermined alignment part is a certain one characteristic of the predetermined alignment part such as the center of gravity aligned with the corresponding characteristic (or characteristics) of the data for the alignment part on the wafer. (Or multiple characteristics). One or more attributes, such as a predetermined alignment site and the center of gravity of the alignment site on the wafer, are determined as described herein or by any suitable method known in the art.

  In additional embodiments, data for a given alignment site includes data captured by an inspection system and aligned to design data stored in a data structure such as a GDSII file. Data captured by the inspection system for a given alignment site is aligned with design data as described herein. In some embodiments, the data for a given alignment site includes at least a portion of a standard reference die image aligned with design coordinates in the design data space. The standard reference die image can include any of the standard reference die images described herein, and the standard reference die image is aligned with the design coordinates as described herein. Aligned. For example, a standard reference die image can be mapped to the design space and then used to align.

  Aligning the data for the alignment site to the data for the predetermined alignment site is performed using any suitable alignment method (s) and / or alignment algorithm (s) known in the art.

  In one embodiment, step 12 is performed during wafer inspection. In addition, this step is performed each time a wafer is inspected using an inspection process recipe. For example, the inspection process includes an initialization phase that is performed at the start of inspection of a lot of wafers and at the start of inspection of each wafer in the lot. During the initialization phase, the (x, y, or two-dimensional) mapping of a given alignment site and the given alignment site in the design data space is accessed from the recipe setup results and stored alignment patch images and inspections Can be downloaded into an image computer processing node that is used to perform alignment with live patch images captured by the inspection system for the wafer being processed. The image computer and processing node may have any suitable configuration known in the art.

  In the inspection process, the method includes scanning the wafer using an inspection system and capturing a swath of inspection data. Each swath is captured as a stream of pixels of some height H (y direction) as the inspection system scans across the die (in the x direction) in rows or columns on the wafer. Each processing node in the image computer processes some part of the swath. For example, the swath is divided into a plurality of portions, that is, “pages”, and each swath portion is directed to a different processing node. The processing node is configured to perform defect detection using pixels in the swath portion received by the processing node. The method and image computer were captured from the alignment of the alignment sites on the wafer (e.g., each in a die) and from the image computer storage media (e.g., downloaded during the initialization phase). Information about the patch image of a predetermined alignment site can be used to align the predetermined alignment site with live stream data of the alignment site on the wafer.

  In some embodiments, a context map (eg, stored in a data structure such as a database) is accessed and downloaded to the processing node. This context data is stored in a suitable format known in the art. This contextual data can be stored and / or used in a compact polygon representation rather than an image format. However, the context map may be rendered into an image to be used for defect detection. This rendering is performed once at initialization or each time the context map is used during inspection. The advantage of the former approach is that rendering the context map at initialization reduces the data processing cycles performed in the inspection process. However, a disadvantage of this approach is that it stores a rendered image of the entire context map and may require a relatively large amount of memory.

  As shown in step 14 of FIG. 1, the method includes determining the position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site in the design data space. For example, the (x, y) position of a predetermined alignment part with respect to design data coordinates (that is, in the design data space) is determined, and the data for the predetermined alignment part is aligned with the data for this alignment part. Therefore, the absolute arrangement of the live pixel coordinates of the alignment site on the wafer can be determined in the design data space. In other embodiments, determining the position of the alignment site on the wafer in the design data space aligns the raw data stream (eg, live image) with data (eg, a reference image) for a given alignment site. Including that. Determining the position of the alignment site on the wafer in the design data space is performed before inspecting the wafer or after acquiring inspection data for the wafer.

  As shown in step 16 of FIG. 1, the method determines the position of inspection data captured for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. Including doing. Inspection data whose position in the design data space is determined includes data (eg, image data) captured for the wafer by the inspection system during inspection. In addition, the location of the inspection data can be determined for some or all of the data captured by the inspection system when inspecting the wafer. For example, the position of the inspection data can be determined only for the inspection data acquired for the inspection target area on the wafer.

  In one embodiment, the method includes aligning the position of the raw data stream corresponding to the alignment site on the wafer with the reference image of the predetermined alignment site as described above, and then combining the inspection data stream and the design data. Measuring the coordinate offset between them to within the sub-pixel accuracy. In addition, the coordinate error between the live inspection data and the design data allows the alignment site on the wafer to be aligned with the predetermined alignment site substantially accurately for all points on the die. Is corrected by shifting the raw test data image with respect to the reference image. One significant advantage of the methods and systems described herein is that the location of inspection data in the design data space can be determined with sub-pixel accuracy. Thus, target and non-target regions on the wafer can be determined as described further herein with a relatively high accuracy of 100 nm or less accuracy.

  In different embodiments, the data for a given alignment site can be used to determine the two-dimensional mapping transform used to map the live image pixel space to the design data space. For example, as described above, this method can be performed by correlating a predetermined alignment site patch image (captured during setup of the inspection process) downloaded for a predetermined search range with live image data. Determining an offset between the image and the live image. Since the (x, y) position of a given alignment site in the design data space is determined at setup time, this method further determines the correspondence between the live image pixel position and the design data coordinates. Can also be included. The method then includes determining a two-dimensional function that maps the live pixel coordinates to the design data space using the correspondence between the live image pixel locations and the design data coordinates.

  In one such example, using a suitable polynomial fit of the grid of alignment sites to absolute coordinates in the design data space, the pixels in the inspection data (eg, live pixel stream) are matched to the corresponding positions in the design data space. Determine the mapping functions that can be used to map to. Similarly, the pixels in the inspection data are mapped to corresponding positions in the context space as will be described later. A plurality of other corrections can be used to provide a substantially accurate mapping. For example, correction is performed based on data provided by the inspection system, such as the pixel size in the x-direction that can be captured by the runtime alignment (RTA) subsystem of the inspection system. This mapping is used for the die-to-die inspection mode. The live pixel stream mapping as described above is performed in real time during wafer inspection or after acquisition of inspection data for the wafer. By this method, determining the position of inspection data in the design data space is performed at the time of inspection of a wafer. Alternatively, determining the position of inspection data in the design data space is performed after inspection of the wafer.

  The location of the inspection data in the design data space is stored and used in the manner described herein.

  In one embodiment, the method includes detecting defects on the wafer using inspection data and a standard reference die for standard reference die based inspection. Thus, the method embodiments described herein include performing a standard reference die-based inspection. In some such embodiments, the method applies the mapping of the standard reference die image in the design data space to the live image captured by the inspection system for the wafer for standard reference die-die inspection mode. Including. The term “standard reference die” generally refers to a reference die on the wafer that has been inspected but does not meet the normal adjacency constraints for the “test” die required for die-to-die inspection. Some commercial inspection systems are configured to use a mode similar to the standard reference die-to-die inspection mode. One implementation of the standard reference die-to-die inspection mode includes comparing the die to any die in the die row. In other implementations, the standard reference die image is a stored image. Thus, the stored standard reference die-die inspection mode is very similar to the standard reference die-die inspection mode, except that the constraint of using a reference die on the wafer is removed. One advantage of this inspection mode is that the stored standard reference die image can be modified to make the standard reference die image “substantially defect free”. In addition, this inspection mode uses standard reference die images from different wafers, which allows for the simplest implementation of iPWQ applications, which is further described herein. .

  In one embodiment, used in the standard reference die-to-die inspection mode, the captured live image for the die being inspected is obtained from a known good die on another wafer (standard reference die). Aligned and compared to stored stored die images. Such alignment and comparison is performed as described herein. In this case, mapping the standard reference die pixel to the design data coordinate space is performed completely offline. For example, alignment sites in a standard reference die are mapped in the design data space as described above, and the mapped standard reference die pixels are stored off-line during inspection and supplied to the inspection system. Thus, for the standard reference die-to-die inspection mode, determining the position of live inspection data in the design data coordinate space is the stored standard reference die that is itself mapped to the design space. • Performed by aligning images or data.

  In other embodiments, for standard reference die-to-die inspection, a known good die on the reference wafer is scanned with a selected pixel size and imaging mode, and a known good die image. The whole is stored in a suitable storage medium (eg, a disk). During wafer inspection, the appropriate standard reference die image swath is downloaded into the inspection system image computer and each time the die is scanned, the frame of the target die (ie, the die being inspected) , Aligned with the corresponding standard reference die frame. Misalignment between frames is corrected using subpixel interpolation. The standard reference die image is then compared to the image of the wafer, thereby detecting defects on the wafer (eg, detecting defective pixels). In this way, the same image can be used to align inspection data to design data space coordinates or for defect detection.

  In different embodiments, the method includes aligning data for alignment sites on the wafer in the inspection data stream to rendered GDS clips for a given alignment site to correct errors in real time. For example, the method includes applying a rendered GDSII clip mapping in the design data space to data for alignment sites on the wafer for die-to-die inspection mode. This method correlates a downloaded alignment site patch image (selected during the setup of the inspection process) for a given search range with live image data and determines an offset between the two images. Including. In another example, aligning data for an alignment site on the wafer in the inspection data stream to data for a given alignment site is by aligning the centroid or other attributes of one or more features in the alignment site. This is done as described further herein.

  In one embodiment, data for each scanned die frame is aligned with data for subsequent die frames in the swath for defect detection in die-to-die inspection mode. In this case, the mapping between a given alignment site and the alignment site on the wafer is not performed online, because the position of the data for each die in the inspection data stream depends on the mechanical errors and other errors of the inspection system. This is because it depends on the source. Thus, in this case, the method includes identifying the alignment site of each die (eg, using an image computer) upon acquisition of inspection data.

  In other embodiments, defect detection is performed in a wafer-to-wafer inspection mode. In one such embodiment, data for an alignment site on one wafer is aligned with data for a given alignment site, and data for an alignment site on this wafer is aligned with data for an alignment site on another wafer. Is done. Alternatively, the data for the alignment sites on both wafers is aligned with the data for a given alignment site that includes any of the data described herein. In this way, after the data for the alignment site on the wafer is aligned with the data for the predetermined alignment site, the inspection data of these wafers are actually aligned and overlaid or compared for defect detection. In some embodiments, the wafer-to-wafer inspection mode includes using a reference die that exists outside the wafer being inspected (ie, off-wafer reference). The implementation of this method is not straightforward, but it is currently used so that inspection systems can achieve die-to-die level overlay tolerances (eg, 0.1 pixel) to obtain adequate sensitivity results. Because it includes the separation of the concept of run-time feedback.

  In one such embodiment, the method includes an RTA of the wafer being inspected and an off-wafer reference image. RTA with off-wafer images is a scan inspection technology that goes from wafer “self-referencing” approaches such as die-to-die comparison and cell-cell comparison to wafer-to-wafer inspection to detect defects on patterned wafers. An image alignment approach used to allow expansion. For example, RTA performs electromechanical alignment of a captured live image with an already captured image prior to binarizing the signal generated by one or more detectors of the inspection system. Performing sub-pixel accurate positioning. An example showing how RTA is performed in the embodiments described herein is described in US Pat. No. 7 of Hwang et al., Which is incorporated by reference as if fully set forth herein. No. 061,625.

  One currently available inspection approach, including a comparison of wafer images and off-wafer images, is the die-database inspection mode used by the Nanogeometry Laboratory (NGR) in Japan. This die-database inspection approach involves a complex series of “step and repeat” image acquisition and stitching, followed by multiple steps of edge-based image processing, process simulation, and detection algorithms. Includes processing. However, this method cannot be used to directly compare images from different wafers. In particular, the die-database inspection mode compares the wafer image with a simulated reference derived from the design layout database. The simulation step of this approach must be carefully calibrated to the specific manufacturing process used to produce the test wafer. Calibration is an expensive and time consuming process. Calibration is a particularly complex task for an integrated process flow with multiple steps. In addition, the “step-and-repeat” image acquisition inspection process has practical limitations on stage inertia, stage vibration, stationary image acquisition, image stitching, etc., so a scan-based inspection process Is typically slower.

  An alternative die-database inspection mode is a logical extension of the inspection mode using the “off-wafer” reference die described above. In this case, the “database” is a rendered image generated from design data and process simulation as described above. Thus, database-based inspections can include “standard reference dies” and design data generated from captured images (possibly with statistical-based enhancements performed as described herein) and Since wafer-to-wafer inspection can be performed using “standard reference dies” strictly generated from process modeling, it is considered a logical extension of the “off-wafer” reference inspection mode. Using a standard reference die that is strictly generated from design data and process modeling is the most complex wafer inspection mode to implement. Many attempts have been made to implement this inspection mode, but the current performance of the attempted implementation is due to the computational complexity (modeling and detection), image collection speed, and image quality issues of this application. Not enough. However, the method described herein can be used in implementation because it can use a common absolute reference (eg, design data) to align inspection data for the wafer under test and the off-wafer reference. High practicality.

  Thus, the methods described herein are used to enable wafer-to-wafer comparisons, which can be a potentially extremely useful application. One motivation for defect inspection using wafer-to-wafer comparison is to discover "systematic defect mechanisms" that can result from specific circuit layout interactions and wafer manufacturing process stacking tolerances. This discovery process involves comparing wafers that have been printed with the same device design but processed differently. The most deterministic approach is to transform process parameters in univariate or multivariate experiments (eg, using a systematic DOE approach). In one embodiment, a wafer and additional wafers (eg, two or more wafers) are used using wafer level process parameter modulation, as described above, or performed in other suitable manners. It is processed. These process parameters can be modified to bring the measurable physical and / or electrical attributes of the resulting wafer closer to acceptable limits. In addition, the method includes detecting defects on the wafer and the additional wafer by comparing inspection data for the wafer and the die on the additional wafer with a common standard reference die. Thus, detecting defects on the wafer is performed as described further herein. In one such embodiment, the method includes determining whether a structural difference between the wafers occurs as measured by “defect” detection. Such an approach is called integrated PWQ (iPWQ). Thus, using the methods described herein enables implementation of iPWQ (eg, using a standard reference die approach to iPWQ). At that time, the PWQ method is expanded to include wafer level process parameter variations and to include a comparison of dies on different wafers with a common standard reference die intended to implement the iPWQ method. The

  In contrast, the discovery of “systematic defect mechanisms” due to lithography is incorporated by reference as if set forth herein in its entirety, US Pat. No. 6,902,855 to Peterson et al. And the PWQ product commercially available from KLA-Tencor. PWQ uses focus and exposure as variables to determine design-lithography interactions, and utilizes a unique ability for lithography tools to transform lithographic exposure process parameters at the reticle shot level. This application is often used for OPC verification. However, PWQ is limited to direct comparison of dies on wafers printed with modulated focus and / or exposure parameters. The effects of other process variables associated with process steps such as etching, deposition, heat treatment, chemical mechanical polishing (CMP), etc. are not directly evaluated by PWQ because these variables are only deformed at the wafer level. However, systematic defect mechanisms associated with or caused by these process variables are discovered using the methods described herein. In particular, the method described herein is used to examine non-lithographic process modulation in PWQ type applications by wafer-to-wafer comparison.

  Scan-based defect detection systems can perform die-to-die image subtraction with “sub-pixel” image alignment to reduce differential image registration noise and thereby increase sensitivity to defects Become. Defects are identified by detecting pixels in the difference image that exceed one or more thresholds. The scan-based image acquisition process includes a feedback mechanism often referred to as RTA. This mechanism accurately aligns the captured image with the image (s) captured from the same wafer slightly before the current image. Depending on the configuration of the inspection system, the feedback mechanism includes a combination of an optomechanical approach, an electromechanical approach, and an electronic / algorithmic approach.

  In one embodiment, the method described herein includes an RTA that uses the stored image as a reference rather than the captured image for the wafer under test. The stored image may be a “standard reference wafer” or an image of a reference wafer. Each die on the wafer under test can be compared to a corresponding die on a standard reference wafer. Although embodiments are described herein as including results of comparing two wafers or images of wafers, those embodiments compare data captured by inspection of two or more wafers. It will be understood that this includes.

  FIG. 4 illustrates various embodiments of computer-implemented methods for performing wafer-to-wafer comparisons. Note that the steps shown in FIG. 4 are not essential to the implementation of the method. One or more steps may be omitted from or added to the method illustrated in FIG. 4, or the method may be implemented as such within the scope of this embodiment.

  As shown in step 220, the method includes a wafer-to-wafer comparison. In one embodiment, the wafer-to-wafer comparison includes comparing a reference wafer image and a test wafer image, as shown in step 222. For example, the reference wafer image used in the methods described herein can be a stored image of the entire reference wafer. The comparison of the reference wafer image and the test wafer image is performed as described herein. Alternatively, as shown in step 224, the wafer-to-wafer comparison includes comparing a standard reference die image with the image of all dies on the wafer (eg, a reference or test wafer).

  In one embodiment, the method detects defects on the wafer using a representation of the wafer noise associated with the standard reference die in a perturbation matrix for inspection data, standard reference die, standard reference die based inspection. including. Thus, the method includes using a relatively compact representation of wafer noise associated with a standard reference die in the form of a perturbation matrix. For example, the image of the reference die on the reference wafer is stored in addition to a perturbation matrix or other suitable data structure that indicates how the die pixels change from die to die on the reference wafer. By storing the image of the reference die in addition to the perturbation matrix instead of the entire reference wafer image, a more compact representation of the reference wafer can be stored. In this way, the perturbation matrix can be included in the representation of the reference wafer to reduce the reference wafer image size to a level that is implemented in a practical and affordable range. The method includes standard reference die-based inspection that includes using perturbation matrix compression of noise signatures.

  Generating a perturbation matrix corresponding to a reference wafer image requires standard reference die-based inspection using a standard reference die obtained from the reference wafer (ie, some kind of self-reference). A single standard reference die image on the reference wafer is used as the RTA reference at run time, which makes the RTA performance sensitive and even the compressed differential data stored for each die on the reference wafer. It is possible to reduce the influence that is considered to be exerted on the reference image that is perturbed. The size of the stored differential data is reduced through the compression algorithm, but also by imposing a limit on the total target area size per die swath. At run time, a perturbation matrix of difference image data is loaded for the entire reference wafer by swath for each corresponding standard reference die swath loaded. The data amount of the perturbation matrix for the entire wafer may be about 1 Gb to about 3 Gb, and the data amount for the standard reference die may be about 1 Gb. In all other methods described herein, including comparison of standard reference dies, a perturbation matrix can be used as described above.

The perturbation matrix is P ₁ (x, y), D _x (1, 2), D _y (1, 2), Diff ₁ , ₂ (x, y) when there are m dice in one row; P ₂ (x, y), D _x (2, 3), D _y (2, 3), Diff ₂ , ₃ (x, y); . . P _m−1 (x, y), D _x (m−1, m), D _y (m−1, m), Diff _{m−1, m} (x, y), where P _i ( x, y) is the pixel value at the i-th die at position (x, y), and D _x (i, i + 1) and D _y (i, i + 1) are the values of die (i) for die (i + 1). Are the offsets in x and y, respectively, and Diff _{i, i + 1} (x, y) is the position x after die (i + 1) is shifted by x and y offset to align with the frame of die (i). , Y is the differential gray level of die (i + 1) with respect to die (i). However, within the interpolation error limit, P ₂ (x, y) is P ₁ (x, y), D _x (1, 2), D _y (1, 2), Diff ₁ , ₂ (x, y). Reconstructed from In addition, P _i (x, y) is reconstructed for the other dies by applying these steps to each die in turn. Of course, this can lead to large interpolation errors, and the image can become blurred as it goes from die to die.

  However, if a standard reference die is stored and all interpolation is performed on this die, the above transitive error accumulation does not occur. Rather, the error is simply an interpolation error associated with reconstructing the die on the wafer from the standard reference die given the offset and difference images. Thus, as shown in step 226, the method includes storing a differential image of each die with respect to the standard reference die.

  FIG. 5 illustrates one embodiment of a method for performing a wafer-to-wafer comparison using such a difference image as a comparison reference. For example, the reference wafer 250 may include a number of dies [(0,0), (0,1). . . (4,2)], one of which (eg, die (2,2)) is designated as the standard reference die. The reference wafer 252 used for comparison with the test wafer is a differential image [Diff (0,0), Diff (0,1). . . Diff (4,2)] is generated. Test wafer 256 is then compared to reference wafer 252. For example, as shown in FIG. 5, defect detection adds the standard reference die image 254 and the corresponding difference image (Diff (1,3)) and then subtracts the test die (1,3). The test die (1, 3) is then executed by generating a difference 258 between the test die (1, 3) and the reference die (1, 3).

  Therefore, the difference image between the die (test object) and the standard reference die is expressed compactly. A lossy compression algorithm can be used to achieve a high degree of compaction. Information that can be lost in such a compression scheme depends on the scheme itself. For example, as shown in step 228 of FIG. 4, the method includes performing irreversible compression on the non-critical region of the difference image and performing lossless compression on the critical region of the difference image. In this way, an “intelligent” compression scheme can be used for a less critical device region that allows a higher loss of information than a critical region. A similar compression scheme can be used for the reference wafer image. For example, as shown in step 230, the method performs irreversible compression on non-critical areas of the wafer image and reversible compression on critical areas of the wafer image. Including.

  Alternatively, the method includes storing per-pixel difference statistics for the standard reference die, as shown in step 232. For example, as shown in step 234, the method includes storing per die statistics for each context type. Each die is divided into one or more context types, which are performed as described further herein. In one such example, the method includes recording statistics for the difference of each (x, y) position in the standard reference die for different groups of dies. As shown in step 236, the context may be a die area. Alternatively, as shown in step 238, the context may be a background type. Difference statistics for each pixel can be determined in a suitable manner.

  In another example, the wafer is divided into N radial sectors and / or M annular rings. For example, as shown in FIG. 6, the wafer 260 is divided into annular rings 1, 2, and 3. Although wafer 260 is shown as being divided into three annular rings, it will be understood that the wafer can be divided into any suitable number of annular rings. In addition or alternatively, as shown in FIG. 7, wafer 260 is divided into wafer sectors A, E, C, D, E, F, G, and H. Although wafer 260 is shown as being divided into eight sectors, it will be understood that the wafer is divided into any suitable number of sectors. The method includes storing per-pixel wafer sectors and / or per-annular statistics as shown in step 240 of FIG. In such an example, for each of (N + M) partitions, the average and standard deviation of the differences for the standard reference die image at (x, y) position can be recorded. To use an 8-bit average and 8-bit standard deviation, store 1 byte of difference for each die on the wafer, versus 2 * (N + M) bytes at each (x, y) location. Must be stored. Thus, if there are 100 dies on the wafer, to use 8 sectors and 8 annular rings, (x, y) positions for 100 bytes per (x, y) position Each requires 32 bytes. In other examples, the method includes storing statistics for each wafer sector and / or annular ring as described above for each context type, as shown in step 242. The context type may be based on die area, as shown in step 244. Alternatively, the context type may be based on the background type, as shown in step 246. The statistics for each context type, and the context type are determined as described herein.

  FIG. 8 shows how such a scheme can be performed when statistics are stored for each (x, y) location on the standard reference die for each annular ring base. In particular, FIG. 8 illustrates one embodiment of a method for performing a wafer-to-wafer comparison using a differential statistic with an annular ring as a reference. For example, as shown in FIG. 8, the reference wafer 262 includes a number of dies [(0,0), (0,1). . . (4,2)], one of which (eg, die (2,2)) is designated as the standard reference die. The reference wafer 264 used for comparison with the test wafer determines the average difference at pixel (x, y) and the standard deviation of the difference at pixel (x, y) with respect to the standard reference die image 266 for each annular ring. Is generated. Test wafer 268 (shown in FIG. 8 with an annular ring overlaid on the test wafer) can be compared to reference wafer 264. For example, test die (1,3) is subtracted from standard reference die image 266, thereby producing a difference 270 between test die (1,3) and standard reference die image 266. As further shown in FIG. 8, the test die (1, 3) is disposed between the annular ring 1 and the annular ring 2. Accordingly, in step 272, the difference image 270 is compared to a statistic 274 (eg, average difference ± k * standard deviation of difference) at each (x, y) position of the test die for each annular ring base. In other words, the difference 270 for the portion of the test die located in the annular ring 1 is compared with the statistics of the annular ring 1 and the difference 270 for the portion of the test die located in the annular ring 2. Is compared to the statistics of the annular ring 2.

  Standard reference die storage can be compacted by storing standard reference die data based on statistics (eg, dividing a die into multiple frames and dividing the frames into different geometries (contexts separated according to bin ranges). ) And save the average / standard deviation of die-to-die differences for each frame / context). For example, as shown in step 248 of FIG. 4, the method includes storing per-die, per-frame, per-context difference statistics for a standard reference die. For example, as shown in FIG. 9, the die [(0,0), (0,1),. . . (M, N)] 276 is formed on the wafer 278. In addition, the die 276 is divided into a plurality of frames 280 as shown in FIG. The die is divided into a plurality of frames 280, and the pixels of each frame are divided based on context (not shown in FIG. 10). Difference statistics for each different context of each frame in each die are determined as described herein.

  FIG. 11 illustrates one embodiment of a method for performing a wafer-to-wafer comparison using context-sorted difference frame statistics. As shown in FIG. 11, the reference wafer 282 includes a number of dies [(0,0), (0,1). . . (4,2)], one of which (eg, die (2,2)) is designated as the standard reference die. The reference 284 used to compare with the test wafer 286 includes a die 276 and a standard reference die image 288 divided into a plurality of frames 280. The frame 280 is configured as described above. Reference 284 is generated by determining statistics 290 such as the average and standard deviation of the differences for each context within each frame and each frame for each die. In order to detect defects on the test wafer 286, the test wafer is compared to the reference 284. For example, to detect defects in the test die (1, 3), the test die (1, 3) is subtracted from the standard reference die image 288 to produce a difference 292 between the test die and the standard reference die image. To do. In step 294, the difference 292 is compared with a statistic 290 (e.g., mean and standard deviation of the difference for each frame and context) for each frame and context, on a per die basis (1, 3) of the reference wafer 282. To do.

  If it is not known that the “standard reference die” is free of defects, the “polishing” method is used to arbitrate once (defect detection can be performed by making a single comparison with a reference die that is completely free of defects). Can only run. In addition, “polishing” is performed such that the standard reference wafer reflects image variations expected on the wafer due to “inherent” or expected process variations. Thus, a standard reference die “polishing” can be performed on all dies on the reference wafer to produce a “defect-free” reference wafer.

  Table 1 below shows a maximum die size of 40 mm × 40 mm, a minimum inspection pixel size of 90 nm, a maximum size die number on the wafer of 44, and a number of pixels in the maximum size die of 1.975E ÷ 11. Frame size of 512 x 512 pixels, maximum size die per frame of 7.535E + 05, average difference and standard deviation difference of 2 bytes, per maximum size die swath Approximate reference data for the various wafer-to-wafer comparisons described above, assuming 0.91 Gpixel, 217 swaths per maximum size die, and 2048 swath height. Shows the size. The standard reference die includes 197 Gpixel or 0.91 Gpixel per swath, assuming a 2K height sensor. In addition, a differential image for each die on the reference wafer or some compressed image thereof must be stored.

  Table 1 clearly shows that the data size for storing the difference image is significantly larger than the data size for storing the frames per die and context-based statistics. However, by saving some of the difference pixels with the largest difference (eg, 0.1%) and the pixels in the critical region, the data size required for the difference image is reduced from 877.8 Gbytes to 8.7 Gbytes. .

  A serpentine scan path can be used to scan the die on the test wafer several times to generate multiple swaths of inspection data. One embodiment of such a serpentine scan is shown in FIG. As shown in FIG. 12, the test wafer 296 includes a die array [(0,0), (0,1). . . (4, 2)]. The test wafer 296 is scanned by a meander scan 298 and a meander scan 300. Although two serpentine scans are shown in FIG. 12, it will be appreciated that the test wafer is scanned using any suitable number of times. Assuming there are 217 swaths per die and performing the same serpentine scan on all die rows, all die are compressed with the standard reference die swath, such as swath 1, then swath 2. You can load the difference. In this case, the size of the memory required to store the test wafer scan reference data is (197 + 8.7) /217=0.95 Gpixel per swath.

  A standard reference die-to-die inspection implementation must be considered when disk input / output (I / O) speed and speed affects throughput. By loading each swath of the “standard reference die” once, disk I / O traffic can be reduced. Such a load can be used (as opposed to the serpentine pattern of adjacent wafer scans) along with a serpentine scan across the wafer with die level stepping from one wafer scan to the next.

  Of course, for all of the inspection modes described herein, one image stored on the disk was used relative to the other image stored on the disk or was just acquired from the wafer in real time. The image can be used to perform the inspection. All of the above data is stored or stored as further described herein, and all the storage or storage steps described herein are performed in any manner described herein. Is done.

  As described above, determining the position of inspection data in the design data space is performed after inspection of the wafer. In one such embodiment, determining the position of the inspection data in the design data space is performed on the portion of the inspection data corresponding to the defect detected on the wafer and corresponds to the defect detected on the wafer. The portion of the inspection data that has not been executed is not executed. In this way, the mapping transformation from pixel or wafer space to design data space is applied only to the arrangement in which the defect is found. In other words, the method includes post-processing mapping from defects detected on the wafer to the design data space. In addition, alignment sites on each die are identified during inspection, but this alignment (eg, alignment error measurement) is performed after defect detection is completed in the post-processing phase. This mapping is then applied to find the location of the defect in the design data space.

  Regardless of when or how to determine the location of inspection data in the design data space, if one or more defects are present on the wafer, the inspection data is Contains data for one or more defects above. Accordingly, the position of one or more defects in the design data space is determined from the position of the inspection data in the design data space. In addition, the location of the one or more defects in the design data space is advantageously determined with substantially the same (eg, subpixel) accuracy as the location of the inspection data in the design data space.

  As described further herein, in some embodiments, inspection data in a swath can be captured by scanning a wafer. In such an embodiment, each swath of test data can be individually aligned in the design data space by aligning the data for the alignment site in each swath with the data for the predetermined alignment site, , Executed as described above.

  In different embodiments, determining the position of the inspection data includes determining the position of the swath of the inspection data in the design data space based on the position of the alignment site in the design data space and the position of the swath in the design data space. Determining the location of the additional swaths of the inspection data in the design data space. In this way, one swath of inspection data can be aligned to the design data space as described above (eg, aligning data for an alignment site on a wafer in a swath of inspection data to data for a predetermined alignment site. The additional swath of inspection data can be aligned with this swath of inspection data.

  For example, as shown in FIG. 13, a swath (eg, swath # N + 1) can be aligned to a previous swath (eg, swath #N) using inter-swath image alignment. In particular, as shown in FIG. 13, swaths # N + 1 and #N partially overlap each other in a region 41 in the wafer space. Thus, both swaths will contain inspection data for features formed in region 41. In doing so, the inspection data for these features is used to align one swath with the other swath. In one such example, FIG. 14 illustrates features 41a and 41b formed in the inter-swath overlap region 41 in a wafer space where inspection data for two successive scans overlap. Features 41a, 41b are used to perform swath-to-swath registration. Features 41a, 41b are further configured as described herein with respect to other alignment features.

  Thus, the first swath for a die row has been rendered from the design database or other predetermined alignment site data described herein for the alignment site (or sites) in that die row. If aligned to the design data space by aligning to the image, the swath after the die row is aligned using the techniques described herein. In particular, by using the position of swath #N with respect to the design data space and the position of the alignment feature within the swath, the position of swath # N + 1 with respect to the design data space can be determined. For example, determining the location of swath # N + 1 stores the alignment feature image captured when performing a swath #N capture scan, and then the alignment feature image is captured when swath # N + 1 is captured. This is done by aligning images of the same feature. By determining the misalignment offset between the two alignment feature images, the absolute position of swath # N + 1 with respect to the design data space is determined.

  During inspection recipe setup, the wafer can be scanned with a relatively large overlap (eg, 50% overlap) between successive swaths to determine suitable alignment sites within the inter-swath overlap region. By using these site positions, the position of each swath with respect to the corresponding previous swath can be determined. Using the position of the first swath with respect to the design data space using the above-described method for aligning a predetermined alignment site with the alignment site on the wafer, and in the overlap region between the first swath and the second swath Using the second swath shift with respect to the first determined portion using the first alignment portion, the absolute position of the second swath with respect to the design data space can be determined. By repeating this procedure for each subsequent swath, the pixels of the entire die can be mapped to the design data space.

  Thus, a preferred alignment site (using the method described above) can be used for each inspection swath (ie, the swath used during inspection where the overlap between swaths is the smallest overlap so that the die can be scanned completely). ) So that there is at least one such site within. The positions of these alignment parts in the design data space are stored in the inspection recipe together with the patch images of the respective alignment parts. At the time of inspection, for each swath, the corresponding alignment site is removed from the recipe and its position is determined in the pixel stream captured by the inspection system. After the alignment site is placed in the pixel stream, the position of the pixel in the inspection swath is determined with sub-pixel accuracy in the design data coordinate space using cross-correlation or other image matching techniques. One advantage of this method is that it performs swath “stitching” that is used to map the pixels for the entire die to the design data coordinate space and finds suitable alignment sites in this space that appear in each inspection swath. Therefore, the setup swath (used only for recipe setup) can be captured with a relatively large overlap, while the inspection swath can be captured with a relatively small overlap (and thus speed is increased). It should be noted that the swath stitching technique is applied to different scan patterns, for example, to capture field by field using an area sensor. The fields are stitched together in a manner similar to that described above.

  Another advantage of the above embodiment over aligning each swath with respect to the design data space is that the data for the alignment site is rendered from the design data, but this approach reduces the number of alignment sites. There is to be finished. In addition, the design data is complicated by the complexity of the model used to predict how a given feature will be printed on the wafer, especially when multiple layers are formed on the wafer. Rendering the data for the alignment site faithfully from can be challenging. However, as described above, data for a given alignment site can be captured in a variety of different ways selected based on the layer being inspected, so that, regardless of the layer being inspected, Suitable data for the alignment site can be provided.

  As described above, swath stitching using “short swaths” in coverage mode can be used to align inspection data with design data. However, in some embodiments, as shown in FIG. 14a, the alignment site 302 is spaced (eg, far away) from the area on the wafer corresponding to the first inspection swath 304a. Placed on top. This situation occurs when only the preferred alignment site is separated from the area of the wafer scanned for the first inspection swath. The placement of the first inspection swath is determined from the inspection area definition (eg, an inspection area that is automatically defined or defined by the user). In such a situation, the method or system described herein performs a series of “miniscans” 306 on the wafer, each as wide as one die, as shown in FIG. 14a. be able to. The swath captured by the mini-scan is used to “stitch” the swath including the alignment site together with the first inspection swath 304a using the inter-swath alignment method described above. Subsequent inspection swaths 304b, 304c are then aligned to the first inspection swath 304a as described further above.

  The methods and systems described herein can capture an inspection swath for a wafer in a number of different ways. For example, as shown in FIG. 14b, the system can capture an inspection swath 308 for the wafer in 100% inspection mode. In particular, the system scans the wafer back and forth to capture overlapping swaths used to inspect 100% of the die area. In another example, as shown in FIG. 14c, the system can capture an inspection swath 310 for the wafer in standard coverage mode. In this coverage mode, the area on the wafer where the swath has been captured may be from about 25% to about 50% of the die area. The swath shown in FIG. 14c corresponds to a 50% coverage mode where alternating swaths are used for inspection. In a different example, as shown in FIG. 14d, the system can capture an inspection swath 312 for the wafer in a “smart scanning” mode. In this mode, about 50% of the die area can be scanned, and the area to be scanned can be selected based on information about the design or expected interaction between the design and the process. In addition, the systems described herein are configured to perform any of the various scanning methods described above (eg, use different scanning methods for different wafers). Further, the methods (or design analysis tools) described herein include using knowledge about the inspection system (eg, scanning capabilities) to determine the optimal “coverage” scheme for the wafer.

  In another embodiment, the method aligns the inspection data to the design data, and then uses the die-relative design data space coordinates determined by the aligning step to coordinate the additional inspection data coordinates to the design data space coordinates. Including conversion. This conversion is performed based on user input or by extracting relevant information from the appropriate design file and / or process recipe (stepper recipe). An alternative approach to determine transformations without information from the user is to align (e.g., overlay) inspection data to design data by manually selecting alignment sites or using an algorithm overlay optimization approach. Including that. Note that this is a die alignment technique. Wafer alignment techniques may not be performed if die relative coordinates are used (ie, if the inspection system already knows exactly where the alignment sites are for each die).

  The methods described herein may or may not include capturing inspection data by performing an inspection of the wafer. In other words, the methods described herein can be performed by a system that does not include an optical or electron beam inspection subsystem (such as the system described further herein). Instead, the system is configured as a “stand-alone” system configured to receive inspection data from the inspection system. Thus, the stand-alone system can capture inspection data from the inspection system. A stand-alone system can capture test data in any manner known in the art (eg, via a transmission medium that can comprise “wired” and / or “wireless” portions). Alternatively, the method is performed by a system that includes an inspection system. In this method, the inspection system forms part of the system and inspection data is captured by the system by performing an inspection of the wafer. In addition, no matter how inspection data is captured, the method described herein uses inspection data of a type known in the industry in a format known in the art. And executed. Inspection data includes data for one or more defects detected on the wafer. In another example, in one embodiment, test data is captured for PWQ, which is further described herein.

  The methods described herein have been successfully used to correlate the examination space to the design data space coordinates with relatively high accuracy, and such correlation can be associated with a large number of as described further herein. Used in steps. For example, the position of inspection data in the design data space is advantageously used to determine whether the inspection data corresponds to an inspection area or non-inspection area on the wafer, and the inspection process It is performed based on the type of area corresponding to different parts of the data. For example, the methods and systems described herein can be used to ensure that the area under inspection is substantially accurately aligned to a given feature in the design or CAD database for all points on the die. By shifting the raw image data with respect to non-critical areas such as CMP pattern fill areas can be ignored, while the inspection is substantially accurate so that inspection can only be performed in critical placement on the die, such as via placement Regions can be generated. These critical locations, or “locations to inspect” areas, are entered at the time of recipe setup, and the results of CAD DRC, DFM analysis such as design scans and / or PWQ analysis, electrical testing, FA, or some combination thereof are used. Determined by “hot spot” analysis performed using.

  For example, in some embodiments, the methods described herein may include an inspection area stored in a standard EDA layout format (eg, GDSII, OASIS, etc.) generated from a layout analysis software tool. And the like, and converting information related to the design data into a format that can be used in the inspection system. Thus, the method includes transferring inspection area information from the design tool to the inspection system. For example, a translator module (not shown in the figure) is configured to generate a region to be inspected from a standard design format such as GDS or OASIS. Thus, a file containing such a design format does not include a design, but includes polygons resulting from the design analysis performed by the EDA tool. Therefore, by using the translator module, conversion between two spaces (ie, design and inspection) can be performed efficiently.

  In other embodiments, the method is performed as described herein to determine the position of defects detected on the wafer in the design data space based on the position of the inspection data in the design data space. And one or more of the design data corresponding to the position of the defect using a data structure in which predetermined values for one or more attributes of the design data are stored as a function of the position in the design data space Determining a value for the attribute. In this way, values for one or more attributes of the design data corresponding to the position of the defect are determined from permanent already extracted design layout attribute data. In other words, the value for the design data attribute (s) corresponding to the defect location is determined from the attributes already calculated based on the design geometry, eg, one or more attributes from polygons in the geometry. (E.g., as a function of geometric operations on the polygons). In this way, the design can be processed at the polygon level, and the determined polygon level attribute values can be stored in the data structure. In that case, the data structure includes a “superset” of data for one or more attribute values of the design data stored in the data structure. An EDA layout analysis tool or other method or system known in the art can be used to generate predetermined values for one or more attributes of the design data as a function of position in the design data space. In this way, the design is preprocessed to determine the value of one or more attributes of the design data as a function of position throughout the design data space, and the values for the one or more attributes are determined in the design data space. Determined for each defect by retrieving the value of one or more attributes in the data structure "on the fly" using the defect location. Data structures in which the predetermined value is stored as a function of design data space location include any suitable data structure known in the art. Similarly, the design data structure may be one or more attributes of the design layout of the design, one or more attributes of the floor plan of the design, one of the cells in the design, or as a function of position in the design data space. Contains predetermined values for multiple attributes, other information about the design, or some combination thereof.

  In one embodiment, the method includes determining the sensitivity of detecting defects at different locations on the wafer, as shown in step 18 of FIG. In one such embodiment, the method determines the sensitivity of detecting defects in different portions of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Including that. In one such embodiment, the method includes performing design-based inspection by transferring inspection area information from the design tool to the inspection system. For example, the inspection area information is used to identify different parts on the wafer and the sensitivity used to detect defects in the different parts. At that time, one or more attributes of the design data include inspection target area information. However, the one or more attributes of the design data can also include any or more of the attribute (s) of the design data described herein.

  The data preparation phase includes generating or capturing data for one or more attributes of the design data. One or more attributes of the design data used to determine the sensitivity of detecting defects in different portions of the wafer include process or yield information associated with the design data. For example, in one embodiment, the one or more attributes of the design data include the design data for the process layer from which wafer inspection data was captured, a different process layer, or some combination thereof, different design data, or some of them Selected based on one or more attributes of inspection data already captured for the wafer for the combination, other wafers, or some combination thereof. In this way, one or more attributes of the design data in the design data space used to determine the sensitivity of detecting defects in different parts of the wafer are the same wafer in the same or different design in the same or different process layers. Alternatively, the selection is made based on the correlation with the attribute of inspection data already collected from different wafers. Test data that has already been collected is stored in a data structure such as a fab database or other suitable database, file, or stored in a knowledge base that is configured as described herein. Is done. Thus, one or more attributes of the design data are selected in this embodiment based on cumulative learning, historical data, or a training set of data.

  In other embodiments, the one or more attributes of the design data include the yield criticality of defects already detected in different parts, the failure probability of defects already detected in those parts, or some combination thereof Selected based on Thus, the sensitivity of detecting defects is based at least in part on one or more attributes of design data selected based on yield criticality and / or failure probability of defects detected in different portions. Process or yield criticality information may include, for example, critical defects determined by PWQ, placement of defects of interest (DOI) based on hot spots (eg, determined from inspection), hot bitmaps determined from logical bitmaps. Including spot information, KP values determined from test results for defects detected in hot spots, other process or yield information described herein, or some combination thereof. The KP value is further determined as described herein. In addition, the failure probability is determined in a manner similar to that described herein for determining a KP value for a defect. Yield criticality is determined in a manner similar to that described further herein to determine yield relevance for defects.

  Data for one or more attributes of the design data is also referred to as “context” data that defines a geometric region in the device design that has different values for the one or more attributes (eg, contact area or dummy fill). Type (s) of features in the region, such as region, “where to inspect” information or “region to be inspected”, “critical” region where process failure may occur, or some combination thereof. The term context data is used herein interchangeably with the terms “context information” and “context map”. Context information is captured from a variety of sources including simulation, modeling and / or analysis software products commercially available from LKA-Tencor, other software such as DRC software, or some combination thereof. Further, the additional context data is determined by data for the attribute (s) of the design data and combined with those data. Data structures such as databases or files containing design data and / or context data can use any suitable format known in the art.

  Determining sensitivity as described above is performed such that defects detected at different parts of the wafer corresponding to design data having different values of one or more attributes of the design data are detected with different sensitivities. Is done. Thus, the method may further include determining, identifying, and / or selecting different portions based on the value of the one or more design data attributes as a function of the spatial position of the design data. it can. The fact that the dimensions of the different parts are different and that the value of the attribute (s) in the design data is available or changes depending on the resolution that is captured can be for all or part of those different parts. Occurs or does not occur at all. For example, if the context map is used to determine sensitivity to different parts as further described herein, the dimensions of the different parts will vary depending on the resolution of the context map.

  In one such embodiment, sensitivity is a context that includes a value for one or more attributes of design data across the design data space, as described further herein, and the location of the inspection data in the design data space. -Determined based on the map. For example, the method includes using a context map to define a relatively high sensitivity area of the die on the wafer relative to the critical area and a variable sensitivity area based on the criticality of the context. In one example, the design data segment is defined to insulate the dense array from the logic, open area, and granular metal. A combination of image gray level and context is also used to define one or more segments in the design data. For example, pixels with intermediate gray levels are grouped into one segment. The image gray level is determined using a simulated image or an image captured by an inspection system or other image acquisition system.

  In some embodiments, determining the sensitivity to detect defects in different portions of the wafer based on the location of the inspection data in the design data space and the context map is performed by the inspection system during inspection of the wafer. For example, the context map is used by the inspection system as described herein when inspecting a wafer. In other embodiments, determining the sensitivity to detect defects in different portions of the wafer based on the location of the inspection data in the design data space and the context map is the inspection system after the wafer inspection data has been captured. It is executed by. For example, the context map is used by the inspection system as described above after inspection data is available offline. In both of these embodiments, the method uses a context map to automatically define a die dummy area (do not inspect the area) on the wafer, and for die dies where different sensitivity thresholds are used. A coarse area can be defined. For example, a context map (eg, a context map that defines a dummy fill area) can be used to automatically define non-inspected areas that do not require inspection, and are therefore excluded for defect detection purposes. Is done. Such regions are typically not well controlled and therefore generate a relatively large amount of noise (in the case of die to die comparisons). Therefore, by excluding such areas, the overall S / N ratio of the inspection can be increased.

  In one embodiment, determining the sensitivity of detecting defects in different parts of the wafer based on the position of the inspection data in the design data space and the context map is to detect the inspection data to detect defects in different parts of the wafer. Determining a sensitivity threshold value to be used with. In this way, sensitivity can be changed between regions by changing one or more thresholds used for defect detection, which is similar to the segmented automatic threshold (SAT) method. ing. For example, low threshold (high sensitivity) detection is used for critical regions and high threshold (low sensitivity) detection is used for non-critical regions. By segmenting the design data and changing the threshold (s) used for defect detection based on one or more attributes of the design data, the overall sensitivity of the inspection process can be increased . Accordingly, these methods and systems described herein provide improved defect detection.

  The method further includes performing a number of different steps using the context map described above. For example, using but not limited to context maps (regardless of whether die-die inspection mode, standard reference die-die inspection mode, etc. are used for defect inspection), determining sensitivity, nuisance defects Various steps can be performed, such as filtering the data, classifying the defects, generating a review sample for online or offline review. In order to use design or context information as further described herein, the absolute position of image pixels or other inspection data captured during the inspection process (e.g., by scanning a wafer) is: It is determined in the design data space (for example, design database coordinates). Mapping inspection data to the design data space within half the inspection pixel size to set detection thresholds substantially accurately (separate critical and non-critical areas substantially accurately) Filtering the nuisance defect from the actual defect and other steps can be performed, but this is performed as described further herein.

  In addition, relatively high bandwidth pixel level context information can be used with a substantially high accuracy mapping from inspection space to design space coordinates in various applications. For example, a relatively high resolution context map can be used to automatically define pixel level regions to be examined with different sensitivities. A relatively high resolution context as described herein is generally more accurate than a multiple threshold (RBMT) based on a relatively coarse (eg, about 50 μm × about 50 μm) user defined region. This is inaccurate because it is ambiguous at the boundary of the inspection target region (for example, boundary uncertainty with a spread of about 5 μm or more).

  In one embodiment, the context map is used at the pixel level to control detection sensitivity at each pixel. However, in a simpler approach (in terms of system complexity), the context map is only used for post-processing defects detected using a detection method that does not detect defects using context information. In this way, inspection or mapping from wafer space to design data space is applied only to inspection data corresponding to detected defects. As described above for die-to-die and standard reference die-to-die inspection, the location of the defect is determined in the design data space. Thereafter, a patch image of the design data of the location of the defect in the design data space is captured and this patch image is used to determine the design context corresponding to the defect. Alternatively, the context map aligned to the design data is used to determine the design data context corresponding to the defect based on the position of the defect in the design data space.

  In standard reference die-to-die inspection, determining the context of each pixel in the inspection data includes determining the context of each standard reference die pixel. Since the standard reference die image is captured in the recipe setup phase, this method aligns the data for the alignment site (selected as described above) in the standard reference die image with the data for the predetermined alignment site. And performing a mapping transformation to determine the placement of each standard reference die pixel in the design data space. These steps are further performed in the recipe setup phase. In addition, the standard reference die is mapped to context data based on the mapping of the standard reference die to the design data space, and the standard reference die pixel is stored offline and inspected with the context corresponding to each pixel. Sometimes supplied to the inspection system or captured by the inspection system. This process is performed offline and is performed only once in the recipe setup phase.

  In one such embodiment, each standard reference die pixel can be associated (“tagged”) with context information. In this way, context information can be “attached” to a standard reference die pixel. In one example, if there are 16 different possible contexts, a 4-bit tag can be attached to each pixel. Alternatively, the context data can be compressed using a suitable compression algorithm or method, or the context data can be represented in polygonal form. In this manner, at inspection time, the reference reference die pixel data and the mapped (transformed) context data associated with the standard reference die pixel data are transferred to the inspection system image computer or other process. Or captured by an image computer or other process of the inspection system. Accordingly, the context corresponding to the inspection data pixel is determined based on the context information of the corresponding pixel in the standard reference die image. In doing so, contextual information corresponding to inspection data pixels can be utilized in defect detection applications and defect classification (and / or grouping by bin ranges) applications, as further described herein. To be executed.

  In other embodiments, the method can assist in wafer inspection using a context map at any resolution. For example, variable resolution context maps are used to assist in wafer inspection and grouping by defect bin range. The resolution of the context map may vary depending on, for example, the accuracy with which the live pixel stream is aligned with the design data and the required accuracy of the application. Different resolution context maps can be represented in many different ways. For example, convert the absolute representation of a polygonal context map (ie, a fractional number of digits in the micron range) to the internal representation of the appropriate pixel size inspection system to generate a pixel level context map be able to. In addition or alternatively, the coarse context map includes context for a relatively coarse area having a lateral dimension of, for example, about 1 μm × about 1 μm. The coarse areas form “tiles” that separate design data. Associated with each tile is contextual data such as feature types (eg, dummy features, contacts, line ends), feature attributes (eg, minimum line width / spacing between geometries, etc.), or some combination thereof.

  In one embodiment, the method uses relatively high resolution layout information and attribute information for a design that is captured from a software program that can be used to analyze the design for critical areas and possible design rule violations. Generating a context map. Such a context map is an analysis software (such as Design Scan) commercially available from KLA-Tencor or an arrangement that is converted into a format for use by an inspection, metrology, or review system and some attributes of each arrangement It is generated using other software, such as DRC software that generates a list of (or labels).

  In other embodiments, the method extracts a feature vector from a CAD layout and generates a relatively low resolution coarse context map by defining an equivalent context group using unsupervised clustering. including. For example, a method for generating a relatively coarse context map (eg, a map that includes areas or tiles of about 1 μm × about 1 μm) includes processing CAD layout files and rendering or analyzing those files. , Extracting several attributes or feature vectors for each tile. For each region, multiple features can be extracted from a predetermined feature set. The value of each feature is its feature vector. The feature vectors for each region can be combined into a series of feature vectors that are used to determine region similarity by evaluating clustering in the feature space. These feature vectors (one or more vectors per tile) are unsupervised clustering known in the art used to find clusters of vectors (ie, tiles with similar attributes). Clustered in feature space using algorithms and / or methods. Examples of such algorithms and methods used in the methods described herein are described in Han US Pat. No. 6,104, which is incorporated by reference as if set forth in its entirety herein. Exemplified in No. 835. Each such cluster is then assigned a unique context code or identification. The die map in which each file is represented by this code or identification is then used by the inspection system as described further herein.

  In different embodiments, this method is used to render a CAD layout patch image, cross-correlate the CAD layout patch image, and separate it according to bin ranges as further described herein. Generating a relatively low resolution coarse context map by identifying equivalent context groups. Other methods of generating a context map (eg, a relatively coarse context map) include rendering a CAD layout file into multiple patch images and dividing design data into multiple patch images. Identifying image cross-correlation between patch images so that patch images having a relatively high cross-correlation are divided into groups of patch images corresponding to the same context type according to bin ranges; Including.

  In some embodiments, the context data used in the methods described herein includes context data for multiple layers that are on or formed on the wafer. For example, some defects are not located in critical areas within the layer where the defect was detected. However, these non-critical defects may be made critical if the critical region of the overlying layer is located in a region on the wafer where it is formed on the wafer. The context map used in any of the steps described herein can be a context map for multiple layers on the wafer.

  In other embodiments, the method may vary the wafer based on the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. Determining the sensitivity of detecting defects in the portion. The multiple attributes of the design data used in this step include the attribute (s) described herein. In one such embodiment, the one or more attributes of the inspection data include one or more image noise attributes, or some combination thereof, when defects are detected in different portions. Thus, one or more attributes of inspection data used in this embodiment include image noise attributes and / or detection or no detection of defects in different regions of the inspection data. The plurality of attributes of the inspection data used in this step includes other attributes described herein. Determining sensitivity in this embodiment is performed with respect to the RBMT setup for the inspection process based on image noise correlated to design attributes. Determining sensitivity in this embodiment is further performed as described herein.

  In other embodiments, the method may include one or more attributes of schema data for a design of a device being processed on a wafer, one or more attributes of an expected electrical behavior of a physical layout for the device. Or aligning one or more parameters that detect defects on the wafer based on some combination thereof. Thus, one or more parameters or inspections to detect defects using the design schema data attribute (s) and other electrical descriptions of the expected behavior of the physical design (layout) Any other parameters of the process can be changed. Detect defects using, for example, critical and non-critical paths, information about active and inactive geometry, physical design (layout) schema data, or other such information about expected electrical behavior Change the sensitivity, determine the part of the wafer where defects should be detected (eg, inspection area and non-inspection area), and determine what part of inspection data should be used to detect defects (eg, One or more other parameters of the inspection process are changed (based on the correlation between the wafer space and the design data space).

  In another example, defect capture rate and electrical behavior monitoring is performed based on the design / image context. For example, electrical behavior is monitored by performing electrical tests, FA, or other tests or analyzes known in the art or by using the results of such tests or analyses. . The results of electrical testing, FA, or other testing or analysis can be correlated to device schema data and contextual information about the physical layout. Design / image context to determine the defect capture rate and electrical behavior being monitored, information about defects detected on the wafer, information about the inspection process used to detect defects, information about the design Can be correlated. For example, using the results of monitoring defect capture rate and electrical behavior, what types of defects are detected on the wafer, which defects should be detected (eg, in an online inspection process), and which defects Can be determined, and weaknesses in the design can be determined. Such information can be used to modify the inspection process as described further herein.

  In an additional embodiment, the method includes one or more to detect defects on the wafer using inspection data based on one or more parameters of an electrical test process to be performed on the wafer. Including changing the parameters. For example, one or more parameters for detecting defects on the wafer or other parameters of the inspection process are changed based on electrical test definitions associated with the associated (physical) design data space. . In this way, the inspection process can be modified based on how the electrical test is performed. In one such example, the area on the wafer that is analyzed by the electrical test process is determined based on one or more parameters of the electrical test process, and one or more parameters or Other parameters of the inspection process are changed so that defects in areas on the wafer that are not analyzed in the electrical test process are inspected with appropriate sensitivity.

  In addition, using one or more parameters of the electrical test process and the location of the defect in the design data space or wafer space, defects that are not tested by the electrical test process (or “escape the electrical test”) Can be identified. In one such example, the area on the wafer to be tested in the electrical test process and the location of the defect on the wafer can be used to determine defects that are not tested by the electrical test process. In another example, the area in the design tested in the electrical test process and the location of the defect in the design data space can be used to determine defects that are not tested by the electrical test process. Similarly, using one or more parameters of the electrical test process and the location of the defect in the design data space or wafer space, the defect varies depending on whether the defect is tested by the electrical test process or not. They can be separated into groups or divided into different groups according to bin ranges.

  In wafer space, design recipe attributes and information about hot spots (eg, information from a hot spot database) can be used to set up an inspection recipe in the monitoring phase. For example, the inspection target area is automatically defined in the monitoring phase in the wafer space. The automatically determined inspection target areas include macro and micro inspection target areas. The automatically determined inspection target area can further include a non-inspection target area. In addition, inspection recipes can automatically change sensitivity, filter nuisance defects, increase the capture rate of known systematic defects (eg, sensitivity to hot spots or hot spot areas) Set up for suppressing detection signals or data corresponding to cold spot areas. In addition, design data attributes and information about hot spots can be used to successfully group and classify defects, or classify defects according to bin ranges, and sample defects, which can be referred to as GDS (ie, GDS Pattern grouping) and / or using GDS pattern grouping pareto to separate defects according to bin ranges based on design data, each performed as described herein.

  In other embodiments, the method periodically alters one or more parameters of an inspection process performed by the inspection system based on the results of one or more steps of the method using feedback control techniques. Including doing. In other embodiments, the method automatically alters one or more parameters of an inspection process performed by the inspection system based on the results of one or more steps of the method using feedback control techniques. Including doing. For example, the monitoring phase includes automatic process control (APC) of the inspection process, including changing the inspection recipe or parameters based on previous weighing results, possibly in combination with prior knowledge of process zone differences. The APC for the weighing process is identified according to any of the embodiments described herein to determine the arrangement in which the measurement is to be performed in addition to the measurement to be performed in subsequent weighing. It is executed on the basis of mechanical defects. The APC for the test process is identified according to any of the embodiments described herein to determine the arrangement in which the test is to be performed and the electrical parameters to be tested in the subsequent electrical test. Is performed based on systematic defects.

  In additional embodiments, the method uses the result of one or more steps of the method to generate a knowledge base and uses the knowledge base to generate an inspection process that is performed by the inspection system. Including. The knowledge base is generated by storing one or more image attributes and / or one or more attributes of design data in a suitable data structure. In addition, the knowledge base includes cumulative learning captured by the inspection system used to generate the inspection process. For example, for the inspection process, the knowledge base is used to determine the cumulative results of the inspection, such as the frequency of defect detection and the percentage of detected defects that are nuisance defects, and using such cumulative results Additional information, such as the probability that the defect is a nuisance defect, can be determined.

  Using such a knowledge base, an inspection process can be generated as described further herein. In this method, the knowledge base is used to generate a new inspection recipe. In addition, the knowledge base is used to generate an inspection process for recipe setup and / or waferless recipe setup. Generating the inspection process includes selecting one or more parameters of the inspection process. In addition, the knowledge base is used to modify the inspection process by recipe optimization and automated recipe optimization. For example, the method includes using a knowledge-based training feedback mechanism for periodic or automatic optimization of one or more parameters of an existing inspection process. Changing the inspection process includes changing one or more parameters of the inspection process.

  In other embodiments, the method includes optimizing a wafer inspection process that uses the location of the inspection data in the design data space and the context map to determine the printability of reticle defects on the wafer. As such, the method includes optimization of a wafer inspection process aimed at determining printability of defects detected on the reticle using CBI in combination with a context map. Optimizing the wafer inspection process includes changing one or more parameters of the wafer inspection process that may include the parameters of the wafer inspection process (s) described herein. . In general, determining the printability of a reticle defect on the wafer includes inspecting the wafer to detect a defect on the wafer that may correspond to a defect on the reticle. In this way, optimizing the wafer inspection process to determine the printability of the reticle defect (s) causes the wafer inspection process to detect defects on the wafer that may correspond to defects on the reticle. Including optimizing.

  In one example, the method includes the location of inspection data captured for a wafer in the design data space and one or more reticle defects in the design data space that are determined as described herein. And using the position to identify the portion of the inspection data used to determine the printability of the reticle defect (s). Thus, by using the design data space location of the reticle defect (s) and the inspection data captured for the wafer, it is used to detect defects on the wafer that can correspond to the reticle defect (s). The portion of the inspection data to be determined can be determined. The attribute (s) of the design data including the context map can be used to select one or more parameters of the wafer inspection process to determine the printability of the reticle defect. For example, using a context map, one or more attributes of the design data corresponding to the portion of the inspection data identified as described above can be determined. Thus, based on one or more attributes of design data corresponding to different parts, one or more parameters of the wafer inspection process used for the different parts of the inspection data identified as described above. select. In doing so, different portions of the inspection data identified as described above, corresponding to design data having different values of one or more attributes, are processed with one or more different parameters, and (a) reticle defect (s) It is possible to detect wafer defects corresponding to. In one such example, the context map is used to determine the criticality of the design data corresponding to different portions of the inspection data captured for the wafer, which is identified as described above, and the criticality is Used to determine the sensitivity when detecting defects in different parts of the inspection data. In one such specific example, different parameters of the wafer inspection process are selected for different parts of the inspection data, and the printability of one or more reticle defects is determined in the critical area of the design data compared to the non-critical area in the design data. Then, it can be determined with higher accuracy.

  One or more parameters of the wafer inspection process are further modified and / or optimized based on the location of the inspection data in the design data space, the context map, and other information described herein. For example, a context map can be used to determine one or more attributes of different parts of the design data where one or more reticle defects are detected, such that one or more design data of the different parts Inspections corresponding to different parts of the design data where the reticle defect (s) were detected using attributes in combination with one or more attributes of the reticle inspection data (such as one or more reticle defect attributes) Wafer inspection process parameters can be selected for different portions of the data. In one such example, the printability of different types of reticle defects placed in portions of design data having substantially the same attribute (s) is determined by one or more different parameters of the wafer inspection process. One or more parameters of the wafer inspection process can be selected. In another example, the printability of the same type of reticle defect located in the portion of the design data having different values of the attribute (s) is determined by one or more different parameters of the wafer inspection process. One or more parameters of the wafer inspection process can be selected.

  The context map used in the embodiment described above to optimize the wafer inspection process to determine the printability of reticle defects is configured as described herein and is Contains any of the context maps described in the document. In addition, any information contained in the context map is used in the embodiments described above to modify one or more parameters of the wafer inspection process.

  In some embodiments, the method includes modifying one or more parameters of an electrical test process to be performed on the wafer based on results detected on the wafer using inspection data. Including. For example, in the test space, the monitoring phase includes defining or modifying test patterns and / or other test parameters using systematic defects identified in accordance with the embodiments described herein. In addition, by using defects detected on the wafer using inspection data, whether one or more of the defects are not tested by the electrical test process (or “escape the electrical test”) One or more parameters can be determined to determine and define an area on the wafer where the electrical test process is performed such that one or more defects are tested by the electrical test process. In this way, the results of the inspection process can be fed forward to the electrical test process, reducing the number of defects that are not tested in the electrical test process. In addition, one or more parameters of the electrical test process may include a defect detected on the wafer using inspection data, a design data space determined as described herein, or a wafer One or more attributes of the defect, including the position of the defect in space, the attribute (s) of the defect described herein determined in any manner described herein, and One or more attributes of the design data, including the attribute (s) of the design data described herein, determined in any manner described in It is changed based on information or some combination thereof. For example, the defect location, the defect attribute (s), and the design data attribute (s) are used to determine a failure probability value for one or more of the defects as described herein. be able to. If a defect that is not tested by an existing electrical test process has a relatively low failure probability value, this method cannot change one or more parameters of the electrical test process. In contrast, if a defect that is not tested by an existing electrical test process has a relatively high failure probability value, the electrical test is performed so that a defect with a relatively high failure probability value is tested by this electrical test process. One or more parameters of the process can be changed. Similarly, one or more parameters of a metering process, such as sampling of the metering process, are selected, determined, or changed as described above.

  By aligning the inspection data with the design data, it becomes possible to inspect “hot spots” on the wafer. A “hot spot” is generally defined as an arrangement of design data printed on a wafer where a fatal defect may exist. In contrast, a “cold spot” is generally defined as an arrangement of design data printed on a wafer where nuisance defects may be present. An example of a nuisance defect is a variation in the critical dimension (CD) of a feature that does not substantially affect the yield of devices formed on the wafer, which may cause the inspection system to be defective in its placement. Show. Some defects are fatal only under some conditions, such as when the defects are in contact with the structure of a device formed on another layer of the wafer. Therefore, an arrangement where such defects can exist in design data printed on a wafer is commonly referred to as a “conditional hot spot”.

  In additional embodiments, the method includes determining whether the defect detected on the wafer is a nuisance defect, as shown in step 20 of FIG. Whether the defect is a nuisance defect is determined based on the position of the inspection data in the design data space and one or more attributes of the design data. For example, in some embodiments, the method determines the position of the defect in the design data space based on the position of the inspection data in the design data space, and the position of the defect in the design data space and the design in the design data space. Determining whether the defect is a nuisance defect based on one or more attributes of the data. The one or more attributes of the design data used to identify the nuisance defect at this step include the attribute (s) described herein. For example, one or more attributes of the design data are defined in the context map. Thus, the method includes applying a context map to defect data and filtering (eg, discarding) defects (eg, nuisance defects) that are not considered important in applications such as but not limited to PWQ. . At this time, the part of the design that is approaching the limit of the capability of the machining process is divided into a critical part and a non-critical part based on the context. In another example, the design data attribute (s) used to identify the nuisance defect at this step includes hot spot information for the design data. In this way, the defect location and hot spot information in the design data space can be used to identify defects detected in the cold spot in the design data as nuisance defects.

  Lithographic PWQ applications typically determine exposure of dies on a wafer with different exposure and focus offsets (ie, modulated dose and focus), design weak areas, and process windows. Identifying systematic defects in the die used to determine. An example of a PWQ application for lithography is incorporated by reference as if fully set forth herein, U.S. Patent Application No. 11/005, filed December 7, 2004, by the same applicant as Wu et al. 658. Many artifacts of focus and exposure modulation appear as defects (die-standard reference die difference) but are actually nuisance defects. Examples of such artifacts include CD variability, and line end pullbacks or shorts in areas where these artifacts have no or little impact on device yield or performance. However, the location of the defect is determined substantially accurately with respect to the design layout using the methods described herein. In addition, by using the methods described herein, the region of interest can be determined with relatively high accuracy, as further described above. These “small” areas to be inspected are centered around known hot spots and are inspected with a relatively high sensitivity, or are known as non-inspection areas or areas with a relatively low sensitivity. Can be centered on the cold spot (systematic nuisance).

  Thus, as described above, the method includes determining whether the defect is a nuisance defect based on the position of the defect with respect to the design data space and whether the position is within the inspection area. . Defects are further filtered according to context, size, redundancy, PWQ “rules”, or some combination thereof. For example, in process space, PWQ analysis and DOE analysis are performed using hot spots in the monitoring phase. In addition, the methods described herein are used to extend PWQ applications below the 65 nm design rule where currently used noise filters do not work due to resolution limitations. Thus, one advantage of the method described herein is that it can be used to extend BF inspection to detect systematic and DFM defects. In particular, the use of CBI as described herein can add the functionality of a BF inspection system such as systematic defect inspection and / or DFM applications below the 65 nm design rule. These methods further allow or retain the root cause of DFM systematic defects relatively quickly. Locating the root cause is performed as described further herein.

  In other embodiments, the method may be based on one or more attributes of the design data in the design data space (defined in the context map as further described above), or Defects that have not been determined to be nuisance defects, as shown in step 22, by comparing with the location of the hot spot, stored in a data structure such as a list or database, Determining whether it is a random defect. In addition, all defects that are not of interest may not be nuisance defects. For example, systematic defects that have a relatively low yield effect or have no effect on yield are defects that are not of interest and are not considered nuisance defects. Such defects appear on the active pattern or device area on the wafer. The methods described herein include identifying such defects. Such defects, or defects that are placed in a cold spot, can have a design context (eg, redundant via), modeling (eg, DesignScan), PWQ, inspection and review, test defect correlation (eg, some placement) A relatively high stacking fault density and a relatively low stacking fault configuration). In addition, the monitoring of these defects is performed by comparing the position of the defects with the positions of the hot and cold spots. In addition, if the patterns in which these defects are placed are common, the grouping method based on the design data described in this specification can be used to separate these defects from the bin range separately from other systematic defects. Can be divided according to. In addition, systematic defect discovery is performed by correlating multiple input sources from design, modeling results, inspection results, weighing results, and test and FA results.

  Systematic DOI includes all pattern dependent defect types. Identifying systematic defects is a valuable task and the impact of these defects on the device can be analyzed. The random DOI includes statistical samples of critical types of random defects. Identifying random defects is a valuable task because critical types of random defects can be analyzed to determine the impact of these defects on the device. In addition, by identifying random defects, one or more inspection process parameters can be modified to suppress detection of random defects that are considered nuisance defects. Furthermore, the inspection process parameter (s) can be modified to distinguish nuisance defects from systematic causes (cold spots).

  Determining whether a defect is a nuisance defect, a systematic defect, or a random defect is also a useful task, but it is the type of defect detected on one or more wafers. This is because the yield can be estimated more accurately based on the relationship with the yield of different types of defects. In addition, the results of the methods described herein can be used, possibly in combination with yield prediction, to make one or more decisions regarding design data and manufacturing processes. For example, the results of the methods described herein can be used to verify an IC design. In another example, the results of the methods described herein can be used to reduce the number of systematic defects and the types of systematic defects that affect the IC design produced by the process. Can provide feedback. In one such example, the results of the methods described herein can be used to change the optical rules used in the design and / or IC design process. In yet another example, the results of the methods described herein to change one or more parameters of one or more processes used to process the wafer level being inspected. Can be used. Preferably, the number of systematic defects and / or systematic defect types caused by the process (s), possibly the number of critical random defects and / or the number of types of critical random defects, is reduced. , Change one or more parameters of the process (es).

  In some embodiments, the method may include one or more as shown in step 24 based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Including classifying a plurality of defects. For example, the position of the defect in the design data space is determined from the position of the inspection data in the design data space. In addition, one or more attributes of the design data related to the location of the defect in the design data space are determined from the three text map or by other methods described herein to classify the defect. One or more attributes related to the location of the defect are used to do this. In other embodiments, the method includes the location of the portion of the inspection data corresponding to the defect in the design data space, and one or more attributes of the design data across the design data space as further described herein. Classifying defects detected in different parts of the wafer based on a context map containing values for. Thus, in this method, a defect can be classified by context using a context map. Classifying the defect (s) in this step is also performed in other ways as described herein.

  In one such embodiment, classifying the defects is performed by the inspection system when inspecting the wafer. For example, the context map is used by the inspection system to classify defects as described herein when inspecting a wafer. In other such embodiments, classifying the defects is performed after inspection data capture for the wafer is complete. For example, the context map is used by the inspection system to classify defects as described herein after inspection data is available offline. Thus, the method uses context maps to classify defects online (eg, using an inspection system) by second pass high resolution defect classification (HRDC), or by HRDC (eg, Including offline classification (using a SEM review station). Typically, second pass defect classification includes defect re-detection and classification, whether performed online by an inspection system or offline by a review system (optical or SEM). Both redetection and classification can be performed manually by the user or automatically (ie, automatic defect classification, ADC). As design rules shrink, the probability of identifying the wrong object as a defect in the review process increases. Design data and context maps are useful for both rediscovery and classification.

  With respect to rediscovery, the context map provides local background information near the defect so that the user or system can locate a certain defect within the review system's field of view. For example, a local image of the wafer generated by the review system can be aligned to the design data so that the location of defects in the design data space can be substantially accurately identified in the aligned local image. . In addition, the review system can use a simulated image of design data (eg, a tone image) for alignment with a local image, using the location of defects in the design data space, The position of the defect in the local image can be determined. Such simulated images are used for defect re-detection and fine alignment in the review process. An example of such a simulation is illustrated in McGhee et al. US Pat. No. 6,581,193, which is incorporated by reference as if fully set forth herein. The methods described herein include any step (s) of the methods described in this patent. Accordingly, these methods and systems described herein are used to perform relatively high accuracy defect detection.

  With respect to classification, the context map provides additional information that is used (along with the data captured by the review) to determine the class to which the defect belongs. The review is further performed using the context map, the data captured by the review and the inspection data. For example, a patch image captured by the time delay integration (TDI) camera of the inspection system and / or a high resolution patch image captured by the inspection system is sent for review of the defect sample. The patch image is used in combination with a context map for optical or SEM review and classification. In this way, the accuracy of coordinates when the defect location can be determined as described further above allows the system to classify defects substantially accurately based on design context and / or DRC failure event codes. can do.

  One or more of the above steps are performed in a monitoring phase in which systematic defects are identified and classified (or separated according to bin ranges) using inspection results and other results described herein. The The monitoring phase includes bias monitoring and standard improvement. The monitoring phase is executed when the product is increased or produced. In identifying and classifying systematic defects detected by inspection in a multi-source space (including correlation between design, wafer, reticle, test, process space), the steps described herein Any combination can be used. In addition, one or more of the steps in the multi-source space can be used in combination with them to verify the systematic defect identification results.

  In addition, the location of defects in the design data space is combined with inspection data, design data, or classification data to identify systematic defects in the monitoring phase (eg, defects placed in hot spots or cold spots). be able to. The identified hot spots can also be used to determine the design context for inspection results when there is a “hit” in the hot spot placement, which can be done with post-processing on-tool or off-tool. Is done. Yield (or KP value) correlated to the design data space can also be used as an attribute to monitor systematic defects. In addition, one or more defect attributes can be used to infer the relevance to a hot spot when there are multiple hot spot candidates.

  In reticle space, the monitoring phase generates information about hot spots that can be compared with inspection results to separate known systematic defects from random defects (eg, hot spot list (s)). Creation). In addition, one or more hot spot attributes, such as context information for the hot spot, can be used to share the hot spot across multiple technologies, layers, or devices, and if possible Which technology, layer, or device can be determined. In addition, systematic defects identified by inspection can be used to define or modify one or more parameters of the metering process, such as metering site placement, measurements, or other parameters.

  In some embodiments, the method includes failure for one or more defects detected on a wafer based on the location of inspection data in the design data space and one or more attributes of the design data in the design data space. Including determining a probability value. In addition, the method determines failure probability attribute values for defects detected in different portions of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Including that. The failure probability value for the defect is determined based on the design data space location of the inspection data corresponding to the defect and one or more attributes of the design data in the design data space, as further described herein.

  In another embodiment, the method is based on determining a coordinate of a position of a defect detected on the wafer in the design data space based on the position of the inspection data in the design data space and based on a floor plan for the design data. And converting the coordinates of the position of the defect into design cell coordinates. In this way, the defect coordinates are converted into design cell coordinates based on the floor plan of the chip design. In one such embodiment, the method uses overlay tolerances to determine different regions around the defect and performs defect repeater analysis using regions for one or more cell types. Determine whether one or more cell types are systematic defect cell types and determine one or more placements of one or more systematic defect geometries within the systematic defect cell types Determining. Thus, the method includes using cell based coordinates for repeater analysis. In particular, defect repeater analysis is performed using overlay tolerances (eg, defining a two-dimensional region surrounding each defect), and for each cell type, determines whether there is a system type with systematic defects. The arrangement of systematic defective geometries in the cell can be determined. In addition, the method includes grouping by defect cell-based bin ranges based on cell context. Dividing according to such bin ranges is performed as further described herein. In one such embodiment, the method includes a spatial lineage based on one or more attributes of the design data for a cell, geometry, or some combination thereof that is located near the systematic defect cell type. Determining whether a physical defect occurs within the systematic defect cell type. In this way, the design context of a cell with spatial systematic defects (surrounding the cell or geometry) can be used as an attribute to further characterize the appearance of spatial systematic defects.

  In other embodiments, the method may include defects according to bin ranges, as shown in step 26, based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Grouping (eg, all or part of a defect). For example, as described herein, the position of the defect in the design data space is determined from the position of the inspection data in the design data space. Then, one or more attributes of the design data used to separate the defects according to the bin range are determined based on the position of the defects in the design data space. One or more attributes of the design data used in this embodiment are probably combined with other inspection results (eg, Integrated Defect Organizer (iDO) results and Integrated Automatic Defect Classification (iADC) results). Including the attribute (s) (eg, yield effects) of the design data described herein, such as values associated with. In addition, one or more attributes of the design data associated with the location of the defect in the design data space can be determined from the context map. Thus, the method includes applying a context map to defects detected during wafer inspection and sorting the defects into contexts.

  Accordingly, the methods described herein include dividing according to bin ranges in a context-based background for wafer inspection. For example, as described above, the method can use a context map to divide defects in context according to bin ranges. In one such example, defects remaining after nuisance filtering can be sorted by context or other information described above, thereby identifying defects that are systematic defects that are not random defects. The context is further used in conjunction with other image derivation attributes associated with defects that are sorted and sorted according to bin ranges.

  Further, these defects are separated according to bin ranges based on the expected electrical parameters of the defects and / or the expected electrical parameters of device features proximate to the defect location in the design data space. The expected electrical parameters of the defects and device features are determined based on previous electrical tests, simulation of the electrical parameters of the defects, review of the defects, or some combination thereof. In addition, fault simulation for one or more defects is based on a group in which the defect (s) are separated according to the location and / or bin range of the defect (s) in the design data space.

  In some embodiments, the method includes the location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one of the reticle inspection data captured for the reticle on which the design data is printed. Or grouping defects according to bin ranges based on a plurality of attributes. Thus, reticle inspection data can be used as an attribute for grouping by bin range. In particular, the reticle inspection data attribute is used in separating defects detected on the wafer according to the bin range. In this embodiment, the one or more attributes of the design data include any of the design data attribute (s) described herein. One or more attributes of the reticle inspection data are: defects detected on the reticle, position of defects detected on the reticle in reticle space, one or more attributes of defects detected on the reticle, on the reticle Includes one or more attributes of design data to be printed on, or attributes of reticle inspection data, such as some combination thereof. The one or more attributes of the defect detected on the reticle include the defect attribute (s) described herein. In addition, the one or more attributes of the design data printed on the reticle include any of the design data attribute (s) described herein.

  The attribute (s) of the reticle inspection data are determined in a suitable manner by the method and system embodiments described herein (eg, by using the output of the reticle inspection system). Alternatively or additionally, the attribute (s) of the reticle inspection data may be stored in accordance with the method and system embodiments described herein in the storage medium in which the attribute (s) is stored and / or Alternatively, the attribute (s) can be captured from the determined reticle inspection system.

  The reticle that caused the defect on the wafer, whether the defect was caused by a defect on the reticle, using separating the defect according to the bin range based at least in part on one or more attributes of the reticle inspection data Defects can be isolated based on one or more attributes of the defect, one or more attributes of design data printed on the reticle that may have caused the defect on the wafer. As such, the results divided according to bin range provide additional information regarding the cause of the defect and / or how the reticle affects the defect and / or design data printed on the wafer. The results divided according to such bin ranges may include one or more parameters of the reticle manufacturing process, one or more parameters of the reticle inspection process, one or more parameters of the reticle defect review process, the reticle repair process To change one or more parameters, one or more parameters of another reticle or design-related process, one or more parameters of other processes described herein, or some combination thereof Advantageously used. Further, in this embodiment, the defect is classified according to the bin range includes the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the reticle inspection data, the book It is performed based on other information described in the specification.

  In another embodiment, the method is based on bin ranges based on the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data. Including grouping defects. In this way, one or more attributes derived from the inspection data can be used in the calculation of the grouping by bin range. In this embodiment, the one or more attributes of the design data include any of the design data attribute (s) described herein. In addition, the one or more attributes of the test data used for bin range grouping include any of the test data attribute (s) described herein. In this embodiment, other information described herein can also be used to separate defects according to bin range. In this embodiment, dividing according to bin ranges is performed as described further herein.

  In an additional embodiment, the method includes the location of inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, the reticle on which the design data is printed. Grouping defects according to bin ranges based on one or more attributes of reticle inspection data captured for. Thus, reticle inspection data can be used as an attribute for grouping by bin range. In particular, the reticle inspection data attribute is used in separating defects detected on the wafer according to the bin range. The one or more attributes of the design data in the design data space used for grouping by bin ranges in this embodiment include the design data attribute (s) described herein. The one or more attributes of the inspection data used for grouping by bin range in this embodiment include any of the inspection data attribute (s) described herein. The one or more attributes of the reticle inspection data used for grouping by bin range in this embodiment include any of the attribute (s) of the reticle inspection data described herein. In this embodiment, dividing according to bin ranges is performed as described further herein. In addition, the results divided according to the bin ranges of this embodiment are used to perform the other step (s) of the method (s) described herein.

  In some embodiments, the method includes the location of inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, and wafer inspection data. For a captured process layer, a different process layer, or some combination thereof, the design data, different design data, or some combination thereof is already captured for that wafer, other wafers, or some combination thereof. Grouping defects according to bin ranges based on one or more attributes of the inspection data being recorded. Thus, attributes determined from inspection data already collected for the same or different wafers, the same or different designs, the same or different process layers can be included in the bin range grouping calculation. Test data that has already been collected is stored in a data structure or in a knowledge base that is configured as described herein. In this way, one or more attributes of test data already captured are determined from cumulative learning data, historical data, or a training set of data. In this embodiment, the one or more attributes of the design data include any of the design data attribute (s) described herein. In addition, the one or more attributes of the test data used for bin range grouping include any of the test data attribute (s) described herein. In this embodiment, other information described herein can also be used to separate defects according to bin range. In this embodiment, dividing according to bin ranges is performed as described further herein.

  In any of the embodiments described above, dividing according to bin ranges is performed on-tool, off-tool, or some combination thereof.

  In additional embodiments, the method may include the location of inspection data in the design data space and the design in the design data space, such as the yield effect associated with design data, possibly combined with other inspection results (eg, iDO results and iADC results). Based on one or more attributes of the data, including selecting at least a portion of the defects for review, as shown in FIG. The one or more attributes of the design data used to select defects for review include the design data attribute (s) described herein. In addition, the location of the inspection data in the design data space is described herein, which is used to determine the attribute (s) of the design data corresponding to the defects as described herein. Used to determine the location of the defect in the design data space. In some such embodiments, the nuisance defects are filtered and separated from other defects detected on the wafer as described herein, and only the DOI (or non-nuisance defects) are reviewed. Or it can be retained for further analysis. In other embodiments, hot spots identified with defect lists, defect and hot spot classifications, and design context are used to improve review sampling (which may include sub-sampling) in the monitoring phase. This can be done during post-processing on-tool or off-tool.

  In other embodiments, selecting defects for review is performed according to the results divided according to bin ranges. For example, some groups of defects are selected for review, while other groups of defects are not selected for review. In other examples, defective groups result in heavier sampling than other groups (ie, defects from one group are selected more frequently for review). The groups of defects that are sampled and the degree to which those groups are sampled are described, for example, in one or more attributes of the design associated with each of the groups, or the specification associated with the group of defects. Determined based on other information that is being made. Selecting a defect for review is further performed as a function of the yield association associated with the defect or defect bin. For example, the defect population can be divided into random defects and systematic defects, and different sample plans can be used for each of the different defect types. Thus, sampling strategies for different types of defects can be dramatically different.

  In some embodiments, the method includes selecting at least a portion of the defects for review, which includes design data in a design data space having different values of one or more attributes of the design data. Includes at least one defect located in each portion. In this way, defects in each different part of the design data are sampled for review. For example, use the context of each defect to sort the defects for review (eg, by context criticality) and to ensure that all contexts where defects are detected are represented in the review sample Generate a sample.

  In other embodiments, the method can review defects as indicated in step 30 based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Determining the order in which For example, the method includes sorting defects based on priority of offline review (eg, optical or SEM review) using a context map. The context of each defect is used to sort review defects (eg, by context criticality) so that systematic and potential systematic defects are given higher priority than other defect types. Is done.

  Align inspection data stream at a sample point across the die on the wafer to a predetermined alignment site (such as a rendered image from the GDS database) to perform sub-pixel alignment of the inspection data at all points on the wafer The method has a number of advantages. For example, since the raw data stream is substantially accurately aligned with the design data, the defect location in the design data space is determined with sub-pixel accuracy (eg, sub-100 nm accuracy and 1000 nm accuracy currently achievable). Is done. If the defect location is of substantially high accuracy, the accuracy of any subsequent review process is greatly increased, and the location of the defect is identified and imaged on a defect review system such as an SEM or FIB system, The rate at which it can be analyzed can be increased. In addition, the context information associated with the defect is used in the HRDC phase, which is performed off-line on the inspection system in the second pass review, or off-line on the SEM or optical review station. . Such information can also be used in other systems, such as an automatic defect location (ADL) system, in addition to any other local context information about the defect that can help to locate the defect automatically or manually. Supplied or taken up by such a system. In addition, the review system can use this information to generate a logical to physical transformation suitable for the system and the wafer under measurement parameters.

  In some embodiments, the method includes one or more of the inspection systems captured for different portions of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Extracting one or more predetermined attributes of the output from the plurality of detectors. In this way, the method is directed to an inspection data region (eg, a specific subset of the region to be inspected) based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. Extracting a predetermined signal or image attribute. The extracted attribute (s) of the output from the one or more detectors includes, for example, the luminance or standard deviation of the signal or image for different portions of the pixel. In addition, the wafer may be a patterned wafer on which a pattern corresponding to design data is printed. Accordingly, the output attribute (s) are extracted based on knowledge about the output corresponding to the pattern formed on the wafer. In addition, information about the structure of the pattern formed on the wafer is extracted from the output of one or more detectors.

  The extracted attribute (s) of the detector output (s) can be used to generate an image of the attribute (s) across different portions of the wafer. Thus, the method includes generating a “design aware image” of the surface of the wafer. These images are used to determine one or more attributes of the wafer, such as the attributes of the wafer determined by metric. In this way, the inspection system extracts the attribute (s) of the output (such as a signal) from one or more detectors in a substantially precisely defined arrangement based on the design data or layout for the design data. It is used like a weighing tool. Thus, in this embodiment, different parts of the wafer can be handled essentially as weighing sites. In addition, using one or more extracted predetermined attributes of the output of one or more detectors of the inspection system, incorporated by reference as if described in full herein. One or more steps may be performed, such as those described in commonly-owned Kirk et al. US patent application Ser. No. 60 / 772,418, filed Feb. 9, 2006.

  The one or more attributes of the design data used in this embodiment include any of the design data attribute (s) described herein. In one such embodiment, the one or more attributes of the design data may be design data, different design data, or for a process layer from which wafer inspection data was captured, a different process layer, or some combination thereof, or Some combination of them is selected based on one or more attributes of inspection data already captured for the wafer, other wafers, or some combination thereof. Thus, one or more attributes of the design data in the design data space used in this embodiment are inspection data already collected from the same or different wafers for the same or different designs in the same or different process layers. It is selected based on the correlation with the attribute. Test data that has already been collected is stored in a data structure or in a knowledge base that is configured as described herein. Thus, one or more attributes of the design data are selected in this embodiment based on cumulative learning, historical data, or a training set of data.

  In other embodiments, the method may be used for different portions of a wafer based on the location of inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data. Extracting one or more predetermined attributes of the output from one or more detectors of the captured inspection system. The one or more attributes of the design data used in this embodiment include any of the design data attribute (s) described herein. In addition, the one or more attributes of the test data include any of the test data attribute (s) described herein. For example, in one embodiment, the one or more attributes of the inspection data may include one or more image noise attributes, or some combination thereof, if one or more defects are detected in different portions. Including. As such, the one or more attributes of the inspection data include, but are not limited to, image noise characteristics and / or detection / no detection of defects in the inspection data region. Extracting one or more predetermined attributes of the output is further performed as described herein. In addition, the extracted attribute (s) of the output are used as described further herein.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system described herein.

  FIG. 15 illustrates another embodiment of a computer-implemented method for determining the location of inspection data in the design data space. Note that the steps shown in FIG. 15 are not essential to the performance of the method. One or more steps can be omitted from or added to the method illustrated in FIG. 15, or the method can be implemented as is within the scope of this embodiment.

  The method shown in FIG. 15 is generally used for CBI. In this embodiment, data preparation phase 42 includes generating database 44. The database 44 includes a CAD layout of design data and one or more context layers of the design data. Database 44 has any suitable configuration known in the art and includes other data or information described herein. In addition, the data in database 44 is stored in other suitable data structures. Database 44 is generated by software 46 using GDSII file 48 and context layer (s) 50 as inputs. Software 46 may be any suitable software known in the art. In general, the software is configured as described further herein, although not shown in FIG. 15, to generate a database using the GDSII file and the context layer (s). ) Configured as executable program instructions (not shown in FIG. 15). The context layer (s) 50 is captured or generated in a manner known in the art and includes context information or data as described herein. In addition, the GDSII file 48 is replaced with other suitable data structures in which design data is stored.

  The method shown in FIG. 15 also includes a recipe setup phase 52. Recipe setup phase 52 includes a step 54 that is performed to determine alignment information 56. Step 54 includes scanning a die on the wafer and is performed by an inspection system configured as described further herein. Step 54 further includes selecting alignment sites on the wafer using data captured by scanning the wafer. The alignment sites on the wafer are selected as described herein. In addition, the alignment sites on the wafer are selected based on inspection swath layout information 58 and other suitable information as further described herein. The inspection swath layout information includes the swath information described herein and is determined as described herein. Selection of alignment sites on the wafer is performed automatically, semi-automatically (or under user assistance), or manually as further described herein.

  Step 54 may also include rendering an image corresponding to the alignment site on the wafer from the CAD layout information of database 44 or capturing other suitable data. For example, step 54 may include suitable data or images, such as a centroid of some features, that may be aligned to the alignment site on the wafer using a CAD patch 60 corresponding to the selected alignment site on the wafer. Or calculating the value of a geometric feature attribute. Step 54 further includes calculating an (x, y) mapping from alignment sites on the wafer to information obtained from CAD layout information. The alignment information 56 includes data for a predetermined alignment part and the (x, y) position of the predetermined alignment part in the design data space.

  The method shown in FIG. 15 also includes a wafer inspection phase 62. The wafer inspection phase 62 includes an initialization phase 64 and an execution phase 66. In an initialization phase 64 as shown in step 68, the method preloads alignment information 56 that includes data for a predetermined alignment site and the (x, y) position of the predetermined alignment site in the design data space. Including doing. As shown in step 70, the initialization phase further includes preloading the context layer (s) 72 from the database 44. The initialization phase further includes, as appropriate, rendering data for a given alignment site from polygons to pixels, as shown in step 74, which is performed as described in the specification. . The context layer 72 contains the context information described herein.

  In an execution phase 66, the method includes performing alignment and mapping of inspection data into the design data space as shown in step 76. This step is performed during wafer inspection. Alignment and mapping are performed as described further herein. The execution phase further includes applying the mapping to the context map, as shown in step 78. The context data is further mapped as described herein. The execution phase further includes applying a context map to the inspection data upon defect detection, as shown in step 80, which is performed as described in the specification. In addition, the execution phase further includes mapping defect coordinates to a context map, as shown in step 82, which is performed as described in the specification. The execution phase further includes an additional step 84 that filters the detected defects by context, classifies the defects, generates review samples, and others described herein. Or any combination thereof. Each additional step 84 is performed as described further herein. Each of the method embodiments shown in FIG. 15 includes other step (s) described herein. In addition, each of the method embodiments shown in FIG. 15 is performed by the system described herein.

  Program instructions for performing the methods as described herein are transmitted over or stored on a carrier medium. The carrier medium may be a transmission medium such as a wired, cable, or wireless transmission link. The carrier medium may further be a storage medium such as a read-only memory, a random access memory, a magnetic or optical disk, or a magnetic tape.

  FIG. 16 illustrates various embodiments of a system configured to determine the location of inspection data in the design data space. In one embodiment, the system includes a storage medium 86 containing design data (not shown in FIG. 16). The storage medium 86 can also store other data and information described herein. The storage medium includes any of the storage media described above or other suitable storage media known in the art. In this embodiment, the system further comprises a processor 88 coupled to the storage medium 86. The processor 88 is coupled to the storage medium in a manner known in the art. In this embodiment, the system is configured as a stand-alone system that does not form part of a process, inspection, metering, review, or other tool. In such an embodiment, the processor 88 receives and / or addresses data from other systems (eg, inspection data from an inspection system) via a transmission medium that can include “wired” and / or “wireless” portions. Configured as follows. Thus, the transmission medium is used as a data link between the processor and other systems. In addition, the processor 88 can send data to other systems via a transmission medium. Such data includes, for example, design data, context data, results of the methods described herein, inspection recipes or other recipes, or some combination thereof.

  The processor 88 may take a variety of forms, including a personal computer system, mainframe computer system, workstation, image processing computer, parallel processor, or other device known in the art. In general, the term “computer system” is broadly defined to include a device having one or more processors that execute instructions from a memory medium.

  However, in other embodiments, the system includes an inspection system 90. The inspection system 90 is configured to capture data for alignment sites on the wafer 92 and inspection data for the wafer. In an embodiment of a system that includes an inspection system, the processor 88 is coupled to the inspection system by methods known in the art. For example, processor 88 is coupled to detector 94 of inspection system 90 such that the processor receives data for alignment sites on the wafer and inspection data generated by the detector. In addition, the processor can receive other outputs of the detector, such as image data and signals. In addition, if the inspection system includes multiple detectors, the processor is coupled to each detector as described above.

  The processor 88 is configured to align data captured by the inspection system for alignment sites on the wafer with data for a predetermined alignment site. The processor is configured to align data according to the embodiments described herein. The processor 88 is further configured to determine the position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site in the design data space. The processor is configured to determine the position of the alignment site on the wafer in the design data space according to the embodiments described herein. In addition, the processor 88 is configured to determine the position of inspection data captured for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space. The processor is configured to determine the location of the inspection data in the design data space according to embodiments described herein. The processor is configured to perform other step (s) of the method embodiment (s) described herein.

  In one embodiment, the inspection system 90 includes a light source 96. Source 96 may be any suitable light source known in the art. The light source 96 is configured to direct light to the beam splitter 98. The beam splitter 98 is configured to allow light from the light source 96 to be incident on the wafer 92 at a substantially normal angle of incidence. Beam splitter 98 comprises suitable optical components known in the art. The light reflected from the wafer 92 reaches the detector 94 through the beam splitter 98. The detector 94 can be any suitable detector known in the art. The output generated by detector 94 is used to detect defects on wafer 92. For example, the processor 88 is configured to detect defects on the wafer 92 using the output generated by the detector. The processor can detect defects on the wafer using methods and / or algorithms known in the art. At the time of inspection, the wafer 92 is placed on the stage 100. Stage 100 may comprise any suitable mechanical and / or robot assembly known in the art. The detection system shown in FIG. 16 can also include other suitable components known in the art (not shown).

  As shown in FIG. 16, the inspection system is configured to detect specularly reflected light from the wafer. As described above, the inspection system shown in FIG. 16 is configured as a BF inspection system. However, the inspection system is replaced with an inspection system configured as a DF inspection system, an EC inspection system, an aperture mode inspection system, or other optical inspection system known in the art. In addition, the inspection system is configured to perform one or more inspection modes. For example, the inspection system shown in FIG. 16 is configured to perform DF inspection by changing the angle of incidence at which light is incident on the wafer and / or the angle at which light is collected from the wafer. In another example, the inspection system includes one or more optical components, such as apertures (not shown), positioned in the illumination and collection paths, and the inspection system is in EC mode inspection and / or aperture Configured to perform mode checking.

  In addition, the optical inspection system shown in FIG. 16 includes commercially available inspection systems such as 2360, 2365, 2371, 23xx systems available from KLA-Tencor. In other embodiments, the optical inspection system shown in FIG. 16 is replaced with an electron beam inspection system. Examples of commercially available electron beam inspection systems that can be included in the system of FIG. 16 include KLA-Tencor's eS25, eS30, eS31 systems. The embodiment of the system shown in FIG. 16 is further configured as described herein. In addition, the system is configured to perform other step (s) of the method embodiment (s) described herein. The system embodiment shown in FIG. 16 has all the advantages of the method embodiments described above.

  The methods and systems described above generally test by aligning data captured for alignment sites on a wafer (eg, BF patch images) with data for a given alignment site (eg, an image derived from a GDSII file). Perform alignment between data and design data. Additional methods and systems described herein generally perform alignment between inspection data and design data, and determine similarities between different defects using techniques such as statistical techniques ( (For example, without using a patch image or SEM image).

  The embodiments described herein are used for context-based setup, inspection, grouping by bin range, review, measurement, testing, analysis, or some combination thereof. The context used in these embodiments is design data or design related information, processes stored in a data structure of a design database or file (eg, GDS file, OASIS file, Open Access file, net list, etc.) Simulation results, electrical simulation results, pattern of interest (POI), hot spot information (eg, OPC, electrical test results, inspection results), process tool data (unfinished products in production), or Including any combination of In addition, these embodiments predict the yield impact of one or more defects and / or one or more groups of defects based on the results produced by the embodiments described herein. Including that. Predicting yield impact is performed as described further herein. Furthermore, the embodiments described herein are advantageously used to provide treatable yield related information relatively quickly.

  The embodiments described herein can be used to group defects detected by an inspection system that incorrectly determines defect placement coordinates (i.e., real defects have been reported). May be placed near the coordinates, but not exactly the reported coordinates). For example, the methods and systems described herein improve defect grouping even when the defect coordinates reported by the inspection system in an attempt to align the patterns with each other are not completely accurate. Used to search for patterns that are at least similar to those close to the reported defect location. In other cases, inspection images or review images (eg, SEM images) captured near the reported defect placement are compared to design data or overlaid on design data to identify defects in wafer space. An exact representation of the design data in the vicinity of the actual placement (as opposed to the placement of defects reported by inspection) and the defect location can be determined. Identify at least all instances of similar patterns in design data (including rotated, flipped, or some other distorted instance of the pattern) and group them into pattern groups according to bin ranges Can do. Then, the actual defect position in the wafer space determined as described above is compared with the arrangement with respect to the pattern group, and the defects arranged at the positions with respect to the pattern group within the predetermined tolerance range are grouped by the bin range. be able to. Such grouping of defects can be performed on-tool or off-tool and can improve the performance efficiency of the methods described herein (eg, coordinates relative to defect placement coordinates reported by inspection). The search range is reduced if there is inaccuracies). In particular, if there are coordinate inaccuracies, the source pattern determined based on the reported inspection coordinates is an approximate source pattern (the pattern is isolated or the coordinates of the defect happen to be substantially Unless it is accurate). Of course, the embodiments described herein are used with test results generated by a very accurate inspection system.

  One embodiment relates to a computer-implemented method that divides defects detected on a wafer according to bin ranges. In general, in the methods described herein, a population of defects selects a source defect, and design data (“source design data”) proximate to the location of the source defect in the design data space (eg, source design data) , All or part of the defect population) compared to the design data close to the position in the design data space (“target setting data”), and there is a match or at least similarity between the compared design data, Grouping based on design data (e.g., GDS design data) by assigning target defects to source defect groups. This comparison is based on a direct comparison between the source design data and the target design data. In addition, this comparison is performed after correcting for minor coordinate inaccuracies between the source and target defect locations in the design data space. Further, the comparison includes searching for source design data in the target design data that causes inaccuracies in coordinates at the source and target defect locations. Alignment and / or searching is improved by using a subpixel alignment technique performed as described herein. Furthermore, comparing the source design data and the target design data has an exact location between the source design data and the target design data, or is similar between the source design data and the target design data Is performed to determine if there is an inexact match. Each of the above steps are further performed as described herein.

  After the target defect population is tested for source defects, the next source defect is selected. A defect that has not yet been grouped is selected as the next source defect. The above steps are repeated until all defects are grouped (or at least tested). The defect population used in the methods described herein can be all defects detected on a wafer, all defects detected on multiple wafers, or detected on one or more wafers. A subset of the detected defects (eg, defects detected on one or more wafers and identified as being near the hot spot). In addition, the methods described herein are performed on the entire defect population or on a subset of defects in the entire defect population (this is based on design function blocks such as logic, memory, etc.). Selected). Grouping by bin range is performed as automatic single pass or multi-pass grouping.

  The method includes comparing portions of the design data that are proximate to the location of the defect in the design data space. For example, as shown in FIG. 17, this method can be used to identify portions 102 of design data (not shown) that are close to the location of the defect 104 in the design data space 106 and defects 110 in the design data space 106. Comparing a portion 108 of design data (not shown) in proximity to the location. The defect 104 is referred to herein as a “source defect” and the defect 110 is referred to herein as a “target defect”. Design data proximate to the position of the defect in the design data space defines background pattern data or background information for the defect.

  As shown in FIG. 17, the portion 102 is larger than the defect 104. The dimensions (x and y directions) of the portion 102 are selected by the user. In addition, the portion 108 is larger than the defect 110. The dimensions of the portion 108 are also selected by the user. The dimension of the portion 108 is typically larger than the dimension of the portion 102 as further described herein. Alternatively, the dimensions of those parts are selected (eg, automatically) by the computer-implemented methods described herein.

  In one embodiment, the dimensions (x and y directions) of these portions are determined at least in part by the location of the defect reported by the inspection system used to detect the defect, the inaccuracy of the inspection system coordinates. It is determined based on one or more attributes of the design data, defect size, inspection system defect size error, or some combination thereof. For example, the method includes defining a portion of design data (ie, a “pattern window”) centered on the reported defect placement. The pattern window has a width and height that are larger than the size of the defect and is selected to account for error in the defect location due to coordinate inaccuracies. For example, if the defect placement coordinates reported by the inspection system are accurate to about ± 3 μm, the pattern window is all from the reported x and y coordinates of the defect placement for a total minimum size of about 6 μm × about 6 μm. In the direction of at least 3 μm. Thus, the better the coordinate accuracy of the inspection system, the smaller the pattern window, resulting in faster and more accurate grouping. The dimensions of the pattern window are further selected such that the pattern window includes a “sufficient” amount of background pattern data, such as a sufficient number of features in the design data. In addition, when the design data in the pattern window is compared to the clip, the pattern window dimensions are selected so that the pattern window includes the entire polygon that is only partially included in the clip.

  The portion of the design data used in the method described herein includes a clip of the design taken around the location of the defect in the design data space. The term “clip” is generally defined as an area of design data around a defect and can be considered to be in the vicinity of the defect. Polygons define a pattern within a clip, but polygons can be partially expanded beyond the clip. Clips used in the methods described herein for some of the plurality of defects can take one or more different dimensions. However, the portion of the design data used in the methods described herein includes design data in an extended bounding box (EBB) around a range of locations where defects may be located . The EBB is selected based on the coordinate accuracy of the inspection system used to detect defects and defect sizes (and possibly inspection system defect size errors). For example, as the coordinate accuracy of the inspection increases, the size of the EBB is reduced. The smaller the EBB, the more accurately the position of the defect within it is determined relative to the larger EBB, and the more accurate position of the defect within the EBB is used to determine one or more attributes of the defect (eg, in the design). The defect position, defect classification, and root cause of the defect) can be determined with higher accuracy, so that the EBB is preferably smaller. In addition, one or more dimensions of the EBB used for at least some of the plurality of defects may be different. The EBB is generally smaller than the clip and can represent where the defect may be located.

  In other embodiments, the dimensions of at least some of these portions are different. For example, as shown in FIG. 17, the difference in size between the portion 108 and the defect 110 is larger than the difference in size between the portion 102 and the defect 104. In other words, the area of the target portion around the target defect is larger than the area of the source portion around the source defect. Thus, the target portion contains more design data than the source portion.

  The source portion of the design data can be compared with different areas of the target portion of the design data. Thus, the method includes searching for a source portion of design data in the target portion. For example, the source portion of the design data can be compared to one region of the target portion, as shown in the source and target portion overlay 112. After this comparison, the position of the source portion relative to the target portion is changed so that the design data in the other region of the target portion can be compared with the source portion of the design data. Thus, the method includes “sliding” the source portion of the design data around in the target portion until a match is identified or until all regions of the target portion are compared to the source portion.

  Comparing parts of the design data is performed using information available for the comparison step. For example, the part of the design data to be compared is the part of the design data stored in a data structure such as a GDS file. In addition, comparing parts of the design data includes comparing polygons in those parts. In other embodiments, the method includes converting a portion of the design data proximate to the location of the defect in the design data space to a bitmap prior to the comparing step. For example, a polygon in the design data portion is converted into a bitmap in order to speed up the processing. The portion of design data is converted to a bitmap using any suitable method or system known in the art. For example, a portion of the design data can be obtained using the method or system described in US Patent No. 7,030,997 of Neuerther et al., Which is incorporated by reference as if described in its entirety herein. Converted to a bitmap. In one such embodiment, comparing the portions of design data includes comparing bitmaps. Comparing the bitmaps is performed in any suitable manner. In addition, comparing portions of the design data includes comparing one or more attributes of the design data in those portions. The one or more attributes to be compared include the design data attribute (s) described herein.

  The method further includes determining whether the design data in those portions is at least similar (similar or exactly the same) based on the result of the comparing step. If one or more attributes of the design data in those parts are determined, the grouping is the common pattern similarity, the common attribute attribute, the common attribute attribute in the feature space. Based on similarity, or some combination thereof. For example, in one embodiment, determining whether design data in those portions is at least similar includes determining whether common patterns in the design data in those portions are at least similar. However, this is performed as described further herein. In other embodiments, determining whether design data in those parts is at least similar includes determining whether common attributes in the design data in those parts are at least similar. This is performed as described further herein. In additional embodiments, determining whether the design data in those portions is at least similar includes determining whether common attributes in the feature space of the design data in those portions are at least similar. However, this is performed as described further herein. In addition, the method includes determining how similar different regions in those parts are. In addition, the design data in those parts may be slightly offset from each other or may contain slightly different design geometries, but those parts are similar to each other if they contain significant common geometry. Determined. This method compares the design data close to the position of each defect in the design data space with the design data close to the position of all other defects in the design data space, and determines which defect based on the “background” pattern. Determining whether they are similar to each other.

  Determining whether the design data in those parts is at least similar is preferably not performed based on whether the defect is located at the same location in the design data. In other words, defects grouped by bin range based on “background” by the method described herein are not necessarily placed in the same position with respect to patterns, features, polygons, or geometry in the design data. Not necessarily. By not relying on defect location matching with respect to design data, the method can more accurately separate defects according to bin range. For example, two defects are in the same type of pattern but are located at different positions in the pattern. In addition, systematic defects within the POI may be localized but may not be localized. However, such defects are due to or related to the same pattern-based problem. Therefore, by separating defects according to the bin range without depending on the similarity between the actual defect positions in the design data, it becomes possible to more accurately classify the defects according to the bin range. More accurate assessment of production problems, and yield prediction and control based on these systematic problems. Determining whether the portions of the design data are at least similar is performed using a suitable algorithm. This method is therefore used as a “similarity checker”. Since the target portion may be larger than the source portion being compared against the target portion, the similarity checker is advantageously used when the actual defect location coordinates in the design data are inaccurate.

  In the embodiment shown in FIG. 17, the entire source portion is compared to different regions of the target portion. In some embodiments, the method includes comparing the entire design data in at least some of those portions with design data in other portions. In addition, the method includes comparing the entire source portion of the design data with different regions of the target portion of the design data. The method then includes searching for a target portion for design data that is at least similar to the entire source portion of the design data.

  The method further includes grouping the defects according to bin ranges such that the positions of the design data proximate to the position of the defect in each of those groups are at least similar. Thus, the method includes grouping defects according to bin ranges based on the design data and / or the context of the design data proximate to the position of the defect in the design data space. For example, using polygons in at least similar or matching portions of design data, defects can be grouped according to bin ranges in an unsupervised manner. In addition, the step of separating according to the bin range includes at least two defects according to the bin range into at least one group such that the design data proximate to the location of the at least two defects within the at least one group is at least similar. Including dividing. Furthermore, the method does not group defects according to bin ranges in rare cases where none of the portions of the design data proximate to the location of the defect in the design data space are determined to be at least similar.

  The method further includes storing the result of the grouping step according to the bin range on a storage medium. Results divided according to bin ranges include the results described herein. In addition, the storing step includes storing the result of the step of dividing according to the bin range in addition to the other results of the steps of the method embodiments described herein. Results are stored by methods known in the art. In addition, the storage medium may be the storage medium described herein or other suitable storage medium known in the art. In any of the method or system embodiments as described herein, after the results are stored, the results in the recording medium can be accessed and utilized. Further, the results can be stored “permanently”, “semi-permanently”, temporarily, or for some period of time. For example, the storage medium can be random access memory (RAM), and the result of the step of dividing according to bin ranges cannot necessarily persist in the storage medium.

  Determining whether the portions of the design data are at least similar includes comparing the result of the comparing step with a predetermined criterion for similarity. For example, the result of the comparing step can be compared with a threshold value. If the design data in those parts is at least similar by at least this threshold, the method can group the defects according to the bin range. In another example, the result of the comparing step can be compared to a “similar percentage” value. If the design data in those parts is at least similar by at least this percentage, the method can group the defects according to the bin range.

  In any case, this method is used when similarity checks are performed on two or more parts of the design data (eg, GDS pattern clips) and a common pattern in the two or more parts is identified. , Including grouping defects according to bin range. The results obtained by determining whether the design data in those parts are at least similar include an indicator that indicates whether the design data in the source part is found in the target part. In addition, the central point of the common geometry can be regarded as an approximate design data space location of systematic defects. Therefore, the (x, y) coordinates of the design data space position of the defect of each group are adjusted (transformed) according to the center point of the geometry corresponding to each group. A coordinate correction vector (or error vector) is determined for the defect divided by each bin range based on the design data space coordinates of the defect and the center point of the common geometry corresponding to the group into which the defect is divided according to the bin range. . To determine the overall systematic uncertainty in the design data space coordinates of the defect location (wafer space and design data space conversion error plus error in the reported coordinates), this method uses a statistically significant number of defects. Determining the average of their transformations or error vectors. The method further includes determining all standard deviations of the error vector and determining an average of only those vectors that fall within ± 1 standard deviation or ± 3 standard deviations. In this way, outliers that can impair the average value can be excluded from the calculation. The determined average value is further used as a global correction value. For example, the global correction values are applied to additional design data space coordinates of defect locations determined by wafer space for design data transformation so that a more accurate overlay is determined in subsequent data processing steps.

  The result of the determining step further includes an x and y offset between the target portion and the location of the source portion within the target portion where at least similar design data was found. These x and y offsets are used to optimize the method of dividing according to bin range. For example, when the parts are first compared, the source part is positioned within the target part such that the center points of the two parts are aligned. However, a predictable or repeatable offset (x) determined between the first used position of the source part in the target part and the position of the source part in the target part where at least similar design data is found. (And / or in the y direction), this offset can be used to tune the overlay used in the comparison step of the method of dividing according to bin range.

  In some embodiments, the design data in these portions includes design data for multiple design layers. Thus, this method separates defects according to bin ranges by checking one design layer for defect background similarity, or one for defect background similarity (ie, multilayer background similarity). It includes separating defects according to bin range by checking a set of design layers. For example, when inspecting a polycrystalline silicon layer (eg, a gate electrode layer) on a wafer, the underlying diffusion layer may be visible to the inspection system and thus affect the inspection results. At this time, the design data included in those portions includes design data for the polycrystalline silicon layer and the diffusion layer in order to improve the accuracy of grouping by the background-based bin range. In addition, the underlying design layer is not visible to the inspection system. However, by using design data for multiple design layers, it is at least similar or located close to the part of the design data that is located on different design data on the underlying layer Defects can be divided into different groups according to bin range.

  Regardless of whether design data in the source portion is found in the target portion, the method includes comparing the source portion to other portions of the design data that are proximate to the location of other defects in the design data space. Since multiple target defects located in close proximity to design data that is at least similar to or the same as the design data in the source portion are detected on the wafer, the design data in the source portion is Comparing with design data can be performed.

  In one such example shown in FIG. 17, portion 102 is compared to portion 114 of design data (not shown) that is proximate to the location of defect 116 in design data space 106. The dimensions of the portion 114 are selected as described herein. The source portion of the design data is compared with design data in different regions of the target portion as described further above. The method further includes determining whether the design data in the source portion is at least similar to at least a portion of the design data in the target portion based on the results of the comparison, which is further described above. To be executed. These portion overlays 118 illustrate the location of the source portion within the target portion where at least similar design data was found. Thus, the method includes grouping the defects 104, 116 according to the bin range, since it is determined that the design data in the portion 102 is at least similar to at least a portion of the design data in the portion 114. It is. In addition, since the design data in the source portion is determined to be at least similar to at least a portion of the design data in both target portions, the defects 104, 110, 116 are grouped by bin range.

  In other such examples, portion 102 is compared to portion 120 of design data (not shown) that is proximate to the location of defect 122 in design data space 106. The dimensions of the portion 120 are selected as described herein. The source portion of the design data is compared with design data in different regions of the portion 120 as further described above. The method further includes determining whether the design data in the portion 102 is at least similar to at least a portion of the design data in the portion 120 based on the result of the comparison, which is further described above. To be executed. The overlay 124 of the portions 102, 120 illustrates the position of the portion 102 within the portion 120 where at least similar design data was found. Thus, the method includes grouping the source and target defects 112 according to the bin range. In addition, since the design data in the source portion is determined to be at least similar to at least a portion of the design data in the three target portions, the source defect and the three target defects are grouped by bin range. The above steps are performed until the background information for each defect detected on the wafer is compared with the background information for all other defects detected on the wafer.

  As described above, this method may be in close proximity to the location of the defect in the design data and / or design data space, possibly in combination with other information such as one or more attributes of the design data and / or design layout. And classifying defects according to bin ranges based on the context of the design data being arranged. In contrast to other methods of separating defects according to bin range based on contextual information, the method described herein uses grouping by bin range based on background information as printed on the wafer. Do not execute. Instead, the method described herein performs grouping by bin ranges based on background information as defined in the design data. Thus, the method described herein performs grouping by background-based bin ranges regardless of whether or how the design data is printed on the wafer. can do.

  Such irrelevance to the design data printed on the wafer is particularly advantageous for the PWQ method and the Focus Exposure Matrix (FPM) method, where the design is printed on the wafer. Data varies (sometimes dramatically) with respect to the process window parameters used in such methods, so the accuracy of the defect grouping method by bin range based on the image of the design data printed on the wafer Decreases. In so applying empirical techniques such as PWQ, this method is based on improved background-based bin ranges by using GDS clips or excerpts of design data at the location of defects in the design data space. Realize grouping. At that time, grouping by bin range is executed by a common pattern. Defects that are separated according to bin range are classified individually or collectively as a group of defects as further described herein. For example, the method classifies defects based on one or more attributes of the design data (eg, one or more attributes of the design data that are located proximate to the defect location in the design data space). This is performed as described further herein.

  Defects detected on the wafer are classified according to the bin range by design data close to the design data space position of the defect, so the position of the defect in the design data space is determined before grouping by bin range is performed. The In one embodiment, the method includes capturing data for x and y coordinates of detected defect locations in the design data space (or determining a transformation function), which is described herein. To be executed. In other embodiments, the method includes determining the position of the defect in the design data space by comparing data captured by the inspection system for the alignment site with data for a predetermined alignment site. Capturing data for alignment sites on the wafer is the approximate wafer space position of the alignment sites on the wafer using product layout data, reticle frame data, and stepper recipe (or input to the stepper) as appropriate. And capturing data at their approximate locations. Such comparison and determination is performed as described further above. In addition, the method includes determining the position of at least a portion of the defect in the design data space by comparing the data captured by the inspection system for the alignment site on the wafer with the data for the predetermined alignment site. . The positions determined for at least some of the defects can then be used to determine the position of other defects in the design data space (eg, converting the reported defect positions to defect positions in the design data space). By generating and using transformations). Determining the location of the defect in the design data space is further performed according to any of the embodiments described herein.

  Sometimes, not all of the above data is available, or the wafer may not be properly aligned with the design data. In such cases, it may be beneficial to empirically determine some of the conversion information from the wafer during inspection or review. In one embodiment, the method includes a defect in the design data space by comparing the data captured by the inspection system upon detection of the defect with the data captured by the review system in an arrangement in the design data space determined by the review. Determining the position of. Thus, the method includes aligning inspection results for one or more defects with review results captured in a design data space arrangement determined by review. In addition, this method can be used to compare at least some of the defects by comparing the data captured by the inspection system at the time of defect detection with the data captured by the review system in an arrangement in the design data space determined by the review. Including determining a design data space location. The positions determined for at least some of the defects are then used to determine the position of other defects in the design data space (eg, generate a transformation that converts the reported defect positions to defect positions in the design data space. By using). However, this approach results in wafer scale offsets that can be complicated by inaccuracies in the coordinates of the inspection system. Thus, if there is a coordinate inaccuracy in the reported location of the defect, it may be convenient to base the transformation function on a statistical sample of measurements.

  After the position of the defect in the design data space is determined, the portion of the design data around the determined position is described herein, where the extracted portion of the design data divides the defect according to the bin range. Extracted to be used to perform other steps. In addition, prior to using the extracted portion of the design data for bin range grouping, each (or one or more) of the extracted portions is mirrored, rotated, scaled, translated (Shift), or some combination thereof, is applied to each of the extracted parts to generate a set of parts including each. These sets of parts are used for grouping by bin range to increase the accuracy of the bin range grouping method.

  The method further includes dimensions in the x direction (eg, width), dimensions in the y direction (eg, length), dimensions in the z direction (eg, height), and other (multiple) described herein. Determining one or more attributes of detected defects, such as attributes), or some combination thereof. One or more attributes are organized and / or stored in a suitable data structure such as a table or list. In other embodiments, dividing defects according to bin ranges is such that when defects are grouped according to bin ranges, portions of the design data proximate to the design data space location of the defects in each of those groups are at least similar, Grouping such that one or more attributes of defects in each of those groups are at least similar. In one such embodiment, the one or more attributes of the defect include one or more attributes of the result of the inspection in which the defect was detected, one or more parameters of the inspection, or some combination thereof. . For example, one or more attributes of the inspection result include one or more other parameters of the inspection, such as polarization, focusing angle, incidence angle, etc., at which optical modes and / or defects are selectively detected. In addition or alternatively, the one or more attributes include any of the other attribute (s) of the defects described herein. As described above, the grouping based on the bin range is executed so that the defects are divided into a plurality of groups based on the design data and (a plurality of) defect attributes. Such grouping by bin range is performed such that different defect types or defects having different attribute (s) arranged in at least similar parts of the design data are divided into different groups.

  In some embodiments, defects separated according to bin ranges as described herein are detected by optical inspection or electron beam inspection. The light or electron beam is performed by the inspection system described herein. In other embodiments, defects separated according to bin ranges as described herein are detected with PWQ or FEM methods, which are performed as described herein. . The embodiments described herein are particularly useful for defects detected with PWQ or FEM methods. For example, the method embodiments described herein can be used to filter defects detected with PWQ and FEM methods so that potential systematic problems can be more easily and more accurately identified. This is performed as described further herein. In addition, the method embodiments described herein are used to divide defects into useful groups that are detected by PWQ or FEM according to bin ranges, which is further described herein. To be executed. Furthermore, the method embodiments described herein are used to prioritize for review, measurement, or testing of PWQ or FEM defects separated according to bin ranges, which Performed as described further in the book. In addition, the method includes grouping inspection and / or electrical test defects according to bin ranges based at least on similar design / layout patterns.

  In one embodiment, the inspection system used to detect defects that are separated according to bin ranges in the embodiments described herein is aligned to three or four alignment sites on the wafer. The alignment site is selected as described further above. In addition, an alignment site that includes one or more alignment features, patterns, and / or geometries that are visible on the physical wafer and in the design data or layout is described herein. Can be used in the way. After aligning the inspection system to the alignment site, the position accuracy of the stage, rotation error, x and y translation error, magnification (enlargement / reduction) error, or some combination thereof is corrected. This correction is performed when the inspection process is performed, or is performed after the processing (that is, performed after the inspection result is output). The correction is based at least in part on the result of comparison of the coordinates for the alignment site reported by the inspection system with the reference coordinates for the same alignment site.

  In some embodiments, the method includes obtaining coordinates for three or four alignment sites in a plurality of dies on the wafer, such as the left, right, top, bottom, and center dies of the wafer. In other embodiments, the alignment sites on the wafer are located on three different dies on the wafer. One such embodiment is illustrated in FIG. As shown in FIG. 18, the wafer 126 includes a plurality of dies 128. The alignment site 130 is located on the dies 128a, 128b, 128c. Although alignment sites are shown only on three dies, it will be understood that alignment sites may be located on each die on the wafer. A subset of the alignment sites for each die or the alignment sites within a subset of the dies can be used in the methods described herein.

  The method further includes identifying three common alignment sites of triangular distribution within the die (ie, alignment sites common to the die printed on the wafer and design data (eg, GDS layout)). For example, as shown in FIG. 18, the alignment sites 130 are arranged in a triangular distribution within the dies 128a, 128b, 128c. In one such embodiment, three different dies are further distributed on the wafer in a predetermined arrangement (eg, a triangle or other arrangement). For example, as shown in FIG. 18, the dies 128a, 128b, 128c are arranged in a triangular array 132 on the wafer 126. Thus, the method includes aligning an image (eg, BF and / or DF image) captured by the inspection system for an alignment site on the wafer with data for a predetermined alignment site. The method includes mapping the coordinates of inspection data captured by the inspection system to design data coordinates (eg, GDS coordinates) and creating a transformation matrix. The transformation matrix can be expressed in a suitable format as follows.

  These alignment site coordinates are further used to perform “tool matching” (eg, automatically) to eliminate coordinate differences between inspection systems. One advantage of such a method is that these coordinates can be determined individually and automatically for each inspected wafer, thereby forming a set of correction factors for each wafer. Another advantage of such a method is in the inspection system or other system on the wafer that may use the determined coordinates to reduce the alignment accuracy between the inspection data and the design data in some other way. Coordinate drift (eg, coordinate drift caused by accumulated errors, stage movement errors, and errors caused by mechanical, electrical, thermal noise) can be determined.

  As described above, comparing design data in those portions includes comparing the entire design data in at least some of those portions with design data in other portions. Thus, the result of such a comparison can be used to determine whether all design data in the source portion is at least similar to at least a portion of the design data in the target portion. However, in alternative embodiments, comparing design data in those parts includes comparing different regions of design data in at least some of those parts with design data in other parts, It is carried out as described further herein. Further, the design data in multiple regions of the source portion may be at least similar or identical to the design data in the target portion region, but the results of such a comparison can be used to A maximum region of design data in a source portion that is at least similar to or identical to a similarly sized region of design data can be identified. Thus, the method includes determining whether design data proximate to the location of the source and target defects in the design data space is “similar” or at least similar. This method is therefore quite effective at certain design layers in separating defects according to bin range on a background basis, as described herein.

  One such embodiment of the method is illustrated in FIG. For example, as shown in FIG. 19, the method defines a portion 134 of design data (not shown) that is proximate to the location of the defect 136 in the design data space 138. Defect 136 is referred to herein as a “source defect”. Defining the design data portion 134 includes selecting the size of the portion, which is performed as described further above. The method further includes dividing, segmenting, or partitioning portions of the design data into one or more different regions. For example, as shown in FIG. 19, the portion 134 is divided into four different regions 140, 142, 144, 146. The different areas into which the portion 134 is divided are in this case called “source quadrants”. In FIG. 19, the portion 134 is shown as being divided into four quadrants, but it will be understood that the portion is divided into any suitable number of regions. All regions can have the same size, or all or some of the regions can be different sizes.

  In this example, the method compares the design data in source quadrants 140, 142, 144, 146 with a portion 148 of design data (not shown) that is close to the location of defect 150 in design data space 138. Including that. The defect 150 is referred to herein as a “target defect”. As shown in FIG. 19, portion 148 is wider than defect 150 and is at least as large as portion 134. The dimensions of the portion 148 are selected as described further above.

  Compare the design data in each of the source quadrants with the design data in different regions of the target portion. Thus, the method includes searching for design data in each of the source quadrants in the target portion. In this example, the method further includes determining whether the design data in the source quadrant is at least similar to the design data in the target portion based on the result of the comparing step. For example, the method includes determining how similar the design data in each of the source quadrants is to the design data in the target portion. The design data that is determined to be at least similar to the design data in the target portion is not in any, part, or all of the source quadrant. As shown in overlay 152, the design data in three of the four source quadrants is the design data in the region of portion 148 at the location of source quadrants 140, 144, 146 shown in overlay 152. Was determined to be at least similar.

  Thus, the method includes comparing design data in the source quadrant with design data in the target portion to determine at least which defects can be grouped according to bin ranges based on the corresponding design data. The result of determining whether the design data in each of the source quadrant and target portion is at least similar is that the number of source quadrants and which source quadrant contains design data that is at least similar to the design data in the target portion. It includes an indicator that indicates whether it has been determined. The result of the determining step may further include an x and y offset between each of the source quadrants in the target portion where design data at least similar to the target portion is found. Whether source defects are grouped together with target defects by bin range, how many source quadrants, and which source quadrants have been determined to contain design data that is at least similar to the design data in the target portion, And design data that is at least similar to the target portion is determined based on an offset between each of the source quadrants in the target portion where it was found.

  In some embodiments, the design data in each of the source quadrant and target portion includes design data for multiple design layers. Thus, this method either separates defects according to bin ranges by checking one design layer for at least similar design data or at least a set of design layers for similar design data (e.g., multiple Divide the defects according to bin range by checking the multi-layer).

  Regardless of whether the design data in the source quadrant has been determined to be at least similar to the design data in the target portion, this method allows each of the source quadrants to be located in the design data space of other defects. Including comparing with other parts.

  In one such example, the design data in the source quadrants 140, 142, 144, 146 is compared to a portion 154 of design data (not shown) that is proximate to the location of the defect 156 in the design data space 138. Portion 154 is configured as described above. The design data in the source quadrant and portion 154 is compared as described above. The method further includes determining whether the design data in each of the source quadrants is at least similar to the design data in portion 154, which is performed as described further above. As shown in overlay 158, two of the four source quadrants (eg, quadrants 144, 146) are at least similar to the design data in portion 154 of the source quadrant location shown in overlay 158. It is determined that the design data is included. Therefore, in this method, it is determined that the design data close to the positions of the defects 136 and 156 in the design data space are not very similar to the defects 136 and 150. Determining whether the design data proximate to the location of the defects 136, 156 in the design data space is small enough to divide the defects 136, 156 into the same group according to the bin range, as further described above. Can do.

  In other such examples, the design data in the source quadrants 140, 142, 144, 146 is compared to a portion 160 of design data (not shown) that is proximate to the location of the defect 162 in the design data space 138. The Portion 160 is configured as described above. The design data in the source quadrant and portion 160 are compared as described above. The method further includes determining whether the design data in each of the source quadrants is at least similar to the design data in portion 160, which is performed as described further above. As shown in overlay 164, two of the four source quadrants (eg, quadrants 142, 144) are at least similar to design data portion 160 of the source quadrant location shown in overlay 164. It is determined that the design data is included. Therefore, in this method, it can be determined that the design data close to the positions of the defects 136 and 162 in the design data space is not very similar to the design data close to the positions of the defects 136 and 150 in the design data space. Determining whether the design data proximate to the location of the defects 136, 162 in the design data space is small enough to divide the defects 136, 162 into the same group according to the bin range, as described further above. Can do.

  The quadrant information determined as described above is stored and / or displayed. This information is used for setup, verification, and troubleshooting purposes.

  The method further dynamically compiles a table, list, or other data structure of a unique pattern in the design data, and the portion of the design data proximate to the location of the defect in the design data space. Or performing on-tool classification of systematic and nuisance defects (eg, defects that are neither real nor noticeable) by comparison with patterns in other data structures. The dynamically created pattern set (or static pattern set) is stored in a data structure such as a library together with a design base classification (DBC) associated with each pattern. Thus, DBC defines groups into which defects are divided according to bin ranges, and the unique pattern includes an example of POI design. At that time, the design data close to the design data space defect position is not compared with the design data close to the other design data space defect position, but is compared with the unique pattern in the dynamically generated pattern set. Such a comparison is performed as described further herein. For example, one embodiment that can utilize such a data structure (which may or may not be dynamically generated) is described in detail below for defects detected on the wafer. A computer-implemented method for assigning a classification.

  In addition, in some embodiments, the computer-implemented method is performed by an inspection system that is used to detect defects. Thus, dividing defects according to bin ranges is performed “on tool”. One advantage of running this method on-tool is that it can reduce the time to results. This method is performed on-tool after a defect is detected (eg, while other defects are detected or during subsequent inspection, analysis of inspection results, reviewing, etc.). In addition, the data used to locate potential systematic defects or systematic defects (hot spots) and group by bin range is stored in a data structure (eg, hot spot database), Used for inspection comparison (monitoring). Therefore, grouping by bin range is performed during inspection to facilitate classification (grouping by bin range for discovery, filtering or monitoring).

  In an alternative embodiment, the computer-implemented method is performed by a system other than the inspection system used to detect defects. Thus, the method embodiments described herein are performed “off-tool”. The system for performing the method off-tool can be configured to perform, for example, a microscope (optical or electron beam), a review system, a system that is not loaded with a wafer (eg, a stand-alone computer system), or a method. There are other suitable systems known in the art. For example, the method is performed after defect detection in the second pass of the wafer where a microscope is used to capture an image of at least a portion of the detected defects. Such image capture may cause the electron beam microscope to fail to image some of the defects (eg, defects that are not visible to the electron beam microscope, such as defects located below the top surface of the wafer). Executed using. Image capture is performed off-line and is used to increase the ability to sample defects for review. Separating defects according to bin ranges is used for defect analysis and sampling as further described herein.

  In some embodiments, the method includes identifying hot spots in the design data based on the result of dividing according to bin ranges. Thus, dividing according to design-based bin ranges is used for hot spot discovery. In addition, hot spot discovery is performed “on-tool”. The method further generates one or more attributes such as generating a data structure containing the discovered hot spots, and hot spots such as placement, design data close to the location of the hot spots, etc. Generating a data structure including. Data structures include lists, databases, and files. Hot spots are used for hot spot management (sometimes on-tool). Hot spot management includes discovering hot spots, generating hot spot data structures using on-tool pattern grouping, and hot spot monitoring. Performed as described further in the book. In addition, hot spots discovered by grouping by design-based bin range are used as inputs for DesignScan, PWQ, DOE, and reviews. Alternatively, hot spots used in the methods described herein are discovered using other methods or systems known in the art, such as a reticle inspection system.

  FIG. 20 illustrates input to and output from module 166 configured to perform a computer-implemented method of separating defects detected on a wafer according to bin ranges in accordance with embodiments described herein. One embodiment is illustrated. Module 166 serves to function as a GDS pattern checker (accuracy checker for portions of design data or design data close to the design data space location of two defects), and / or a similarity checker (inaccuracy checker) Composed. The module is configured to perform one or more of the steps described herein on or off tool. For example, the module is configured to perform one or more of the steps described herein on-tool after processing (eg, on-tool, after defect detection). In addition, the module is configured to perform one or more of the steps described herein upon defect detection. A module performs other functions described herein, such as defect organization, if the module is configured to perform on-tool one or more of the steps described herein. Configured as follows.

  Input to module 166 includes defect list 168. In one embodiment, defect list 168 includes defect information, such as information contained in a KLARF file or other standard file generated by an inspection system. The input to the module can also include coordinate conversion information determined as described above and design data. In such an embodiment, module 166 is configured to convert the position of the defect in defect list 168 as reported by the inspection system to the position of the defect in the design data space.

  Alternatively, module 166 performs functions in wafer space by accessing transformed design data space coordinates provided through other software modules (software modules configured to perform conversion functions). Configured to do. In another alternative, the defect list 168 includes the position of the defect in the design data space. In such an embodiment, the defect location reported by the inspection system is converted to a defect location in the design data space by another software module. Such defect information may be stored in a suitable data file format or in program means via intra-process or inter-process communication between collections of computing hardware on the same computing hardware or networked. To the module 166. In this manner, defect information is provided to module 166 by another system via a transmission medium that couples the module to the other system. Transmission media includes any suitable transmission media known in the art and includes "wired" and "wireless" transmission media or some combination thereof.

  Additional inputs (not shown in FIG. 20) are further provided to module 166 to perform one or more steps of one or more embodiments described herein. Used by module. Additional inputs include other available defect and / or design data information, such as electrical inspection data, defect information for multiple wafers, hot spot or weak spot information ("weak spot" is not limited) Is generally defined as the placement of potential weaknesses in a design identified by model-based simulation such as post-OPC validation software and, but not limited to, empirical methods such as PWQ), search window size (E.g., the size of the location of the design data close to the location of the source and target defects in the design data space as described above or the enlargement of the source defect and the enlargement of the target defect), some predetermined criterion of similarity (e.g. Threshold), or some combination thereof.

  In addition, hot spots are grouped in advance based on design data. For example, hot spots that are located in proximity to at least similar design data correlate with each other, and embodiments of the methods and systems described herein may provide such correlation of hot spots. Execute. Correlated hot spots can be used to separate defects according to bin range as described further herein. In one such embodiment, module 166 groups defects according to bin ranges so that defects in each group have locations in the design data space that are at least similar to the locations of only hot spots that correlate with each other. Configured to divide. In this way, the module is configured to divide defects according to bin ranges without using design data. In addition, one or more attributes of correlated hot spots can be determined for later use in analysis (eg, yield information such as KP can be determined for correlated hot spots). Thus, when defects are grouped according to bin ranges corresponding to correlated hot spots, the module reports the expected yield effect determined for the correlated hot spots for the defect group.

  Module 166 is configured to function as a GDS pattern checker by separating defects according to bin range in defect list 168 by “checking” design data that is close to different defect locations in the design data space. The Thus, the module 166 is configured to group the defects according to the bin range so that the defects in each group are located in the design data space adjacent to the matching design data. In addition or alternatively, the module 166 acts as a similarity checker by separating defects according to bin ranges in the defect list 168 by checking the similarity of design data close to different defect locations in the design data space. Configured to work.

  The output of module 166 includes an output 170. The output 170 may be, but is not limited to, when defects are divided into the same group according to the x and y coordinates of the defect location as reported by the inspection system, the x and y coordinates of the defect location in the design data space, and the bin range. Identification symbol of the group in which the defect is divided according to the bin range (for example, 1, 2, 3, a, b, c, etc.) (for example, when the defect is divided into the same group according to the bin range, the identification symbol is the same) And x and / or between the center of the target portion and the center of the region in the target portion where design data that matches or at least resembles the design data in the source portion is located. Contains a list of various information, including shifts or offsets in the y direction. The output includes one or more data structures having a suitable format known in the art (eg, a normal text file format). In addition, the output may be stored on a suitable storage medium known in the art for later access and / or analysis. The output is stored and used as described further herein.

  In addition, or alternatively, as shown in FIG. 21, the output of module 166 can be used to determine the location of each defect in the design data space and the location of each defect in the design data space. It includes a table that exemplifies how similar (eg,% similarity) to the design data proximate to the location. In the example shown in FIG. 21, the portion of the design data close to the positions of defects 1 and 2 in the design data space has 40% similarity, but the positions of defects 1 and 3 in the design data space. The portion of the design data close to is 95% similar. In this way, the method can use the output shown in FIG. 21 to determine which defects are grouped into the same group according to the bin range. For example, if the portion of the design data that is close to the position of the defect in the design data space has a similarity greater than 90%, the defects are divided into the same group according to the bin range. In addition, as shown in FIG. 21, the portion of the design data proximate to the location of defect 1 in the design data space is the portion of the design data proximate to the locations of defects 3 and 4 in the design data space. % Similarity. Thus, the defects 1, 3, 4 are divided into the same group according to the bin range.

  In other examples, as shown in FIG. 22, the output of module 166 includes a graph (eg, a bar graph) showing the number of defects (eg, defect count or frequency) as a function of different groups. Each different group includes defects located at design data space locations close to design data that are the same, or at least similar, as described further above. Thus, the output shown in FIG. 22 provides information on which pattern types are more defective in the design. The chart shows pattern type decomposition by various design contexts (eg, background pattern context by functional blocks). The information in the chart may further include an annular or on-wafer as described further herein to provide information about the spatial distribution of defects located in the design data space proximate to the common design pattern. Divided by cornered zones. This information and similar or other information can be used to perform one or more steps of the methods described herein (eg, defect sampling based on background pattern context). Additional information regarding defects grouped according to bin range is also determined using any of the step (s) of the method (s) described herein.

  Module 166 outputs only one of the formats shown in FIGS. However, this module can output in multiple formats from those shown in FIGS.

  Additional examples of different inputs and outputs of module 166 are illustrated in FIG. As shown in FIG. 23, one input to module 166 includes a wafer map 172 illustrating the location of detected defects on the wafer. The wafer map is generated by the inspection system. The wafer map illustrates the location of the defect on the wafer and does not illustrate other information about the defect. For example, bar graph 174 corresponding to wafer map 172 illustrates all of the detected defects in a single group corresponding to the layer of the wafer that was inspected.

  The output of module 166 includes a wafer map 176 illustrating the location of detected defects on the wafer, and defects grouped according to bin range are shown in a wafer map having the same characteristics (eg, , Different colors or symbols for different groups). Defects are divided according to bin ranges as further described herein (eg, automatic grouping of defects by a common GDS layout). Thus, the wafer map 176 shows the groups into which the individual defects are separated according to the position and bin range of the individual defects on the wafer. The output is sent to and used by a spatial signature analysis (SSA) tool, such as KLARITY DEFECT SSA, commercially available from KLA-Tencor, to enhance the monitoring function and the ability to determine the root cause.

  The module output further includes a stacked die map, a stacked reticle map, or a stacked wafer map in which defects are displayed to represent a pattern group. This stack map can be used to illustrate where systematic defects tend to appear statistically on many dies, reticles, or wafers, and this stack map identifies spatial signatures Also useful. Further, the output of the modules described herein may include one or more GDS clips, one or more SEM images, one or more optical images, or some combination thereof. The output of the module is displayed by a user interface, such as the user interface embodiments described further herein.

  A bar graph 178 corresponding to the wafer map 176 illustrates the number of defects divided into respective groups according to the bin range. In addition, the layout pattern signature corresponding to each group of defects is shown in the bar graph. Thus, the bar graph illustrates the pattern in the design that exhibits (or causes) the greatest defectivity. For example, if the number of defects divided into the layout pattern signature 2 according to the bin range is relatively large, this indicates that there is a potential pattern-dependent failure mechanism corresponding to this layout pattern signature. This information can be used to perform one or more steps of the methods described herein (eg, defect sampling based on design background context). Additional information regarding defects grouped according to bin ranges is also determined using any of the step (s) of the method (s) described herein. Module 166 can generate an output that includes a wafer map 176 and a bar graph 178. The output of the module is displayed by a user interface, such as one of the user interface embodiments described further herein.

  One example showing how the output of module 166 is used in the manner described herein is for the correlation of different density zones in a device layout with different defects. For example, the device layout can be partitioned into different zones. The different zones are determined based on the design pattern density of different regions of the device, as shown in FIG. In one example, the main cell block in the device can be partitioned into different zones. In another example, the device layout can be automatically partitioned based on the density of various device structures (eg, contacts, vias, metal lines, etc.) on the device layout. In one embodiment, the method embodiments described herein include determining defect densities for different portions of the design data. For example, in the method described herein, information about device layout partitioning can be used to determine defect densities for different portions of cells in the design data. In such a case, the number of defects detected in each zone in the design data can be determined. Such information is plotted in a bar graph or other suitable output format.

  In other embodiments, the module 166 divides the design data into multiple “functional blocks” or “cell blocks”. Cell blocks are defined in the design data and identify the boundaries of large and small subcells in the design such as input / output (I / O) blocks, digital signal processor (DSP) blocks, and the like. The module can determine the frequency of defects in each cell block. In this way, it is possible to determine whether the effect of the yield problem experienced by large or small cells in the design is large or small.

  In the embodiments described herein, a statistical approach can be used to determine the design cell in which the defect is located. For example, in some embodiments, determining whether a defect is a systematic defect, and two or more of the systematic defects are located in one or more different portions of the design data. And determining whether there is a correlation between the systematic defects and the probabilities. In particular, as described further herein, the region information in the design data (ie, hierarchical design data) is used in combination with the position of the defect in the design data space, and the defect in the design data such as a cell in the design data. Can be determined. As further described herein, a hierarchy of defects in the design data may be used to determine which portions of the design data can or should be changed to improve yield. it can. One problem in determining the defect hierarchy is that the smaller the cell, the closer the cell size approaches the coordinate accuracy of the inspection system and the smaller the accuracy with which the cell in which the defect is located can be determined. Is lower. To overcome this problem, statistics can be used to determine the probability that defects are located in various parts of the design data (eg, the probability that each defect is located in a different cell). it can. Thus, for systematic defects, statistics can be used to determine whether there is a correlation between the systematic defects and the probability that the defects are located in various parts of the design data. .

  In other embodiments, the input provided to module 166 includes design data (eg, GDS layout), inspection data (eg, physical defect data), and optionally a memory bitmap and / or a logical bitmap. Including. A module may use some or all of its inputs to find, characterize, monitor, and dispose of defects (eg, one or more) that may or may not affect yield. One or more additional steps can be performed, such as making a feasible decision. The module is configured to perform the steps described above, but in addition to the step of generating a hot spot / weak spot data structure, a defect by using design data Grouping (e.g., defects detected by optical or electron beam inspection systems and / or defects detected by electrical inspection displayed in a bitmap), generating a review sample plan, inspection recipe , Review review recipe modification (eg, determine where to review), review recipe optimization, defect analysis recipe modification (eg, inline FIB process and / or FA) Where to analyze in the process (Determined based on the configuration context in combination with other information described herein), sampling of the defect analysis recipe, FIB process, EDX process, or other defect analysis process The steps of generating a recipe, generating a sampling recipe for the weighing process, and predicting one or more attributes of the DOI such as the DOI and possibly type and placement may be performed. In addition, any of the sampling plans or sampling recipes described above are dynamically determined based on the results divided according to bin ranges. In one such example, the module analyzes the design data or captures the analysis results of the design data, such as results from DRC, to predict the potential DOI detected in the inline defect data and bitmap data. Configured.

  As described above, the module 166 is configured to generate a data structure such as a database. For example, in some embodiments, the method includes the location of systematic defects and potential systematic defects in the design data space and one or more attributes of the systematic defects and potential systematic defects. Generating a data structure. Such a database is commonly referred to as a “hot spot” database. The database also includes information about weak spots, conditional hot spots, cold spots (non-critical areas of the design that can cause systematic defects with little or no yield impact (eg, dummy structures, Dummy fill area etc.)). The database may also include the placement of potential and actual systematic defects and other attribute (s) (eg, design context, KP, other yield characteristics, etc.).

  A hot spot database can capture data from a variety of sources. For example, the database is configured as a flexible database containing data on systematic issues from all (or at least some) possible sources. For example, some of the inputs to the module can be included in the database. In one such example, inspection results (eg, PWQ results, defects detected by BF and / or DF inspection, memory bitmaps, logical bitmaps, etc.) can be stored in a database. In some embodiments, the database further includes design rules for one or more semiconductor manufacturing processes such as lithography and CMP. In other embodiments, the database includes simulations performed on design data, such as results of OPC simulations. Thus, multi-source correlation can be used to identify hot spots and systematic defects.

  As described above, the method includes separating defects according to bin ranges based on design data. In one such embodiment, the method described herein includes determining whether the defect is a nuisance defect based on one or more attributes of the design data. In this way, nuisance defects are identified based on context information. In some embodiments, the method removes a portion of the defect from the inspection process result in which the defect was detected based on design data proximate to the position of the defect to increase the S / N ratio of the inspection process result. Including removing. Thus, information about the design placed close to the position of the defect in the design data space is used to reduce the noise of the inspection result and thereby increase the S / N ratio of the inspection result. For example, defects in non-functional areas of the design are separated according to bin ranges and filtered as nuisances from the inspection results before the inspection results are used for later analysis. In another example, the defects are classified based on whether the defects are arranged in the inspection target area or the non-inspection area of the wafer. In additional examples, systematic defects, but defects located in parts of the design where nuisance defects (eg, non-DOI) are known to appear are removed from the inspection results and the DOI results The S / N ratio can be increased. One or more portions of the design that are known to exhibit nuisance defects are determined by the user and stored in a data structure such as a design library. For example, portions of the design that are known to exhibit nuisance defects include polygons that the user has selected for use specifically for grouping by supervised bin ranges. In addition, if the POI is defined prior to performing the binning method according to the bin range, the dividing method according to the bin range uses the defined POI to perform supervised dividing according to the bin range. To do. Alternatively, POI is performed by a method as further described herein. The methods described herein include supervised separation on an inspection system according to bin ranges and excluding nuisance defects from inspection results.

  As described above, removing some of the defects and increasing the S / N ratio of the inspection result is advantageous when post-processing the inspection result. For example, removing some of the defects (eg, removing non-yield affecting defects) is performed before dividing the defects according to the bin range, and the resulting S / N ratio divided according to the bin range for the defect type of interest. Can be increased. In addition, analysis of test results or results of method embodiments described herein is faster and more accurate when the resulting signal-to-noise ratio is high and contains less noise. In a particularly advantageous example, in the PWQ method, the main noise source is a line end short (LES) detected as a defect. However, LES generally does not significantly affect yield. Thus, users generally do not care about LES, and because a relatively large number of LES can appear, detected LES can overwhelm other defects that are highly relevant to yield. In doing so, removing the detected LES from the test results as described herein is particularly beneficial for further processing of the test results. The defect may include a defect detected by an optical or electron beam inspection system. In addition, as further described herein, an inspection recipe is created based on the design context to distinguish these defects during inspection. Thus, by using the methods and systems described herein, more DOIs can be detected, more nuisance defects can be suppressed, and systematic and random defects can be classified. In addition, an inspection recipe can be created that can sort systematic defects according to bin ranges on a pattern basis.

  In other embodiments, the method reviews at least some of the defects in one or more of the group to increase the S / N ratio of the results of the inspection process, and the inspection process in which the defects are detected Determining whether one or more of the group of defects corresponds to the nuisance defect by removing one or more groups corresponding to the nuisance defect from the result of. Reviewing at least some of the defects is performed as described herein or by other suitable methods known in the art. Determining whether one or more defect groups correspond to a nuisance defect is performed using the results of the review in a suitable manner. If one or more groups of defects correspond to a nuisance defect, one or more groups may be removed from the inspection result (filtered away) to increase the DOI S / N ratio in the inspection result it can.

  As discussed above, the embodiments described herein advantageously use defect data and / or defect information as printed on the wafer using design data and defect locations in the design data space. Separate defects according to bin range as opposed to background information. However, the design data in the design data space is used in combination with other information to separate the defects according to the bin range (eg, the separation distance between the defects in the different groups divided according to the bin range) ). For example, in one embodiment, dividing defects according to bin ranges means that when grouping defects according to bin ranges, the portions of the design data that are close to the position of the defect in their respective design data space are at least similar. And grouping such that one or more attributes of the defects in each of those groups are at least similar. These defect attribute (s) include the defect attribute (s) described herein. In addition, the defect attribute (s) includes the defect attribute (s) determined from the result of the inspection. In doing so, the grouping by bin range is performed using a combination of the design and one or more attributes of the defect. Thus, this method can divide the defects into a plurality of groups based on the design data and the defect attribute (s). Thus, it is possible to separate different types of defects which are arranged in the design data space of at least a portion of similar design data. Thus, bin range grouping is advantageously used to distinguish between different defect features in the area of the design data and the rate at which the different defect features occur.

  In other embodiments, the portion of the design data proximate to the location of the defect includes design data where the defect is located. In other words, the portion of the design data that is compared to divide according to bin range includes design data “behind” the defect. Thus, grouping by bin range includes grouping by geometry bin range by using the geometry in the design data where the defect is located. Such binning grouping is performed on defects for which defect placement is reported with relatively high coordinate accuracy so that the probability that the correct geometry is used for binning grouping is relatively high. Using design data “behind” a defect is possible in the embodiments described herein because the design data used in the embodiments is not design data that is printed on the wafer. It is. In contrast, defects on the wafer can obscure design data printed at the same location on the wafer or in the area surrounding the defect, and thus are further printed on the wafer. The accuracy of the method of separating defects according to the bin range based on such design data is reduced. In other embodiments, the portion of the design data proximate to the defect location used in the embodiments described herein includes design data around the defect location. In addition, grouping by bin range is performed using geometry where the defect is located and geometry around or close to the position of the defect in the design data space.

  As described above, grouping by bin range is performed regardless of the position of the defect in the design data portion. Such binning grouping is particularly advantageous for defects detected by inspection systems that report defect placement with relatively low accuracy. In addition, such binning grouping yields a substantially very accurate result of binning grouping, such as parts of design data that exhibit a particularly high degree of defect and / or a particularly high defect rate, etc. Bring important information. However, in an additional embodiment, dividing defects according to bin range means that when grouping defects according to bin range, the portions of the design data that are close to the position of the defect in each of those groups are at least similar, Grouping so that the positions of the defects in each of those groups with respect to the inner polygons are at least similar. In this way, the grouping by bin range is performed using a combination of the design data portion and the position of the defect in the design data space and the portion of the design data close to the position of the defect. In doing so, grouping by bin range is performed based in part on where the defect is located in the geometry. In other words, grouping by bin range is performed based on the partial position of the defect in combination with design data close to the partial position. Such bin range grouping is preferably performed for defects whose placement is reported with relatively high coordinate accuracy so that positions between substantially accurate portions of the defect are used for bin range grouping. Is done. In this way, the defects that affect the device in different ways can be separated because they are arranged in the same part of the design data, but have different locations. For example, by using such bin range grouping, a defect that is placed between two features in a portion of the design data and thus has a relatively high probability of creating an empty portion in the device. It can be separated from defects that are placed in a way that fits perfectly in one of the features, and therefore has a much lower probability of creating voids in the device. Thus, grouping by bin range is thus conveniently used to identify the rate at which defects with different yields and defects with different yields occur in the design data area. .

  In some embodiments, the step of binning according to bin ranges is such that when the defects are grouped according to bin ranges, the portions of the design data proximate to the position of the defect in each of those groups are at least similar. Grouping so that the hot spot information for portions of the design data proximate to the location of the defect in each is at least similar. Hot spot information includes any of the hot spot information described herein or other hot spot information known in the art. Hot spot information is determined for different portions of the design data as further described herein. Thus, this method can perform grouping by bin range using a combination of design data and port spot information. In one such example, design data hot spots that have a similar effect on yield are divided according to bin ranges as described above before the method is performed. Therefore, the defects are divided according to the bin range based on the similarity of the design data, and the defect groups obtained as a result of the grouping by the bin range are divided into defect subgroups having similar yield influences. An example of this is that all parts of at least similar design data are associated with the same hot spot information when, for example, some of the positions are located above or below different design data. There is no possibility. At that time, defects arranged close to at least similar parts of the design data can be classified based on hot spot information for the respective parts of the design data. In this way, the overall yield of the process used to process the wafer can be evaluated quickly and accurately. In addition, hot spot information can be used for grouping by bin range to check or verify that the similarity of some of the design data has been correctly determined. For example, if at least a portion of design data determined to be similar is not associated with at least similar hot spot information, the defects corresponding to the portion of design data are divided into the same group according to the bin range. I can't.

  In other embodiments, the method may include the one or more attributes of the design data in which one or more defects in the group are proximate to the position of the defect in the design data space, the one or more attributes of the defect. Or determining whether it is a systematic defect or a random defect based on some combination thereof. Thus, the method includes grouping defects together into a group. For example, systematic defects are classified as a nuisance defect or an unfocused defect as a group. Such classification is performed on individual defects. The defect attribute (s) used to determine if the defect is a systematic defect or a random defect is, for example, a defect in multiple dies if the defect is present in approximately the same location in multiple dies. Includes substantially the same attribute (s), including the case where the distribution of defects in a die is regular and / or clustered. In one example, defects that appear on only one die on the wafer are classified as random defects, and defects that appear on multiple dies in approximately the same arrangement are classified as systematic defects. Thus, the methods described herein are used to determine the cause of defects detected on a wafer by an inspection process (in-line inspection process and / or electrical inspection process) using information about the defects. The

  In some embodiments, the method may result from at least some review of defects in one or more groups, one or more attributes of design data, one or more attributes of defects, or Classifying one or more groups of defects based on some combination thereof. At least some reviews of defects in one or more groups are performed as described herein or by any suitable method known in the art. The one or more attributes of the design data and the one or more attributes of the defect include the attribute (s) described herein. In this way, defects can be grouped together into a group based on a substantial amount of information, so that defect classification can be performed relatively quickly and relatively accurately.

  In other embodiments, the method includes determining whether a group into which defects are divided according to bin ranges as described herein includes systematic or potential systematic defects. In this way, defects are grouped together into one group as systematic or potential systematic defects. However, defects are further classified individually as systematic or potential systematic defects. For example, defects are classified in these embodiments based on the position of the defect with respect to the polygon in the design and whether hot spots, cold spots, etc. are located at approximately the same position. Accordingly, the method described herein uses information such as design data to locate the cause of defects detected on a wafer by an inspection process (in-line inspection process and / or electrical inspection process). used.

  In some embodiments, the method includes monitoring systematic defects, potential systematic defects, or some combination thereof over time using the result of dividing according to bin ranges. For example, the results of the step according to bin ranges can be used to identify systematic problems in the design data, and the identified systematic problems can be monitored for recurrence over wafer and / or time. Monitoring systematic and / or potential systematic defects is performed using the results of the methods described herein.

  In addition, monitoring systematic and / or potential systematic defects is performed in a manner similar to statistical process control (SPC) methods. For example, yield-based SPC can be performed by monitoring systematic defects, potential systematic defects, random defects, or some combination thereof, where different SPC methods and / or algorithms are of different types. Used for defects. In one such example, SPC parameters are used to monitor different types of defects, and SPC parameters are determined or selected based on the potential yield effects of different types of defects, which are Executed as described in the book. Thus, different types of defects are monitored simultaneously for SPC, but use different SPC parameters. In other embodiments, only a subset of defects detected by inspection is used for SPC. For example, non-nuisance systematic and / or potential systematic defects are monitored for SPC purposes so that the process is monitored for design-based process limits. In additional examples, only systematic defects that are determined to have a potentially significant impact on yield will be able to accurately and accurately detect machining process yield changes caused by these defect changes. SPC is monitored. In addition, more accurate prediction, monitoring, and control of yield related problems can be advantageously promoted by using different methods to estimate the impact of systematic defect groups and random defect yields. In this way, this method can provide information regarding the processing of devices used to monitor and improve processing yield (e.g., increasing systematic defects over time, over time). Including systematic defects, changes in systematic defects over time, etc.).

  In one embodiment, the method includes locating the cause of pattern-based defects (eg, systematic defects). For example, if one or more pattern-based defect groups are dominant, the method may include in-line inspection data and / or electrical inspection data of a number of other wafers for the same layer and the same device. Including. For example, in-line inspection data and / or electrical inspection data is captured for about 100 to about 1000 other wafers. This data is captured from a storage medium such as a defect database or a fab database. If such data is not available, the method will inspect wafers that have already been processed (or process other wafers) in the process performed on the wafer where the systematic defect was detected, and then inspect the wafer. Generating such information.

  The method further includes performing a pattern-based separation of defects detected on the additional wafer according to bin ranges, which is performed as described herein. The method includes determining whether one or more pattern-based defect groups are dominant for additional wafers. If the additional wafer exhibits common pattern-based defect commonality, the method includes determining whether the wafer has been processed through a common equipment (or processing tool). Thus, the method can perform device commonality analysis. This method has two dominant pattern-based defect groups: a specific instrument, a specific chamber (eg, an instrument or chamber whose parameters are drifting for some reason), or a specific root step (eg, an instrument and two Or whether it correlates with an integration problem between or more steps. If the dominant pattern-based defect group correlates to a specific instrument or a specific chamber, the cause of the pattern-based defect group is isolated and optionally identified. The method includes stacking data to determine if there is a spatial signature for the group of interest. Spatial signatures are useful in narrowing down or pinpointing the cause of process-related, OPC-related, or design-related systematic problems, or combinations thereof.

  If the dominant pattern-based defect group does not correlate with a particular instrument or a particular chamber, the method includes performing data mining to attempt to correlate the defect with other process factors. Data mining is a preferred method known in the art based on information about defects and design data stored in one or more storage media, such as a fab database, and information generated during device processing. It is executed by. If a relatively strong correlation is identified between the one or more process factors and the defect, the process factor (s) that correlate with the defect are identified as the cause of the defect. If a relatively strong correlation is not identified between one or more other process factors and the defect, the method can perform an arbitrary pattern search of the design for potential POI and cause the pattern-dependent defect. Setting up a new inline hot spot monitor to be located. However, if process conditions are excluded, the process itself or the design itself is evaluated and adjusted if necessary to sort out or remove the problem. In addition, the likely source and / or root cause can be inferred by comparing the attribute (s) of the systematic defect with the results of the process window mapping.

  In this way, data reduction can be performed using information about systematic and / or potential systematic defects. For example, there are over 50,000 to over 200,000 hot spots generated by a full die pattern based search for a single POI or from empirical techniques such as electrical functional testing and lithographic PWQ results. Therefore, data reduction techniques are performed on the data in order to process and analyze this data in a meaningful and timely manner. In one such example, for pattern-based hot spots, the method includes dividing the hot spots into “similar” groups according to bin ranges. For example, each group is located in proximity to at least a similar pattern in the design data and / or is in proximity to design data having one or more attribute (s) that are at least similar. (E.g., hot spots that are located within a relatively low pattern density region of the design can be grouped by bin range). In doing so, the method includes separating hot spots according to bin ranges based on design context and / or design attribute (s). In an additional example, with respect to empirical techniques such as PWQ, this method can be used to remove defects that are close to the placement of designs that have little or no yield impact from the defect population on which review sampling is performed. Including (cold spot). By performing data reduction as described above, using the data organized as described further herein, review samples generated (eg, for further relevance to yield) ) Can be improved.

  The methods and systems described herein include CBI that combines design and yield-based post-processing of inspection results (performed on-tool or off-tool). For example, after nuisance defects, systematic defects, and random defects have been identified, the defects can be organized in some way (eg, using a defect organizer (DO) or an inline defect organizer (iDO)). In one example, the results are stored in a data structure such as a database. In other examples, as described above, after defects are grouped according to bin ranges based on portions of the design data proximate to the position of the defects in the design data space, the defects in those groups are further designated as design data. Separation can be based on one or more attributes of the design data proximate to the position of the defect in space, one or more attributes of the defect, or some combination thereof. These defects can be separated using iDO based on one or more attributes of the design data and / or one or more attributes of the defects. As such, grouping by design-based bin range is used in combination with iDO in the embodiments described herein. In particular, the output of grouping by design-based bin range can be input to iDO.

  One or more attributes of the design data used to further separate the grouped defects by bin range based on the design data include, but are not limited to, in the design data close to the position of the defect in the design data space. One or more attributes of the pattern or structure, pattern density proximate to the position of the defect in the design data space, functional block in which the defect is located, one or more attributes of the device (eg, n-MOS or p -MOS). One or more attributes of the defects used to further divide the defects divided according to the bin range include, but are not limited to, size, shape, brightness, contrast, polarity, texture.

  Grouping by design-based bin range and iDO results are illustrated in a bar graph. This bar graph can exemplify the comparison between the total number of defects and the pattern in the design data in which the defect is detected, and the number of defects in the subgroup that varies depending on the pattern. Use design-based bin range grouping in combination with iDO, as described above, to separate random and systematic defects, prioritize groups with defects sorted according to bin range, and / or Identify and possibly prioritize changes to be made to the design data (e.g., using the potential yield impact of the defect group, which is determined as described further herein) . In particular, the value given in grouping by design-based bin ranges to separate systematic and random defects is increased by using iDO to further separate systematic (and possibly random) defects. be able to. In addition, the values given in the grouping by design-based bin ranges to separate systematic and random defects combined with iDO in some cases to separate systematic (and sometimes random) defects. It can be increased by using yield relevance.

  Thus, the systematic defect population and the random defect population are processed separately (eg, the systematic defect population and the random defect population are sampled independently). Different populations or different information for systematic and random defects can be used to produce separate results for systematic and random defects. For example, systematic and random defects are exemplified in different bar graphs or other graphs or text representations that are automatically processed and / or used by the user. After sampling defects for review, systematic defects, and optionally some of the random defects, are reviewed using a suitable review system (eg, a relatively high magnification optical review system or SEM). . Defect review results can be used to normalize defect densities for both systematic and random defects.

  The methods and systems described herein provide a number of benefits to the user. For example, these methods and systems can achieve efficient reference yield improvement, deviation detection improvement, review system efficiency improvement, root cause detection efficiency improvement, and knowledge retention improvement. In addition, the results of the embodiments described herein include various types of information that are useful to the resulting consumer (eg, the device manufacturer's consumer). Such other types of information include information such as process tool owners, designers, integration engineers, and the like.

  Furthermore, it is estimated that over 90% of the 90 nm design rule and beyond yield loss is caused by systematic problems. Therefore, the systematic yield problem is significant in the 90 nm design rule and is dominant in the design rule of less than 90 nm. Therefore, by separating systematic defects from nuisance and random defects as described above, these systematic problems can be successfully evaluated, analyzed and controlled. Furthermore, the arrangement of systematic defects can be compared with the arrangement of functional blocks in the design data. In this way, systematic defects can be correlated with one or more functional blocks and this information can be used to improve the signal-to-noise ratio. In particular, the method includes separating defects based on the functional block in which the defect is located to improve the S / N ratio. Similarly, the method includes partitioning defects based on hierarchical cells in which design data is organized by design. Thus, to improve the signal-to-noise ratio, defects grouped by bin ranges and / or defects assigned DBCs can be identified by the functional block (or any level of the hierarchy) in which the defect is located (e.g., Memory or logic circuit). The portion of design data used in the embodiments described herein may correspond to a cell structure or cell hierarchy.

  The percentage of defects per functional block is determined by the method described herein. In this way, functional blocks containing design problems are identified based on the percentage of defects detected in each functional block and / or grouped into groups corresponding to the functional blocks according to bin ranges. Additional information regarding defects located within the functional blocks can be used to identify design issues in each block. The above information is also used to select and / or prioritize correction design issues based on how much defects can be eliminated by correction. For example, if it is determined that about 70% of the defects are caused by four design problems in four different functional blocks of the design, only those four design problems are selected for correction or others are corrected These four design issues can be selected for correction before (eg, by prioritizing design issues based on the number or percentage of defects caused by the design issues). A user (eg, a chip designer) can select a cell design to use, and can choose to use a cell design that shows fewer systematic defects over time, such information about the cell design Are generated using the embodiments described herein.

  In other embodiments, the method prioritizes one or more POIs in the design data and optimizes at least one of the one or more POIs based on the results of the prioritization step. Including. In one such embodiment, the POI (s) are prioritized based on the number of defects detected in the POI (s). The number of defects detected in each POI can be determined, for example, by comparing the POI (s) or one or more attributes of the POI (s) with the portion of the design data corresponding to the group, Defects in the group corresponding to a portion of the design data (and / or one or more attributes of the portion of the design data) that are at least similar to the POI (or attributes of the POI) Is determined from the result of the step of dividing according to the bin range. Thus, the POI with the highest number of defects detected is assigned the highest priority, the POI with the next highest number of defects detected is assigned the next highest priority, and so on.

  In other embodiments, the method includes prioritizing one or more systematic defect types for yield optimization (eg, changing process parameters, design, OPC, etc., or some combination thereof). By doing). In one such embodiment, systematic defect types are classified as POIs or groups of POIs, where POIs are determined as described above, and defects detected on or near the POI. Is prioritized based on the number of Priority is further enhanced by prioritizing systematic defects using the criticality of systematic defect (s) detected in the POI, the frequency of POI in the design, and the sensitivity of the POI to process variations. .

  In addition, or alternatively, the POI (s) are prioritized based on other results or combinations of the step (s) of the method (s) described herein. . For example, prioritizing POI (s) may include determining a defect criticality index (DCI) for one or more defects detected in the POI (s) and one or more defects. Prioritizing the POI (s) based on the DCI for. The DCI is determined in this embodiment as further described herein. In other examples, prioritizing the POI (s) may include determining a KP value for one or more defects detected in the POI (s) and a KP for the one or more defects. Prioritizing the POI (s) based on the value. In yet another example, based on the combination of the number of defects detected in or near the POI (s) and the DCI for one or more of the defects detected in or near the POI (s). And prioritize the POI (s). Thus, prioritizing the POI (s) is based on the degree of defect indicated by the POI (s) such that a high priority is assigned to the POI (s) having a high degree of defect ( Prioritizing POIs).

  Further, the POI (s) may be identified and / or prioritized based on one or more attributes of the POI (s), possibly in combination with other results described herein. Is done. The attribute (s) of the POI (s) can be, for example, the feature dimensions in the POI (s), the feature density in the POI (s), or the feature (s) in the POI Type, location of POI (s) in the design, yield sensitivity of POI (s) to defects, etc., or some combination thereof. In such an example, the POI (s) that are susceptible to yield due to defects are assigned higher priority than the POI (s) that are less susceptible to defects due to yield.

  Further, the POI (s) may optionally be combined with one or more attributes of the POI (s) and / or other results described herein to one or more attributes of the design. Prioritized based on. One or more attributes of the design include, for example, redundancy, electrical connectivity, electrical attributes, etc., or some combination thereof. In particular, the cells in the design data can have a context beyond the patterns contained within the cells. Such contexts may include, for example, cell hierarchy, redundancy (or none), etc. Thus, the one or more attributes used in the embodiments described herein include the context of the cell in which the POI (s) is located, which is the POI (s) in the design data space. And the POI design data (if the design data is specific to the cell in the design data). In one such example, non-redundant POIs (eg, non-arrays) in the design are assigned higher priority than redundant (multiple) POIs (eg, arrays). The POI (s) are further prioritized based on connectivity redundancy between cells (eg, routing or redundant vias). Such context of design is captured and / or determined in a manner known in the art.

  Optimizing at least one of the POIs based on the results of the prioritization step may include the feature (s) of the feature (s) of the POI (s), the (multiple) of the POI (s) ) Changing one or more attributes of the POI, such as feature density, or combinations thereof. One or more attributes of the POI are changed by changing design data corresponding to the POI. Preferably, the POI (s) is changed to reduce the degree of defect of the POI (s) (eg, the number of defects detected with the POIs) and detected with the POI (s) Change one or more attributes (eg, DCI, KP, etc.) of the defect and / or increase the yield of the device that includes the POI (s). In addition, the high-priority POI (s) determined by the prioritization step is modified and optimized before the low-priority POI (s) determined by the prioritization step. Is done. In this way, the POI (s) exhibiting the maximum defect degree and / or the defect degree having the greatest influence on the yield are POI (s) indicating the defect degree having a low defect degree and / or a small influence on the yield. And / or optimized prior to In doing so, the result of the prioritization step indicates which POI (s) are modified and / or optimized to obtain the greatest improvement in yield, and those POIs are It is modified and / or optimized before the POI (s).

  Thus, without timely guidance that POI (s) have the greatest impact on yield, changes made to design data and / or manufacturing processes are delayed, resulting in delayed yield improvements and market launch. This embodiment is advantageous over other already used methods and systems for modifying design data because of the longer time to market. Further, the POI (s) modified in this step are included in the design (s) printed on the wafer prior to the detection of defects separated according to bin ranges in the embodiments described herein. The POI (s) that contain only the POI but have been modified to optimize the POI (s) include the POI (s) included in the designs. For example, if multiple designs include POI (s), POI (s) in different designs may be modified based on prioritization and / or other results of the methods described herein. Optimized, which can increase the yield of devices fabricated with each of the different designs.

  In an additional embodiment, the method prioritizes one or more POIs in the design data and one or more RETs of the one or more POIs based on the results of the prioritization step. Optimizing features. Prioritizing the POI (s) in this embodiment is performed as described above. The RET feature (s) optimized in this step includes the RET feature (eg, OPC feature) included in the design. Optimizing one or more RET features of one or more POIs based on the results of the prioritization step includes changing one or more attributes of the RET feature (s). For example, the dimensions of the RET feature (s), the shape of the RET feature (s), the location of the RET feature (s) relative to the feature in the POI (s), etc. The attribute (s) of the RET feature (s) modified in this step are preferably the RET feature (s) of the RET feature (s) that reduce the degree of defect and / or increase the yield in the POI (s). Attribute).

  In addition, optimizing one or more RET features based on the results of the prioritization step of this embodiment has the highest priority before optimizing the RET feature (s) for other POIs. Optimizing the RET feature (s) for the POI that has been determined to have degrees. Thus, the RET feature (s) with high priority POI (s) are changed before the RET feature (s) with low priority POI (s) are changed. Thus, the RET feature (s) of the POI (s) exhibiting the maximum defect degree and / or defect degree having the greatest influence on the yield is a defect degree having a low defect degree and / or a small influence on the yield. Is modified and / or optimized before the RET feature (s) of the POI (s) indicating In doing so, the results of the prioritization step indicate which POI (s) are modified and / or optimized to obtain the greatest improvement in yield, and for those POI (s) The RET feature is modified and / or optimized before the RET feature of the other POI (s).

  Therefore, without timely guidance where POI (s) have the greatest impact on yield, changes to the design are delayed, resulting in delayed yield improvement and longer time to market. Embodiments are advantageous over other already used methods and systems for modifying design data. Furthermore, the RET feature (s) of the POI (s) that are modified in this step are printed on the wafer prior to the detection of defects separated according to bin ranges in the embodiments described herein. Only the RET features of the POI (s) included in the design are included, but the RET features of the POI (s) that are modified and / or optimized are included in the designs Contains RET feature (s) of POI (s). For example, if multiple designs include (multiple) POIs with the same (multiple) RET feature (s) in different designs based on prioritization and / or other results of the methods described herein ( The RET feature (s) of the POI (s) can be modified and optimized, thereby increasing the yield of devices fabricated with each of the different designs.

  In some embodiments, the method uses the design data regarding the defect placement to model the electrical characteristics of the device being processed and relates the defect parameters in the defect placement based on the modeling results. Including determining gender. Thus, the result of the modeling step is used to determine the parameter relevance of the defect. For example, the result of the modeling step is used to determine how a defect changes one or more electrical parameters of a device being processed using the design. The defects whose parameter relevance is determined as described above may be systematic defects. Parameter relevance is used in the step (s) of the method (s) described herein. For example, the parameter relevance may be combined with other information described herein (eg, one or more defect attributes, one or more attributes of design data, etc.) to determine the DCI of the defect. And prioritize the POI (s) as described herein.

  Modeling the electrical characteristics of the device in this embodiment can be performed using any suitable method or system known in the art. The electrical characteristics of the device being modeled include one or more electrical characteristics of the device. The parameter relevance of the defect is determined using the modeled electrical characteristics and the designed electrical characteristics. For example, the modeled electrical characteristics can be compared with the designed electrical characteristics to determine the degree to which a defect changes the electrical characteristics. The parameter relevance is then determined based on the degree to which the defect changes the electrical characteristics (eg, a defect that significantly changes the electrical characteristics has a parameter relevance compared to a defect that does not change the electrical characteristics too much). strong). Parameter relevance is similarly determined using the modeled electrical characteristics of the device and a range of suitable electrical characteristics. For example, the modeled electrical property is compared to this range and used to determine the parameter relevance if the modeled electrical property is in or outside this range . In such an example, if the modeled electrical characteristic is near or outside the tolerance range, the defect is more parameter related than if the modeled characteristic was within the tolerance range. Is determined to be strong. Parameter relevance is further determined based at least in part on information from many different sources, including but not limited to simulation, optical inspection results, defect review results, electrical test results, or some combination thereof. Is done.

  In one embodiment, the method includes assigning priorities to systematic defects and potential systematic defects based on parameter relationships determined for or associated with systematic defects and potential systematic defects. . For example, hot spot priorities or severities are ranked based on parameter relevance. Parameter relevance can determine how and to what extent defects in the hot spot affect the electrical parameters of the device.

  Parameter relevance is further used to isolate or prioritize defects that are likely to cause device parameter problems (eg, yield loss). For example, one or more attributes of the design data and / or one of the defects that is close to the position of the defect in the design data space, such as electrical test results or other information about the electrical characteristics of the device such as resistance, capacitance, timing, etc. Or it can be used in combination with multiple attributes to determine which defects affect the electrical characteristics of the device and which defects do not. Other information regarding electrical test results or electrical characteristics is determined by this method (eg, using simulation) or is captured from other sources (eg, netlist information). In this way, defects that are likely to cause parametric problems can be separated from defects that are unlikely or likely to cause parametric problems. In so doing, defects that only affect the device's geometric composition or material properties are separated from defects that affect the device's ability to function according to its intended purpose. In addition, electrical defects may be used using electrical test results or other information regarding the electrical characteristics of the device in combination with one or more attributes of the design data and / or one or more attributes of the defects. Critical parameter defects (eg, electrical defects that can significantly affect the electrical characteristics of the device) and non-critical parameter defects (eg, electrical that do not significantly affect the electrical characteristics of the device) ).

  In some embodiments, the method includes determining a DCI for a defect (eg, one or more of the defects). The DCI is determined based on one or more attributes of the design data proximate to the position of the defect in the design data space, one or more attributes of the defect, or some combination thereof. For example, using one or more attributes of design data proximate to the position of the defect in the design data space, one or more attributes of the defect, or some combination thereof, to reduce the potential yield impact of design-based defects. The value of the defect data can be increased. In a particular example, the size and location of the defect in the design data can be used to determine the DCI and investigate the possibility that the defect can cause an electrical failure. The DCI can then be used to show the defect yield relevance. In particular, the defect size can be used to investigate the possibility that the defect will spoil the die, or otherwise change one or more electrical attributes of the device being processed on the wafer. For example, as the defect size increases and the pattern complexity increases, the possibility that the defect will spoil the die or change one or more electrical attributes of the device. Thus, using a relationship that describes the possibility that a defect spoiles the die or alters one or more electrical attributes of the device as a function of defect size and pattern complexity, The relative risk of defects can be determined. The relative risk of each defect is determined immediately after inspection, so that a more appropriate decision can be made based on the relative risk.

  Alternatively, DCI is the probability that a defect will spoil the die or change one or more electrical attributes for different defect sizes and possibly different types of defects (possibly across the die). This is determined using a statistical method that includes determining, which is used to determine the DCI for the defect. For example, in one embodiment, the method may include one or more attributes of the design data in which one or more of the defects are proximate to the position of the defect in the design data space, one or more attributes of the defect (defect size). One in a device that has been processed for design data based on the location of the defect reported by the inspection system used to detect the defect, inaccuracies in the coordinates of the inspection system, or some combination thereof. Or determining the probability of causing multiple electrical faults (or changing one or more electrical attributes of the device, thereby causing parametric electrical problems) and one or more defects based on that probability Determining the DCI for. This probability is determined in this way using appropriate statistical methods known in the art.

  DCI for defects is used in various ways in the embodiments described herein, such as for sampling where defects are selected for review. In particular, for each defect classification or group of defects, DCI is used to sample defects with the same classification instead of performing a random sampling of commonly classified defects or commonly separated defects according to bin ranges. Or divided into the same group according to bin range. By using DCI for sampling, the distribution of DCI can be used to determine if a die is spoiled or has a high probability of changing one or more electrical attributes, and the die is spoiled. Or more defects with a high probability of changing one or more electrical attributes can be sampled. In doing so, defects that are likely to affect yield can be sampled more for review and, therefore, defect reviews that are particularly useful for identifying and classifying defects that are likely to affect yield Results can be generated. DCI is used not only to sample potential systematic and systematic defects, but also to sample random defects.

  In some embodiments, the method includes determining a high density zone on the electrical fault density map. The fault density map is output by generating a “logical bitmap” or physical transformation of fault test chains or fault flip-flops (detected by structural tests, a type of scan-based test). All fault lines or areas found by scan-based testing are shown as such in the graphical rendering of the die under test (DUT). The terms “logical bitmap” and “bitmap” are used interchangeably herein. Stacking (ie, overlaying) logical bitmaps for different dies of the same layer (s) and design to indicate the number of faults at each point on the die and create a fault density map it can. Defects that appear in the fault density map with a frequency greater than a predetermined value can be considered as systematic defects. Defects found close to hot spots in the die coordinate space can be considered systematic defects or systematic candidates that affect yield.

  In some embodiments, information from the inline inspection results is used to analyze the results of the electrical inspection process (eg, a bitmap) to determine whether the cause of the electrical defect is determined from the inline inspection results can do. Different test results can be aligned with each other as described herein to correct in-line test results and electrical test results. In addition, different inspection results can be first aligned with the design data and then the inspection results can be aligned with each other. In either case, the bitmap results are overlaid with inline test results.

  The method further includes locating the cause of electrical defects in the bitmap based on the in-line inspection data and the design data. In addition, different fault types and their candidate locations or paths can be analyzed to determine the number of electrical faults that overlap with physical defects. These “hits” provide evidence that the physical defect is responsible for the cause of the electrical defect. Thus, the ratio of hits to fault types is determined as the number of faults of that type corresponding to the reported physical defect divided by the number of faults of that type. By evaluating this hit ratio, it can be determined whether the failure type has a tendency to stratify on the reported physical defects. In addition, the hit ratio of physical defects and in-line inspection results can be used to determine the number of physical defects of the same type that caused an electrical failure. In this way, the number of defects of the same type that caused an electrical failure can be used to determine a statistical prediction of significance in defect yield.

  Additional information regarding physical defects is also used to determine the cause of the bit failure. Such information may include, but is not limited to, an image of physical defects corresponding to the placement of bit faults, classification results for physical defects, grouping results by bin range for physical defects, or some combination thereof. This can be a bitmap image of the entire die where bit faults are located, an image showing a stack (ie, overlay) of bitmap images of multiple dies (eg, repeated electrical faults on the die) Used) in combination with bitmap information, such as detailed information (e.g., table or list data) about bitmap results.

  In some embodiments, the method includes using a defect transition table (DTT) method to identify hot spots where no defects have been detected or non-killer or non-significant defects have been detected. In general, multiple rows of the DTT contain inspection results for different defects, and different columns of the DTT contain inspection results generated by inspections performed at different times. The inspection results are arranged in a sequence in time order. Thus, the table shows which defects have been redetected in different layers in the semiconductor manufacturing process. The table may further include additional information regarding defects detected at different layers, or provide access (eg, links). In this way, additional information such as an image of the defect can be used to determine if the defect has changed in different layers and how it has changed.

  In additional embodiments, the method determines a KP value for one or more of the defects based on one or more attributes of the design data, one or more attributes of the defects, or some combination thereof. including. Similarly, the method is based on one or more attributes of design data corresponding to one or more groups, one or more attributes of defects in one or more groups, or some combination thereof. Determining KP values for one or more groups of defects. The KP value for systematic defects is used to determine additional attributes of systematic defects such as yield ratio. In addition, the KP value is used to perform the additional steps described herein. For example, the KP values for systematic defects are used to determine which defects have been selected for review. In particular, systematic defects with relatively high KP values are selected for review. In addition, the method includes monitoring the KP value for systematic defects and generating an output signal when the KP value exceeds a predetermined KP value. The output signal can be an automated report, a visual output signal, an audible output signal, or some other output signal used to inform the user of potential problems with the process. Thus, the output signal can be an alarm signal.

  As described further herein, one of the advantages of the methods and systems described herein is to collectively access, correlate, store, and display information from a number of different sources. And / or can be processed. Such information includes, but is not limited to, information in the GDS file, information about processes performed on the wafer (usually called WIP data, taken from sources such as a fab manufacturing execution system (MES) database), Includes in-line inspection results, in-line weighing or measurement results, electrical test results, and line end yield information. Such information is used to determine yield relationship information regarding systematic defects. Further, the yield ratio or other yield relationship information determined for systematic defects is used to assign yield relationship context to systematic defects. Both yield relationship context information and design context can be assigned to systematic defects. In one embodiment, instead of classifying defects based on design context, systematic defects can be classified based on yield limiting context.

  As described further herein, hot spot-based inspection for systematic defects outputs inspection results including detected systematic defects and design context corresponding to systematic defects. In this way, peripheral features in the design data are identified and used for SPC applications. For example, if the process drifts out of process limits, these features tend to fail first, so SPC can be performed by monitoring the placement of peripheral features in the design data. Thus, SPC runs faster by monitoring a subset of all features in the design, including the most important features in the design instead of all features in the design, and features in the design that are most sensitive to process changes. Process drift can be detected faster because it is monitored in the SPC. Similarly, peripheral feature information can be used to generate a recipe for a metering process, such as a CD measurement process. The CD measurement process can be any suitable CD measurement process known in the art (eg, CDSEM, scatterometer CD measurement, etc.). Generating a recipe for the CD measurement process includes determining an arrangement on the wafer where the CD measurement is performed in the process (eg, an arrangement in which peripheral features are printed). In addition, a wafer inspection result, such as a BF image captured at the location on the wafer where the CD measurement is performed, is attached to the recipe or fed to the weighing system, which allows the weighing system to use the result. It can be measured by moving to an arrangement on the wafer.

  However, in addition to the test data, the portion of the design that corresponds to the systematic defect is related to the yield probability of the semiconductor manufacturing process and the KP of the systematic defect. In one such embodiment, the inspection system or other system described herein is a systematic defect such as a defect that most likely affects the probability and yield of each individual die. The yield result for can be output. Systematic defect KP is also used for SPC applications. For example, SPC monitoring applications and review sampling can be improved by taking advantage of the probability of each die being obtained and which defects are most likely to affect yield. Thus, SPC is performed based on context-based yield. In addition, improved SPC monitoring and review sampling can improve root cause analysis and baseline reduction.

  In another embodiment, the method includes monitoring a KP value for a group of defects according to a time course and determining the significance of the group of defects based on the results of the monitoring. For example, as the KP value continues to be updated over time, hot spots with low KP values are eliminated or downgraded to conditional hot spots, weak spots, or cold spots. . Thus, a low or zero KP value is assigned to the identified potential hot spot (ie, a cold spot). In other embodiments, the method includes determining a KP value for the group of defects based on the electrical fault density associated with the design data. Thus, hot spots that have been determined not to overlay a relatively high fault density zone on the electrical fault density map are downgraded at the KP and, as appropriate, a hot spot database and / or associated inspection recipe. Removed from.

  In one embodiment, the method includes monitoring a KP value for one or more POIs in the design data, and a portion of the design data proximate to the defect locations divided into one or more groups according to the bin range. Assigning a KP value for one or more POIs to one or more of the groups where. For example, monitoring the KP value for one or more POIs in the design data may be other than electrical faults, electrical fault densities, electrical faults determined for one or more POIs over time ( (Multiple) attributes, or some combination thereof, and based on test results captured for one or more POIs over time. The electrical failure, electrical failure density, and other attributes of the electrical failure are determined using suitable methods or systems known in the art. The test results are captured as described herein. Monitoring the KP value is performed by the method of this embodiment, but monitoring the KP value may be performed by a different method or system, and the assigning steps described above are performed by the method. The In addition, monitoring the KP value is performed in the setup phase before performing the method of dividing according to the bin range, thereby reducing the time between inspections and reducing the KP value to one of the defects. Can be assigned to one or more groups. Assigning a KP value for one or more POIs to one or more of the groups means that a portion of the design data close to at least some positions of the grouped defects by bin range is assigned to one or more POIs. Comparing with the corresponding part of the design data. A portion of design data proximate to at least some positions of defects within a group is at least similar to a portion of design data corresponding to a POI determined based on the result of the comparing step; A KP value corresponding to the POI can be assigned to defects in the group (eg, all of the defects).

  The methods described herein include generating information for one or more diagnostic or repair processes that are sensitive to hot spots (eg, having high signal and low noise for hot spots). This information can be used to automate or optimize one or more diagnostic or repair processes for hot spots. One or more processes can be used for hot spot verification and analysis, incorporating new learning, optimizing non-inspected areas and nuisance defect filtering, reporting, and distinguishing between design and process limits. As described above, this method includes wafer inspection, reticle inspection, optical inspection, macro defect inspection, electron beam inspection, optical defect review, SEM defect review, ellipsometry, CDSEM and other metrology processes, defect analysis process, FIB process, Used to generate recipes for diagnostic and repair processes, such as other FA processes, defect repair processes, etc.

  In some embodiments, the method is performed on a wafer on which design data is printed based on the results of prioritizing one or more POIs in the design data and prioritizing steps. Optimizing one or more processes. Prioritizing one or more POIs is performed as described herein. Optimizing one or more processes in this embodiment includes focus, dose, exposure tool, resist, post-exposure bake (PEB) time, PEB temperature, etch time, etch gas composition, etch tool, deposition Including changing one or more parameters of one or more processes such as tools, deposition times, and the like. Preferably, the parameter (s) of the process (es) are changed to reduce the defect degree of the POIs (eg, the number of defects detected in the POIs), ) Modify one or more attributes (eg, DCI, KP, etc.) of the defects detected in the POI and / or increase the yield of the device containing the (multiple) POI.

  In addition, one or more parameters of one or more processes have only the POI with the highest priority determined by the prioritization step or a relatively high priority determined by the prioritization step. Optimize for POI (s). In this way, one or more parameters of one or more processes are changed and / or optimized based on the POI (s) exhibiting the highest defectivity and / or the defectivity with the highest yield effect. be able to. In doing so, the result of the prioritization step results in the greatest improvement in yield if any POI (s) is used to change and / or optimize one or more parameters of one or more processes. It shows.

  Thus, without guidance that the POI (s) have the greatest impact on yield, it is not possible to identify or create a timely opportunity to optimize the process with respect to yield and stability, and as a result until it is brought to market. This embodiment is advantageous over other already used methods and systems for changing and / or optimizing the process because of the increased time required for the process and the efficiency of process optimization.

  In addition, the process (s) modified and / or optimized in this step may be performed in the design data on the wafer prior to the detection of defects separated according to bin ranges in the embodiments described herein. One or more processes that contain only the process used to print the POI, but are modified and / or optimized, are used to print other design data that also contains the POI (s) Process (s) to be performed. For example, if multiple designs include POI (s), they are used to print multiple designs based on prioritization and / or other results of the methods described herein. One or more processes can be modified and optimized to increase the yield of devices fabricated with each of the different designs.

  In other embodiments, the method is based on the results of the grouping step by bin range and / or other results of the other step (s) of the method (s) described herein. Including altering one or more parameters of a process to be performed on or to be performed on the wafer. This process includes processes known in the art such as CMP, deposition (electrochemical deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition), lithography, etching, ion implantation, cleaning, and the like. Bin range so that defects divided into one or more groups according to the bin range are reduced on the wafer after subsequent processing of the wafer or on other wafers after processing of other wafers One or more parameters can be changed based on the result of grouping by.

  For example, if an etching process is performed on a wafer prior to inspection, the other wafers processed by the etching process using the modified parameter (s) have fewer defects in one or more of the group Preferably using feedback control techniques to show fewer defects with a relatively high DCI, or show fewer defects, such as a relatively high KP value, or some combination thereof Thus, one or more parameters of the etching process can be changed. Such modification of the parameter (s) is performed based on prioritization of the group of defects or other information described herein such as DCI and KP values. In this way, the process is modified based on the group of defects that has the greatest impact on yield.

  In another example, if an etch process was performed on the wafer prior to inspection, the wafer was grouped after the post-etch process was performed on the wafer using the modified parameter (s). Show fewer defects in one or more, show fewer defects with a relatively high DCI, show fewer defects, such as with a relatively high KP value, or show some form of combination thereof, Preferably, feedforward control techniques can be used to change one or more parameters of the post-etch process to be performed on the wafer. The parameter (s) of the post-etch process or other process (s) are also modified as described further above.

  Changing one or more parameters of the process as described above determines how one or more parameters should be changed, and one in the recipe used to execute the process. Changing the value of one or more parameters. Such changes can be made by accessing the recipe stored in a storage medium coupled to, for example, a fab database or a process tool that performs the process, using the methods and systems described herein. This is done by making a change directly to.

  Alternatively, changing one or more parameters of the process, as described above, determines how to change one or more parameters and determines the value of one or more parameters. Other methods or systems used to change the value of one or more parameters in the recipe used to perform the process (eg, a fab database coupled to a process tool that performs the process) Or a processor). Other values such as recipe identification, process tool identification, instructions to change one or more parameters, so that the value of one or more parameters to be changed can also change the process by other methods or systems Can be sent along with the information.

  In one embodiment, the method includes changing the process of inspecting the wafer based on the result of the step of dividing according to the bin range. The process of inspecting a wafer can be modified in this embodiment based on the results of grouping by bin range as described herein. In addition, in this embodiment, the parameter (s) of the process for inspecting the wafer can be changed. For example, one or more parameters of a process for inspecting a wafer that is modified based on the result of a bin range grouping step may include, but are not limited to, an inspection area (or alternatively, Area), sensitivity, inline bin range grouping process, inspection area where wafers are inspected, or some combination thereof. In one particular example, the result of grouping by bin range indicates the number of defects contained in one or more of the groups, and the area to be inspected is the number of defects in the group (s) that contain a relatively large number of defects. It is changed to include a position on the wafer corresponding to the position in the design data space. In other examples, the process of inspecting a wafer is modified to inspect more or differently based on the results of grouping by bin range. The process of inspecting the wafer is further modified based on the results of the step (s) of the method (s) described herein.

  As described herein, defects are detected by an inspection process. In one embodiment, the method includes reviewing the placement on the wafer where the one or more POIs in the design data are printed and the placement of the one or more POIs with defects based on the results of the review step. By the way, determining whether it has been detected and modifying the inspection process to improve one or more defect capture rates. Reviewing the arrangement in this embodiment is performed using methods or systems known in the art. Thus, reviewing the placement on the wafer is performed at the POI placement to determine whether a defect has been detected in the POI placement. In one such embodiment, the method includes an arbitrary pattern search to identify the placement of one or more POIs in the design data, and one on the wafer from the placement of one or more POIs in the design data. Or determining the placement of a plurality of POIs. Determining the placement of the POI (s) in this way is performed as described further herein.

  In addition, in some such embodiments, the method includes displaying POI placement with and without hits in the review step to assist in the review. In doing so, the results of the review are used to determine where defects have occurred but have not been captured by the inspection system. Thus, the POI (s) can be reviewed to find where missed defects (or uncaptured defects) should be found and where inspection process changes or optimizations should be performed.

  Based on this information in addition to the results of the review (eg, one or more attributes of the defect, one or more attributes of the design data, etc.), one of the inspection processes such as optical mode, focusing angle, incident angle, etc. Alternatively, multiple parameters may be changed so that defects are preferably captured at a higher rate of POI placement in subsequent inspections. Thus, this method includes set-up tuning based on the analysis results of defect capture rate in POI. One or more parameters of the inspection process to be changed are determined by any suitable method, such as using a rules database. The one or more defect capture rates improved in this embodiment include defect capture rates for one or more defect types in one or more POIs. Similarly, in order to improve one or more defect capture rates, the above-described embodiments can provide one or more hots in the design instead of reviewing the placement on the wafer on which the one or more POIs are printed. • Performed by reviewing the placement on the wafer corresponding to the spot location.

  In addition, if the method described above is performed for multiple POIs, the POIs are prioritized as described further herein, and the inspection process is performed for the POI with the highest priority or high priority. Changed to improve defect capture rate. In this way, the inspection process is optimized for the highest priority POI or higher priority POIs (such optimization may result in inspection process optimization for lower priority POIs). There is).

  In other embodiments, the method includes changing the process of inspecting the wafer during inspection based on the results of the inspection. Thus, the method includes modifying the inspection process using in-situ process control techniques. The results of the inspection used to modify the inspection process include the results described herein. In addition, changing the inspection process in this embodiment includes changing one or more parameters of the inspection process.

  As further described above, the method includes optimizing the inspection recipe. The inspection recipe to be optimized includes an in-line inspection recipe and / or an electrical inspection recipe. In one embodiment, the method includes changing the process of inspecting the wafer based on the hot spot information. In other embodiments, the method includes generating a process for inspecting a wafer based on hot spot information and design data. In addition, the method includes modifying or generating a process for inspecting the wafer based on the hot spot information and / or the predicted POI. For example, an inspection recipe may only be inspected for hot spot and POI locations and / or not inspected for systematic nuisance defects, or the data captured in such locations may be suppressed in some other way. Configured to be In other examples, as described above, the method embodiments described herein include identifying hot spots in the design (eg, based on systematic defects). Thus, method embodiments may be a source of hot spots and the placement of hot spots in the design is used to modify the inspection process using feedforward control techniques.

  The method further includes modifying the process of inspecting the wafer based on other available information. In one such example, the method includes modifying an inspection recipe based on hot spot information in addition to design data, inspection results, one or more bitmaps. Thus, the information available in this method is to detect defects that affect or may affect yield while reducing the sensitivity of inspection recipes to detect defects that do not affect yield. Used to optimize the sensitivity of inspection recipes. Generating and optimizing the inspection recipe is further performed as described further herein (eg, based on the detectability of the DOI).

  In some embodiments, the method includes determining sensitivity to detect defects on the wafer based on the design data. In some such embodiments, the sensitivity is different for at least two different portions of the wafer that correspond to at least two different portions of the design data. In addition, the method includes identifying an “inspection area” (or “where the area should be inspected”) on the wafer. Inspection results are not captured in the non-inspection area, or defect detection is not performed on inspection results captured in the non-inspection area. However, in this method, when data acquisition and defect detection are performed in a non-inspection area, the detected defects are inspected before additional processing of inspection results such as grouping by bin range is performed. And determining whether it is arranged in the target area or in the non-inspection area. When defects are arranged in the non-inspection area, no additional processing is performed on these defects. Thus, grouping by pattern-based bin range is constrained to sensitive regions in the design data to optimize the grouping throughput by bin range. In other embodiments, grouping information is used as described further herein after defects are grouped by common design data (eg, pattern grouping or other contextual data). Count, bin grouping, monitoring, analysis, sampling, review, testing, and more.

  This embodiment of the method may or may not use hot spot information. For example, the method includes identifying portions of the design data that are critical to yield and / or vulnerable to defects that reduce yield based on knowledge about the design data. Thus, the sensitivity to detect defects in those portions of the design data is higher than the sensitivity to detect defects in other portions of the design data. The method includes aligning the inspection data with the design data as the inspection data is captured, which is performed as further described herein. The sensitivity of the inspection process can then be changed based on the position of the inspection data in the design data space. In such embodiments, the sensitivity of the inspection process is changed in real time. Additional examples of design-driven inspection or measurement recipes include Bevis, US Pat. No. 6,886,153, and Hamamatsu et al., Which are incorporated by reference as if set forth in full herein. Illustrated in US patent application Ser. No. 10 / 082,593, filed Feb. 22, 2002, published as Application Publication No. US2003 / 0022401. The method described herein includes the step (s) described in this patent and this patent application.

  In one embodiment, the method includes selecting at least some of the defects to review based on the results of the bin range grouping step. For example, the result of the bin range grouping step is used to determine which of the defects are most critical as described herein (eg, by determining the DCI for the defect). ) The most critical defects can be selected for review. In other examples, the results of grouping by bin range can be used to determine which of the defects are systematic defects as described further herein. Thus, this method includes review sampling from portions of the design data that are prone to DOI. In addition, using information about which defects are systematic and also whether the systematic defects are visible to review systems such as SEM and / or whether the systematic defects are related to yield. , At least some of the defects to review can be selected (eg, only defects that are visible from the SEM are selected for review). Selecting defects in this way can make it difficult to relocate defects during review, and in particular a significant amount of time for the review system to look for defects that are not actually visible from the review system. This is particularly beneficial because it takes a relatively long time to spend. The results of selecting the defects for review include the placement of the selected defects on the wafer and other results of the step (s) of the method (s) described herein.

  In other embodiments, the method includes generating a process for sampling defects to review based on the results of the binning grouping step. Thus, this method is used to sample defects for review instead of or in addition to selecting defects for review (the method, other methods, configured to perform the method). Generating a process) (by another system or other system). Such a process is used to sample defects detected on multiple wafers for review and / or to sample defects for review performed by multiple review systems. The sampling process is a process in which defects detected in a part of the design data corresponding to a group of defects divided according to a bin range containing a relatively large number of defects are divided according to a bin range containing a relatively small number of defects. It is generated based on the result of the grouping step by bin range so that a large amount of samples are sampled compared to the defects detected in the part of the design data corresponding to the groups. The process of sampling defects for review is grouped by bin ranges in combination with other results of the step (s) of the method (s) described herein, such as DCI for defects, KP values for defects, etc. Generated based on the result of the step.

  In other embodiments, the method includes generating a process for selecting defects for review based on hot spot information. The process of selecting defects for review is generated based not only on hot spot information, but also other information available in the method. For example, the process of selecting defects for review is generated based on design data, one or more attributes of the defects, one or more bitmaps, and hot spot information. Preferably, the process of selecting defects for review is such that a defect detected at a hot spot or a specific type of defect, such as a systematic defect, is selected for review while being detected at a cold spot. And other types of defects, such as nuisance defects, are generated so that they are not selected for review. Thus, the methods described herein affect or affect yield while increasing the review process throughput by largely excluding defects from review samples that do not affect yield. A defect sample containing most of the possible defects can be output.

  In other embodiments, the method is more effective than CDSEM, optical, or other forms and classification or verification of physical defect review after defects are separated according to bin ranges by at least similar design data as described above. Including using binning grouping results for the purpose of creating “informative” review samples. In one such embodiment, the method includes pattern group identification as described above that illustrates the pattern group identification on the x-axis and the number of defects detected in each pattern group on the y-axis. Generating a Pareto chart. Thus, this figure shows the number of defects detected in different patterns. However, other data indicating the number of defects detected in different patterns is used in the method steps described herein. The embodiments described herein further include generating electrical, systematic, and / or random Pareto diagrams.

  The method includes analyzing data for one or more of the different patterns illustrated in this figure to determine one or more physical defect types detected in each pattern type. Multiple defect types are detected in the pattern group. The method is further divided into one or more groups corresponding to one or more different signatures according to bin ranges by analyzing the data for one or more of the different spatial signatures illustrated in this figure. Determining one or more attributes of the defect. The defect attribute (s) include, but are not limited to, size and die placement (or die identification symbol) as well as other attributes known in the art. The die placement indicates whether the pattern has a higher appearance frequency in a particular placement, zone, or region of the wafer, such as edge, center, 3 o'clock position.

  A defect sampling plan is determined from the results of the analysis steps described above. For example, the method includes determining whether a strong signal is emitted from the analysis step described above. This strong signal indicates which defects (eg, which pattern and which defect type and / or attribute are determined by the analysis step) should be sampled at a higher or lower rate. The sampling plan described above can reduce the throughput of review systems that are relatively slow in some other methods, such as electron beam based review systems, atomic force microscopes (AFM), or scanning probe microscope based review systems. May be particularly useful for enhancing.

  The methods described herein are further used to optimize review recipes. For example, in one embodiment, the method includes modifying the process for reviewing defects on the wafer based on hot spot information and other information available in an appropriate manner. Review recipe parameters that are modified or selected based on this information include review process data collection parameters and data processing parameters. This method further includes the type of review system to be used to review the defects (e.g., optical or electron beam) and the manufacture and model of the review system to be used to review the defects, Including selecting additional parameters for the review process.

  The method further includes providing information to the review system that is used to assist in determining the placement on the wafer on which the review is to be performed. For example, the location of the defect being reviewed is reported to the review system in design data space, die space, and / or wafer space. In addition, other information regarding defects and / or defect locations may be sent to the review system. For example, in addition to the portion of the design data corresponding to the defect location, an image or overlay of the defect generated by in-line inspection is supplied to the review system. In this way, the review system can use some or all of this information to find the placement of selected defects on the wafer during review. In addition, the results of one or more steps of one or more methods described herein can be sent to the review system so that the review system can use those results. Then, automatic defect position identification (ADL) is executed based on the edge placement error. In addition, the method includes determining where to measure or test for review based on the results of the test and systematic identification (possibly using yield association and / or process window mapping). The review is further published on Oct. 20, 2005, published as US Patent Application Publication No. 2006/0082763 on April 20, 2006, which is incorporated by reference as if set forth in its entirety herein. Includes user-assisted review performed using methods and systems such as those disclosed by Teh et al. In commonly-assigned US patent application Ser. No. 11 / 249,144. Thus, use cases for bin range grouping methods (and methods for assigning classifications to defects further described herein) include systematic discovery and user-assisted review.

  In one embodiment, the method includes altering the wafer weighing process based on the result of the bin range grouping step. For example, the weighing process is modified so that the most critical defects as determined from the result of the binning grouping step are measured in the weighing process. Thus, changing the metrology process includes changing the arrangement on the wafer where measurements are performed in the metrology process. In addition, by sending inspection and / or review results, such as a BF image and / or SEM image of the defect selected for measurement, to the metrology system, the results are used to perform the measurement. Can be determined. For example, the metrology process includes generating an image of an approximate placement of defects on the wafer, and comparing this image with the results of inspection and / or review for defects, the metrology system is correct if necessary. The position on the wafer is corrected so that measurements are performed on the wafer placement and thus for the correct defects. Thus, the measurement is performed with a substantially accurate placement on the wafer. Changing the weighing process may further include the type (s) of measurement to be performed, the wavelength (s) at which the measurement is performed, the angle (s) at which the measurement is performed, or some combination thereof Changing one or more other parameters of the metering process. The metering process includes any suitable metering process known in the art, such as a CD measurement metering process.

  In another embodiment, the method includes changing the sampling plan of the metrology process for the wafer based on the result of the grouping step by bin range. The method thus includes adaptive sampling. For example, the sampling plan for the weighing process is modified so that the most critical, more defects as determined from the result of the bin range grouping step are measured in the weighing process. In this way, the most critical defects are sampled more in the weighing process, which can advantageously output more information about the most critical defects. The metering process includes a metering process known in the art. In addition, the metering process includes a suitable metering system known in the art, such as SEM. In addition, the metrology process includes performing suitable measurements known in the art of suitable attributes of defects or features formed on the wafer, such as profile, thickness, CD, and the like.

  Similarly, this method can analyze defects based on hot spot information or other information available in an appropriate manner (eg, metrology or composition analysis), or repair defects on the wafer. Including changing the process. For example, the method includes modifying processes such as electron dispersive X-ray spectroscopy (EDS or EDX) to analyze the composition of defects or defect repair or FIB processes of FA. The process of analyzing or repairing defects is modified as described herein with respect to modifying other processes. For example, the analysis or repair process is modified to be performed only on selected defect placements, which are selected as described herein. In addition, one or more parameters of the analysis or repair process are selected and changed based on other results of the step (s) of the method (s) described herein. Such results can include, for example, defect classification, defect root cause, defect size, defect criticality (indicating accuracy when analysis and / or repair is performed), yield impact, analysis and / or repair. One or more attributes of the design data in proximity to the indicating defect (feature dimensions, feature density, hierarchy, redundancy, etc.), as well as the accuracy with which analysis and / or repair is performed. Additional examples of methods and systems for generating recipes for metering tools are illustrated in McGhee et al. US Pat. No. 6,581,193, which is incorporated by reference as if described in full herein. ing. The methods and systems described herein are configured to perform the additional step (s) described in this patent.

  In some embodiments, the method includes locating the root cause of the defect based on one or more attributes of the design data. In other embodiments, the method includes locating the root cause of one or more groups in which the defects are separated according to bin ranges. For example, in one embodiment, the method may result from at least some review of defects in one or more groups, one or more attributes of design data, one or more attributes of defects, or Locating one or more root causes of the group of defects based on some combination thereof. Thus, the method includes determining the root cause of defects individually or collectively as a group. The root cause of a defect or group of defects is determined based on analysis results obtained from a diagnostic system such as, for example, an EDS system used to analyze the defect by measuring the defect composition. An example of such an EDS system is illustrated in Wang et al., US Pat. No. 6,777,676, which is incorporated by reference as if fully set forth herein.

  The root cause phase includes identifying the source, cause, and / or correction of systematic defects. The root cause phase is performed in multi-source space using the correlation between design space, wafer space, reticle space, test space, process space. For example, in one embodiment, the method includes locating one or more root causes of a group of defects by mapping at least some of the defects in the one or more groups to the results of an experimental process window. Including. Experimental process window results are generated by the method, other methods, systems configured to perform the methods, or systems other than systems configured to perform the methods. In addition, the PWQ method or other suitable experiment is used (eg, performing an etching process on different wafers with one or more different parameters) and defects on the wafer after the PWQ method or other experiment Can be used to capture the results of the experimental process window. The results of the experimental process window include results captured by inspection and / or review of defects detected on the wafer. For example, the results of the experimental process window may include the image of the defect, the portion of the design data proximate to the position of the defect in the design data space, the position of the defect in the design data space determined as described herein. Or other inspection and / or defect review results described herein.

  Mapping at least some of the defects to the results of the experimental process window is performed using the results of the inspection process. For example, if the experimental process window results include a portion of the design data close to the position of the defect in the design data space or an image of the defect on the wafer, mapping the defect to the experimental process window result is a bin range. An image of a defect divided into one or more of the groups according to is detected in the design data space close to design data that is at least similar to the design data close to the position of the defect divided according to the bin range Comparing with the image in the result of the experimental process window for the defect. In another example, if the experimental process window result includes the position of the defect in the design data space, mapping the defects separated according to the bin range to the experimental process window result in this embodiment is Comparing the position of the defect in the design data space in the window result with the position of the defect divided according to the bin range in the design data space.

  Thus, the result of the mapping step indicates where in the process window space the process performed on the wafer prior to the detection of the defect was performed. In particular, the mapping results show that the defects separated according to the bin range and the defects included in the results of the experimental process window are at least similar and are located at least close to similar design data. If indicated, the value of one or more parameters in the process window in which defects included in the results of the experimental process window were detected correlates with the defects separated according to the bin range, and the bin range As the root cause of the defects divided according to or used to locate the root cause of the defects divided according to the bin range.

  In other embodiments, the method locates one or more root causes of a group of defects by mapping at least some of the defects in the one or more groups to the result of a simulated process window. Including that. The simulated process window results include results similar to the experimental process window results described above. However, rather than performing experiments on a physical wafer, by simulating an image that shows how design data is printed on a wafer with various values of one or more parameters of the process, Capture the results of a simulated process window. The process includes a process included in processing a device corresponding to the design data. For example, this embodiment includes modeling a patterning process (eg, lithography or etching) for systematic defect placement and uses the results of such modeling to determine the root cause of systematic defects. I can find out. The simulated process window results are generated using any suitable method or system known in the art. For example, PROLITH software commercially available from KLA-Tencor can generate simulated process window results. In addition, the result of the simulated process window is the result of the method, other methods, systems configured to perform the method, or systems other than systems configured to perform the method. Generated by the system. Locating the root cause in this embodiment is performed as described above with respect to the results of the experimental process window.

  The root cause phase includes determining the source and / or correction of systematic defects. One possible source for systematic defects is process window shift. In addition, knowledge of the hot spot signature provides information about where the process is operating within the process window. The root cause phase further includes determining the most significant opportunity to improve the process to expand the process window. In addition, the root cause phase involves determining the most significant systematic issues in improving reticle design. The root cause phase further includes determining the most significant systematic issues in improving and / or implementing next generation technology.

  In some embodiments, the method includes determining the percentage of dies that are formed on one or more affected wafers of the group of defects. For example, determining the number of detected dies on a wafer in which a defect in the group is detected at least once, and determining the number of inspected dies in which the defect in the group is detected at least once. The ratio can be determined by dividing by. The number of detected dies on the wafer in which a defect in the group is detected at least once is used to detect the design data space position of the defect, the design data space position of the die printed on the wafer, and the defect. Determined based on information about the inspection process. The result of these steps can be multiplied by 100 to get this percentage. In one specific example, if there are 300 defects grouped according to bin range, the defects in this group are placed on 5 dies on the wafer, there are 6000 dies on the wafer, and the percentage is , [(5) (100)] / (6000) or 0.083%. Thus, this percentage reflects the die impact limit for groups of defects. Such percentages are determined for multiple groups of defects, and each (or at least some) of these percentages is displayed in a chart such as a bar graph generated by the method. The chart thus shows the die impact limit that varies depending on the group in which the defects are divided according to the bin range. Such a chart is displayed in a user interface that is configured as described further herein. The method further includes prioritizing one or more groups of defects based on the percentage determined in this embodiment. Such prioritization is performed as described further herein, and the results of such prioritization are used as further described herein.

  In other embodiments, the method includes determining one or more POIs in the design data corresponding to at least one of the groups and at least one of the groups corresponding to the one or more POIs according to the bin range. Determining the ratio of the number of defects divided into the number of one or more POI placements on the wafer. One or more POIs in the design data corresponding to at least one of these groups are determined as described herein. If all instances of one or more POIs on the wafer are not inspected by the inspection process used to detect defects, the placement of one or more POIs on the wafer used in this embodiment The number is the number of inspected placements of one or more POIs on the wafer. Thus, this method calculates the ratio or percentage of POIs in which defects were detected on the wafer compared to the number of POI arrangements printed on the wafer (or the number of inspected arrangements of POI on the wafer). Including performing a marginal analysis by determining. In such an embodiment, the number of POI placements on the wafer is identified by an arbitrary pattern search. In addition, the number of POI inspected locations on the wafer is identified by any pattern search and using information about the results of any pattern search and the inspection process, thereby inspecting the POI on the wafer. The number of placements made can be determined. In addition, the methods described herein include an optional pattern search that identifies the placement of the POI on the wafer and determines the area of the POI. The POI defect density is then determined using the area of the POI and the number of POI placements on the wafer (or the number of POI placements tested on the wafer). The method further includes prioritizing the one or more POIs based on the ratio determined in this embodiment. Such prioritization is performed as described further herein, and the results of such prioritization are used as described herein.

  In an additional embodiment, the method includes determining one or more POIs in the design data corresponding to at least one of the groups and at least one of the groups corresponding to the one or more POIs according to the bin range. The number of defects and the number of one or more POI placements in the design data (or all placements of one or more POIs in the design data during the execution of the inspection process used to detect the defects) Determining the ratio to the number of tested placements of one or more POIs in the design data. Thus, the method determines the ratio or percentage of the number of defects in a group corresponding to the POI compared to the number of POI placements in the design (or the number of POI placements examined in the design). Including performing a marginal analysis. In such an embodiment, the number of POI arrangements in the design data is identified by an arbitrary pattern search. In addition, the number of POI examined locations in the design data is determined as described above. As described further herein, one or more POIs corresponding to at least one of the groups can be determined. The method further includes prioritizing one or more of the POIs based on the ratio determined in this embodiment. Such prioritization is performed as described further herein, and the results of such prioritization are used as described herein.

  In another embodiment, the method determines a POI in design data corresponding to at least one of the groups and forms on the wafer where the defects divided into at least one of the groups according to the bin range are located. Determining a percentage of the die that has been made and assigning a priority to the POI based on the percentage. Thus, the method includes performing a criticality analysis based on the percentage of dies affected by the defect. For example, the number of defects grouped by bin range is divided by the number of POI design instances on the reticle used to print design data on the wafer and the number of times the reticle is printed on the wafer. The The result of this step can be multiplied by 100 to obtain this percentage. In a specific example, if there are 300 defects grouped by bin range, the 2000 design instances of POI correspond to groups on the reticle, and the reticle is printed 1000 times on the wafer, depending on the bin range. The percentage of dies formed on the wafer where the grouped defects are placed is equal to [(300) (100)] / [(2000) (1000)] or 0.015%, which is essentially There is a wafer-based limit to this group of defects.

  Thus, the method includes prioritizing systematic defects by the number of inspected dies on the wafer where the defects have been detected at least once. For example, a higher priority can be assigned to a POI when a systematic defect appears in 10% of the POI design instances in the die versus 1% of the POI design instances in the die. In another example, a defect group with a high number of dies with defects detected on the wafer may be assigned a higher priority than a defect group with a low number of dies with defects detected on the wafer. it can. In addition, the method includes generating a chart, such as a bar graph, showing the percentage of dies formed on the wafer where the defects grouped in different groups according to the bin range are located. Thus, such a chart graphically illustrates the die base limit for different groups of defects. Such a chart is displayed on a user interface configured as described herein. Such prioritization results are used as described herein.

  In yet another embodiment, the method includes prioritizing one or more of the groups by the number of total design instances on a wafer in which a defect included in one or more of the groups is detected. The number of all design instances on the wafer used in this embodiment is the total number of design instances on the wafer if not all of the design instances on the wafer are inspected during the execution of the inspection process used to detect defects. The number of Thus, the method includes prioritizing systematic defects that are known by the number of all design instances on the wafer (or the number of all inspection design instances). In doing so, the method includes prioritizing known systematic defects based on wafer-based marginality. For example, a defect group with a large number of design instances with defects detected on the wafer has a higher priority than a defect group with a small number of design instances with defects detected on the wafer. Can be assigned. Such prioritization is further performed based on the percentage of placement of design instances (or inspected design instances) on the wafer where a defect is detected. For example, the number of defects detected and grouped by bin range can be divided by the total number of design instances on the wafer (or the total number of design instances inspected). Multiply the result of this step by 100 to obtain the above ratio. In addition, the method includes generating a chart, such as a bar graph, that indicates the number of design instances (or the number of design instances inspected) on the wafer in which different groups of defects were detected. Such a chart is displayed on a user interface configured as described herein. Such prioritization is further performed as described herein, and the results of such prioritization are used as described herein.

  In some embodiments, the method includes grouping according to the number of design instances on the reticle that are used to print design data on a wafer that has been detected at least once in one or more of the groups. Prioritizing one or more of the. The number of design instances on the reticle used in this embodiment is the number of design instances examined. Thus, the method includes prioritizing systematic defects that are known by the number of design instances on the reticle in which the defects are found at least once. For example, a defect group with a large number of design instances with defects detected on the reticle has a higher priority than a defect group with a small number of design instances with defects detected on the reticle. Assigned. In addition, the method includes generating a chart, such as a bar graph, that indicates the number of design instances on the reticle in which different groups of defects have been detected. Such a chart is displayed on a user interface configured as described herein. Such prioritization is further performed as described herein. In addition, such prioritization results are used as described herein.

  In other embodiments, the method is divided into one or more of the number of placements on the reticle in which defects detected in one or more of the groups according to the bin range were detected, and one or more of the groups according to the bin range. Determining a reticle-based limit for one or more of the groups based on the total number of portions of the design data printed on the reticle that are at least similar to the portion of the design data proximate to the location of the defect. . The number of placements on the reticle used in this embodiment includes the number of placements examined. For example, reticle-based marginality is determined by dividing the number of placements in the stacked reticle map where at least one defect in the group is detected by the total number of design instances on the reticle. The result of this step can be multiplied by 100 to determine the percentage of design instance placement corresponding to the group in which the defect was detected. In one particular example, if 300 defects are grouped according to the bin range, there are 2000 design instances for the POI corresponding to that group on the reticle, and the grouped defects by bin range are: Detected at 50 locations on the reticle (determined from the stacked reticle map), the reticle-based marginality for this group of defects is [(50) (100)] / (2000) or 2.5% be equivalent to. In addition, the method includes generating a chart, such as a bar graph, showing the reticle-based marginality or percentage of the arrangement in which defects in different groups were detected. Such a chart is displayed in a user interface that is configured as described further herein. The method further includes prioritizing one or more of the groups of defects based on the reticle-based marginality determined for one or more of these groups. For example, a group that exhibits a relatively high reticle-based marginality is assigned a higher priority than a group of defects that exhibit a low reticle-based marginality. Such prioritization is further performed as described herein, and the results of such prioritization are used as described herein.

  The steps of the above-described embodiments are performed for a group of defects as described above, or for individual defects grouped by bin range.

  Each of the method embodiments described above includes other step (s) of the method (s) described herein. In addition, each of the above-described method embodiments is performed by the system described herein.

  As described in detail above, an embodiment of a method for classifying defects according to bin ranges includes determining DCI. In addition, some methods include determining DCI for one or more defects detected on the wafer, and may include separating the defects detected on the wafer according to bin ranges. For example, it may not be included. For example, one embodiment of a computer-implemented method for determining DCI for defects detected on a wafer is to determine the probability that a defect will change one or more electrical attributes of a device being processed on the wafer in the design data space. Determining based on one or more attributes of design data for the device proximate to the location of the defect. The probability that a defect changes one or more electrical attributes of the device may be the probability that the defect changes one or more electrical parameters of the device and / or spoils the device die. The one or more attributes of the design data include the design data attribute (s) described herein. This probability is further determined based on one or more attributes of the design data in combination with one or more attributes (eg, defect size) of the defects. In addition, this probability is combined with one or more attributes of the defect, the placement of the defect reported by the inspection system used to detect the defect, and inaccuracies in the coordinates of the inspection system. Determined based on attribute (s).

  In one particular example, determining the probability includes determining one or more attributes of the design data, such as a critical area for defects in the design data. In this way, the critical area, reported defect size, reported defect placement can be used to determine the probability that a defect will change one or more electrical attributes of the device. For example, as the defect size increases and the pattern complexity increases, the probability that the defect will change one or more electrical attributes of the device also increases. Thus, using a relationship describing the possibility of spoiling or changing one or more electrical attributes of the device as a function of defect size and pattern complexity, the relative of each defect on each wafer Risk can be determined.

  In another example, to determine whether a defect changes one or more electrical attributes of the device, design data proximate to the position of the defect in the design data space, and the probability of the position of the defect in the design data, Using the defect size as an input to the model, the probability is determined. Thus, this probability is the probability that the defect will change one or more electrical attributes of the device if the defect is located at a particular spot in the design layout.

  The method further includes determining a DCI for the defect based on the probability that the defect changes one or more electrical attributes of the device. For example, DCI is an index that at least roughly correlates with this probability. In one example, a high DCI is determined for defects for which a relatively high probability is determined. In other words, DCI indicates a high degree of criticality for defects that have a relatively high probability of changing one or more electrical attributes of the device. The DCI is determined from the probability using a suitable method, algorithm, data structure, rule, etc., or some combination thereof that describes the relationship between the DCI and the probability. The methods described herein may include experimental results (eg, results of inspection, metrology, review, testing, or some combination thereof), simulation results, empirical data, design information, historical data, or Using any combination to generate such methods, algorithms, data structures, rules, and the like. In addition, DCI can have a suitable format (numeric, alphanumeric, text string, etc.). The DCI can be expressed in such a way that the user can easily understand the value of the DCI. For example, a value between 1 and 10 is assigned to DCI. 10 is the highest DCI and 1 is the lowest DCI. Additionally or alternatively, DCI may be used in a method or system, such as one or more of the embodiments described herein, to perform one or more of the steps described herein. DCI can be expressed in various forms.

  The method further includes storing the DCI on a storage medium. The storing step also includes storing the DCI in addition to other results of the method embodiments described herein. The DCI is stored by methods known in the art. Storage media includes the storage media described herein or other suitable storage media known in the art. In any of the method or system embodiments as described herein, the DCI can be accessed and utilized after being stored in the recording medium. Furthermore, it should be noted that DCI may be stored “permanently”, “semi-permanently”, or temporarily for some period of time. In addition, storing the DCI is performed in other ways as described herein.

  In one embodiment, the defect for which DCI is determined includes a random defect. In other embodiments, the defects for which DCI is determined include systematic defects. Thus, DCI is determined for both random and systematic defects. Defects are determined as random defects or systematic defects as further described herein. In addition, although embodiments of this method are described above as including determining the DCI for defects, this method can be detected on a single defect, several defects, or a wafer. It should be understood to include determining the DCI for all defects. The defect (s) for which DCI is determined in this way is selected by the user. Alternatively, the defect (s) for which the DCI is determined in this way are selected by the method (eg, one or more attributes of the defect (s), the defect (s) in the design data space). Based on one or more attributes of the design data proximate to the location (s), the defect (s) and / or other information about the design data described herein, or some combination thereof .

  In some embodiments, the one or more electrical attributes include device functionality. Thus, DCI is determined based on the probability that a defect will cause a malfunction or malfunction of the device. In other embodiments, the one or more electrical attributes of the device include one or more electrical parameters of the device. Thus, DCI is determined based on the probability that a defect will change one or more electrical parameters of the device. This probability is then the probability that the defect causes an electrical parameter problem. The problem of electrical parameters may not be considered as an electrical defect in electrical testing, but this is an indication that the defect will change the electrical performance of the device, and other wafers if the defect persists It can begin to cause electrical defects over time. The electrical parameter (s) includes electrical parameter (s) known in the art such as device speed, drive current, signal quality, power distribution and the like.

  In one embodiment, the one or more attributes of the design data include redundancy, a net list, or some combination thereof. In other embodiments, the one or more attributes of the design data include feature dimensions in the design data, feature density in the design data, or some combination thereof. Such attributes are used to determine probabilities as described above. In additional embodiments, the one or more attributes of the design data include one or more attributes of the design data for multiple design layers of the device. Thus, this probability is determined based on multi-layer context information for the defect, which can also occur if the defect affects one or more layers of the design by propagating through the device and on the wafer. Devices formed in are typically advantageous because they are typically formed of multiple layers. Thus, a defect changes the design data printed on multiple layers of the device, and if there is a change in any of these layers, or part of the layers, or all of the layers, Or several electrical attributes change. In doing so, it uses one or more attributes of the design data to determine this probability, determines the probability based on how the defect can affect one or more layers of the device, Thereby, in some cases, the probability and DCI determined from the probability can strongly indicate a potential parameter problem and have a high yield relevance.

  In some embodiments, determining the probability includes determining the probability using a correlation between an electrical test result for the design data and one or more attributes of the design data. For example, the method includes performing data mining to determine if there is a correlation between one or more attributes of the design data and the electrical test results. In particular, one or more attributes of the design data printed on the wafer, such as line width, spacing, etc. are measured and the electrical test results for the wafer are used to determine the attribute (s) and electrical test of the design data. A correlation between the results can be determined. The electrical test results may include measurements of one or more electrical attributes of one or more devices formed on the wafer, or may include one or more electrical attributes of the device (s). Used to determine. Thus, this correlation is determined as a correlation between one or more attributes of the design data and one or more electrical attributes. Electrical test results include suitable electrical test results obtained using methods or systems known in the art. Defects are identified as random defects according to the embodiments described herein. Such correlation can be used to determine probabilities for both systematic and random defects. Using such a correlation to determine the probability compares using the correlation and one or more attributes of the design data that are located close to the location of the defect in the design data space. This is advantageous because the probability can be determined quickly.

  In other embodiments, determining the probability is reported by the inspection system used to detect one or more attributes of the design data combined with the probability that the defect is located in the design data space. Determining the probability based on the location of the defect, the inaccuracy of the inspection system coordinates, the size of the defect, the defect size error of the inspection system, or some combination thereof. In one such embodiment, the defect includes a random defect. In this manner, the defect size reported by the inspection system, the placement of defects, and the inaccuracy of the inspection system coordinates can be used to determine the DCI for random defects. Determining DCI using defect size, defect size error, reported defect placement, and coordinate inaccuracy as described above is advantageous because the size and placement of random defects may be relatively unpredictable. is there. Therefore, the accuracy of DCI can be improved by using such information to determine DCI.

  In additional embodiments, determining the probability includes determining the probability based on the one or more attributes of the design data in combination with the one or more attributes of the defect. In one such embodiment, the defects include systematic defects. In this way, systematic defect attributes can be used to determine DCI for systematic defects. Defects are identified as systematic defects by the embodiments described herein. Since the embodiments described herein can determine the location of systematic defects in the design data space with relatively high accuracy, one or more attributes of the systematic defects determine the DCI for the defects. Used to do.

  In one embodiment, determining the DCI includes determining the DCI for the defect based on the probability in combination with the classification assigned to the defect. For example, DCI can be determined based on probability, and then DCI can be modified based on defect classification, thereby improving DCI. In one such example, if the defect classification indicates that the defect is a short-circuit defect, the DCI for the defect is changed so that the changed DCI has a higher criticality for the defect than the initially determined DCI. As shown. In a different example, if the defect classification indicates that the defect is a partial short circuit defect, the DCI determined for the defect is changed so that the changed DCI is greater than the initially determined DCI for the defect. A low criticality can be indicated. The classification of defects used in this embodiment is determined according to the embodiments described herein, or using other methods or systems known in the art to classify defects. Or assigned to a defect. In addition, the DCI may be the result of other step (s) of the method (s) described herein (eg, KP value for defects) or other available information (eg, hot Corrected using spot information).

  In some embodiments, the method includes determining design data proximate to a defect location in the design data space by determining the location of the inspection data in the design data space, which is described herein. Performed as described. In other embodiments, the method includes determining design data proximate to the position of the defect in the design data space by defect alignment, which is performed as described herein. In additional embodiments, the method includes, at least in part, the location of the defect reported by the inspection system used to detect the defect, inaccuracies in the coordinates of the inspection system, one or more of the design data. Determining design data proximate to the location of the defect based on the attributes of the defect, the defect size, the defect size error of the inspection system, or some combination thereof, as further described herein. Executed. In this way, at least part of the design data that is close to the position of the defect in the design data space is an arrangement that is likely to be able to locate the defect within the reported accuracy of the defect and the coordinate accuracy of the inspection system. To be determined. Design data that exceeds the location where defect location is likely to be possible is determined in a similar manner.

  In one embodiment, the method includes modifying the DCI based on design data yield sensitivity to defects. Thus, the DCI is modified based on the sensitivity of yield effects within a region (eg, cell or functional block) in the design. For example, the method may be performed as described herein, including determining a position of a defect in the design data space, and / or due to a defect located at this position Yield sensitivity due to defects in the design data close to. Such yield sensitivity is determined using the embodiments described herein. For example, the method includes modeling electrical characteristics of a device being processed using the design data with respect to position in the design data space for different values of one or more attributes of the design data, which includes defects. Is selected based on the method of changing one or more attributes. Such modeling is performed as described herein, and the modeled electrical characteristics are used to determine how the yield is when the value of one or more attributes of the design data changes. This can be used to determine if it changes, and this can be used to determine the yield sensitivity of the design data for defects located at that location and / or for defects in the design data close to this location. Thus, the position of the defect in the design data space is used to determine the yield sensitivity of the design data to the defect. If the yield sensitivity of the design data for a defect is relatively high, the DCI for that defect can be modified so that the modified DCI exhibits a higher degree of criticality than the DCI that was originally determined. Similarly, if the design data yield sensitivity to a defect is relatively low, the DCI for that defect can be modified so that the modified DCI exhibits a lower degree of criticality than the DCI originally determined. .

  As further described above, DCI can be used in a variety of ways in the embodiments described herein. For example, in one embodiment, the method includes changing the process performed on the wafer based on the DCI determined for the defect. In one such embodiment, the process is a metrology process or includes one or more measurements on the wafer. Thus, the method includes adapting the measurement process based at least in part on DCI. In other embodiments, the process is a defect review process. In doing so, the method includes adapting the defect review process based at least in part on the DCI. Changing this process as described above involves changing one or more parameters of the process. In addition, such changes are performed as described further herein.

  In other embodiments, the method includes changing the process used to detect the defect based on the DCI determined for the defect. Changing the process used to detect the defect includes changing one or more parameters of the process as further described herein. In addition, changing the process used to detect defects based on DCI is performed using feedback control techniques. In one such example, if the DCI for a defect indicates that the defect is relatively critical, the process used to detect the defect is a potential defect corresponding to the defect for which the DCI was determined. One or more arrangements on the wafers that are to be placed are modified so that they are inspected with a higher sensitivity than is already used to inspect those arrangements. The other parameter (s) of the process can be varied as well.

  In some embodiments, the method includes generating a process for inspection of additional wafers on which the device is processed based on the DCI determined for defects. Thus, the method includes creating a completely new inspection process instead of changing the already used process where the defect was detected. A new inspection process is generated for one or more layers of the additional wafer. For example, a process is generated for a layer in which a defect with a determined DCI is detected. However, such an inspection process is also generated for one or more other layers of the additional wafer. For example, if the DCI for a defect indicates that the defect is relatively critical, the process of inspecting subsequently formed layers on the wafer may be caused by the defect for which the DCI is determined. Is generated by selecting one or more parameters of the inspection process such that one or more arrangements on the subsequently formed layer are potentially inspected with relatively high sensitivity. Other parameter (s) of the process are selected as well. Creating a process for inspecting additional wafers is also performed as described further herein.

  In one embodiment, the computer-implemented method for determining DCI is performed by an inspection system used to detect defects. Thus, this method is performed on-tool. In other embodiments, the computer-implemented method for determining DCI is performed by a system other than an inspection system used to detect defects. The method is then performed off-tool. The system used to perform this method off-tool is configured as described further herein.

  DCI for defects is used in various ways in the embodiments described herein, such as for sampling where defects are selected for review. For example, for each group in which defects are separated according to bin ranges, DCI is used for sampling instead of performing random sampling of grouped defects. In addition, the DCI determined for a defect can be a large number of defects that have a high probability of changing one or more electrical attributes of the device, and defects that have a high probability of changing one or more electrical attributes. Used to determine whether to sample. DCI is used to sample not only systematic defects but also random defects.

  Each of the method embodiments for determining DCI described above includes other step (s) of the method (s) described herein. In addition, each of the method embodiments for determining DCI described above is performed by the system embodiments described herein.

  Another embodiment relates to a computer-implemented method for determining a memory repair index (MRI) of a memory bank formed on a wafer. A memory die includes a memory bank (often a large number of memory banks). Each memory bank includes an array block area (or row area) and a redundancy area. The redundancy area includes a number of rows and a number of columns and is used to repair the memory bank. The number of rows and columns included in the memory bank may be user defined. The array block area may be generally square or rectangular. Redundant rows are formed along one side of the array block region, and redundant columns are formed along the other adjacent side of the array block region. The memory bank further includes a row decoder adjacent to the redundant row, a column decoder adjacent to the redundant column, and a sense amplifier adjacent to the column decoder. The method further includes determining the placement of redundant rows and columns, sense amplifiers, and decoders for each array block region. Such an arrangement is determined using methods or systems known in the art.

  The method includes determining the number of redundant rows and redundant columns required to repair the memory bank based on defects located in the array block area of the memory bank. For example, in some embodiments, the method includes determining which of the defects located in the array block area cause an error in the bits in the memory bank and the error in those bits. Determining the position of the bit causing the error based on the arrangement of the defect causing the error. Alternatively, this method determines which of the defects in the array block area can cause errors in the bits in the memory bank and the placement of the defects that can cause errors in those bits. Determining a position of a bit that may cause an error. Determining which of the defects in the array block area cause or can cause a bit error is performed using one or more attributes of the defect. Includes the defect attribute (s) described herein and / or the results of one or more other steps of the method (s) described herein. For example, the reported defect placement, the coordinate accuracy of the inspection system used to detect the defect, the defect size, and the inaccuracy of the defect size of the defect system are optionally determined as described herein. In combination with DCI for defects, and in some cases, further in combination with correlated inspection and / or electrical test results for memory banks, defects can cause or cause bit errors. Used to determine if there is sex.

  In one such embodiment, determining the number of redundant rows and redundant columns needed to repair the memory bank is performed using the location of the bit causing the error. This step is performed separately using bit positions that can cause errors. For example, individual error bits are not necessarily replaced on a one-to-one basis with redundant rows and columns. Instead, if individual error bits are “adjacent” to each other along the same logical row or column, that entire row or column is a candidate for replacement by an available redundant row or column. Thus, the position of the bit that is or can cause an error can be used to determine which error bits are "adjacent" to each other along the same logical row or column, Can be used to determine the number of redundant rows and columns needed to repair a memory bank. As such, the method includes a predictive bit error estimate that is used to determine and / or monitor the amount of redundancy consumed by an errored bit.

  In addition, the two memory bits may be physically adjacent to each other in the layout, but may belong to different logical rows or logical columns. In other words, physical adjacency does not correlate with logical or electrical adjacency. For example, if logical row 1 comprises 256 bits, these 256 bits are not necessarily adjacent to each other in the physical layout of the bank or segment. In so doing, physical (or topological) addresses are converted to logical (or electrical) addresses through a mapping function that may be different for each device. Such mapping is performed using any suitable method or system known in the art. For example, Klarity Bitmap, commercially available from KLA-Tencor, uses graphics to create topological address-to-electrical address mapping, or provides some other easy-to-use means. Therefore, by using such a mapping function in this way, it is possible to determine an MRI that accurately reflects the repairability of the memory bank.

  Defects located in the array block area are identified in or from the results of the memory bank inspection. For example, the inspection can detect defects in both the array block area and the redundancy area (or across the entire memory bank), and the defects are redundant with the defects in the array block area based on the placement of the defects. Divided into defects in the region, this is determined by the embodiments described herein. By isolating defects in the array block area, redundancy area, decoder area, and sense amplifier area, defects that can be repaired using such isolation can be separated from defects that cannot be repaired, The value of the test result is increased. In addition, dividing these defects into defects in the row region, the redundancy region, the decoder region, and the sense amplifier region can be rule-based or region-based.

  The method further includes comparing the number of redundant rows required to repair the memory bank with the number of available redundant rows in the memory bank. In addition, the method includes comparing the number of redundant columns required to repair the memory bank with the number of available redundant columns in the memory bank. In some embodiments, comparing the number of redundant rows is performed separately for each bank of the memory die, and comparing the number of redundant columns is performed for each bank of the memory die. Executed separately. Comparing the number of redundant rows and comparing the number of redundant columns is performed in a suitable manner.

  In another embodiment, the method determines the number of available redundant rows and the number of available redundant columns based on the defects located in the redundant rows of the memory bank and the redundant columns of the memory bank. Including doing. Defects located in redundant rows and columns are identified as described above. Determining the amount of available redundant portion as described above may be advantageous because a memory bank failure can occur if the redundant portion is sufficiently defective. In addition, if the redundant part is partially defective, the amount of redundant part available for repairing the memory bank is reduced, and if the number of errors exceeds the amount of redundant part without defect, the memory bank It may not be repairable. The amount of available redundancy is further determined by the fact that each bank has its own set of redundant rows and columns, as described further above, and error bits within each bank are within the same bank. Is determined for each individual memory bank in the die.

  The amount of available redundancy is further determined based on the defects located in the redundancy area and one or more attributes of the defects located in the redundancy area. The attribute or attributes used in this step include the defect attribute (s) described herein. Determining the available redundancy is performed using the results of the step (s) of the method (s) described herein in addition or separately. For example, using the reported defect size of the defect in the redundancy area, the coordinate accuracy of the inspection system used to detect the defect, and the classification assigned to the defect, the defect fails in the redundancy area. Can be determined, but this is used to determine the amount of available redundancy.

  The method further includes determining the MRI of the memory bank based on the result of comparing the number of redundant rows and the result of comparing the number of redundant columns. MRI indicates whether the memory bank can be repaired. For example, if the number of redundant rows and / or columns required to repair an error bit is greater than the number of available redundant rows and / or columns, the memory bank is not repairable and the die is repaired Can not. An MRI can be determined based on such a comparison and a value can be assigned to the MRI that indicates whether the memory bank is repairable. For example, a first value may be assigned to the MRI if the memory bank is repairable and a second value may be assigned to the MRI if the memory bank is not repairable. Different values for the MRI are expressed in a suitable format (eg, so that the values are easy for the user to understand and / or so that the methods described herein can be used according to embodiments). Suitable formats include, but are not limited to, numeric values, alphanumeric characters, text strings, and the like.

  The method further includes storing the MRI on a storage medium. The storing step includes storing the MRI in addition to other results of the method embodiment (s) described herein. The MRI is stored by methods known in the art. In addition, the storage medium may be the storage medium described herein or other suitable storage medium known in the art. In any of the method or system embodiments as described herein, after the MRI is stored, the MRI in the recording medium can be accessed and utilized. Furthermore, the results can be stored “permanently”, “semi-permanently”, temporarily for some period of time. Storing the MRI is performed in addition or separately as described herein.

  Thus, although the method embodiments described above are used for early detection of memory loss using MRI, this is advantageous for a number of reasons and is used in a variety of ways. For example, in one embodiment, the method includes determining MRI for a plurality of memory banks formed in the die and predicting a die repair yield based on the MRI for the plurality of memory banks. Including. Predicting the repair yield of a die based on the MRI determined for the memory banks in the die, since each bank or segment of the die has a corresponding set of redundant rows and redundant columns available for repair, It is advantageous. Bits causing errors in a particular bank or segment are replaced only with the corresponding redundant row or column available. Thus, one bank may “run out” of redundancy, but redundancy may remain in other banks in the die. In this case, the die can no longer be fully repaired because at least one bank or segment is not repairable. The method can then determine the yield of the repair process performed on the die based on the MRI for the memory banks in the die. In addition, the MRI is determined for the die based on the MRI determined for the memory bank in the die, which indicates whether the die can be repaired. For example, if the MRI for a memory bank indicates that any of the memory banks is not repairable, the MRI is determined to be a value indicating that the memory die is not repairable.

  In other embodiments, the method includes determining the MRI for each memory bank of one or more dies on the wafer and determining the MRI for one or more dies based on the MRI for each memory bank. Determining a memory yield. These steps are performed as described above. This embodiment of the method is used to determine die-to-die memory yield. In addition, the memory yield for one or more dies can be used to determine the memory yield for the wafer.

  In other embodiments, the method includes combining the memory yield prediction with a yield prediction outside the memory to determine a total yield prediction.

  In additional embodiments, the method includes performing placement of the wafer based at least in part on the one or more memory yields for the one or more dies on the wafer. For example, the methods described herein can be used to perform inline placement of wafers, thereby improving (eg, increasing efficiency) WIP planning and reducing production costs. For example, determine and use the number of dies that have a memory yield below some predetermined threshold and use it to determine whether to perform repairs on the wafer, remake the wafer, scrap the wafer, etc. can do. In one such example, the number of dies with memory yields below a predetermined threshold can be compared to other predetermined thresholds to determine whether repair should be performed on the wafer. Both thresholds can be selected to represent the minimum wafer-based yield required to do. For example, the threshold may correspond to a minimum memory yield where the wafer estimate does not exceed the cost of completing the wafer (eg, by one or more embodiments described by a user or described herein). Selected). In other embodiments, the method includes determining a memory yield for the wafer based on a memory yield for one or more dies on the wafer. Thus, memory yield is the yield after the memory repair process, provided that the process is performed on one or more dies on the wafer. As described above, the memory yield for a wafer can be used to dispose of the wafer. For example, the value of the wafer after the memory repair process is determined at least in part based on memory yield, and this value can be compared to the cost of completing the wafer to determine whether the wafer should be scrapped. it can.

  In one embodiment, comparing the number of redundant rows includes determining a portion of the redundant row necessary to repair the memory bank, and comparing the number of redundant columns includes: Determining the MRI for the memory bank includes determining a MRI for the memory bank based on a portion of the redundant row and a portion of the redundant column. Including.

  A method that includes determining the MRI based on the ratios described above includes the other steps described herein. For example, in one such embodiment, the method may determine an MRI for each memory bank of one or more dies on the wafer and one or more based on the MRI for each memory bank. Determining the memory yield of the plurality of dies. The steps of this embodiment are performed as described further herein. In other examples, in such other embodiments, the method is based on determining the MRI for each memory bank of one or more dies on the wafer and based on the MRI for each memory bank. Determining the memory yield of one or more dies, and determining the memory yield of the wafer based on the memory repair yield for each of the one or more dies. The steps of this embodiment are performed as described further herein. Thus, the method includes predicting memory yield based on wafer-to-wafer using MRI. Similarly, an MRI can be determined for each die on the wafer and the MRI for each die can be used to determine wafer-based memory yield. For example, wafer-based memory yield is calculated by dividing the sum of the MRI for each die on the wafer by the number of dies on the wafer, and for die on the wafer that is good or repairable for that memory. Determined by determining the percentage. The percentage of dies on the wafer that are good or can be repaired is sometimes combined with information about the repair process, such as yield or success rate over time, and thus performed on the wafer. It is possible to appropriately predict the memory yield for the repair process.

  In some embodiments, the MRI further indicates the probability that the memory bank will not be repairable. Thus, MRI indicates whether the memory bank is repairable and the probability that the memory bank is not repairable. The probability that a memory bank is not repairable is performed as described above, comparing the number of available redundant rows with the number of redundant rows required for repair and the available redundant columns. And the number of redundant rows required for repair, and possibly one or more attributes of the defect, one or more attributes of the memory design, one or more of the repair process, or Determined by combining multiple attributes. Such attributes include, for example, a success rate as a function of time over a repair process performed in another memory bank that is at least similar in design to the memory bank for which the probability is determined. Such MRI is represented by two values, one being a value indicating whether or not the memory bank can be repaired, and the other being a value indicating the probability that the memory bank is not repairable. Alternatively, the MRI is represented by a single value, which is a value indicating whether the memory bank is repairable and the probability that the memory bank is not repairable. Two values and a single value are expressed in the format described herein. In one such embodiment, the method includes determining an MRI for each memory bank of one or more dies on the wafer and an MRI for each of the memory banks of one or more dies. Determining the MRI of the one or more dies based on. These steps are performed as described herein. In one such embodiment, the MRI for one or more dies indicates the probability that one or more dies will not be repairable (the MRI for each memory bank will make the memory bank unrepairable) This shows the probability, and as explained further above, die repairability is related to memory bank repairability). In one such embodiment, the method includes determining a wafer-based memory yield prediction based on MRI threshold settings for one or more dies on the wafer. Determining the wafer-based memory yield prediction is performed as described above, but the wafer yield is no longer the yield of the repair process as described above.

  In some embodiments, the method includes one or more defects located in the decoder area of the memory bank, one or more defects located in the sense amplifier area of the memory bank, or Identifying irreparable defects in a memory bank (eg, memory bank logic peripherals) based on some combination thereof. For example, a memory bank test is performed to detect defects in all areas of the memory bank (including, for example, logic peripheral circuits, decoder areas, and sense amplifier areas) and is described herein. The placement of defects in the memory bank, as determined by certain embodiments, is used to determine in which region of the memory bank each or one or more of the defects is located. The number of non-repairable defects in the memory bank is determined based at least in part on the number of defects detected and located in the decoder and sense amplifier areas. The method further includes estimating the memory yield based at least in part on the unrepairable defects in the memory bank, which includes the die if there are any unrepairable defects. This is advantageous because it can be spoiled.

  In one embodiment, the method includes changing one or more parameters of the electrical test process based on MRI using a feed forward control technique. In other embodiments, the method uses an MRI using a feed forward control technique so that if the memory bank is not repairable, the die in which the memory bank is located is not tested during the electrical test process. Changing one or more parameters of the electrical testing process based on For example, the memory test takes a relatively long time. Therefore, based on the prediction that a memory bank or memory die determined as described above is not repairable, that information is provided to a prober or other memory test system to affect the memory test. Receive a non-repairable die. In this way, the amount of testing can be reduced and the cost of memory testing can be reduced. In addition, memory tests include open / short circuit tests, functional tests, electrical parameter tests. If such a test can be eliminated by using the method described herein to determine which die can be repaired, the memory test process is performed in a fairly short time. Apart from that, the electrical test process can be modified to collect relevant test data for further FA on the non-repairable die, and the prediction of various possible failure mechanisms It is possible to narrow the test to a specific arrangement based on the impact. In addition, memory repair includes using a laser or electrical means to blow fuses, thereby rerouting the decoder to redundant rows and / or columns. After the memory repair, a memory test can be performed to verify the repair and to perform further tests such as a load test. Thus, by determining which dies can be repaired as described herein, memory repairs and additional memory tests can be performed only on repairable dies, and therefore can be quite time consuming. Can be shortened.

  In some embodiments, the method includes one or more repair processes based on one or more attributes, MRI, or some combination thereof of defects located in the array block region of the memory bank. Including changing the parameters. For example, the memory repair process is modified so that no repair is attempted for a memory die that includes a memory bank that has been determined to be unrepairable. In addition, the memory repair process is modified to increase the probability of successful repair. The one or more parameters of the repair process that are modified in this embodiment include the parameter (s) of the repair process.

  In some embodiments, the defects include defects detected at the gate layer of the memory bank. In other embodiments, the defects include defects detected in the metal layer of the memory bank. For example, in memory processing, inspection is performed on a gate layer and a metal layer. The methods described herein are performed on defects detected in one or more of these layers. In addition, most memory processing includes inspection at the gate and metal layer, and the test results obtained at the gate and metal layer can predict yield well, and inspection is performed at the capacitor layer for bit repair. You can also Therefore, the test results generated in the gate layer, metal layer, and capacitor layer were used not only to predict yield, but in addition, the embodiments described herein were detected in the capacitive layer Can be performed on defects.

  In one embodiment, the method includes predicting the bit error mode of the defect based on the placement of the defect in the memory bank. Thus, the defect placement is used to predict the bit error mode. Such information is useful in determining the amount of redundancy required to repair the memory bank. For example, a defect in the p-MOS region of the memory bank causes a sense amplifier failure, which consumes more redundancy than a defect in the n-MOS region. One or more attributes of the design data proximate to the defect and / or one or more defect attributes (eg, size) of the defect are also used to improve the prediction of the bit error mode. In addition to assisting in predicting the redundancy required for repair, or when memory in the die is formed, prediction of failure mode results in bit error (s) ( (Multiple) defects can be identified quickly or appropriately. Early prediction makes it possible to identify and review DOIs that are not possible without FA if bit errors are discovered during testing. It is also possible to identify and review defects that may be related to potential failure of the device, and to reduce the potential failure rate using available redundancy. In this way, defects can be mapped to areas of memory (eg, sense amplifiers), defect and / or area attributes can be used in combination with rules, and bit error modes can be predicted inline. it can.

  In some embodiments, the method evaluates the number of available redundant columns in the memory bank, the number of available redundant rows, or some combination thereof by the memory bank designer based on MRI. Including determining whether to be done. Thus, this method suggests that a “redundancy analysis” be performed to suggest the designer whether a particular memory bank should perform additional rows or columns within the redundancy region. Including. The method described herein is particularly useful in providing feedback on die design because it can be used for early detection of deadly wafers and can speed up yield learning.

  In other embodiments, the method includes determining DCI for one or more of the defects located in the array block region. The DCI for one or more defects is determined as described herein. In one such embodiment, determining the number of redundant rows and redundant columns needed to repair a memory bank is performed using DCI for one or more defects. In other embodiments, determining the number of redundant rows and redundant columns required to repair the memory bank is obtained by determining the DCI for each of the defects located in the array block area of the memory bank. Determining, comparing the DCI with a predetermined threshold, and determining the number of redundant rows and redundant columns needed to repair all defects having a DCI higher than the predetermined threshold Including. For example, DCI is determined for all defects located in the array block area. The DCI is determined for defects located in the array block area as further described herein. In addition, the method includes using DCI to predict the number of row or column failures caused by the defect. For example, if the number of defects defined by the user with a DCI greater than a predetermined value is greater than the number of rows or columns in the redundancy area, MRI (in this example, redundant rows or redundant columns required for repair) Is defined to be greater than 1 (fail). In contrast, the number of defects whose DCI is less than the second predetermined value, which is defined by the user and may be different from the first predetermined value, is greater than the number of rows or columns in the redundancy region. If so, it is determined that the MRI is less than 1 (passed, possibly with some repair). In addition, this method allows for the use of available redundant rows and / or columns that may be needed to repair the memory bank if all defects with a DCI above the threshold require repair. Including determining a maximum count or percentage.

  Using DCI to determine if the memory in the die can be repaired, the actual yield of the individual defects is dependent on the pattern failure caused by the defect, the placement of the defect (eg, the top of the layer, within the layer) Or the like), which varies depending on one or more attributes of the defect, such as the defect size. DCI is determined based on such variations in defects as described herein, thereby reflecting how different defects actually affect yield. In addition, since the systematic defects can have many of the actual yield effects, the method described herein is that which defects detected in the memory bank are systematic defects. And then determining an MRI as described herein based on the criticality of the systematic defect. Systematic defects are identified by the embodiment (s) described herein.

  In some embodiments, the method includes determining an MRI for failure of the memory bank due to a defect located within the array block region of the memory bank. Thus, the method includes determining an index for segment failure due to defects detected in non-redundant regions of the memory bank. Similarly, the method includes determining an index for segment failure due to defects detected in the redundant region of the memory bank.

  In other embodiments, the method includes determining an MRI for failure of the memory bank due to a defect located in the redundant row and redundant column of the memory bank. Thus, the method includes determining an index for logical row and / or column faults. Such an index is used to change one or more parameters of the test process as described above.

  In some embodiments, the method includes generating a stack map of similar memory bank designs that illustrate the spatial correlation between defects detected in the memory bank. Thus, the method includes generating a stacked map that exhibits spatial correlation. Such a stack map is generated by any suitable method known in the art.

  In one embodiment, the method includes determining an MRI based on the die. The method also includes determining MRI on a wafer basis and / or lot basis. Determining MRI on a die basis, wafer basis, and / or lot basis is performed as described herein.

  In other embodiments, the method includes determining an index or memory yield prediction that indicates when a die on the wafer is failed due to a defect located in the array block region. Thus, the method includes determining an index or probability indicating that the die is not functioning due to a bad memory bank. This index is determined as described further herein.

  In an additional embodiment, the method determines the MRI for a memory bank in a die on the wafer and the space between two or more of the memory banks indicated by the MRI that it is not repairable. Generating a die stacking map that exemplifies dynamic correlation. Determining the MRI for the memory bank within the die is performed as described herein. In addition, the stack map is generated in any suitable manner known in the art.

  In yet another embodiment, the method determines between an MRI for a memory bank in a die on the wafer and between two or more of the memory banks indicated by the MRI that it is not repairable. Generating a stacking map of reticles used to form memory banks on the wafer illustrating the spatial correlation. Determining the MRI for the memory bank within the die is performed as described herein. In addition, the stack map is generated in any suitable manner known in the art.

  In some embodiments, the method identifies a memory bank of a die that is affected by a detected defect in the die and ranks the memory bank based on the effect of the defect on the memory bank. Including. Thus, the method includes ranking the list of affected memory banks. The impact of a defect on a memory bank is determined based on information described herein (eg, one or more attributes of the defect, one or more attributes of design data for the memory bank, etc.). The The effects of defects on the memory banks used to rank the memory banks include the effects (eg, adverse effects) of the defects on the memory banks. The memory banks are ranked so that the memory bank with the highest impact of defects is assigned the highest rank and the memory bank with the lowest impact of defects is assigned the lowest rank. Such ranking of the memory banks is used, for example, to determine the relationship between the placement of the memory banks in the die and the extent to which the defects affect the memory banks. In addition, using such a relationship can predict the cause of at least some of the defects, and use this prediction to reduce those defects on additional wafers and / or to the memory bank first Reducing the number of defects that have the greatest impact (e.g., changing the process performed on the memory bank prior to detecting the defect and / or changing the design of the memory bank) The defects that have a low impact on the memory bank can then be reduced (eg, using one or more of the changing steps described above).

  In other embodiments, the method includes determining a percentage of the memory bank formed on the wafer that is affected by a defect in an unrepairable area of the memory bank. The memory bank affected by the defect in the non-repairable area of the memory bank is determined as described herein. This ratio is determined based on the number of such memory banks and the total number of memory banks formed on the wafer. In addition, the method includes determining the percentage of dies that are affected by possible redundancy faults and / or that are affected by unrepairable faults. Possible redundancy failures and non-repairable failures are identified as described herein. In addition, dies that are subject to possible redundancy and / or irreparable failures are identified as described herein. The number of affected dies and the total number of dies formed on the wafer can be used to determine the percentage of dies affected by possible redundancy and / or irreparable failures.

  In some embodiments, the method includes a stacked wafer of faults that may occur in a memory bank formed on the wafer that illustrates a spatial correlation between the faults that may occur. Including generating a map. Thus, the method includes generating a stacked wafer map of indices (relative to spatial correlation) that are divided according to possible faults or bin ranges. Possible faults are identified as described herein, and the laminated wafer map is generated in any suitable manner. Alternatively, the stacking map can display or overlay the probability that the die has a memory fault by a method such as color binning probability bins.

  In other embodiments, the method includes determining an MRI for a plurality of dies formed on the wafer and ranking the plurality of dies based on the MRI. Thus, the method includes generating a ranked list of affected dies on the wafer. The MRI for multiple dies is determined as described herein. In addition, ranking multiple dies based on MRI is performed as described herein and the results of such ranking are as described herein. used.

  Each of the method embodiments for determining MRI described above includes other step (s) of the method (s) described herein. In addition, each of the method embodiments for determining MRI described above is performed by the system embodiments described herein.

  Other embodiments relate to different methods of dividing defects detected on the wafer according to bin ranges. The method includes comparing a defect location in the design data space with a hot spot location in the design data. Comparing the position of the defect with the hot spot is performed in a suitable manner. Hot spots located close to at least similar design data are correlated with each other. Hot spots can be correlated to each other by other methods or systems. Alternatively, hot spots can be correlated with one another according to one embodiment of the method. For example, in one embodiment, the method correlates hot spots by identifying POI placement in design data associated with systematic defects, and similar patterns in POI and design data. Correlating and correlating POI placement with placement of similar patterns in the design data as correlated hot spot locations. In one such embodiment, the systematic defects can be contained in a data structure such as a list of systematic defects, design data, or files for the design data generated by other methods or systems. In other such embodiments, the method includes identifying systematic defects and / or determining a POI in the design data for systematic defects. For example, systematic defects are identified by separating defects detected on the wafer according to bin ranges based on the portion of the design data that is close to the position of the defect in the design data space, which is performed as described above. Is done. The POI is determined by extracting the pattern of the part of the design data corresponding to the group in which the defect is divided according to the bin range. Thus, design background-based grouping can be used to correlate hot spots with each other, which is performed as described further herein. Further, it is possible to correlate hot spots with each other by separating hot spots according to bin range, which is performed as described further herein. Correlating hot spots with each other is performed on-tool. The location of the correlated hot spots is the “hot spot list” or some information indicating which hot spots are correlated with each other, the hot spot identification in the list, the location of the hot spots in the list Are stored in other suitable data structures. This list is essentially used as reference data in the bin range grouping method.

  The method further includes associating a hot spot having a location that is at least similar to the defect. In particular, defects and hot spots having at least similar positions in the design data space are determined based on the result of the comparing step described above. Defects and hot spots having locations in the design data space can be associated with each other in a suitable manner. In addition, the method includes grouping defects by bin ranges so that defects in each of the groups are associated only with hot spots that correlate with each other. In this way, each group of defects can correspond to a group of correlated hot spots.

  The method further includes storing the result of the grouping step according to the bin range on a storage medium. The storing step includes storing the results of the bin range grouping step in addition to other results of the method embodiments described herein. The result of the bin range grouping step is stored by methods known in the art. In addition, the storage medium may be the storage medium described herein or other suitable storage medium known in the art. In any of the method or system embodiments as described herein, after the bin range grouping step results are stored, the bin range grouping results in the recording medium result. And access their results. Furthermore, it should be noted that the results of the bin range grouping step can be stored “permanently”, semi-permanently, temporarily, or for only a short time. Storing the results of the bin grouping step is further performed according to other embodiments described herein.

  In one embodiment, the method includes assigning a DBC to one or more of the groups. Assigning a DBC to one or more of the groups is performed according to the embodiments described herein. In other embodiments, the method includes determining a DCI for one or more of the defects. Determining the DCI for one or more of the defects in this embodiment is performed by any of the embodiments described herein.

  In other embodiments, the computer-implemented method is performed by an inspection system that is used to detect defects on the wafer. Thus, the computer-implemented method is performed on-tool. In addition, the method includes performing on-tool hot spot management. Hot spot management includes, for example, hot spot discovery, hot spot monitoring, hot spot revision, or some combination thereof, each performed as further described herein. For example, in some embodiments, hot spots are identified by an inspection system used to detect defects on the wafer. In this way, hot spots are identified or discovered on-tool. Such identification or discovery of hot spots is performed as described herein (eg, by performing a design background-based grouping of defects detected on the wafer). .

  In other embodiments, the method includes monitoring hot spots using inspection results of one or more wafers on which design data is printed. Monitoring the hot spot based on the results of the inspection is performed as described herein. Such monitoring of hot spots is performed “on-tool”. Monitoring hot spots may additionally or alternatively be the result of one of the methods of grouping by bin range described herein, as a result of the above-described inspection, as described herein. The result of assigning one or more DBCs to one or more defects, performed as described, any other result of any of the methods described herein, or Is implemented using some combination of

  In other embodiments, the method includes inspecting the wafer based on the correlation between hot spots. For example, locations on the wafer corresponding to different groups of correlated hot spots are inspected differently. Inspecting the wafer based on the correlation between the hot spots is also performed based on the correlation and one or more attributes of the design data corresponding to the group of correlated hot spots. For example, the location of a group of correlated hot spots corresponding to design data having a particularly high yield sensitivity to defects is used to determine the location on the wafer to be inspected with higher sensitivity than normal sensitivity. be able to. The one or more attributes of the design data used in this embodiment include any of the design data attribute (s) described herein. In addition, one or more parameters of the inspection process can be changed so that locations on the wafer corresponding to different groups of correlated hot spots are inspected differently. The one or more parameters of the examination include the parameter (s) described herein.

  In some embodiments, the method includes monitoring systematic defects, potential systematic defects, or some combination thereof over time using the result of the step of binning according to bin ranges, Is performed according to the embodiments described herein. In another embodiment, the method identifies systematic and potential systematic defects in the design data based on the results of the step of binning according to bin ranges, and systematic and potential systematic defects over time. Monitoring the occurrence of The steps of this method embodiment are performed as further described herein.

  In an additional embodiment, the method includes performing a defect review based on the result of the step of dividing according to bin ranges. For example, a defect review may be performed with different groups of defects corresponding to different groups of correlated hot spots (eg, using at least one different value of one or more parameters of the review process). To be executed. Reviewing wafers based on bin range grouping results can also be performed based on bin range grouping results and one or more attributes of the design data corresponding to the group of correlated hot spots Is done. Thus, reviewing defects based on the results of the bin range grouping step is performed as described above with respect to inspecting the wafer based on the correlation between hot spots. The

  In other embodiments, the method includes generating a process for selecting defects to review based on the results of the step of dividing according to bin ranges. Generating the process of selecting defects for review in this embodiment is performed according to any of the embodiments described herein. In addition, the process of selecting defects for review may be combined with information about correlated hot spots associated with a group of defects, and possibly the method (s) described herein. Combine bin results by combining the results of other step (s) with other information described herein (eg, one or more attributes of design data, one or more attributes of defects, etc.) Based on the result of the grouping step by Further, generating a process for selecting a defect includes selecting a value for one or more parameters of the process used to select the defect.

  In other embodiments, the method includes generating a process for inspecting a wafer on which design data is printed based on the results of the step of dividing according to bin ranges. Generating a process for inspecting a wafer in this embodiment is performed by any of the embodiments described herein. In addition, the process of inspecting the wafer may be combined with information about correlated hot spots associated with the group of defects, and possibly other methods of the method (s) described herein. Grouping the results of the step (s) into bin information in combination with other information described herein (eg, one or more attributes of design data, one or more attributes of defects, etc.) Is generated based on the result of this step. Further, generating a process for inspecting a wafer includes selecting values for one or more parameters of the process used to inspect the wafer.

  In other embodiments, the method includes modifying the process of inspecting the wafer on which the design data is printed based on the result of the step of dividing according to bin ranges. Changing the process of inspecting the wafer in this embodiment is performed by any of the embodiments described herein. In addition, the process of inspecting the wafer may be combined with information about correlated hot spots associated with the group of defects, and possibly other methods of the method (s) described herein. Grouping the results of the step (s) into bin information in combination with other information described herein (eg, one or more attributes of design data, one or more attributes of defects, etc.) It is changed based on the result of the step. Further, changing the process of inspecting the wafer includes selecting values for one or more parameters of the changed process used to inspect the wafer.

  In some embodiments, the method includes determining the percentage of dies that are formed on one or more affected wafers of the group of defects. In this embodiment, the die percentage is determined by the embodiments described herein.

  In another embodiment, the method includes determining a percentage of dies formed on the wafer in which the defects divided into at least one of the groups according to the bin range are disposed, and at least one based on the percentage. Assigning a priority to one group. Determining this percentage and assigning priority is performed according to any of the embodiments described herein.

  In additional embodiments, the method includes the number of total hot spots that correlate with hot spots associated with defects included in one or more of the groups and the number of defects included in one or more of the groups. Prioritizing one or more of the groups. For example, the number of hot spots in a group of correlated hot spots is compared with the number of defects in the group corresponding to the hot spot group. As a result, the degree of defect of the group of correlated hot spots is determined (eg, by determining the percentage of correlated hot spots at which defects were detected and / or the correlated hot spots at which defects were detected. By determining the percentage of spots). Thus, defect groups are prioritized by the correlated hot spot defect degree. For example, a defect in a group that is detected with a large number, a large percentage, or a large percentage of corresponding hot spots, and a defect that is detected with a small number, a small percentage, or a small percentage of corresponding hot spots. Assign a higher priority than the group. Thus, defect groups are prioritized based on the defect degree of the cross-wafer hot spot.

  In other embodiments, the method includes the number of corresponding hot spot arrangements on a reticle used to print design data on a wafer in which defects in one or more of the groups are detected at least once. Prioritizing one or more of the groups. For example, a group of defects corresponding to a large number of hot spot arrangements on the reticle can be assigned a higher priority than a group of defects corresponding to a small number of hot spot arrangements on the reticle. Thus, defect groups are prioritized based on cross-wafer potential defect degrees. In addition, if the number of times the reticle is printed on the wafer is known or has been determined, the group traverse reticle defect potential is used to cross the wafer for one or more defect degrees of the group. The potential can be determined or extrapolated. The result of this prioritization step can be used to perform one or more other steps as described herein.

  In some embodiments, the method is associated with the number of placements on the reticle in which defects classified into one or more of the groups according to the bin range were detected, and the defects included in one or more of the groups. Determining a reticle-based limit for one or more of the groups based on the total number of hot spot placements on the reticle that correlate with the hot spots being detected. For example, the number of hot spot placements in a group of correlated hot spots on the reticle is compared to the number of placements in which defects in the group corresponding to the group of correlated hot spots were detected. Thus, reticle-based marginality is based on such comparison results and is a measure of the degree of defect in the placement of correlated hot spots on the reticle. Such reticle-based marginality is used in one or more steps as described herein.

  Each embodiment of the method of separating defects according to the bin ranges described above includes other step (s) of the method (s) described herein. In addition, each of the method embodiments for separating defects according to the bin ranges described above is performed by the system embodiments described herein.

  Other embodiments relate to different methods of dividing defects detected on the wafer according to bin ranges. In this embodiment, the method includes comparing one or more attributes of the design data proximate to the location of the defect in the design data space. In one embodiment, the one or more attributes include pattern density. In other embodiments, the one or more attributes include one or more attributes in the feature space. The feature space includes one or more feature vectors derived from design data. Unlike the design space, the feature space determines defect groups in a supervised way (eg, a technique of grouping by the nearest bin range) or an unsupervised way (eg, a natural grouping technique). It is possible to efficiently consider a number of attributes that may be useful. One or more attributes of the design data used in this step may additionally or alternatively be the design data, defect data, hot spots, or other (multiple) POIs described herein. ) Attribute.

  The method further includes determining whether one or more attributes of the design data proximate to the defect location are at least similar based on the result of the comparing step. Determining whether one or more attributes are at least similar is performed in a manner similar to other steps for determining similarity as described herein. In addition, when the defect is grouped according to the bin range, the method groups so that one or more attributes of the design data close to the position of the defect in each of those groups are at least similar. Including doing. This binning grouping step is performed in the same manner as the other binning grouping steps described herein. The method further includes storing the result of the bin range grouping step on a storage medium, which is performed as described herein.

  In some embodiments, the method includes determining whether the defect is a random defect or a systematic defect using the attribute (s). In addition, the attribute (s) can be used directly for random or systematic defects. One or more attributes can be used to determine whether defects that are separated according to bin ranges and / or defects that are not separated according to bin ranges are random or systematic defects. In addition, one or more attributes of the design data may include other results described herein and / or other information described herein (eg, one or more attributes of defects and hot Can be used in combination with spot information) to determine whether a defect is a random defect or a systematic defect. In one example of the embodiment described above, one or more attributes of the design data used to determine whether the defect is systematic or random is the design data at the location of the defect with respect to the feature. Including one or more attributes of the feature at. For example, one or more attributes of the design data proximate to the position of the defect in the design data space have a relatively high pattern density and a relatively small feature size, and the design data having such an attribute is a systematic defect ( If known to be susceptible to (determined experimentally, or by simulation, or by other suitable method or system), those defects are determined to be systematic defects.

  In other embodiments, the method includes ranking one or more of the groups using the attribute (s). The one or more attributes used to rank one or more groups of defects separated according to the bin range include the attribute (s) described herein. In one example, defects located within a high pattern density region of the design have a significant negative impact on yield, so rank groups of defects separated according to bin range based on pattern density, thereby increasing the The group of defects associated with the density may be ranked higher than the group of defects associated with the low pattern density. Such ranking results are used as described herein (eg, these results are used in steps that include prioritization results instead of prioritization results). ).

  The attribute (s) can also be used to rank defects within a group. For example, in an additional embodiment, the method includes ranking defects included in at least one of the groups using one or more attributes. The design data attribute (s) used to rank the defects within the group include the attribute (s) described herein. In addition, the attribute (s) used to separate the defects according to the bin range may or may not be the same attributes used to rank the defects within the group. May be. In this embodiment, if defects are divided and ranked according to bin ranges, defects can be conveniently subdivided by group and rank, and more information about the effect on defect yield can be obtained. Ranking the defects within the group is performed as described herein. In addition, defects within multiple groups are ranked separately within those groups. The results of ranking the defects within the group described above are used in one or more steps described herein.

  The attribute (s) can also be used to separate defects within a group according to bin ranges. For example, in other embodiments, the method includes using one or more attributes to divide defects included in at least one of the groups into subgroups according to bin ranges. The design data attribute (s) used to subdivide the defects in the group into subgroups according to the bin range include the attribute (s) described herein. In addition, the attribute (s) used to group the defects according to the bin range may be the same attributes used to group the defects into subgroups according to the bin range, and It doesn't have to be the same. In this embodiment, if the defects are divided into groups and subgroups according to the bin range, the defects can be conveniently divided into groups and subgroups, and more information about the effect on the yield of defects can be obtained. Dividing the defects within a group into subgroups according to bin ranges is performed as described herein. In addition, defects in multiple groups are divided into one or more subgroups separately according to bin ranges. The result of dividing the defects into groups and subgroups described above according to the bin range is used in one or more steps described herein.

  In some embodiments, the method includes analyzing defects included in at least one of the groups using one or more attributes. In this way, the defect (s) can also be used to analyze defects within a group. DCI determination is an example of this type of analysis. For example, in yet another embodiment, the method includes assigning DCI to one or more of the defects using the attribute (s). The attribute (s) of the design data used to analyze the defect includes the attributes described herein. This analysis includes, in addition or alternatively, other analyzes described herein.

  In other embodiments, the method includes determining one or more yield associations of the defect using one or more attributes. In this way, yield (s) of individual defects can be estimated using attribute (s). The one or more attributes used to determine yield relevance include the attribute (s) described herein. In such an example, defects located in close proximity to design data having a relatively high pattern density are more yield related than defects located in close proximity to design data having a relatively low pattern density. Is judged to be high. In addition, the yield relevance is determined based on one or more attributes of the design data and the probability that the defect will affect the yield based on the one or more attributes. The defects for which yield relevance is determined may or may not be defects that are separated according to bin ranges.

  In an additional embodiment, the method includes determining one or more overall yield relationships for the group using the attribute (s). Thus, the attribute (s) can be used to estimate overall yield relevance. The overall yield relevance is determined as described above.

  In some embodiments, the method includes dividing design data proximate to a defect location into design data in a region around the defect and design data in a region where the defect is located, Executed as described in the book. In addition, attribute (s) can be used to distinguish a neighborhood centered at a defect from an area where a defect may be present.

  In other embodiments, the method includes identifying structures in the design data for grouping or filtering according to bin ranges using rules and attribute (s). For example, the method includes identifying structures that are vulnerable to LES, large poly blocks, etc. using rules of design data, one or more attributes, and are proximate to such structures. The defects that are placed in this way are grouped by bin range and / or filtered from the results. These rules are generated by using the methods described herein, using experimental and / or simulation results, or using suitable methods.

  In other embodiments, the method may be reviewed, measured, tested, or some combination thereof based on inspection results generated upon detection of defects and based on defects identified as systematic defects. Including determining the placement on the wafer, which is performed according to the embodiments described herein. In some embodiments, the method may include review, measurement, testing, or some combination thereof based on inspection results generated upon detection of defects, defects identified as systematic defects, defect yield relevance. Including determining the placement on the wafer to be performed, which is performed as described herein. In additional embodiments, the method may include reviewing, measuring, testing, or based on inspection results generated upon detection of defects, defects identified as systematic defects, and process window mapping. This includes determining the placement on the wafer where any combination is performed, which is performed as described herein.

  In some embodiments, the method includes performing a systematic discovery using the results of the step of dividing according to bin ranges and the results of the user-assisted review. For example, the results of the bin range grouping step can be used to assist the review by the user (eg, to determine where to review, how to review, etc.). The review generates a review result (e.g., a high magnification image) for at least one defect in one or more of the groups, and the user can select one or more of the one or more defects or defects. Displaying the results to the user so that the group can be identified as a systematic defect.

  In other embodiments, the method isolates defects based on the functional block in which the defect is located to improve the S / N ratio included in the result of the step of dividing according to the bin range prior to the comparing step. Including that. The functional block in which the defect is located is determined as described herein. Separating defects by functional block prior to the comparing step eliminates defects in some (eg non-yield related) functional blocks so that they cannot be used in other steps of the method. The S / N ratio as a result of grouping by bin range is increased. In addition, grouping by bin range is performed based on one or more attributes of the design data in combination with the functional block in which the defect is located, which results in a high S and the result of grouping by bin range. The / N ratio can be well separated. Furthermore, grouping by bin range is performed separately for each functional clock or for one or more different functional blocks, thereby increasing the S / N ratio of the result of grouping by bin range. it can.

  In other embodiments, the design data is organized into hierarchical cells, and the method includes prior to the comparing step, defects are placed to improve the S / N ratio included in the result of the step of dividing according to bin ranges. Including isolating defects based on the hierarchical cells that are present. Design data is organized into hierarchical cells as further described herein. Separating defects based on hierarchical cells is performed as described above with respect to functional block based isolation. Dividing defects based on hierarchical cells is used to improve the S / N ratio of the result of grouping by bin range as described above.

  In additional embodiments, when the design data is organized into hierarchical cells by design and defects are placed in multiple of the hierarchical cells, the method may include: Correlating defects with each of the hierarchical cells based on the probability that the defect is placed in each of the hierarchical cells based on some combination of. Thus, if a defect can be placed in multiple cells, the defect can be correlated to the cell based on the probability that the defect is placed in a different cell, Determined based on region. These probabilities are determined by methods known in the art.

  In some embodiments, defects have been detected in the inspection process, and the method can include reviewing the placement on the wafer where one or more POIs in the design data are printed and the result of the review step. Based on determining whether a defect has been detected at the location of one or more POIs and modifying the inspection process to improve one or more defect capture rates, Is performed as described further herein.

  Each embodiment of the method of separating defects according to the bin ranges described above includes other step (s) of the method (s) described herein. In addition, each of the method embodiments for separating defects according to the bin ranges described above is performed by the system embodiments described herein.

  As described above, the portion of the design data close to the position of the defect is design data (eg, POI design example) corresponding to a different DBC (eg, DBC bin definition) stored in a library or other data structure. Compared with One embodiment that can utilize such a library or data structure is a computer-implemented method of assigning a classification to defects detected on a wafer. The method includes comparing a portion of design data proximate to a defect location in the design data space with design data corresponding to a different DBC. Comparing those portions of design data (or “source portion” of design data) with design data corresponding to different DBCs (or “target portion” or “reference pattern” of design data) is described herein. It is executed as it is. In some embodiments, the method includes comparing one or more attributes of the portion of the design data with one or more attributes of the design data corresponding to different DBCs. The attribute or attributes of the design data in those portions and the attribute or attributes of the design data corresponding to the different DBCs that are compared in this step are the attribute (s) described herein. Including. In addition, the one or more attributes used in the comparing step include one or more attributes in the feature space. Further, the comparing step includes comparing the portion of the design data with the reference pattern to determine whether there is an exact match or similarity between the source pattern and the reference pattern. Further, the comparing step is performed using a rule that includes any of the rules described herein, or a rule that is based on the method of performing the comparing step described herein. The Further, the comparing step includes comparing the position of the defect in the design data space with the position of the hot spot in the design data space, which is performed as described herein.

  The dimensions of at least some of these parts are different in some embodiments, and the dimensions are selected and / or determined as described further herein. In other embodiments, the design data in these portions includes design data for multiple design layers. Such portions of design data are configured and used in this manner as further described herein. The design data in these parts includes other design data described herein. For example, the design data close to the position of the defect includes design data in which the defect is arranged in one embodiment. Thus, the design data used in this method includes design data under or behind the defect or design data on which the defect is located. In other embodiments, the design data proximate to the defect location includes design data around the defect location.

  In an additional embodiment, the method is performed as described herein, converting a portion of design data proximate to a defect location to a first bitmap prior to the comparing step. And converting the design data corresponding to the DBC into a second bitmap prior to the comparing step performed as described herein. In one such embodiment, the step of comparing includes comparing the first bitmap and the second bitmap. Such a comparison is performed as described further herein. An embodiment of a method for assigning a classification to a defect includes determining a position of the defect in the design data space according to the embodiments described herein.

  In one embodiment, the DBC identifies one or more polygons in the design data where the defect is located or in the design data located near the defect. Thus, the one or more polygons in which the defect is arranged or one or more polygons arranged in the vicinity of the defect are identified by the DBC assigned to the defect. As such, one or more polygons are determined that are or are likely to be affected by the defect. In addition, one or more polygons in which the defect is located or one or more polygons located near the defect are identified and information about these polygons is used to The position of the defect can be determined with respect to the polygon. In some embodiments, the DBC identifies the placement of defects within one or more polygons in the design data. Thus, the method includes determining where the defect is located or close within the polygon based on the DBC assigned to the defect.

  In another embodiment, the method includes dividing design data proximate to a defect location into design data in a region around the defect and design data in a region where the defect is located. Thus, the method includes distinguishing a neighborhood centered around the defect from an area where the defect may be present. This separation is performed as described further herein. In addition, the results of this division are used in computer-implemented methods to assign classifications to defects as described further herein.

  A DBC different from design data corresponding to a different DBC is stored in the data structure. In addition, the DBC different from the design data corresponding to the different DBC is stored in the data structure as described above. In particular, a DBC different from design data corresponding to a different DBC is stored as a DBC library file in the data structure. In addition, in one embodiment, the data structure includes a library that includes examples of design data organized by technology, process, or some combination thereof. In this way, the data structure is organized as a design library that includes a collection of POI design examples that are used to classify defects on-tool, and the POI design examples are technical, process step, or other suitable information. Is organized by The data structure can include any suitable data structure known in the art, including any of the storage media described herein or other suitable storage media known in the art. It is stored in one storage medium or the like.

  The method further includes determining whether the design data in those portions is at least similar to design data corresponding to different DBCs based on the result of the comparing step. This determining step is performed according to the embodiments described herein. In some embodiments, the determining step includes determining whether the design data in the portion is at least similar to design data corresponding to different DBCs and comparing the design data in the portion based on the result of the comparing step. Determining whether or not has one or more attributes that are at least similar to one or more attributes of design data corresponding to different DBCs. The one or more attributes include the attribute (s) described herein. For example, one or more attributes may include information about the inspection system used to detect the defect (eg, the type of inspection system, one of the inspection systems that the inspection system was operating at the time the defect was detected). Or parameters) and / or attributes related to defects (eg, size, approximate bin, polarity, etc.).

  In addition, the method includes assigning to the defect a DBC corresponding to design data that is at least similar to the design data in those portions. The assigning step is performed in a suitable manner. In some embodiments, the assigning step includes design data having one or more attributes that are at least similar to the design data in those portions and at least similar to one or more attributes of the design data in those portions. Assigning a DBC corresponding to to a defect. In one embodiment, the one or more attributes include one or more attributes of the result of the inspection in which the defect was detected, one or more parameters of the inspection, or some combination thereof. The one or more attributes may additionally or alternatively include other attribute (s) described herein.

  The method further includes storing the result of the assigning step on a storage medium. These results are stored in a storage medium in a suitable manner or as described herein. Storage media includes any of the storage media described herein or other suitable storage media known in the art.

  The computer-implemented method described above is performed by an inspection system used in one embodiment to detect defects. Thus, assigning classifications to defects as described herein is performed on-tool. In other embodiments, the computer-implemented method is performed by a system other than an inspection system used to detect defects. Thus, assigning classifications to defects as described herein is performed off-tool.

  In one embodiment, the method, when grouping defects assigned to one or more of the DBCs according to bin ranges, identifies those groups with respect to the polygons contained in the portion of the design data proximate to the defect location. Grouping so that the positions of the defects in each are at least similar. Thus, the method includes grouping the defects based on the DBC and the position of the defects within the portion. The position of the defect with respect to the polygon is determined as described herein. In addition, such binning grouping is further performed as described herein.

  In some embodiments, the method includes monitoring hot spots in the design data based on the result of the assigning step. For example, design data corresponding to a DBC or a different DBC is associated with a hot spot in the design data. Hot spots are identified in the design data as described herein. Monitoring hot spots in the design data as described above is related to the design data corresponding to the hot spots or different DBCs, and the number of defects assigned to the DBCs associated with the hot spots is the time. Determining whether it changes over time. In addition, monitoring hot spots in the design data based on the results of the assigning step is in addition to other data described herein, such as one or more attributes of defects assigned different DBCs. It is executed based on the result of the step of assigning in combination. In addition, the method includes monitoring hot spots based on placement (eg, approximate placement). In other embodiments, the method includes splitting hot spots according to bin ranges based on design data corresponding to DBC. Separating hot spots according to such bin ranges is performed as described further herein. Separating hot spots according to bin ranges includes hot spot placement and includes one or more data structures (eg, lists, databases, hot spots) that indicate which hot spots are at least similar. File). This separation of hot spots according to bin ranges is performed on-tool.

  In other embodiments, the method includes monitoring systematic defects, potential systematic defects, or some combination thereof over time using the result of the assigning step. For example, the result of the assigning step is used to identify systematic problems in the design data and monitor the identified systematic problems for wafers and / or time. A systematic problem is determined based on the result of the assigning step as further described herein. In addition, monitoring systematic defects, potential systematic defects, or some combination thereof is further performed as described herein.

  In one embodiment, the design data corresponding to different DBCs may be one or more other based on the location of the design data proximate to the location of the defect detected on one or more other wafers in the design data space. The defects detected on the wafers are identified by grouping them. Such grouping of defects is performed as described herein. The grouping result is used to identify design data corresponding to different DBCs. For example, design data corresponding to each group of defects is identified as design data corresponding to different DBCs. In addition, different DBCs corresponding to design data may be performed as described herein to classify defects into groups, one or more attributes of design data, one or more of defects, or Determined by multiple attributes, other information described herein, or some combination thereof.

  In other embodiments, the method detects a defect to determine whether the defect is a nuisance defect based on the DBC assigned to the defect and to increase the S / N ratio of the result of the inspection process. Removing nuisance defects from the results of the inspection process. Thus, the method includes nuisance filtering. The defect determined as a nuisance defect may be a defect that is assigned a nuisance DBC (eg, a DBC of LES), a defect that is not assigned a DBC, or a defect that is not related to yield, or a defect It may be a defect to which a DBC indicating that the defect has not been assigned. Increasing the S / N ratio of the test result is particularly advantageous when performing one or more other steps using the test result, so that the S / N ratio of the result of the other step is reduced. Get higher.

  In some embodiments, the method includes determining one or more POIs in the design data by identifying one or more features in the design data that exhibit pattern dependent defects. Thus, the method includes identifying the POI (s) in the design data. One or more features in the design data that exhibit pattern-dependent defects may be based on experimental results, simulation results, results of grouping by bin ranges, other results described herein, or some combination thereof. It is determined. Such a result is generated as described herein. The identified features are used to determine one or more POIs and perform an arbitrary pattern search of the design data. Patterns in design data that are determined to be at least similar to features identified by any pattern search are identified as POIs. One or more POIs are determined in this manner for a plurality of pattern dependent defects.

  Defects that were assigned DBC in the manner described herein were detected in the inspection process. In one embodiment, the method includes reviewing the placement on the wafer where the one or more POIs in the design data are printed and the placement of the one or more POIs with defects based on the results of the review step. By the way, determining whether it has been detected and modifying the inspection process to improve one or more defect capture rates. Each step of this embodiment is performed as described herein.

  In other embodiments, the method includes determining a KP value for one or more of the defects. In additional embodiments, the method includes determining a KP value for one or more of the DBCs based on one or more attributes of the design data corresponding to the DBC. In other embodiments, the method comprises determining a KP value for one or more of the defects based on one or more attributes of the design data corresponding to the DBC assigned to the one or more defects. Including. Each of these steps is performed as described herein. In some embodiments, the method includes monitoring KP values for one or more of the DBCs and assigning KP values for the DBCs assigned to the defects to the defects. KP values for one or more DBCs are monitored as described herein. In this way, the KP value of one or more DBCs over time and / or so that the KP value for the DBC assigned to the defect when the defect is detected is assigned to the defect with relatively high accuracy. Or it can be modified for the wafer. Assigning a KP value to a defect based on the DBC assigned to the defect is further performed as described herein.

  In some embodiments, the method includes selecting at least some of the defects to review based on the result of the assigning step. For example, the result of the assigning step is used to determine which of the defects are most critical as described herein (eg, one or more of the DBCs assigned to the defects). Based on attributes), the most critical defects can be selected for review. In another example, the result of the assigning step is used to determine which of the defects are systematic defects as described further herein. Thus, this method includes review sampling from regions in the design data that are prone to DOI.

  In one embodiment, the method determines whether the DBC assigned to the defect corresponds to a systematic defect visible to the review system and selects only the defect visible to the review system for review. Sampling defects for review. The DBC corresponding to systematic defects visible or invisible from the review system is determined by methods known in the art. The DBC corresponding to the systematic defect visible from the review system is determined prior to this method, and the DBC has some sort of identifying information indicating whether the DBC corresponds to a visible defect or an invisible defect. Assigned. Thus, the defect is selected for review based on this identification information. Selecting only defects that are visible from the review system is performed so that defects that are not visible from a review system such as an SEM are not selected for review. Selecting defects in this way can make it difficult to relocate defects during review, and in particular a significant amount of time for the review system to look for defects that are not actually visible from the review system. This is particularly beneficial because it takes a relatively long time to spend. The results of selecting the defects for review include the placement of the defects selected for review on the wafer and other results of the step (s) of the method (s) described herein.

  The method includes adapting a process, measurement, or test based on the result of the assigning step. For example, in other embodiments, the method includes generating a process for sampling defects for review based on the result of the assigning step. Accordingly, the method may include, instead of or in addition to selecting a defect for review, the method, other methods, a system configured to perform the method, to sample the defect for review, Or creating a process for use by other systems. Such a process is used to sample defects for review of defects detected on multiple wafers and / or sample defects for review performed by multiple review systems. The sampling process is generated based on the result of the assigning step, so that a relatively large number of defects assigned the same DBC are sampled in large quantities compared to a relatively small number of defects assigned the same DBC. . The process of sampling defects for review is based on the result of the step of assigning in combination with other results of the step (s) of the method (s) described herein, such as DCI for the defect, KP value for the defect, etc. Based on.

  In additional embodiments, the method includes modifying the process of inspecting the wafer based on the result of the assigning step. In this embodiment, the parameter (s) of the process for inspecting the wafer can be changed. For example, one or more parameters of a process for inspecting a wafer that is changed based on the result of the assigning step may include, but are not limited to, an area to be inspected (or alternatively, an area not to be inspected), sensitivity, Includes grouping processes with inline bin ranges, inspection areas where wafers are inspected, or some combination thereof. In one particular example, the result of the assigning step indicates the number of defects assigned different DBCs, and the inspection target area further includes design data corresponding to DBCs assigned a relatively large number of defects. To include a position on the wafer corresponding to the additional position at. In other examples, the process of inspecting the wafer is modified to inspect more or differently based on the result of the assigning step. The process of inspecting the wafer is further modified based on the results of the step (s) of the method (s) described herein.

  In some embodiments, the method includes changing the process of inspecting the wafer during inspection based on the result of the inspection. Changing the process of inspection in this embodiment is performed as described further herein.

  In other embodiments, the method includes changing the wafer weighing process based on the result of the assigning step. For example, the weighing process is modified so that the most critical defects as determined from the result of the assigning step are measured in the weighing process. Thus, changing the metrology process includes changing the arrangement on the wafer where measurements are performed in the metrology process. In addition, by sending inspection and / or review results, such as a BF image and / or SEM image of the defect selected for measurement, to the weighing process, the results are used to perform the measurement. To decide. For example, the metrology process includes generating an image of an approximate placement of defects on the wafer, and comparing this image with the results of inspection and / or review for defects, the metrology system is correct if necessary. The position on the wafer is corrected so that measurements are performed on the wafer placement and thus for the correct defects. Thus, the measurement is performed with a substantially accurate placement on the wafer. Changing the weighing process further includes one or more other parameters of the weighing process, such as the type of measurement performed, the wavelength at which the measurement is performed, the angle at which the measurement is performed, etc., or some combination thereof. Including changing. The metering process includes any suitable metering process known in the art, such as a CD measurement metering process.

  In some embodiments, the method includes changing the sampling plan of the metrology process for the wafer based on the result of the assigning step. The method thus includes adaptive sampling. For example, the sampling plan of the weighing process is modified so that more critical defects, as determined from the result of the assigning step, are measured in the weighing process. In this way, the most critical defects are sampled more in the weighing process, which can advantageously output more information about the most critical defects. The metering process includes a metering process known in the art. In addition, the metering system is implemented by a suitable metering system known in the art, such as SEM. In addition, the metrology process performs suitable measurements known in the art of suitable attributes of defects or features formed on the wafer known in the art, such as profile, thickness, CD, etc. Including.

  In other embodiments, the method can prioritize one or more of the DBCs (eg, DBCs assigned to defects) and wafers on which design data is printed based on the results of the prioritization step. Optimizing one or more processes performed above. In one such embodiment, the DBC (s) is prioritized based on the number of defects to which the DBC is assigned. The number of defects to which each DBC is assigned is determined from the result of the assigning step. In one such example, the DBC assigned to the maximum number of defects is assigned the highest priority, the DBC assigned to the next highest number of defects is assigned the next highest priority, and so on. .

  In addition or alternatively, the DBC (s) may be the other result of the step (s) of the method (s) described herein or the item (s) described herein. Prioritization based on the combination of the results of the step (s) of the method. For example, prioritizing DBC (s) can be based on determining DCI for one or more defects to which DBC (s) are assigned and DCI for one or more defects. Prioritizing the DBC (s). The DCI is determined in this embodiment as further described herein. In another example, prioritizing the DBC (s) may determine a KP value for one or more defects to which the DBC (s) are assigned and for one or more defects. Prioritizing the DBC (s) based on the KP value. In yet another example, the DBC (s) is based on a combination of the number of defects to which the DBC (s) are assigned and the DCI for one or more of the defects to which the DBC (s) are assigned. Prioritized. Thus, prioritizing the DBC (s) is detected in the design data corresponding to the DBC (s) so that a high priority is assigned to the DBC (s) corresponding to a high degree of defect. Prioritizing the DBC (s) based on the degree of defect

  Further, the DBC (s) may be prioritized based on one or more attributes of the design data corresponding to the DBC (s), possibly in combination with other results described herein. The One or more attributes of the design data include, for example, the dimensions of the features in the design data, the density of the features in the design data, the type of features included in the design data, and the location of the design data corresponding to the DBC (s) in the design Susceptibility of design data yield effects to defects, etc., or some combination thereof. In such an example, the DBC (s) corresponding to design data that is susceptible to yield impact due to defects has a higher priority than the DBC (s) corresponding to design data that is less susceptible to defects due to yield. Assigned.

  Further, the DBC (s) may be one of the designs, possibly in combination with one or more attributes of the design data corresponding to the DBC (s) and / or other results described herein. Or prioritized based on multiple attributes. One or more attributes of the design include, for example, redundancy, netlist, etc., or some combination thereof. In particular, the POI in the design data can have a context that exceeds the pattern contained within the POI. Such context includes, for example, the label of the cell containing the POI, the hierarchy of the cells above the cell containing the POI, the redundancy (or lack of redundancy) impact of systematic defects on the POI, and so on. Thus, the attribute or attributes used in the embodiments described herein include the POI context in which the design data corresponding to the DBC (s) is located, which is in the design data space. Based on the position of the design data corresponding to the DBC (s) and / or the design data corresponding to the DBC (if the design data corresponding to the DBC is specific to a cell in the design data) Determined. In such an example, the DBC (s) corresponding to design data having redundancy so that systematic defects do not affect yield in the design are redundant so that systematic defects affect significant yield. Is assigned a lower priority than the DBC (s) corresponding to design data that does not have Such context of the cell is captured and / or determined in a manner known in the art.

  Optimizing one or more processes in this embodiment includes focus, dose, exposure tool, resist, PEB time, PEB temperature, etching time, etching gas composition, etching tool, deposition tool, deposition time, Including changing one or more parameters of one or more processes, such as a CMP tool, one or more parameters of a CMP process. Preferably, by changing the parameter (s) of the process (s), the degree of defect in the design data corresponding to the DBC (s) (eg, defects detected in the design data corresponding to the DBC (s)) And / or change one or more attributes (eg, DCI, KP, etc.) of defects detected in the design data corresponding to the DBC (s) and / or to the DBC (s) Increase device yields with corresponding design data.

  In addition, the one or more parameters of the one or more processes may be set to a relatively high priority determined only by the DBC having the highest priority determined by the prioritization step or by the prioritization step. Optimize for DBCs with degrees. Thus, changing one or more parameters of one or more processes based on the design data corresponding to the DBC (s) exhibiting the highest defectivity and / or the defectivity affecting the highest yield And / or optimize. As such, the prioritization step results in the greatest improvement in yield if which DBC (s) is used to change and / or optimize one or more parameters of one or more processes. Shows what will bring.

  Thus, without guidance that the DBC (s) have the greatest impact on yield, many changes are made to the process without significant yield or some improvement, and thereby process optimization turnaround time and cost. This embodiment is advantageous over other already used methods and systems for modifying and / or optimizing the process.

  Further, the process (s) modified and / or optimized in this step may be performed on the wafer (s) on the wafer prior to the detection of defects assigned DBC in the embodiments described herein. One or more processes that contain only the processes used to print the corresponding design data, but that are modified and / or optimized, include other designs that also contain the design data corresponding to the DBC (s). Includes the process (es) used to print. For example, if multiple designs include design data corresponding to DBC (s), to print the multiple designs based on prioritization and / or other results of the methods described herein. One or more of the processes used in the process can be modified and optimized to increase the yield of devices fabricated with each of the different designs.

  In an additional embodiment, the method includes locating the root cause of the defect based on the DBC assigned to the defect. For example, the root cause is further determined based on one or more attributes of the design data corresponding to the DBC assigned to the defect. One or more attributes can be used to determine the root cause, as further described herein. The design data attribute (s) used to determine the root cause include the design data attribute (s) described herein. In addition, other information and / or results of the step (s) of the method (s) described herein can be attributed to the attribute (s) of the design data to determine the root cause of the defect. Used in combination.

  In other embodiments, the method includes locating at least some root causes of the plurality of defects by mapping at least some of the plurality of defects to the results of the experimental process window, This is performed as described herein. In another embodiment, the method includes determining at least some root causes of the plurality of defects by mapping at least some of the plurality of defects to a simulated process window result. This is done as described herein.

  In other embodiments, the method includes locating a root cause corresponding to one or more of the DBCs and assigning a root cause to the defect based on the root cause corresponding to the DBC assigned to the defect. . For example, the root cause of the defect already detected in the design data corresponding to the DBC is associated with the DBC. The root cause of the already detected defect is performed as described herein or by any other suitable method known in the art. Thus, the root cause of the defect is determined as the root cause associated with the DBC assigned to the defect.

  In other embodiments, the method includes determining the percentage of dies formed on the wafer that are affected by the defects to which one or more of the DBCs are assigned. For example, the percentage is determined by the number of dies on the wafer in which a defect assigned the same DBC has been detected at least once. Such a percentage is determined by dividing the number of dies in which at least one defect assigned the same DBC is detected by the total number of dies inspected. The result of this step can be multiplied by 100 to obtain this percentage. This proportion therefore reflects the die impact limit of defects assigned the same DBC. Such percentages are determined for a plurality of DBCs assigned to defects, and each or at least some of these percentages are displayed in a chart such as a bar graph generated by the method. Therefore, this chart shows the die impact limit that varies depending on the DBC assigned to the defect. Such a chart is displayed in a user interface that is configured as described further herein. The method further includes prioritizing defects assigned one or more of the DBCs based on the percentage determined in this embodiment.

  In some embodiments, the method includes determining a POI in design data corresponding to at least one of the DBCs, the number of defects to which at least one of the DBCs is assigned, and the number of POI placements on the wafer. And determining the ratio. Thus, the method performs a marginal analysis by determining the ratio or percentage of the number of defects assigned DBC compared to the number of POI arrangements corresponding to the DBC printed on the wafer. including. In such an embodiment, the number of POI placements on the wafer is identified by an arbitrary pattern search. In addition, the methods described herein include an arbitrary pattern search that identifies the placement of POIs within the inspected region of the design, and determining the cumulative area of POIs in the inspected region of the design. including. The ratio of the number of defects to which the DBC is assigned and the cumulative area of POI in the inspected region of the design can then be used to determine the defect density of the DBC corresponding to the POI. The method further includes prioritizing one or more DBCs based on the ratio determined in this embodiment.

  In other embodiments, the method determines one or more POIs in the design data corresponding to at least one of the DBCs, and determines the number of defects to which at least one of the DBCs is assigned and 1 in the design data. Determining a ratio to the number of one or more POI arrangements (eg, for an inspected area of the wafer). Thus, the method determines the ratio or percentage of the number of defects assigned DBC corresponding to the POI found on the wafer compared to the number of POI placements in the design on the inspected area of the wafer. To perform a marginal analysis. In such an embodiment, the number of POI placements on the wafer is identified by an arbitrary pattern search. The method further includes prioritizing one or more of the DBC (s) based on the ratio determined in this embodiment.

  In an additional embodiment, the method includes determining a POI in design data corresponding to at least one of the DBCs, and a die formed on the wafer on which the defect to which at least one of the DBCs is assigned is located. And determining a priority for the POI based on the ratio. Thus, the method includes performing a criticality analysis based on the percentage of dies affected by the defect. For example, the number of defects assigned the same DBC is divided by the number of design instances of POI in the reticle used to print design data on the inspected area of the wafer, and the reticle is on the wafer. Divide by the number of times printed and inspected. The result of this step can be multiplied by 100 to obtain this percentage. Thus, the method includes prioritizing systematic defects that are known by the number of dies on the wafer in which the defects have been detected at least once. For example, a POI in which a systematic defect is detected can be assigned a higher priority when the POI appears at 10% of the die versus 1% of the die. In another example, a defect on a wafer with many defects detected with the same DBC assigned defect is compared to a defect on a wafer with fewer defects detected with a different DBC assigned defect. Can be assigned a high priority. In addition, the method includes generating a chart, such as a bar graph, showing the percentage of dies formed on the wafer where defects assigned different DBCs are located. Thus, such charts graphically illustrate the die base limits for different DBCs. Such a chart is displayed on a user interface configured as described herein.

  In yet another embodiment, the method includes prioritizing one or more of the DBCs by the number of detected defects that have been assigned one or more of the DBCs. Thus, the method includes prioritizing systematic defects that are known by the total number of defects to which the DBC has been assigned. In doing so, the method includes prioritizing known systematic defects based on wafer-based marginality. For example, the DBC assigned to the defect when the number of design instances where defects are detected on the wafer is large is the DBC assigned to the defect when the number of design instances where defects are detected is small. A higher priority can be assigned. Such prioritization is further performed based on the percentage of placement of design instances on the wafer in which defects are detected. For example, the number of defects detected and assigned DBC is divided by the total number of inspected design instances corresponding to DBC on the wafer. The result of this step can be multiplied by 100 to obtain the above ratio. In addition, the method includes generating a chart, such as a bar graph, showing the number of design instances on the reticle in which defects assigned different DBCs were detected. Such a chart is displayed on a user interface configured as described herein.

  In some embodiments, the method includes a design instance on a reticle that is used to print design data on a wafer on which a defect to which one or more of the DBCs are assigned is detected at least once. Including prioritizing one or more of the DBCs by number. Thus, the method includes prioritizing systematic defects that are known by the number of design instances on the reticle in which the defects are found at least once. For example, the DBC assigned to the defect when the number of design instances in which defects are detected on the reticle is large is the DBC assigned to the defect when the number of design instances in which defects are detected on the reticle is small. A higher priority can be assigned. In addition, the method includes generating a chart, such as a bar graph, showing the number of design instances on the reticle in which defects assigned different DBCs were detected. Such a chart is displayed on a user interface configured as described herein.

  In other embodiments, the method includes proximity to the number of placements on the reticle where a defect to which one or more of the DBCs are assigned is detected and the position of the defect to which one or more of the DBCs are assigned. Determining reticle-based marginalities for one or more of the DBCs based on the total number of portions of the design data printed on the reticle that are at least similar to the portion of the design data to be processed. For example, reticle-based marginality is determined by dividing the number of placements in a stacked reticle map where at least one defect assigned DBC is detected by the total number of inspected design instances on the reticle. . The result of this step can be multiplied by 100 to determine the percentage of design instance placement corresponding to the DBC in which the defect to which the DBC is assigned has been detected. In addition, the method includes generating a chart, such as a bar graph, showing the reticle-based marginality or percentage of the arrangement in which defects assigned different DBCs were detected. Such a chart is displayed in a user interface that is configured as described further herein. The method further includes prioritizing one or more of the DBCs based on the reticle-based marginality determined for one or more of the DBCs. For example, a DBC that exhibits a relatively high reticle-based marginality is assigned a higher priority than a DBC that exhibits a low reticle-based marginality. The steps of the above-described embodiment are performed for a group of defects that are assigned the same DBC, or for individual defects that are assigned a DBC.

  Each of the method embodiments for assigning a classification to a defect as described above includes other step (s) of the method embodiment (s) described herein. In addition, each of the method embodiments described above for assigning a classification to a defect is performed by the system embodiments described herein.

  Another embodiment relates to a method for changing the inspection process for a wafer. The method includes reviewing an arrangement on the wafer where one or more POIs in the design data are printed. The method further includes determining based on the result of the step of reviewing whether the defect was to be detected at the placement of the one or more POIs. In addition, the method can improve one or more defect capture rates and / or improve the signal-to-noise ratio for defects located in at least some of the one or more POIs. Including changing the inspection process. Each of these steps is performed as described further herein. For example, one or more parameters of the inspection process are modified based on POI prioritization, which is determined as described herein.

  One use case of the method described above is for optical system sensitivity applications. For example, in one embodiment, changing the inspection process includes changing the optical mode of the inspection system used to perform the inspection process. Thus, changing the optical mode used for inspection improves the signal-to-noise ratio in detecting one or more defects corresponding to at least some of the one or more POIs. Can do. Optical modes include those known in the art.

  In another embodiment, the method includes an optical of an inspection system used to perform an inspection process based on the result of determining whether a defect should be detected at one or more POI locations. Including determining the mode. In this way, the optical mode with the highest S / N ratio for the defect to be detected is determined. Optical modes include those known in the art. In addition, the determined optical mode and / or the defect to be detected are used to select other parameters of the modified inspection process, such as the type of inspection system used to perform the inspection process. be able to.

  In some embodiments, changing the inspection process includes changing the inspection process to enhance capture of the DOI associated with the one or more POIs. Changing the inspection process to enhance acquisition includes changing one or more parameters of the inspection process. Detection enhanced by changing inspection process parameters includes detection of DOIs associated with POIs in inspection results (e.g., increasing defect counts for yield critical systematic DOI). One or more parameters that have been modified to enhance acquisition are only the result of the inspection process and / or the result of the reviewing step (eg, the result of reviewing the placement on the wafer on which one or more POIs are printed) Not based on).

  In some embodiments, changing the inspection process includes changing the inspection process to suppress noise in the results of the inspection process. Changing the inspection process to suppress noise includes changing one or more parameters of the inspection process. Noise that is suppressed by changing the parameters of the inspection process includes noise in the inspection results (eg, background noise, nuisance defects, etc.). The one or more parameters that have been modified to suppress noise are the result of the inspection process and / or the result of the reviewing step (eg, the result of reviewing the placement on the wafer on which the one or more POIs are printed) As well as selected).

  In other embodiments, changing the inspection process may change the inspection process to reduce the detection of non-focused defects or to improve the grouping of non-focused defects by bin range. including. Changing the inspection process to reduce detection of defects that are not of interest includes changing one or more parameters of the inspection process. Non-focused defects that are less likely to be detected by changing inspection process parameters include non-focused defects (eg, non-yield related systematic defects, cold spot defects, etc.). One or more parameters that have been modified to reduce the detection of defects that are not of interest are the result of the inspection process and / or the result of the reviewing step (eg on the wafer on which one or more POIs are printed). Selected based on (not only the result of reviewing the placement).

  Changing the inspection process to improve one or more defect capture rates includes changing one or more parameters of the inspection process. For example, in one embodiment, changing the inspection process includes changing an algorithm used in the inspection process. The algorithm to be modified is a defect detection algorithm or other algorithm used in the inspection process. The algorithm to be modified includes any suitable algorithm known in the art. In addition, changing the inspection process includes changing a plurality of algorithms used in the inspection process.

  In additional embodiments, changing the inspection process includes changing one or more parameters of an algorithm used in the inspection process. Algorithms in which the one or more parameters are changed include defect detection algorithms or other algorithms used in the inspection process. In addition, changing the inspection process includes changing one or more parameters of a plurality of algorithms used in the inspection process. The one or more parameters in the algorithm (s) include those algorithm parameters, preferably the parameter (s) that affect the defect capture rate.

  Each of the method embodiments described above for altering the inspection process for a wafer includes other step (s) of the method embodiment (s) described herein. In addition, each of the method embodiments for modifying the inspection process for a wafer described above is performed by the system embodiments described herein.

  An additional embodiment relates to a system configured to display and analyze design data and defect data. One embodiment of such a system is shown in FIG. As shown in FIG. 25, the system includes a user interface 182. The user interface 182 may include one or more of a semiconductor device design layout 184, inline inspection data 186 captured for a wafer on which at least a portion of the semiconductor device is formed, and electrical test data 188 captured for the wafer. Configured to display. In one embodiment, the electrical test data includes logical bitmap data. Design, inspection (or metrology), test, overlay data is represented in design space, device space, reticle space, or wafer space. The user interface is further configured to display modeled data for the semiconductor device and / or FA data for the wafer. In addition, the user interface is configured to display information for a particular hot spot or DOI based on input from the user (eg, selection of a hot spot or DOI by the user). Thus, the user interface is configured to display information regarding different hot spots or DOIs at different times. However, the user interface may display information about different hot spots or DOIs simultaneously (eg, in a wafer map or bar graph) using one or more different indicia (eg, colors, symbols, etc.). Configured. The user interface is further configured to display information in the hot spot database. By utilizing the display of information in the hot spot database, the user can select one or more hot spots by selecting a subset of hot spots of interest using a predetermined analysis or inspection recipe. A spot list can be created. The user interface is displayed on the display device 190. Display device 190 includes any suitable display device known in the art.

  The system also includes a processor 192. The processor 192 is configured to analyze one or more of the design layouts, in-line inspection data, electrical test data after receiving an instruction to perform analysis from the user via the user interface. The processor is further configured to analyze the data and / or FA data modeled as described above. For example, the user interface 182 is configured to display one or more icons 194. Each icon corresponds to a different function performed by the processor. Thus, although five icons are shown in FIG. 25, the user interface is configured to display a number of icons corresponding to the number of possible functions. The user can then cause the processor to perform one or more functions by selecting (eg, clicking) one or more icons. In addition, the user interface can display various functions that are available to the user in other ways known in the art (eg, drop down menus). In this way, the user interface combines design / layout visualization and analysis operations with inline process data visualization and analysis operations and functional / structural electrical test data visualization and analysis operations. Configured as an integrated user interface.

  The system is configured to process data with high resolution, commonly referred to as a “drill down function”. For example, the system uses an input such as a wafer map showing defects detected on the wafer to select two or more dies for the stack, selects the defects shown in the die stack results, Are configured to perform certain functions. The system is further configured to use data collectively from multiple domains, commonly referred to as a “drill-across function”.

  In one embodiment, the user interface is further configured to display the overlay 196 with at least two of the design layout, in-line inspection data, electrical test data, and other information described herein. Is done. In one such embodiment, the electrical test data includes logical bitmap data. In such embodiments, the processor is configured to overlay different data according to the embodiments described herein. Thus, the system is configured to generate and display an overlay of data from two or more of the three domains (eg, design, inspection, electrical test). Using such an overlay of data, the physical location of the defect is mapped to a logical location, and the electrical test result (eg, electrical fault) and the electrical test result (eg, electrical fault) using this mapping Can be identified.

  In one embodiment, the processor is further configured to determine the defect density in the design data space after receiving an instruction to perform this determination from the user via the user interface. As such, the system is configured to perform fault density calculations as further described herein. The user interface is further configured to display the results of the fault density calculation.

  In an additional embodiment, the processor is configured to perform defect sampling for review after receiving an instruction to perform defect sampling from a user via the user interface. In another embodiment, the processor groups the defects based on the similarity of the design layout close to the position of the defects in the design data space after receiving an instruction to perform the grouping from the user via the user interface. Configured to do. Thus, the system is configured to perform sampling and data reduction (eg, data reduction by grouping by pattern dependent bin ranges) techniques. These techniques are performed as described further herein.

  In some embodiments, the processor is configured to monitor a KP value for a group of defects according to a time course and to determine the significance of the group of defects based on the KP value according to a time course. In this way, the system is configured to perform defect tracking (eg, using a DTT method and / or using an image). The user interface is further configured to display the results of monitoring the KP value and the significance of the group of defects over time. The processor and system shown in FIG. 25 are further configured as described herein. For example, the processor and system are configured to perform other step (s) of other methods described herein. In addition, the system shown in FIG. 25 includes other components described herein, such as an inspection system, which are configured as described further above. The system shown in FIG. 25 has all the advantages of the method described herein.

  Another embodiment relates to a computer-implemented method for determining the root cause of electrical defects detected on a wafer. In one such embodiment, the result of inspection of the wafer for electrical defects includes a logic device bitmap. The method includes determining the location of electrical defects in the design data space. The location of electrical defects in the design data space is determined as described herein.

  In some embodiments, the method includes correlating a spatial signature of a defect, such as a systematic defect, with a process condition. For example, after converting scan base and structural test results to wafer space coordinates, a particular spatial signature can be correlated to one or more process conditions. A method and system for performing spatial signature analysis of defect data is described in Kulkarni et al., US Pat. No. 5,991,699, Satya et al., Which is incorporated by reference as if set forth herein in its entirety. Illustrated in US Pat. No. 6,445,199 and Eldredge et al. US Pat. No. 6,718,526. The methods and systems described herein are configured to perform any step (s) of the methods described in these patents.

  The method further includes determining whether the location of the portion of the electrical defect defines a spatial signature corresponding to the one or more process conditions. This step may include comparing the spatial signature for the electrical defect portion with a set of spatial signatures corresponding to the process conditions, or applying a rule to the location of the electrical defect portion, or some other suitable Executed in a way. In addition, if the location of the portion of the electrical defect defines a spatial signature corresponding to the one or more process conditions, the method can identify the root cause of the portion of the electrical defect as one or more process conditions. Including identifying as. Thus, the method described above includes performing spatial signature analysis on the logical bitmap data. The method further includes storing the result of the identifying step on a storage medium. The results of the identifying step include the results described herein. In addition, the method performs the storing step as further described herein. Storage media includes the storage media described herein.

  Each of the method embodiments described above for determining the root cause of an electrical defect includes other step (s) of the method embodiment (s) described herein. In addition, each of the method embodiments described above for determining the root cause of electrical defects is performed by the system embodiments described herein.

  The root cause of other defects is also determined by the methods described herein. For example, wafer-based or reticle-based spatial signatures with pattern groups (and such combinations) mapped on the process window are particularly useful in determining correlations to help locate root causes. In one example, on one side of the process window, defects x and y are at the boundary and tend to fail first from the outside of the wafer. At the other side of the process window, the defect z tends to fail first at the wafer side. As such, the possible root cause is determined by observing which systematic defects on the wafer are most likely to fail (possibly with respect to the outer annular ring).

  Other embodiments select defects detected on the wafer for review, discovery for classification / investigation, and monitoring for verification / root cause analysis including on-tool, off-tool, and on-SEM To a computer-implemented method for doing this. The method includes identifying one or more zones on the wafer. One or more zones are associated with the location of one or more defect types on the wafer. One embodiment of one or more such zones is shown in FIG. As shown in FIG. 26, the zone 198 on the wafer 200 is identified as being associated with the location of one or more defect types on the wafer. For example, this zone is associated with a defect type caused by a focus error close to the outer edge of the wafer in a lithographic process or etch variation from the wafer center to the wafer edge.

  The method further includes selecting defects detected in only one or more zones to be reviewed. For example, as shown in FIG. 26, the wafer map 202 is overlaid with a zone 198 layout. In this manner, the defects shown in the wafer map 202 are selected for review based on the located zone and the one or more defect types associated with the zone. In one such example, if the zone shown in FIG. 26 is associated with a defocus error close to the outer edge of the wafer, this method will cause defects in zone 198 (only, primarily, or in large quantities). select. Alternatively, the defects are selected from zones on the wafer other than zone 198.

  Although only one zone is shown in FIG. 26, it will be understood that the wafer is divided into any number of suitable zones. In addition, the zones are defined on the wafer as an annular zone, a cornered zone, a cornered radial zone, or a rectangular zone as shown in FIG. However, the zones can be irregular (eg, polygonal) shapes. In addition, all or part of the zone may or may not have the same characteristics such as shape and / or size.

  The method described above is used to prepare a defective sample so that the results of the review of the defective sample can be interpolated from die to wafer. In contrast, a typical review sample plan contains 100 to 200 defects for recipe optimization and 25 to 100 defects for monitoring diffusion across the wafer. However, there are tens of thousands of hot spots on a single die. Hot spots are reviewed for discovery. Systematic defects are reviewed for monitoring and verification. Therefore, even after selecting 100 to 200 defects from this population, it is preferable not to review them all on the same die. Instead, the selected defects are preferably spread over multiple dies. In the method described above, zone analysis results are used to identify the correlation between a particular defect type and a particular zone on the wafer. In doing so, the method described herein can be used to identify wafer position specific defects. As such, the method includes biasing the sampling plan towards these zones to provide results suitable for use in die-wafer interpolation. The method further includes storing the result of the selecting step on a storage medium. The result of the selecting step includes the result described herein. In addition, the method performs the storing step as further described herein. Storage media includes the storage media described herein.

  Each of the method embodiments for selecting defects for review described above includes other step (s) of the method embodiment (s) described herein. In addition, each of the above-described method embodiments for selecting defects for review is performed by the system embodiments described herein.

  Another embodiment relates to a computer-implemented method for evaluating one or more yield-related processes on design data. One such embodiment is shown in FIG. Note that the steps shown in FIG. 27 are not essential to the performance of the method. One or more steps may be omitted or added from the method illustrated in FIG. 27, or the method may be implemented as is within the scope of this embodiment.

  As shown in FIG. 27, the method includes identifying potential faults in the design data using rule checking, as shown in step 204. Alternatively, potential faults in the design data are identified using potential hot spots observed from repeater analysis or defect density maps. The potential faults identified in this step include one or more different types of DOI. In some embodiments, the potential fault identified in this step includes a post-patterning potential fault (eg, a post-etch potential fault). In addition, after a potential fault is identified, it is propagated throughout the design, but is detected by searching for common patterns in the design (eg, via an arbitrary pattern search). In some embodiments, the method includes an arbitrary pattern search that identifies all similar POI placements. Common patterns are identified by searching for patterns that have been rotated or flipped to find all potential obstacles. Further, potential faults in the design data are identified in step 204 using other suitable methods (eg, modeling), software, and / or algorithms known in the art. In addition, a potential failure can cause failure of a device that has been machined to design data, or one or more electrical parameters of a device in an undesirable manner without actually causing device failure. Includes areas or patterns in design data that may change.

  As shown in step 206, the method further includes determining one or more attributes of the potential failure. The attribute (s) of the potential fault to be determined includes, for example, a type. The potential failure's attribute (s) are captured by experimental testing, simulation results, design data, or other methods. Since the method includes identifying potential faults as described above, the method includes modifying the design data prior to processing to eliminate as many potential faults as possible. Such modification of the design data is performed as described herein. However, it is conceivable that not all potential obstacles can be eliminated prior to processing. In addition, potential faults identified in the methods described herein may or may not actually cause faults during processing or affect yield. Thus, although some of the potential faults are eliminated prior to processing (and therefore inspection), the method described herein is used when a potential fault is actually rejected during design inspection. Important information regarding where the test should be performed can be given so that it can be detected as quickly as possible. In addition, the method described herein allows different areas of the design so that inspection of areas on the wafer of portions of the design data that contain potential obstacles in the design is performed with the most suitable inspection parameters. Can provide important information on how to be tested, which can increase the probability of being detected by the test if the potential fault actually causes the fault.

  As shown in step 208, the method includes determining whether a potential fault is detectable based on one or more attributes of the potential fault. Whether a potential fault is detectable is determined based on the attribute (s) of the potential fault in combination with the known functionality of various inspection systems. As shown in step 210, the method can identify which of a number of different inspection systems (eg, BF, DF, voltage contrast, EC, electron beam, etc.) based on one or more attributes. Determining whether it is most suitable for detecting a physical failure.

  In some embodiments, the method includes selecting one or more parameters of the inspection system determined to be most suitable, as shown in step 212. In one such embodiment, the parameter (s) is selected based on one or more attributes of the potential defect. The parameter (s) is selected as described further herein. In addition, the parameter (s) selected in this step include the parameter (s) of the inspection system that are variable and / or controllable. An example of such a parameter is an optical mode or an inspection mode. Preferably, the parameter (s) are selected to optimize the inspection of the wafer for potential faults (eg, defects at potential fault placement, increasing defect capture rate of defects at potential fault placement). Increase sensitivity to).

  In some embodiments, the method may be based on one or more attributes of design data that are proximate to the location of the potential fault, possibly in combination with other information described herein. Prioritizing one or more of the faults (eg, sensitivity of design data to defects, sensitivity of electrical parameters of devices corresponding to design data to defects, etc.). Such prioritization is performed as described further herein. In addition, the most suitable inspection system and inspection system parameters are selected based on the prioritization results as further described herein. For example, in such an embodiment, the most suitable inspection system and inspection system parameters may be used to inspect for potential faults having one or more highest priorities so that the most important defects are detected by the inspection process. Should be selected to optimize. Selecting such determinations and parameters of the most suitable inspection system may result in, or may not, optimize the inspection for potential faults with one or more lowest priorities. There is also.

  In other embodiments, the method includes determining the impact of a potential failure on the yield of the fabricated device using the design data, as shown in step 214. Thus, this method is used for recipe optimization and monitoring. In other embodiments, the method includes determining the impact of a potential failure that is undetectable but determined to affect yield. Thus, the method includes determining the percentage of yield loss that cannot be detected by inspection. One example of a method for predicting yield used in the methods described herein is Sataya et al., US Pat. No. 6, incorporated by reference as if fully set forth herein. No. 813,572.

  Thus, the method described above is used for fully automated prediction, tracking and validation of hot spots (after any initial manual setup has been performed). The above-described method further includes storing the results of determining which of a plurality of different inspection systems are most suitable for detecting potential faults stored on the storage medium. The results of this step include the results described herein. In addition, the method performs the storing step as further described herein. Storage media includes the storage media described herein.

  Each of the method embodiments for evaluating one or more yield related processes described above includes other step (s) of the method (s) described herein. In addition, each of the method embodiments for evaluating one or more yield-related processes described above is performed by the system described herein.

  The methods and systems described herein are used to provide a comprehensive design, defect, and yield solution. For example, as described above, the method includes dividing defects (detected by in-line inspection and / or electrical inspection) into systematic defects and random defects. The method and system embodiments described herein are further used to manage hot spots.

  Defects related to parameter yield loss can be used as input for simulations, such as simulations, that determine device electrical parameters based on semiconductor manufacturing process parameters. In this way, defects related to parameter yield loss can be used in combination with information about processes performed on the wafer to tune or optimize the simulation. In addition, simulation results can be used to identify parameters of a process that is performed on a wafer that is modified to reduce defects associated with parameter yield loss. Further, simulations and results of the methods described herein can be used to identify parameters of one or more processes that are critical in reducing parameter yield loss.

  Defects related to systematic patterning loss are used to identify pattern defects related to the interaction between device design and process. In this way, information about these defects can be used to change the process, change the design, or change the process and design to reduce these defects.

  The above steps are performed in a design feedback phase that is performed to take advantage of lessons learned and improve future designs. In other words, knowledge transfer from the hot spot database and monitoring phase can be made to the design phase (eg, technical research and development, product design, RET design, etc.). This phase is performed in multi-source space (eg, using correlation between design space, wafer space, test space, and process space). This phase further includes improving the design based on hot spots that are strongly correlated with a particular cell design. In addition, this phase includes improving the design using hot spots that are strongly correlated with the proposed design rules.

  Information about random defects can be used to determine defect limit yield (ie, maximum yield achievable if all systematic and repeater defects are eliminated). Such information can also be used to perform on-line and off-line monitoring in combination with simulations that determine the impact of random defects on the device and identify random defects that are the best yield killer.

  The methods described herein include monitoring semiconductor processing processes using the results of these methods. The results used to monitor the semiconductor processing process include the results described herein (eg, inline inspection data, systematic defect information, random defect information, fault density map, binning grouping results, etc. Or a combination of the results described herein. The method described herein further includes changing one or more parameters of one or more semiconductor processing processes based on the results of any of the methods described herein. Including. The parameter (s) of the semiconductor processing process (s) are controlled using feedback technology, feedforward technology, field technology, or some combination thereof. Thus, the methods described herein and the results generated by those methods are used for SPC applications.

  As further described herein, the methods and systems described herein can be grouped by bin ranges, review sampling, inspection setups, or any other analysis described herein. Is used for on-tool yield prediction based on design data. The methods and systems described herein have a number of advantages over other currently used methods and systems. For example, currently used methods and systems for KP analysis use historical yield data for overall random yield loss prediction by considering defect density by size distribution and / or classification. One drawback of such methods and systems is that other defect groups (eg, size bins, class bins, layers) may be used when calculating the probability that one or more defects will spoil a die. It is not considered. In addition, these methods and systems require statistically significant historical data for setup. In other examples, the methods and systems currently used for KP analysis consider size and / or classification (eg, similar pattern density) within a region to better predict the KP of detected defects Using historical yield data and yield loss prediction per defect. One disadvantage of such methods and systems is that statistically significant historical data is required for setup. In another example, the methods and systems currently used for critical area analysis (CAA) determine yield loss prediction by defect, and the critical area across the die by geometry (line width, spacing) for various defect sizes. Depends on pre-calculation. This approach performs a relatively large amount of computation, but once computed, defects in a region larger than the critical region based on placement are expected to be killer. One disadvantage of such methods and systems is that statistically significant historical data is required for setup. In addition, such methods and systems require a large amount of preprocessing, and the accuracy of the methods and systems is limited by the defect coordinate accuracy.

  In contrast, the methods and systems described herein use very accurate coordinates, resulting in improved yield prediction over CAA and the methods described herein. The The methods and systems described herein are further used for active CAA. For example, this approach does not preprocess the data to generate a look-up table across multiple sizes and placements, but calculate yields based on improved placements and sizes. This requires design data that can be used in the inspection system and may be computationally efficient. In addition, the methods and systems described herein include omitting analysis for systematic defects or by pattern grouping, which further improves computational efficiency. In addition, the method and system described herein can be used to predict the yield of on-tool results, so that results can be reviewed (e.g., recipes while the wafer is on the chunk). Can be used to prioritize defects (manual review for optimization, high resolution image capture, etc.).

  Other modifications and alternatives of various aspects of the invention will be apparent to those skilled in the art upon reference to this specification. For example, a method and system for using design data in combination with inspection data is implemented. Accordingly, this description is to be construed as illustrative and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It will be understood that the form of the invention shown in the drawings and described herein is to be construed as a presently preferred embodiment. Elements and materials can be used in place of those illustrated and described herein, parts and processes can be reversed, and several features of the invention can be utilized independently. All of which will be apparent to those skilled in the art after utilizing this description of the invention. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as set forth in the appended claims.

2 is a flow diagram illustrating one embodiment of a computer-implemented method for determining the location of inspection data in a design data space. 1 is a schematic diagram illustrating the top surface of different embodiments of a predetermined alignment site. 1 is a schematic diagram illustrating the top surface of different embodiments of a predetermined alignment site. FIG. 6 is a hierarchy diagram illustrating various embodiments of a computer-implemented method for performing a wafer-to-wafer comparison. 1 is a schematic diagram illustrating one embodiment of a computer-implemented method for performing a wafer-to-wafer comparison. FIG. 6 is a schematic diagram illustrating the top surface of one embodiment of inspection data captured for a region of the surface of a wafer divided into a plurality of annular rings. FIG. 4 is a schematic diagram illustrating the top surface of one embodiment of inspection data captured for a region of the surface of a wafer divided into a plurality of radial sectors. 6 is a schematic diagram illustrating another embodiment of a computer-implemented method for performing a wafer-to-wafer comparison. 1 is a schematic diagram illustrating the top surface of one embodiment of an array of dies printed on a wafer. FIG. 6 is a schematic diagram illustrating the top surface of one embodiment of inspection data captured for a die printed on a wafer that is divided into a plurality of frames. FIG. 6 is a schematic diagram illustrating an additional embodiment of a computer-implemented method for performing a wafer-to-wafer comparison. 1 is a schematic diagram illustrating the top surface of one embodiment of an array of dies printed on a wafer and scan paths on the wafer. Fig. 6 is a schematic diagram illustrating the top surface of a continuous swath of inspection data captured for a wafer. Illustrates the top surface of successive swaths of inspection data captured for a selected wafer and alignment site by a computer implemented method for determining the position of swath (N + 1) with respect to swath N using data in the swath overlap region It is the schematic to do. FIG. 4 is a schematic diagram illustrating the top surface of one embodiment of a swath with different inspection data captured for a wafer whose alignment site is relatively far from the first inspection swath. FIG. 6 is a schematic diagram illustrating the top surface of various embodiments of different swaths of inspection data captured for a wafer. FIG. 6 is a schematic diagram illustrating the top surface of various embodiments of different swaths of inspection data captured for a wafer. FIG. 6 is a schematic diagram illustrating the top surface of various embodiments of different swaths of inspection data captured for a wafer. 6 is a flow diagram illustrating another embodiment of a computer-implemented method for determining the location of inspection data in a design data space. 1 is a schematic diagram illustrating aspects of various embodiments of a system configured to determine the location of inspection data in a design data space. 6 is a schematic diagram illustrating one embodiment of a computer-implemented method of separating defects detected on a wafer according to bin ranges. FIG. 6 is a schematic diagram illustrating the top surface of one embodiment of an alignment site on a wafer in three different dies, arranged on a wafer in a triangular shape. 6 is a schematic diagram illustrating another embodiment of a computer-implemented method of separating defects detected on a wafer according to bin ranges. FIG. 4 illustrates one embodiment of input to and output from a module configured to perform a computer-implemented method of separating defects detected on a wafer according to bin ranges according to embodiments described herein. It is a schematic diagram. 21 is a schematic diagram illustrating different embodiments of the output of the module of FIG. 21 is a schematic diagram illustrating different embodiments of the output of the module of FIG. 21 is a schematic diagram illustrating one embodiment of the inputs and outputs of the module of FIG. 21 is a schematic diagram illustrating the top surface of one embodiment of the output of the module of FIG. 1 is a schematic diagram illustrating aspects of one embodiment of a system configured to display and analyze design data and defect data. 1 is a schematic diagram illustrating the top surface of one embodiment of one or more zones on a wafer associated with the location of one or more defect types on the wafer. 6 is a flow diagram illustrating one embodiment of a computer-implemented method for evaluating one or more yield-related processes with respect to design data.

Claims (19)

A computer-implemented method for determining the location of inspection data in a design data space, comprising:
Aligning data captured by the inspection system for alignment sites on the wafer with data for a predetermined alignment site;
Determining the position of the alignment site on the wafer in the design data space based on the position of the predetermined alignment site in the design data space;
Determining the position of inspection data captured for the wafer by the inspection system in the design data space based on the position of the alignment site on the wafer in the design data space;
Including
The steps are performed in the order listed,
Defects in different parts of the wafer based on the location of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data Determining the sensitivity of detecting, wherein the one or more attributes of the inspection data are one or more image noise attributes, or some combination thereof, when defects are detected in the different portions Including
The data for the predetermined alignment site is captured by one or more simulated images showing how the predetermined alignment site is printed on the wafer, or by the inspection system, and a data structure A computer-implemented method comprising data aligned to design data stored in a body.   The data for the predetermined alignment site includes one or more attributes of the predetermined alignment site, and the data for the alignment site includes one or more attributes of the alignment site and aligns them. The method of claim 1, comprising aligning the one or more attributes of the predetermined alignment site to the one or more attributes of the alignment site.   The method of claim 1, wherein the data for the predetermined alignment site includes at least a portion of a standard reference die image aligned with design coordinates in the design data space.   The predetermined alignment site comprises at least one alignment feature or at least two alignment features having one or more attributes that are unique in the x and y directions, and the first of the at least two alignment features. A feature has one or more attributes that are unique in the x direction, and a second feature of the at least two alignment features has one or more attributes that are unique in the y direction. Item 2. The method according to Item 1.   The data for the alignment site is in a swath of the test data, and determining the position of the test data determines the position of the swath in the design data space based on the position of the alignment site. The method of claim 1, further comprising: determining a position of an additional swath of the inspection data in the design data space based on the position of the swath. Said one or more attributes of the design data, current process layers the inspection test data is captured has been performed of the wafer, different process layers other than the Puroseru layer, or the current for some combination thereof The design data for the inspection being performed , different design data other than the design data, or the current wafer being inspected against some combination thereof , another wafer other than the installed wafer, or their The method of claim 1, wherein the method is selected based on one or more attributes of inspection data already captured for any combination. The one or more attributes of the design data are processed for the defect yield criticality, which is the actual yield of defects already detected in the different parts, for the design data already detected in the different parts The method of claim 1, wherein the defect is selected based on a failure probability of the defect, which is a probability that a defect causes one or more electrical failures in the device , or some combination thereof.   Further, determining sensitivity includes determining sensitivity to detect the defect in the different portions of the wafer based on the location and context map of the inspection data in the design data space, The method of claim 1, wherein the map includes values for one or more attributes of design data in the design data space.   Further, one or more attributes of schema data for the design of the device being processed on the wafer, one or more attributes of the expected electrical behavior of the physical layout for the device, or some combination thereof The method of claim 1, comprising changing one or more parameters for detecting defects on the wafer based on:   The method further includes generating a knowledge base using the results of one or more steps of the method and generating an inspection process performed by the inspection system using the knowledge base. The method according to 1.   Further comprising: classifying defects detected in the different portions of the wafer based on the position of the portion of the inspection data corresponding to the defects in the design data space and the context map; The method of claim 1, comprising: values for one or more attributes of the design data in the design data space.   The inspection data includes data for defects on the wafer, and the method further includes determining a position of the defect in the design data space based on the position of the inspection data in the design data space; Determining whether the defect is a nuisance defect based on the position of the defect in the design data space and one or more attributes of the design data in the design data space. The method according to 1.   Further, one or more of the inspection systems captured for different portions of the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space The method of claim 1, comprising extracting one or more predetermined attributes of outputs from the plurality of detectors.   And a failure probability for one or more defects detected on the wafer based on the location of the inspection data in the design data space and one or more attributes of the design data in the design data space. The method of claim 1, comprising determining a value.   Further, determining coordinates of a position of a defect detected on the wafer in the design data space based on the position of the inspection data in the design data space, and based on a floor plan for the design data Converting the coordinates of the location of a defect to design cell coordinates.   The method of claim 1, wherein an image of a reticle generated by a reticle inspection system is used as design data in the design data space, and the reticle is used to print the design data on the wafer.   The method of claim 1, wherein a simulated image showing how a reticle image is printed on the wafer is used as the design data in the design data space.   2. The method of claim 1, further comprising generating a context map for the design data in the design data space based on reticle inspection data captured for a reticle used to print the design data on the wafer. The method described. Furthermore, in claim 1 comprising performing the wafer inspection process so to determine printability of reticle defects on the wafer using the said position and a context map of the inspection data in the design data space The method described.

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