KR102547617B1 - Semiconductor device test apparatus that provides an accelerated environment and method for testing semiconductor devices in an accelerated environment using the same - Google Patents

Abstract

Provided is a semiconductor device test apparatus that provides an accelerated environment. The semiconductor device test apparatus includes: a chamber that covers at least one semiconductor device under test mounted on a test board, and provides an accelerated environment to the covered semiconductor device under test. The accelerated environment provided by the chamber includes a high temperature environment higher than room temperature. Therefore, it is possible to quickly test the semiconductor device under test.

Description

Semiconductor device test apparatus that provides an accelerated environment and method for testing semiconductor devices in an accelerated environment using the same}

The present invention relates to a semiconductor device test apparatus providing an accelerated environment and a method for testing a semiconductor device in an accelerated environment using the same, and more specifically, to provide a constant high-temperature environment to a semiconductor device under test to reduce test time while simplifying the accelerated environment. It relates to a semiconductor device test device provided and a method for testing a semiconductor device in an accelerated environment using the same.

The semiconductor device test apparatus may refer to a device for inspecting, for example, a soft error effect (SEE) whether a semiconductor device under test operates properly.

On the other hand, the semiconductor device may rapidly increase the frequency of inspection as the process difficulty increases.

Accordingly, it may take a long time to inspect the semiconductor device under test.

Meanwhile, it is difficult to infinitely provide a test device for inspecting a semiconductor device under test within a production space where semiconductor devices are produced.

Therefore, it can be a key factor in testing the semiconductor device under test to quickly test whether the semiconductor device under test operates properly with a simplified test device.

On the other hand, a conventional semiconductor device test apparatus is mainly used in a room temperature environment. For example, Korean Unexamined Patent Publication No. 10-2012-0035115 discloses a method for inspecting a semiconductor device in which a semiconductor chip is mounted on a wiring board, wherein (a) the bottom surface of the wiring board is opposite to the top surface on which the semiconductor chip is mounted. a step of preparing the semiconductor device in which a plurality of external terminals are provided; and (b) a step of performing an inspection for determining whether the semiconductor device is good or bad by measuring the flatness of the plurality of external terminals; ) step, the direction toward the convex portion when the wiring board is bent is the (+) direction so that the lower surface of the wiring board is directed downward and convex upward, and the lower surface of the wiring board is directed downward, When the direction toward the convex portion when the wiring board is bent so as to be convex downward is the (-) direction, the allowable range in the (+) direction of the flatness is the allowable range in the (-) direction of the flatness A method for inspecting a semiconductor device is disclosed in which a flatness standard smaller than a range is formed and the semiconductor device is inspected using the flatness standard.

However, as in the prior art, it may take a long time to test whether a semiconductor device under test operates properly in a room temperature environment with a semiconductor device test apparatus.

Accordingly, conventionally, a semiconductor device test apparatus providing a high-temperature environment has been developed in order to shorten the time required to test whether a semiconductor device under test operates properly.

However, a conventional semiconductor device test apparatus providing a high-temperature environment may have a large temperature deviation in a high-temperature environment.

In the case of such a conventional semiconductor device testing apparatus, an inconsistent temperature environment may be provided to the semiconductor device under test due to the large temperature deviation as described above, so that the test result of the semiconductor device under test may be inaccurate. Of course.

Therefore, a semiconductor device test apparatus capable of quickly acquiring reliability information by inspecting a soft error effect (SEE) in an accelerated environment while providing a constant acceleration environment, that is, a high-temperature environment higher than room temperature, to the semiconductor device under test is provided. It is necessary.

A technical problem to be solved by the present invention is to provide a semiconductor device test apparatus providing an accelerated environment capable of quickly inspecting a semiconductor device under test and a method for testing a semiconductor device in an accelerated environment using the same.

Another technical problem to be solved by the present invention is to provide a semiconductor device test apparatus providing an accelerated environment with improved reliability in inspection of a semiconductor device under test and a method for testing a semiconductor device in an accelerated environment using the same.

Another technical problem to be solved by the present invention is to provide a semiconductor device test apparatus providing an accelerated environment with improved space utilization and a semiconductor device test method in an accelerated environment using the same.

The technical problem to be solved by the present invention is not limited to the above.

In order to solve the above technical problem, the present invention provides a semiconductor device test apparatus providing an acceleration environment.

According to an embodiment, the semiconductor device testing apparatus for providing an accelerated environment includes a chamber covering at least one semiconductor device under test mounted on a test board and providing an acceleration environment to the covered semiconductor device under test. The accelerating environment provided by the chamber may include a high-temperature environment higher than room temperature.

According to an embodiment, the chamber includes a chamber body covering the semiconductor device under test, and a chamber window through which a test beam is transmitted to a region in which the semiconductor device under test is mounted, wherein the chamber body comprises: From the test beam, it may be formed of a non-metallic material that does not generate secondary particles.

According to an embodiment, the chamber further includes a heater providing the high-temperature environment to the semiconductor device under test covered by the chamber body, wherein the chamber body extends to the semiconductor device under test covered by the chamber body. The provided high-temperature environment may be maintained with a temperature deviation of 0 ° C. or more and 0.01 ° C. or less.

According to an embodiment, a plurality of chambers are provided, and the plurality of chambers are disposed side by side along an axial direction of a test beam to be fixedly irradiated, and are farther away from the test beam in consideration of the dose of the test beam. As the temperature increases, the temperature of the high-temperature environment provided to the semiconductor device under test may be controlled to increase.

According to an embodiment, a stage for moving the test board on which the semiconductor device under test is mounted may be further included toward an axis of the test beam to be fixedly irradiated.

In order to solve the above technical problem, the present invention provides a method for testing a semiconductor device in an accelerated environment.

According to an embodiment, the method for testing a semiconductor device in an accelerated environment may include mounting at least one semiconductor device under test on a test board, including a chamber providing an acceleration environment to the semiconductor device under test mounted on the test board. covering, and providing an acceleration environment to the semiconductor device under test covered by the chamber, wherein the providing of the acceleration environment includes providing a high-temperature environment higher than room temperature to the semiconductor device under test; It may include maintaining a high-temperature environment with a temperature deviation of 0 ° C. or more and 0.01 ° C. or less.

According to an embodiment, a plurality of chambers are provided, the plurality of chambers are arranged side by side along an axial direction of a test beam to be fixedly irradiated, and the providing of the acceleration environment includes the dose of the test beam. In consideration of the above, controlling the temperature of the high-temperature environment provided to the semiconductor device under test to increase as the plurality of chambers are further away from the test beam, and toward the axis of the test beam to be fixedly irradiated, The method may include controlling the movement of the test board on which the test semiconductor device is mounted.

According to an embodiment of the present invention, a chamber covering at least one semiconductor device under test mounted on a test board and providing an acceleration environment to the covered semiconductor device under test, wherein the acceleration environment provided by the chamber includes: A semiconductor device test apparatus providing an accelerated environment including a high-temperature environment higher than room temperature may be provided.

Accordingly, according to the present invention, since the high-temperature environment can be provided to the semiconductor device under test, the inspection time can be shortened compared to the case of inspecting the semiconductor device under test at room temperature.

Therefore, according to the present invention, the semiconductor device under test can be rapidly inspected.

Meanwhile, according to an embodiment of the present invention, the chamber may maintain the high-temperature environment provided to the semiconductor device under test covered by the chamber with a temperature deviation of 0 °C or more and 0.01 °C or less.

Accordingly, according to the present invention, since the high-temperature environment can be constantly provided to the semiconductor device under test, reliability can be improved in inspection of the semiconductor device under test.

Also, according to an embodiment of the present invention, the chamber may be provided with a simplified configuration.

Accordingly, according to the present invention, there is a technical effect of improving space utilization by replacing a conventional bulk test device for inspecting a semiconductor device under test.

1 is a diagram for explaining a semiconductor device test apparatus providing an acceleration environment according to an embodiment of the present invention.
2 to 11 are diagrams for explaining a method of testing a semiconductor device in an acceleration environment according to an embodiment of the present invention.
12 (a) to 13 (b) are diagrams for explaining an experimental example of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content will be thorough and complete, and the spirit of the present invention will be sufficiently conveyed to those skilled in the art.

In this specification, when an element is referred to as being on another element, it means that it may be directly formed on the other element or a third element may be interposed therebetween. Also, in the drawings, shapes and thicknesses of regions are exaggerated for effective description of technical content.

In addition, although terms such as first, second, and third are used to describe various elements in various embodiments of the present specification, these elements should not be limited by these terms. These terms are only used to distinguish one component from another. Therefore, what is referred to as a first element in one embodiment may be referred to as a second element in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. In addition, in this specification, 'and/or' is used to mean including at least one of the elements listed before and after.

In the specification, expressions in the singular number include plural expressions unless the context clearly dictates otherwise. In addition, the terms "comprise" or "having" are intended to designate that the features, numbers, steps, components, or combinations thereof described in the specification exist, but one or more other features, numbers, steps, or components. It should not be construed as excluding the possibility of the presence or addition of elements or combinations thereof. In addition, in this specification, "connection" is used to mean both indirectly and directly connecting a plurality of components.

In addition, terms such as “… unit”, “… unit”, and “module” described in the specification mean a unit that processes at least one function or operation, which may be implemented as hardware or software or a combination of hardware and software. there is.

In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

The semiconductor device test apparatus may refer to a device for inspecting, for example, a soft error effect (SEE) whether a semiconductor device under test operates properly.

On the other hand, the semiconductor device may rapidly increase the frequency of inspection as the process difficulty increases.

Accordingly, it may take a long time to inspect the semiconductor device under test.

Meanwhile, it is difficult to infinitely provide a test device for inspecting a semiconductor device under test within a production space where semiconductor devices are produced.

Therefore, it can be a key factor in testing the semiconductor device under test to quickly test whether the semiconductor device under test operates properly with a simplified test device.

On the other hand, a conventional semiconductor device test apparatus is mainly used in a room temperature environment.

However, as in the prior art, it may take a long time to test whether a semiconductor device under test operates properly in a room temperature environment with a semiconductor device test apparatus.

Accordingly, conventionally, a semiconductor device test apparatus providing a high-temperature environment has been developed in order to shorten the time required to test whether a semiconductor device under test operates properly.

However, a conventional semiconductor device test apparatus providing a high-temperature environment may have a large temperature deviation in a high-temperature environment.

In the case of such a conventional semiconductor device testing apparatus, an inconsistent temperature environment may be provided to the semiconductor device under test due to the large temperature deviation as described above, so that the test result of the semiconductor device under test may be inaccurate. Of course.

Therefore, in the present invention, while providing a constant acceleration environment, that is, a high-temperature environment higher than room temperature, to the semiconductor device under test, by examining the soft error effect (SEE) in the acceleration environment, it is possible to quickly obtain reliability information. An environment providing semiconductor device test device is provided.

Hereinafter, a semiconductor device test apparatus for providing an acceleration environment according to an embodiment of the present invention will be described with reference to the drawings.

1 is a diagram for explaining a semiconductor device test apparatus providing an acceleration environment according to an embodiment of the present invention.

According to an embodiment of the present invention described below, it is assumed that the semiconductor device under test (dut) tested through the semiconductor device testing apparatus 100 is mounted on a test board (uut), as shown in FIG. 1 . it did

Accordingly, even if there is no separate explanation in the embodiments of the present invention described below, the semiconductor device testing apparatus 100 may include the test board uut as one configuration.

Alternatively, according to an exemplary embodiment, the semiconductor device test apparatus 100 does not include the test board uut as one configuration, but the semiconductor device under test dut has conventionally been tested. ) may be provided in a state mounted on a test board (uut) prepared to test.

In addition, in the embodiments of the present invention described below, it is assumed that at least one semiconductor device under test (dut) is mounted on the test board (uut), even if there is no separate explanation. Here, at least one or more may mean that the number of semiconductor devices under test (dut) mounted on the test board (uut) is 1, 2, 3, or n.

Referring to FIG. 1 , the semiconductor device test apparatus 100 providing the acceleration environment may include at least one of a chamber 10 and a stage 30 .

Hereinafter, each configuration is explained.

chamber(10)

Referring to FIG. 1 , the chamber 10 covers at least one semiconductor device under test (dut) mounted on the test board (uut), and provides an acceleration environment to the covered semiconductor device under test (dut). can do. Meanwhile, the accelerated environment may be understood as a concept including a high-temperature environment higher than room temperature. More specifically, the high-temperature environment herein may be understood as a concept including a high temperature of 180 °C or higher and 200 °C or lower.

To this end, as shown in FIG. 1 , the chamber 10 may include at least one of a chamber body 11, a chamber window 12, a heater 13, and a temperature sensor 14. .

Hereinafter, each configuration of the chamber 10 is described.

chamber body(11)

Referring to FIG. 1 , the chamber body 11 may cover at least one semiconductor device under test dut mounted on the test board uut.

To this end, an opening may be formed at one side of the chamber body 11 to accommodate therein at least one semiconductor device under test dut mounted on the test board uut. When at least one semiconductor device under test (dut) mounted on the test board (uut) is accommodated therein through the opening, the chamber body 11 surrounds the accommodated semiconductor device under test (dut). can cover

To this end, the chamber body 11, as shown in FIG. 1, may have the shape of a pentahedron in which the opening is formed. However, the shape of the chamber body 11 is not limited to the above-described pentahedral shape, and as described above, a shape capable of surrounding and covering the at least one semiconductor device under test dut while being accommodated therein. provided, it is not limited.

Accordingly, the chamber body 11 can maintain the high-temperature environment when the high-temperature environment is provided to the semiconductor device under test (dut) covered by the chamber body 11 from a heater 20 described later. there is.

More specifically, the chamber body 11 may maintain the high-temperature environment provided to the semiconductor device under test (dut) covered by the chamber body 11 with a temperature deviation of 0 °C or more and 0.01 °C or less. .

Accordingly, according to the present invention, since the high-temperature environment can be constantly provided to the semiconductor device under test dut, reliability can be improved in the inspection of the semiconductor device under test dut. .

To this end, as shown in FIG. 1 , the chamber body 11 covers the semiconductor device under test dut and may be made of a heat insulating material.

Meanwhile, the chamber body 11 may not react with a test beam (ry, see FIG. 10) irradiated to inspect at least one or more semiconductor devices under test (dut) mounted on the test board (uut). can Here, the test beam (ry, see FIG. 10) may be understood as a concept including radiation.

To this end, the chamber body 11 may be formed of a material that does not react with the test beam ry (see FIG. 10). For example, the chamber body 11 may be formed of a non-metallic material. More specifically, for example, the chamber body 11 may be formed of paper, heat-resistant plastic, eg, plastic having heat resistance at 180° C. or higher and 200° C. or lower.

Accordingly, according to the present invention, when the test beam ry (see FIG. 10) is irradiated to at least one semiconductor device under test dut mounted on the test board uut, the chamber body 11 ) is non-reactive with the irradiated test beam (ry, see FIG. 10), so secondary particles may not be generated from the test beam (ry, see FIG. 10).

On the other hand, unlike the embodiment of the present invention, when the chamber body is formed of metal, when the test beam (ry, see FIG. 10) is irradiated, the chamber body reacts with the test beam (ry, see FIG. 10) Secondary particles may be generated.

In this case, it goes without saying that the reliability of the inspection result may be lowered.

However, according to the present invention, as described above, the chamber body 11 may be formed of a material that does not react with the test beam (ry, see FIG. 10), and thus the secondary particles may not occur.

Therefore, according to the present invention, reliability can be improved in the inspection result of the semiconductor device under test (dut).

Chamber window (12)

Referring to FIG. 1 , the chamber window 12 may transmit the test beam ry (see FIG. 10 ) to a region where the semiconductor device under test dut is mounted.

To this end, when the chamber body 11 covers the at least one semiconductor device under test dut mounted on the test board uut, the chamber window 12 may cover the at least one semiconductor device under test. It may be provided in an area of the chamber body 11 corresponding to the area where the dut is mounted.

Meanwhile, as described above, the chamber window 12 transmits the test beam ry (see FIG. 10 ) to a region where the semiconductor device under test dut is mounted, the test beam ry (see FIG. 10 ). Reference) may be formed of a material that transmits. For example, the chamber window 12 may be made of vinyl, kapton, or polyimide.

Accordingly, according to the present invention, when the test beam (ry, see FIG. 10 ) is irradiated to the region where the semiconductor device under test (dut) is mounted, the semiconductor device under test is passed through the chamber window 12 . Of course, the test beam (ry, see FIG. 10) can reach (dut).

Meanwhile, according to one embodiment, the chamber body 11 and the chamber window 12 described above may be made of the same material.

More specifically, the chamber body 11 and the chamber window 12 may be formed of the same material that transmits the test beam (ry, see FIG. 10).

In this case, the chamber window 12 may be integrally provided with the chamber body 11 instead of being formed separately from the chamber body 11 .

Accordingly, according to the present invention, when the test beam (ry, see FIG. 10) is irradiated to the semiconductor device under test (dut) mounted on the test board (uut), the integrally provided chamber body (11) ) and the chamber window 12 transmits the irradiated test beam (ry, see FIG. 10) to the region where the semiconductor device under test dut is mounted, so that the semiconductor device under test dut is not subject to the test. Of course, the beam (ry, see FIG. 10) can be reached.

heater(13)

The heater 13 may provide the high-temperature environment to the semiconductor device under test (dut) covered by the chamber body 11 .

To this end, the heater 13 may be provided on one side of the chamber body 11 . Here, one side may be understood as a concept including at least one of the inside and outside of the chamber body 11 . More specifically, as described above, the interior of the chamber body 11 here refers to an interior surrounded and covered by the chamber body 11 while accommodating the at least one semiconductor device under test (dut). can do. Meanwhile, here, the outside of the chamber body 11 is one side of the test board uut, for example, one side or the other side of the test board uut on which the semiconductor device under test dut is mounted. (See FIG. 1).

However, the position where the heater 13 is disposed is not limited to the above-described embodiments, and as described above, the high-temperature environment is provided to the semiconductor device under test dut covered by the chamber body 11 There are no restrictions as long as you can do it.

Accordingly, according to the present invention, since the high-temperature environment can be provided to the semiconductor device under test (dut) through the heater 13, it is easier to inspect the semiconductor device under test (dut) at room temperature. Inspection time can be shortened.

Therefore, according to the present invention, of course, the semiconductor device under test (dut) can be quickly inspected.

Temperature sensor(14)

The temperature sensor 14 may measure a temperature provided to at least one semiconductor device under test dut mounted on the test board uut.

To this end, as shown in FIG. 1 , the temperature sensor 14 may be disposed adjacent to the semiconductor device under test dut.

Accordingly, according to an embodiment of the present invention, the temperature sensor 14 may measure the actual temperature provided to the semiconductor device under test (dut).

Therefore, according to the present invention, it is of course possible to accurately determine and control the high-temperature environment provided to the semiconductor device under test (dut), that is, the temperature.

In the above, each configuration of the chamber 10 has been described.

According to the embodiment of the present invention described above, the chamber 10 includes each of the above-described components, that is, the chamber body 11, the chamber window 12, the heater 13, and the temperature sensor ( 14) may be provided with a simplified configuration including at least one of them.

Accordingly, according to the present invention, there is a technical effect of improving space utilization by replacing a conventional bulk test device for inspecting a semiconductor device under test.

In addition, according to the present invention, as described above, of course, the semiconductor device under test (dut) can be rapidly inspected.

On the other hand, according to one embodiment, the chamber 10, as shown in Figure 8, may be provided in a plurality (10a ~ 10d). This assumes that the test board uut on which the at least one semiconductor device under test dut is mounted is provided in a plurality (uut1 to uut4), as shown in FIG. 8 .

More specifically, when a plurality of chambers 10 are provided on each of the plurality of test boards uut1 to uut4, the plurality of chambers 10a to 10d and the plurality of test boards ( As shown in FIGS. 9 to 11 , uut1 to uut4 may be arranged side by side along the axis ax direction of the irradiated test beam ry. Meanwhile, here, it is assumed that the test beam ry is fixedly irradiated in a non-moving state.

In this case, the test board uut on which the at least one semiconductor device under test dut is mounted may be formed of a material that transmits the test beam ry. Here, with regard to the material through which the test beam ry is transmitted, reference is made to the description of the previous embodiment as it overlaps with the description of the previous embodiment.

Accordingly, according to the present invention, when the test beam ry is fixedly irradiated, the test board ( Of course, the test beam ry may reach the semiconductor device under test dut mounted on uut.

Meanwhile, according to an embodiment of the present invention, in the plurality of chambers 10a to 10d, the temperature of the high-temperature environment provided to the semiconductor device under test (dut) increases as the distance from the test beam (ry) increases. can be controlled.

According to the present invention, this is in consideration of the dose of the test beam ry. Here, the dose can be interpreted as including the number of particles irradiated to a given area during a unit time or the number of particles irradiated to a unit area during a given time, and includes flux. can be interpreted

That is, according to the present invention, as shown in FIG. 10, when the plurality of chambers 10a to 10d are arranged side by side along the direction of the axis ax of the test beam ry to be fixedly irradiated, the test It is considered that the dose of the test beam ry reaching the chamber 10d distant from the test beam ry may be relatively smaller than that of the chamber 10a adjacent to the beam ry.

Meanwhile, as described above, when the dose of the test beam ry reaching the chamber 10d distant from the test beam ry is relatively smaller than the chamber 10a adjacent to the test beam ry, the An acceleration environment may be different in the chamber 10d farther from the test beam ry than in the chamber 10a adjacent to the test beam ry. More specifically, the acceleration environment may be more accelerated in the chamber 10a adjacent to the test beam ry than in the chamber 10d distant from the test beam ry.

In this case, the acceleration environment provided to the semiconductor device under test dut inside the plurality of chambers 10a to 10d may not be constant. Therefore, reliability may be deteriorated in the inspection of the semiconductor device under test (dut).

However, according to the present invention, as described above, in the plurality of chambers 10a to 10d, as the distance from the test beam ry increases, the temperature of the high-temperature environment provided to the semiconductor device under test dut increases. can be controlled to increase.

Accordingly, according to the present invention, even when the dose of the test beam ry reaching the chamber 10d distant from the test beam ry is relatively smaller than the chamber 10a adjacent to the test beam ry. , The acceleration environment can be constantly provided to the semiconductor device under test (dut) by controlling the temperature of the high-temperature environment to be high so as to correspond to the small dose.

Accordingly, according to the present invention, reliability can be improved in the inspection of the semiconductor device under test (dut).

To this end, according to an embodiment, as shown in FIG. 8 , the plurality of heaters 13a to 13d provided in each of the plurality of chambers 10a to 10d are further away from the test beam ry. A temperature provided to the semiconductor device under test (dut) may be controlled to increase.

Accordingly, it goes without saying that a high-temperature environment may be created in the semiconductor device under test dut inside the plurality of chambers 10a to 10d as the distance from the test beam ry increases.

stage(30)

9 to 11, the stage 30 moves the test board uut on which the semiconductor device under test dut is mounted toward the axis ax of the test beam ry to be fixedly irradiated. It can be moved (mv).

More specifically, as shown in FIG. 9, the stage 30 moves (mv) the test board (uut) toward one side of the axis (ax) of the fixedly irradiated test beam (ry), As shown in FIG. 10, after the fixed irradiation test beam ry is moved (mv) to pass through the test board uut on which the semiconductor device under test dut is mounted, as shown in FIG. Similarly, the test board uut may be moved mv to the other side of the axis ax of the fixed irradiated test beam ry.

Accordingly, according to the present invention, the test beam ry may be uniformly irradiated to the at least one semiconductor device under test dut mounted on the test board uut. Here, uniform irradiation of the test beam ry may mean that a dose reaching the at least one semiconductor device under test dut is uniform.

Accordingly, according to the present invention, reliability can be improved in the inspection of the semiconductor device under test (dut).

In the above, the semiconductor device test apparatus 100 providing an acceleration environment according to an embodiment of the present invention has been described.

Hereinafter, modified examples of the present invention are described.

In a modified example of the present invention described below, a description overlapping with the above-described semiconductor device test apparatus providing an accelerated environment may be omitted. However, just because overlapping descriptions are omitted in the following does not exclude them, and overlapping descriptions below refer to the description of the previous embodiment.

According to a modified example of the present invention, in the above-described embodiment, the plurality of chambers 10a to 10d include at least one of a low-temperature chamber having a relatively low temperature and a high-temperature chamber having a relatively high temperature than the low-temperature chamber. can include

According to a modified example of the present invention, the low-temperature chamber has a height from the mounting surface of the test board (uut) on which the at least one semiconductor under test (dut) is mounted to an inner upper wall of the low-temperature chamber, It may be relatively lower than the high temperature chamber. On the other hand, in the high-temperature chamber, the height from the mounting surface of the test board (uut) on which the at least one semiconductor under test (dut) is mounted to the inner upper wall of the low-temperature chamber is higher than that of the low-temperature chamber. Of course, it can be as high as .

Meanwhile, it is assumed here that the low-temperature chamber and the high-temperature chamber have the same area.

Accordingly, according to a modified example of the present invention, a high-temperature environment provided to the at least one semiconductor device under test (dut) in the low-temperature chamber may be constantly maintained.

This means that according to the modified example of the present invention, since the temperature of the high-temperature environment provided by the low-temperature chamber is relatively lower than that of the high-temperature chamber, the low-temperature chamber of relatively low temperature may be more sensitive to temperature changes as described above. it is taken into account For example, from the viewpoint of the semiconductor device under test (dut), a change of 1 °C at a low temperature may be more sensitive than a change of 1 °C at a high temperature.

Accordingly, according to a modified example of the present invention, even when the plurality of chambers 10a to 10d include the low-temperature chamber as described above, the acceleration environment is constantly provided to the semiconductor device under test (dut). can

Meanwhile, according to a modified example of the present invention, since the high-temperature chamber has a relatively higher height than the low-temperature chamber, as described above, the high-temperature environment is provided to the at least one semiconductor device under test (dut). It goes without saying that the time to lower the temperature later, that is, after the end of the test, can be shortened compared to the low-temperature chamber.

In the above, modified examples of the present invention have been described.

Hereinafter, a method for testing a semiconductor device in an accelerated environment according to an embodiment of the present invention will be described with reference to the drawings.

In the method for testing a semiconductor device in an accelerated environment described below, a description overlapping with the above-described apparatus for testing a semiconductor device providing an accelerated environment may be omitted. However, just because overlapping descriptions are omitted in the following does not exclude them, and overlapping descriptions below refer to the description of the previous embodiment.

2 to 11 are diagrams for explaining a method of testing a semiconductor device in an acceleration environment according to an embodiment of the present invention.

Referring to FIG. 2 , the method for testing a semiconductor device in the acceleration environment includes a step of mounting (S110) at least one semiconductor device under test (dut) on the test board (uut), and mounting the device on the test board (uut). Covering the chamber 10 providing the accelerated environment to the semiconductor device under test dut (S120) and providing the accelerated environment to the semiconductor device under test dut covered by the chamber 10 It may include at least one of the steps (S130).

Hereinafter, each step is explained.

Step S110

Referring to FIG. 3 , in step S110, at least one semiconductor device under test dut may be mounted on the test board uut.

Meanwhile, in this step, the test board uut on which the at least one semiconductor device under test dut is mounted may be disposed on the stage 30 .

In this step, when a plurality (uut1 to uut4) of the test boards (uut) on which the at least one semiconductor device under test (dut) is mounted are provided, the plurality of test boards (uut1 to uut4) are shown in FIG. 3 As shown in , they may be arranged side by side along the direction of the axis (ax, see FIG. 10) of the test beam (ry, see FIG. 10). Meanwhile, at this time, as described above, it is assumed that the test beam ry is fixedly irradiated in a non-moving state.

Meanwhile, in this step, the arrangement of the at least one semiconductor device under test (dut) mounted on the test board (uut) may vary according to the characteristics of the semiconductor device under test (dut). For example, referring to FIGS. 4(a) to 4(c) , the at least one semiconductor device under test dut may be arranged in a circular shape on the test board uut (FIG. 4( a)), may be arranged in one column (see FIG. 4 (b)), or may be arranged to have a plurality of rows and columns (see FIG. 4 (c)). However, the arrangement of the semiconductor device under test (dut) is not limited to the above-described embodiment, and as described above, according to the characteristics of the semiconductor device under test (dut), the test board (uut) is mounted Of course, the arrangement may vary.

Accordingly, the shape of the chamber 10 may be different in a step to be described later. This will be described later in detail with reference to FIG. 6 .

Step S120

Referring to FIG. 5 , in step S120 , the chamber 10 providing an acceleration environment to the semiconductor device under test dut mounted on the test board uut may be covered.

Accordingly, the chamber 10 may cover at least one semiconductor device under test (dut) mounted on the test board (uut) to provide the covered semiconductor device under test (dut) with the acceleration environment. Of course there is. Meanwhile, as described above, the accelerating environment herein may be understood as a concept including a high-temperature environment higher than room temperature. More specifically, the high-temperature environment herein may be understood as a concept including a high temperature of 180 °C or higher and 200 °C or lower.

To this end, the chamber 10, as described above with reference to FIG. 1, includes at least one of the chamber body 11, the chamber window 12, the heater 13, and the temperature sensor 14. It goes without saying that either one may be included. Regarding the overlapping description of the chamber 10, reference will be made to the description of the previous embodiment.

Meanwhile, in the above-described step, when the plurality of test boards uut1 to uut4 are arranged side by side along the direction of the axis (ax, see FIG. 10) of the test beam (ry, see FIG. 10), in this step As shown in FIG. 5, the chamber 10 is provided in a plurality (10a to 10d), and the plurality of chambers 10a to 10d are arranged side by side along the axial direction of the test beam to be fixedly irradiated. Of course you can.

Meanwhile, referring to FIGS. 6 (a) to 6 (f) , in the previous step S110, the at least one semiconductor device under test (dut) is subjected to the test according to the characteristics of the semiconductor device under test (dut). When the mounting arrangement on the board uut is different, the shape of the chamber 10 covering the semiconductor device under test dut may be different in step S120.

For example, as shown in FIG. 6 (a), when the at least one semiconductor device under test (dut) is arranged in a circular shape on the test board (uut), the chamber 10 is formed in FIG. 6 ( As shown in d), it may be provided in a circular shape according to the arrangement of the at least one semiconductor device under test (dut).

More specifically, as shown in FIG. 6 (d) , the chamber body 11 may be provided in a cylindrical shape and the chamber window 12 may be provided in a circular or donut shape.

For another example, as shown in FIG. 6 (b) , when the at least one semiconductor device under test (dut) is arranged in a row on the test board (uut), the chamber 10 may be configured in FIG. 6 As shown in (e), according to the arrangement of the at least one semiconductor device under test (dut), a rectangular shape having a long length in the one column direction may be provided.

More specifically, as shown in FIG. 6 (e), the chamber body 11 may be provided in a rectangular pillar shape having a long length in the one column direction, and the chamber window 12 may be It may be provided in a rectangular shape having a long length in the column direction.

For another example, as shown in FIG. 6 (c), when the at least one semiconductor device under test (dut) is arranged to have a plurality of rows and columns on the test board (uut), the chamber ( 10), as shown in FIG. 6(f), may be provided in a rectangular shape having a long length in the plurality of row and column directions according to the arrangement of the at least one semiconductor device under test (dut).

More specifically, as shown in FIG. 6 (f), the chamber body 11 may be provided in a rectangular pillar shape having a long length in the plurality of row and column directions, and the chamber window 12 is , It may be provided in a rectangular shape having a long length in the plurality of row and column directions.

However, the shape of the chamber 10 is not limited to the above-described embodiment, and may vary according to the arrangement of the semiconductor device under test (dut).

Step S130

In step S130 , the acceleration environment may be provided to the semiconductor device under test dut covered by the chamber 10 .

To this end, in this step, as shown in FIG. 7, as the plurality of chambers 10a to 10d move away from the test beam ry, the high-temperature environment provided to the semiconductor device under test dut Controlling the temperature to increase (S131), and controlling the test board uut on which the semiconductor device under test dut is mounted to be moved toward the axis ax of the test beam ry that is fixedly irradiated. It may include at least one of the steps (S132).

Steps S131 and S132 are described below.

Step S131

Referring to FIG. 8 , in step S131, the temperature of the high-temperature environment provided to the semiconductor device under test (dut) increases as the plurality of chambers 10a to 10d move away from the test beam ry. can be controlled Here, according to an embodiment, the control may be performed by a control unit (not shown) connected to the chamber 10, and in this case, the control includes automatic control by the control unit (not shown). can be understood as Alternatively, according to an embodiment, the control may be performed by a user using the chamber 10, and in this case, the control may be understood as a concept including manual control by the user.

On the other hand, in this step, the temperature of the high-temperature environment provided to the semiconductor device under test (dut) is controlled to increase as the plurality of chambers 10a to 10d move away from the test beam ry, as described above. This may be because the dose of the test beam ry was considered as described. Regarding this, since it overlaps with the description of the previous embodiment, reference will be made to the description of the previous embodiment.

Accordingly, according to the present invention, even when the dose of the test beam ry reaching the chamber 10d distant from the test beam ry is relatively smaller than the chamber 10a adjacent to the test beam ry. , The acceleration environment can be constantly provided to the semiconductor device under test (dut) by controlling the temperature of the high-temperature environment to be high so as to correspond to the small dose.

Accordingly, according to the present invention, reliability can be improved in the inspection of the semiconductor device under test (dut).

Step S132

9 and 10, in step S132, the test board uut on which the semiconductor device under test dut is mounted is moved toward the axis ax of the test beam ry to be fixedly irradiated. can be controlled Here, the control can also be understood as a concept including at least one of the above-described automatic control and manual control.

Accordingly, according to the present invention, the test beam ry may be uniformly irradiated to the at least one semiconductor device under test dut mounted on the test board uut. Here, uniform irradiation of the test beam ry may mean that a dose reaching the at least one semiconductor device under test dut is uniform. Regarding this, since it overlaps with the description of the previous embodiment, reference will be made to the description of the previous embodiment.

Therefore, according to the present invention, reliability can be improved in the inspection of the semiconductor device under test (dut).

In the above, the method for testing a semiconductor device in an acceleration environment according to an embodiment of the present invention has been described.

Hereinafter, experimental examples of the present invention are described.

12 (a) to 13 (b) are diagrams for explaining an experimental example of the present invention.

12 (a) shows six first to sixth semiconductor devices dut1 to dut6 mounted on a test board uut through one chamber 10 manufactured according to an experimental example of the present invention. In this case, data (ex1) showing the temperatures measured in the six semiconductor devices under test (dut1 to dut6), and FIG. 12 (b) shows a test board (uut) through one chamber manufactured according to the comparative example. When the six first to sixth semiconductor devices under test (dut1 to dut6) mounted on are covered, this is data cp1 representing temperatures measured at the six semiconductor devices under test (dut1 to dut6).

Referring to FIG. 12 (a), in the experimental example (ex1) of the present invention, it can be observed that the temperature of the first semiconductor device under test dut1 and the sixth semiconductor device under test dut6 are 77.04 °C. there is.

In addition, referring to FIG. 12 (a), in the experimental example (ex1) of the present invention, it can be observed that the temperature difference between the second semiconductor device under test dut2 and the fourth semiconductor device under test dut4 is 0.01 °C. can

Meanwhile, referring to FIG. 12 (b), unlike the experimental example of the present invention, in the comparative example (cp1), the first to sixth semiconductor devices dut1 to dut6 have a temperature deviation of at most 7.13 ° C. that can be observed

Accordingly, the semiconductor device test apparatus 100 providing an accelerated environment according to the experimental example of the present invention provides a high-temperature environment higher than room temperature to the semiconductor devices under test dut1 to dut6, but sets the provided high-temperature environment to 0 ° C or higher. to 0.01 ° C or less.

13 (a) is a case where three test boards (uut1 to uut3) equipped with at least one semiconductor under test (dut) are covered through a plurality of chambers 10 manufactured according to an experimental example of the present invention. , data (ex2) showing temperatures measured on the three test boards (uut1 to uut3), and FIG. 13 (b) shows at least one of the semiconductors under test (dut ) covers the three test boards (uut1 to uut3), the data (cp2) represents the temperature measured on the three test boards (uut1 to uut3).

Referring to FIG. 13 (a), in the experimental example (ex2) of the present invention, it can be observed that the average temperature deviation of the three test boards uut1 to uut3 is 1.64 °C.

Meanwhile, referring to FIG. 13 (b), unlike the experimental example of the present invention, in the comparative example (cp2), it can be observed that the average temperature deviation of the three test boards uut1 to uut3 is 2.41 ° C. .

Accordingly, the semiconductor device test apparatus 100 providing an accelerated environment according to the experimental example of the present invention provides a high-temperature environment higher than room temperature to the semiconductor devices under test dut1 to dut6, but the temperature difference between the test boards uut. It is also proven that it can be minimized.

In the above, the present invention has been described in detail using preferred embodiments, but the scope of the present invention is not limited to specific embodiments, and should be interpreted according to the appended claims. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

10: chamber
11: chamber body
12: chamber window
13: heater
14: temperature sensor
30: stage
100: Semiconductor device test device providing acceleration environment

Claims (7)

A chamber covering at least one semiconductor device under test mounted on a test board and providing an acceleration environment to the covered semiconductor device under test;
The accelerated environment provided by the chamber includes a high-temperature environment higher than room temperature,
the chamber,
a chamber body covering the semiconductor device under test and a chamber window through which a test beam is transmitted to a region where the semiconductor device under test is mounted;
The chamber body,
A semiconductor device test apparatus for providing an acceleration environment formed of a non-metallic material that does not generate secondary particles from the test beam.
A chamber covering at least one semiconductor device under test mounted on a test board and providing an acceleration environment to the covered semiconductor device under test;
The accelerated environment provided by the chamber includes a high-temperature environment higher than room temperature,
the chamber,
a chamber body covering the semiconductor device under test, and a heater providing the high-temperature environment to the semiconductor device under test covered by the chamber body;
The chamber body,
A semiconductor device test apparatus providing an accelerated environment, wherein the high-temperature environment provided to the semiconductor device under test covered by the chamber body is maintained at a temperature deviation of 0 ° C. or more and 0.01 ° C. or less.
A chamber covering at least one semiconductor device under test mounted on a test board and providing an acceleration environment to the covered semiconductor device under test;
The accelerated environment provided by the chamber includes a high-temperature environment higher than room temperature,
The chamber is provided in plurality,
The plurality of chambers provided,
Arranged side by side along the axial direction of the test beam to be fixedly irradiated,
A semiconductor device test apparatus providing an accelerated environment, wherein the dose of the test beam is controlled so that the temperature of the high-temperature environment provided to the semiconductor device under test increases as the distance from the test beam increases.
A chamber covering at least one semiconductor device under test mounted on the test board and providing an acceleration environment to the covered semiconductor device under test,
The accelerated environment provided by the chamber includes a high-temperature environment higher than room temperature,
Further comprising a stage for moving the test board on which the semiconductor device under test is mounted toward the axis of the test beam to be fixedly irradiated,
The test beam is fixedly irradiated to form a fixed irradiation area to which the test beam reaches;
The stage completely passes the test board on which the semiconductor device under test is mounted, which is defined as passing in a direction from one outer side of the fixed irradiation area, through the fixed irradiation area, and to the other outer side of the fixed irradiation area. and reaching the test beam to the at least one semiconductor device under test mounted on the test board.
mounting at least one semiconductor device under test on a test board;
covering a chamber providing an acceleration environment to the semiconductor device under test mounted on the test board; and
Providing an acceleration environment to the semiconductor device under test covered by the chamber;
In the step of providing the acceleration environment,
Providing a high-temperature environment higher than room temperature to the semiconductor device under test, maintaining the provided high-temperature environment at a temperature deviation of 0 ° C. or more and 0.01 ° C. or less,
the chamber,
a chamber body covering the semiconductor device under test and a chamber window through which a test beam is transmitted to a region where the semiconductor device under test is mounted;
The chamber body,
From the test beam, a method for testing a semiconductor device in an accelerated environment, including being formed of a non-metallic material that does not generate secondary particles.
mounting at least one semiconductor device under test on a test board;
covering a chamber providing an acceleration environment to the semiconductor device under test mounted on the test board; and
Providing an acceleration environment to the semiconductor device under test covered by the chamber;
In the step of providing the acceleration environment,
Providing a high-temperature environment higher than room temperature to the semiconductor device under test, maintaining the provided high-temperature environment at a temperature deviation of 0 ° C. or more and 0.01 ° C. or less,
The chamber is provided in plurality,
The plurality of chambers provided,
Arranged side by side along the axial direction of the test beam to be fixedly irradiated,
In the step of providing the acceleration environment,
controlling the temperature of the high-temperature environment provided to the semiconductor device under test to increase as the plurality of chambers move away from the test beam, in consideration of the dose of the test beam; and
and controlling the test board on which the semiconductor device under test is mounted to be moved toward the axis of the test beam to be fixedly irradiated.
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