JPH0513524A - Method for inspecting semiconductor element - Google Patents

Method for inspecting semiconductor element

Info

Publication number
JPH0513524A
JPH0513524A JP1535691A JP1535691A JPH0513524A JP H0513524 A JPH0513524 A JP H0513524A JP 1535691 A JP1535691 A JP 1535691A JP 1535691 A JP1535691 A JP 1535691A JP H0513524 A JPH0513524 A JP H0513524A
Authority
JP
Japan
Prior art keywords
semiconductor
tray
wafer
probe
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1535691A
Other languages
Japanese (ja)
Other versions
JP2913344B2 (en
Inventor
Yuichi Abe
祐一 阿部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP1535691A priority Critical patent/JP2913344B2/en
Publication of JPH0513524A publication Critical patent/JPH0513524A/en
Application granted granted Critical
Publication of JP2913344B2 publication Critical patent/JP2913344B2/en
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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To provide a semiconductor element inspecting method which can easily and efficiently perform environmental tests on a semiconductor element while the element is maintained in the state of a semiconductor wafer. CONSTITUTION:An inspecting jig 1 is provided with a tray 3 for supporting a semiconductor wafer 2 on which a large number of semiconductor elements (semiconductor chips) are formed. On the tray 3, a lid body 5 on which probes 4 are arranged in corresponding to the electrode pads of all semiconductor elements formed on the wafer 2. An electrode terminal 6 on which electrode terminals electrically connected to each probe 4 are arranged is provided at a prescribed part, for example, on the side of the lid body 5. The lid body 5 is provided with spacers 7 and clamping mechanisms 8. The tray 3 is carried into an oven for environmental tests, with the lid body 5 being fixed to the tray 3 by means of the clamping mechanisms 8.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[発明の目的][Object of the Invention]

【0002】[0002]

【産業上の利用分野】本発明は、半導体素子の検査方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device inspection method.

【0003】[0003]

【従来の技術】一般に、半導体素子は、精密写真転写技
術等により半導体ウエハ上に同時に多数形成され、この
後、スクライブラインに沿って各半導体素子(半導体チ
ップ)に切断される。
2. Description of the Related Art Generally, a large number of semiconductor elements are simultaneously formed on a semiconductor wafer by a precision photo transfer technique or the like, and then cut into semiconductor elements (semiconductor chips) along scribe lines.

【0004】このような半導体素子の製造工程において
は、従来からいわゆるウエハプローバおよびテスタを用
いた半導体ウエハの状態(切断前)における半導体素子
の電気的特性の検査や、いわゆるハンドラおよびテスタ
を用いたパッケージ後の半導体素子の電気的特性の検査
等が行われている。
In the manufacturing process of such a semiconductor element, conventionally, a so-called wafer prober and a tester have been used to inspect the electrical characteristics of the semiconductor element in a state of a semiconductor wafer (before cutting), and a so-called handler and tester are used. Inspection of electrical characteristics of semiconductor elements after packaging is performed.

【0005】また、例えば高温環境あるいは低温環境下
で長時間(例えば数十時間)に亘って電気的特性の変化
を検査する環境試験は、例えば多数のICソケットを配
列したトレー等を用いて、ソケットにICの端子を挿入
してパッケージ後の半導体素子についてのみ行われてい
る。これは、上述の如く環境試験は長時間を要するた
め、ウエハプローバ等を用いてチップに切断前の半導体
ウエハの状態で環境試験を行うことが、スループットの
点で現実的に不可能なためである。すなわち、パッケー
ジ後の半導体素子の環境試験を行う場合、上述したトレ
ー等を用いて数千ないし数万個の半導体素子について同
時に環境試験を行うが、従来のウエハプローバを用いて
半導体ウエハの状態で環境試験を行うと一台のウエハプ
ローバで一枚の半導体ウエハ(例えば数十ないし百数十
個の半導体素子が形成されている)の環境試験を行うた
めに例えば数十時間必要となり、上記数の半導体素子の
同時に行うためには、数十ないし数百台のウエハプロー
バが必要となり現実的には困難となるためである。
In addition, for example, in an environmental test for inspecting a change in electrical characteristics for a long time (for example, several tens of hours) under a high temperature environment or a low temperature environment, for example, using a tray having a large number of IC sockets arranged, This is done only for the semiconductor element after the IC terminal is inserted into the socket and packaged. This is because the environmental test requires a long time as described above, and therefore it is practically impossible to perform the environmental test in the state of the semiconductor wafer before cutting into chips using a wafer prober or the like in terms of throughput. is there. That is, when performing an environmental test on a semiconductor device after packaging, the environmental test is performed on several thousand to tens of thousands of semiconductor devices at the same time using the above-mentioned tray, etc. When an environmental test is performed, it takes, for example, several tens of hours to perform an environmental test on one semiconductor wafer (for example, several tens to hundreds of semiconductor elements are formed) with one wafer prober. This is because, in order to simultaneously perform the above semiconductor device, several tens to several hundreds of wafer probers are required, which is difficult in reality.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、周知の
如く近年は例えば半導体素子(チップ)をパッケージン
グせずに基板に直接貼り付ける等の実装方法(例えばT
AB等)が開発されており、このような場合半導体素子
がパッケージ状態にならないので、ソケットに挿入可能
な端子が用いられず上述したような環境試験ができない
という問題が発生している。また、例えば基板上に半導
体素子(半導体チップ)を実装してから環境試験を行う
と、不良になった場合、半導体素子のみの交換が容易に
できないため、基板全体が不良になり、製造コストの観
点から好ましくない。
However, as is well known, in recent years, for example, a mounting method such as directly attaching a semiconductor element (chip) to a substrate without packaging (eg, T
(AB, etc.) has been developed, and in such a case, since the semiconductor element is not packaged, terminals that can be inserted into the sockets are not used and the above-described environmental test cannot be performed. In addition, for example, when a semiconductor element (semiconductor chip) is mounted on a substrate and then an environmental test is performed, if the semiconductor element fails, it is not possible to easily replace only the semiconductor element, resulting in failure of the entire substrate, resulting in a reduction in manufacturing cost. It is not preferable from the viewpoint.

【0007】本発明は、かかる従来の事情に対処してな
されたもので、半導体ウエハの状態での半導体素子の環
境試験を容易に、かつ、効率的に実施することのできる
半導体素子の検査方法を提供しようとするものである。
The present invention has been made in response to such a conventional situation, and a method of inspecting a semiconductor element capable of easily and efficiently performing an environmental test of a semiconductor element in a state of a semiconductor wafer. Is to provide.

【0008】[発明の構成][Structure of Invention]

【0009】[0009]

【課題を解決するための手段】すなわち、本発明の半導
体素子の検査方法は、半導体ウエハが設けられるウエハ
支持体と、前記半導体ウエハ上に形成された複数の半導
体素子の各電極パッドに対応した探針を配置された蓋体
と、前記探針と電気的測定装置との電気的接続を行うた
めの電極ターミナルとを具備した検査用治具を用い、前
記ウエハ支持体上に設けられた前記半導体ウエハの前記
各電極パッドと、前記探針とが接触する如く、前記蓋体
を前記支持体上に固定し、この状態で前記検査用治具を
所定の検査環境下に配置し、前記電極ターミナルおよび
前記探針を介して前記半導体素子の電気的特性の測定を
行うことを特徴とする半導体素子の検査方法。
That is, a method of inspecting a semiconductor device according to the present invention corresponds to a wafer support on which a semiconductor wafer is provided and electrode pads of a plurality of semiconductor devices formed on the semiconductor wafer. The inspection jig provided with a lid in which a probe is arranged and an electrode terminal for electrically connecting the probe and an electrical measuring device is used, and the inspection jig provided on the wafer support is used. The lid is fixed on the support so that each of the electrode pads of the semiconductor wafer and the probe come into contact with each other, and in this state, the inspection jig is placed under a predetermined inspection environment to A method of inspecting a semiconductor device, characterized in that electrical characteristics of the semiconductor device are measured through a terminal and the probe.

【0010】[0010]

【作 用】上記構成の本発明の半導体素子の検査方法で
は、従来実施することのできなかった半導体ウエハの状
態での半導体素子の環境試験を容易に、かつ、効率的に
実施することができる。
[Operation] According to the semiconductor element inspection method of the present invention having the above-described structure, it is possible to easily and efficiently carry out the environmental test of the semiconductor element in the state of the semiconductor wafer, which could not be conventionally performed. ..

【0011】[0011]

【実施例】以下、本発明の一実施例を図面を参照して説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0012】図1に示すように検査用治具1は、被検査
体である半導体素子(半導体チップ)を多数形成された
半導体ウエハ2を支持するための支持体として、例えば
矩形板状に形成されたトレイ3を備えており、半導体ウ
エハ2は、このトレイ3上の所定位置に載置されるよう
構成されている。
As shown in FIG. 1, the inspection jig 1 is formed in a rectangular plate shape, for example, as a support for supporting a semiconductor wafer 2 on which a large number of semiconductor elements (semiconductor chips) to be inspected are formed. The semiconductor wafer 2 is configured to be placed at a predetermined position on the tray 3.

【0013】また、このトレイ3上には、トレイ3とほ
ぼ同じ大きさに形成された板状体からなり、半導体ウエ
ハ2に形成された全ての半導体素子の電極パッドに対応
してプローブ(探針)4が配列された蓋体5がトレイ3
上を覆う如く配置される。この蓋体5の所定部位、例え
ば側方には、各プローブ4と電気的に接続された電極端
子が配列された電極ターミナル6が設けられており、こ
の電極ターミナル6を介して外部の電気的測定装置(例
えば後述するテスタ)と各プローブ4との電気的な接続
を実施するよう構成されている。
Further, on the tray 3, a plate-like member having a size substantially the same as that of the tray 3 is formed, and probes (search probes) corresponding to the electrode pads of all the semiconductor elements formed on the semiconductor wafer 2 are formed. The lid 5 on which the needles 4 are arranged is the tray 3
It is placed so as to cover the top. An electrode terminal 6 in which electrode terminals electrically connected to the respective probes 4 are arranged is provided at a predetermined portion of the lid body 5, for example, on a lateral side, and an external electrical terminal is provided through the electrode terminal 6. The measuring device (for example, a tester described later) and each probe 4 are electrically connected.

【0014】さらに、この蓋体5には、スペーサ7およ
び図示しないスプリングの作用により支点8aを中心と
して図示矢印の如く回動自在に構成されトレイ3を弾性
的に保持するクランプ機構8が設けられている。そし
て、スペーサ7によって蓋体5とトレイ3との間隔が所
定間隔以下にならないように保持するとともに、クラン
プ機構8によって蓋体5とトレイ3とが着脱自在に一体
的に所定圧力で保持される如く構成されている。
Further, the lid 5 is provided with a clamp mechanism 8 which is configured to be rotatable around a fulcrum 8a as shown by an arrow in the figure by the action of a spacer 7 and a spring (not shown) and which elastically holds the tray 3. ing. The spacer 7 holds the lid 5 and the tray 3 so that the distance between them does not become less than a predetermined distance, and the clamp mechanism 8 detachably holds the lid 5 and the tray 3 integrally at a predetermined pressure. It is configured as follows.

【0015】すなわち、従来例えばプローブ装置等によ
り検査を実施する際には、針先高さのばらつき等がある
ため、探針の針先と電極パッドとが接触した位置から一
定距離、一定圧力で探針と電極パッドとを押圧するいわ
ゆるオーバードライブをかけて、探針と電極パッドとを
確実に電気的に接触させる。本実施例においては、クラ
ンプ機構8によって押圧することによりオーバードライ
ブをかけ、スペーサ7によりこのオーバードライブ量を
制限することにより、上記オーバードライブをかけた状
態と同様な状態で各プローブ4と半導体ウエハ2の電極
パッドとの接触が行われるよう構成されている。
That is, when performing an inspection with a probe device or the like in the related art, there is a variation in the height of the needle tip, so that there is a certain distance and a certain pressure from the position where the needle tip of the probe contacts the electrode pad. By applying so-called overdrive that presses the probe and the electrode pad, the probe and the electrode pad are surely brought into electrical contact with each other. In this embodiment, by pressing the clamp mechanism 8 to overdrive and limiting the amount of overdrive by the spacer 7, each probe 4 and the semiconductor wafer are in the same state as in the above overdriving state. It is configured to make contact with the second electrode pad.

【0016】なお、これらのスペーサ7およびクランプ
機構8は各種の変形が可能であり、例えばこれらを蓋体
5側でなくトレイ3側に設けたり、蓋体5およびトレイ
3とは別体に構成したりすることもできる。また、固定
方法は、例えば機械的なクランプ機構、ねじによる固定
機構等あらゆるものを使用することができる。但し、蓋
体5とトレイ3とを正確に位置決めした状態で固定する
必要があることから、固定前に蓋体5とトレイ3との相
対位置をある程度移動させることのできる自由度を有
し、かつ、固定した後はこれらの相対位置が動かないよ
うにすることのできるものでなければならない。また、
本実施例では、半導体ウエハ2に形成された全ての半導
体素子の電気的な検査を実施するため、半導体ウエハ2
に形成された全ての半導体素子の電極パッドに対応した
プローブ4を有する蓋体5を用いるが、例えば半導体ウ
エハ2上の一部の半導体素子の電気的な検査を行えばよ
い場合は、検査を実施する半導体素子に対してのみプロ
ーブ4を設けられたものを用いてもよい。
The spacer 7 and the clamp mechanism 8 can be modified in various ways. For example, they are provided not on the lid 5 side but on the tray 3 side, or are constructed separately from the lid 5 and tray 3. You can also do it. Further, as the fixing method, for example, a mechanical clamp mechanism, a screw fixing mechanism, or the like can be used. However, since it is necessary to fix the lid body 5 and the tray 3 in a state where they are accurately positioned, there is a degree of freedom that the relative position between the lid body 5 and the tray 3 can be moved to some extent before fixing. And, after being fixed, these relative positions must be immovable. Also,
In the present embodiment, all the semiconductor elements formed on the semiconductor wafer 2 are electrically inspected.
The lid 5 having the probes 4 corresponding to the electrode pads of all the semiconductor elements formed on the substrate is used. However, for example, when some semiconductor elements on the semiconductor wafer 2 may be electrically inspected, the inspection is performed. You may use what provided the probe 4 only with respect to the semiconductor element to implement.

【0017】上記トレイ3と蓋体5は、蓋体5に設けら
れた各プローブ4が確実に半導体ウエハ2上の各電極パ
ッドに接触するよう正確に位置決めされた状態で当接さ
れ、クランプ機構8によって固定された状態で搬送さ
れ、例えばオーブン等に収容されて環境試験が実施され
る。
The tray 3 and the lid 5 are brought into contact with each other in a state where each probe 4 provided on the lid 5 is accurately positioned so as to surely come into contact with each electrode pad on the semiconductor wafer 2, and a clamp mechanism is provided. It is conveyed in a state of being fixed by 8, and accommodated in, for example, an oven or the like, and an environmental test is performed.

【0018】図2は、上記検査用治具1を用いて自動的
に半導体ウエハ2の半導体素子の電気的な検査を実施す
る自動検査装置の構成を示すものである。同図に示すよ
うに自動検査装置10は、それぞれ半導体ウエハ2、ト
レイ3、蓋体5を、例えば棚状に複数収容するウエハ収
容部11、トレイ収容部12、蓋体収容部13を備えて
おり、これらの各収容部には、各収容部へ半導体ウエハ
2、トレイ3、蓋体5を搬入・搬出するためのウエハ搬
送機構14、トレイ搬送機構15、蓋体搬送機構16が
それぞれ設けられている。
FIG. 2 shows the construction of an automatic inspection apparatus for automatically performing an electrical inspection of semiconductor elements on a semiconductor wafer 2 using the inspection jig 1. As shown in the figure, the automatic inspection device 10 includes a wafer housing portion 11, a tray housing portion 12, and a lid housing portion 13, which each house a plurality of semiconductor wafers 2, trays 3, and lid bodies 5, for example, in a shelf shape. Each of these accommodating parts is provided with a wafer transfer mechanism 14, a tray transfer mechanism 15, and a lid transfer mechanism 16 for loading and unloading the semiconductor wafer 2, the tray 3, and the lid 5 into and from the respective accommodating parts. ing.

【0019】また上記各搬送機構の側方には、トレイ3
等を複数順次搬送可能な搬送機構として例えばベルト搬
送機構17が設けられており、このベルト搬送機構17
の搬送路に沿って、例えば画像解析等により半導体ウエ
ハ2および蓋体5等の位置認識を行う位置認識部18
と、トレイ3と蓋体5の組立を実施するクランプ組立機
構部19と、組立られたトレイ3と蓋体5および半導体
ウエハ2(組立体)を搬送する組立体搬送機構20と、
この組立体を多数例えば棚状に収容可能に構成され、内
部を所定の環境、例えば所定の温度に保持可能に構成さ
れた環境試験用のオーブン21とが設けられている。
A tray 3 is provided on the side of each of the above-mentioned transfer mechanisms.
For example, a belt transport mechanism 17 is provided as a transport mechanism capable of sequentially transporting a plurality of the like.
A position recognizing unit 18 for recognizing the positions of the semiconductor wafer 2 and the lid 5 and the like along the transport path of, for example, image analysis or the like.
A clamp assembly mechanism section 19 for assembling the tray 3 and the lid body 5; and an assembly transport mechanism 20 for transporting the assembled tray 3, lid body 5 and semiconductor wafer 2 (assembly).
A large number of this assembly can be housed, for example, in the shape of a shelf, and an oven 21 for an environmental test is provided, which is capable of maintaining the inside thereof in a predetermined environment, for example, a predetermined temperature.

【0020】上記構成の自動検査装置10では、まず、
トレイ搬送機構15によって、トレイ収容部12内のト
レイ3を取り出し、このトレイ3をベルト搬送機構17
上の所定位置に載置する。
In the automatic inspection apparatus 10 having the above structure, first,
The tray 3 is taken out from the tray accommodating section 12 by the tray transfer mechanism 15, and the tray 3 is transferred to the belt transfer mechanism 17.
Place it in the specified position above.

【0021】次に、ウエハ搬送機構14によって、ウエ
ハ収容部11内の半導体ウエハ2を取り出し、例えば半
導体ウエハ2のオリエンテーションフラットの位置を検
出すること等による粗位置決めを実施して、この半導体
ウエハ2をトレイ3上の所定位置に載置する。
Next, the semiconductor wafer 2 in the wafer housing 11 is taken out by the wafer transfer mechanism 14 and rough positioning is performed by, for example, detecting the position of the orientation flat of the semiconductor wafer 2, and the semiconductor wafer 2 Is placed at a predetermined position on the tray 3.

【0022】この後、例えばCCDカメラ等で撮像する
ことにより、位置認識部18でこのトレイ3上の半導体
ウエハ2(電極パッド)の正確な位置を認識し、この後
ベルト搬送機構17を所定距離移動させてこのトレイ3
および半導体ウエハ2をクランプ組立機構部19に搬送
する。
Thereafter, the position recognizing section 18 recognizes the accurate position of the semiconductor wafer 2 (electrode pad) on the tray 3 by taking an image with a CCD camera or the like, and then the belt conveying mechanism 17 is moved to a predetermined distance. Move this tray 3
Then, the semiconductor wafer 2 is transferred to the clamp assembly mechanism section 19.

【0023】また、上記動作と同時に、蓋体搬送機構1
6によって蓋体収容部13内の蓋体5を取り出し、同様
に位置認識部18でこの蓋体5(プローブ4)の正確な
位置を認識し、この後、この蓋体5をクランプ組立機構
部19に搬送する。
At the same time as the above operation, the lid transport mechanism 1
The lid body 5 in the lid body accommodating portion 13 is taken out by 6, and the position recognizing portion 18 similarly recognizes the accurate position of the lid body 5 (probe 4). Transport to 19.

【0024】そして、上記位置認識結果に基づき、クラ
ンプ組立機構部19において、半導体ウエハ2上の各電
極パッドにプローブ4が正確に接触するよう、蓋体5を
トレイ3上に配置し、蓋体5のクランプ機構8をトレイ
3に掛けて、間に半導体ウエハ2を挟んだ状態で蓋体5
とトレイ3とを固定する。
Based on the position recognition result, the lid assembly 5 is placed on the tray 3 in the clamp assembly mechanism section 19 so that the probe 4 can accurately contact each electrode pad on the semiconductor wafer 2, The clamp mechanism 8 of No. 5 is hung on the tray 3 and the semiconductor wafer 2 is sandwiched between
And Tray 3 are fixed.

【0025】しかる後、ベルト搬送機構17を所定距離
移動させてこの蓋体5、トレイ3、半導体ウエハ2から
なる組立体をクランプ組立機構部19から搬出し、組立
体搬送機構20によってこの組立体をオーブン21内に
配置する。オーブン21は、複数例えば数十個の組立体
を棚状に収容できるように構成されており、このオーブ
ン21は複数配置されている。また、オーブン21内に
は、蓋体5に設けられた電極ターミナル6に対応して図
示しない電気的接続機構が設けられており、この電気的
接続機構、電極ターミナル6およびプローブ4を介して
テスタ22と半導体ウエハ2に形成された半導体素子の
電極パッドとが電気的に接続されるよう構成されてい
る。
Thereafter, the belt transfer mechanism 17 is moved by a predetermined distance, the assembly including the lid 5, the tray 3 and the semiconductor wafer 2 is carried out from the clamp assembly mechanism section 19, and the assembly transfer mechanism 20 carries out the assembly. Is placed in the oven 21. The oven 21 is configured so that a plurality of, for example, dozens of assemblies can be housed in a shelf shape, and a plurality of the ovens 21 are arranged. In addition, an electric connection mechanism (not shown) is provided inside the oven 21 corresponding to the electrode terminal 6 provided on the lid 5, and the tester is connected via this electric connection mechanism, the electrode terminal 6 and the probe 4. 22 and the electrode pad of the semiconductor element formed on the semiconductor wafer 2 are electrically connected.

【0026】そして、各オーブン21内に所定数の組立
体が配置されると、このオーブン21の図示しない開閉
機構が閉められ、内部が所定の環境例えば所定温度に設
定され、テスタ22によって各半導体ウエハ2の各半導
体素子の電気的な検査が順次実施される。
When a predetermined number of assemblies are arranged in each oven 21, the opening / closing mechanism (not shown) of the oven 21 is closed, the inside is set to a predetermined environment, for example, a predetermined temperature, and each semiconductor is set by the tester 22. Electrical inspection of each semiconductor element of the wafer 2 is sequentially performed.

【0027】このように、本実施例によれば、従来実質
的に行うことのできなかった半導体ウエハ2の状態での
各半導体素子の環境試験を容易に、かつ、効率的に実施
することができる。したがって、例えばTAB等によ
り、切断した後の半導体素子をパッケージングせずに直
接基板上に実装するような場合でも、基板上に実装する
前に各半導体素子の環境試験を行うことができ、従来に
較べて生産効率の向上を図ることができる。
As described above, according to this embodiment, it is possible to easily and efficiently carry out an environmental test on each semiconductor element in the state of the semiconductor wafer 2, which could not be practically performed conventionally. it can. Therefore, for example, even when the semiconductor element after cutting is directly mounted on the substrate by TAB or the like without packaging, the environmental test of each semiconductor element can be performed before mounting on the substrate. It is possible to improve the production efficiency compared to.

【0028】[0028]

【発明の効果】以上説明したように、本発明の半導体素
子の検査方法によれば、半導体ウエハの状態での半導体
素子の環境試験を容易に、かつ、効率的に実施すること
ができる。
As described above, according to the semiconductor element inspection method of the present invention, the environmental test of the semiconductor element in the state of the semiconductor wafer can be carried out easily and efficiently.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例方法に用いる検査用治具の構
成を示す図である。
FIG. 1 is a diagram showing a configuration of an inspection jig used in a method according to an embodiment of the present invention.

【図2】本発明の一実施例方法に用いる自動検査装置の
構成を示す図である。
FIG. 2 is a diagram showing a configuration of an automatic inspection device used in a method according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 検査用治具 2 半導体ウエハ 3 トレイ 4 プローブ(探針) 5 蓋体 6 電極ターミナル 7 スペーサ 8 クランプ機構 8a 支点 1 Inspection Jig 2 Semiconductor Wafer 3 Tray 4 Probe (Probe) 5 Lid 6 Electrode Terminal 7 Spacer 8 Clamping Mechanism 8a Support Point

Claims (1)

【特許請求の範囲】 【請求項1】 半導体ウエハが設けられるウエハ支持体
と、前記半導体ウエハ上に形成された複数の半導体素子
の各電極パッドに対応した探針を配置された蓋体と、前
記探針と電気的測定装置との電気的接続を行うための電
極ターミナルとを具備した検査用治具を用い、前記ウエ
ハ支持体上に設けられた前記半導体ウエハの前記各電極
パッドと、前記探針とが接触する如く、前記蓋体を前記
支持体上に固定し、この状態で前記検査用治具を所定の
検査環境下に配置し、前記電極ターミナルおよび前記探
針を介して前記半導体素子の電気的特性の測定を行うこ
とを特徴とする半導体素子の検査方法。
Claim: What is claimed is: 1. A wafer support on which a semiconductor wafer is provided, and a lid on which a probe corresponding to each electrode pad of a plurality of semiconductor elements formed on the semiconductor wafer is arranged. Using each of the electrode pads of the semiconductor wafer provided on the wafer support, using an inspection jig including an electrode terminal for electrically connecting the probe and an electrical measuring device, The lid is fixed on the support so that the probe contacts with the probe, and the inspection jig is placed in a predetermined inspection environment in this state, and the semiconductor is provided via the electrode terminal and the probe. A method for inspecting a semiconductor device, which comprises measuring the electrical characteristics of the device.
JP1535691A 1991-02-06 1991-02-06 An inspection device and an inspection method for a semiconductor element. Expired - Lifetime JP2913344B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1535691A JP2913344B2 (en) 1991-02-06 1991-02-06 An inspection device and an inspection method for a semiconductor element.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1535691A JP2913344B2 (en) 1991-02-06 1991-02-06 An inspection device and an inspection method for a semiconductor element.

Publications (2)

Publication Number Publication Date
JPH0513524A true JPH0513524A (en) 1993-01-22
JP2913344B2 JP2913344B2 (en) 1999-06-28

Family

ID=11886524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1535691A Expired - Lifetime JP2913344B2 (en) 1991-02-06 1991-02-06 An inspection device and an inspection method for a semiconductor element.

Country Status (1)

Country Link
JP (1) JP2913344B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999268A (en) * 1996-10-18 1999-12-07 Tokyo Electron Limited Apparatus for aligning a semiconductor wafer with an inspection contactor
US6084419A (en) * 1997-02-24 2000-07-04 Tokyo Electron Limited Method and apparatus for inspecting semiconductor integrated circuits, and contactor incorporated in the apparatus
JP2008547213A (en) * 2005-06-20 2008-12-25 エプコス アクチエンゲゼルシャフト Electrical multi-layer component with reduced parasitic capacitance
JP2016162803A (en) * 2015-02-27 2016-09-05 株式会社東京精密 Prober and method for preheating probe card
JP2020148430A (en) * 2019-03-15 2020-09-17 株式会社アルバック Freezing vacuum dryer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999268A (en) * 1996-10-18 1999-12-07 Tokyo Electron Limited Apparatus for aligning a semiconductor wafer with an inspection contactor
US6084419A (en) * 1997-02-24 2000-07-04 Tokyo Electron Limited Method and apparatus for inspecting semiconductor integrated circuits, and contactor incorporated in the apparatus
JP2008547213A (en) * 2005-06-20 2008-12-25 エプコス アクチエンゲゼルシャフト Electrical multi-layer component with reduced parasitic capacitance
US8058965B2 (en) 2005-06-20 2011-11-15 Epcos Ag Electrical multilayer component with reduced parasitic capacitance
JP2016162803A (en) * 2015-02-27 2016-09-05 株式会社東京精密 Prober and method for preheating probe card
JP2020148430A (en) * 2019-03-15 2020-09-17 株式会社アルバック Freezing vacuum dryer

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