JP2003023056A - Method for sorting defect of semiconductor device, method for predicting yield of the semiconductor device, method for manufacturing the semiconductor device, defect-sorting system of semiconductor device and semiconductor device-sorting apparatus, and program used therefor and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute an accurate defect fatalness evaluation, a yield prediction and a fault position specification in an in-line defect checking step. SOLUTION: A method for sorting defects of a semiconductor device comprises steps of extracting a wiring position which becomes a fault candidate by superposing layout pattern data of a semiconductor chip with a defecting image, discriminating wirings of the extracted fault candidate according to a wiring function type, and sorting a short-circuit mode type, a disconnection mode type or the like according to a wiring fault mode type.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device (logic integrated circuit, memory integrated circuit), LCD substrate, C.
The present invention relates to a defect classification technique and a technique to which the defect classification technique is applied in an in-line inspection process for a CD substrate or the like.

[0002]

2. Description of the Related Art In recent years, in order to strengthen the market competitiveness of semiconductor products, shortening the product development period has become an essential requirement. However, it takes several tens of days from the line introduction until the electrical characteristic inspection at the time of product completion to judge whether the product is good or defective, so the procedure to wait for the result of the electrical characteristic inspection and narrow down the problematic process. Then, there was a problem that the measures were delayed.

In order to solve this problem, a method of inspecting or observing the performance of the pattern of the semiconductor wafer and the foreign matter on the wafer by an optical beam or an electron beam during the semiconductor manufacturing process has been proposed. Used (hereinafter referred to as in-line inspection). The in-line inspection information of the defect typified by the foreign matter and the pattern abnormality obtained here includes the defect size that affects the fatality of the defect, the defect occurrence position for performing a detailed analysis later, the number of defects, or There is a defect image obtained from an electron beam device or the like. In recent years, it has become possible to extract a problematic process by performing defect classification such as whether the wiring is broken or short-circuited due to the defect. On the other hand, in the case of a wafer in which many defects are found by in-line inspection, the profit may not be obtained even if the manufacturing is continued thereafter. Therefore, it is important to estimate the expected number of non-defective products (predicted yield) by in-line inspection.

[0004]

However, the following problems have not been solved by the above conventional techniques.

(1) In a memory product, which is a type of semiconductor device, a method is used in which a part of the memory that is defective and cannot perform a predetermined function is replaced with a redundant memory provided in advance. In this redundant circuit design, a relief method is defined for each defect occurrence state (defective mode). For example, "a defect between word lines can be remedied by a spare module, but if the word line and the power supply line are shorted, it cannot be remedied due to the circuit design", "a short circuit occurs between the word line and the data line. In such a case, a plurality of types of relief circuits are needed. " Therefore, there is a possibility that the accuracy of the defect fatality evaluation and the yield prediction accuracy may be deteriorated only by the physical information such as the short circuit and the disconnection of the wiring.

(2) Further, in the formation of semiconductor wiring, a polishing process called CMP (Chemical Mechanical Polishing) is introduced. In this polishing step, if the polishing condition is adjusted to a portion where the wiring patterns are not dense, there is a problem that a phenomenon called erosion occurs in which the insulating film is excessively polished in the pattern dense portion. Therefore,
By arranging the pseudo wiring (dummy pattern) that is not involved in the circuit operation function of the semiconductor in a portion where the actual wiring is not dense, the density of the wiring pattern is eliminated and the polishing defect due to the density dependence is suppressed. Such a technique has been used. In many cases, even if a short circuit occurs between the actual wiring and the dummy pattern, the circuit function of the semiconductor is hardly affected. Therefore, similar to the above (1), it is difficult to accurately evaluate the lethality of a defect and to predict the yield only by physical information such as a short circuit of wiring.

As described above, according to the conventional technique, it is difficult to accurately evaluate the lethality of defects and to predict the yield in the in-line defect inspection process. An object of the present invention is to provide a defect classification method for solving this problem, and a yield prediction method and a manufacturing method to which the method is applied.

[0008]

In order to achieve the above-mentioned object, in the defect classification method for a semiconductor device according to the present invention, the wiring pattern which is a defect candidate is obtained by superimposing the layout pattern data of the semiconductor chip and the defect image. Is extracted and the wiring function types of the extracted defect candidate wires are discriminated to classify the wiring failure mode types such as the short mode type and the disconnection mode type.

Further, in the semiconductor device yield prediction method according to the present invention, the wiring pattern of the defect candidate is extracted by superimposing the layout pattern data of the semiconductor chip and the defect image, and the wiring function of the extracted wiring of the defect candidate is extracted. By classifying the types, wiring failure mode types such as short mode type and disconnection mode type are classified, and the influence of the wiring failure mode type on the semiconductor chip based on the classification result of the wiring failure mode type and the design information. The yield of semiconductor devices is predicted by determining

Further, in the method of manufacturing a semiconductor device according to the present invention, the wiring function of the extracted defect candidate wiring is extracted by extracting the wiring position of the defect candidate by superimposing the layout pattern data of the semiconductor chip and the defect image. By classifying the types, the wiring failure mode types such as short mode type and disconnection mode type are classified, and the problem process is extracted based on the classification result of the wiring failure mode type. You will be taken measures.

Further, in the method of manufacturing a semiconductor device according to the present invention, the wiring function of the extracted defective candidate wiring is extracted by superposing the layout pattern data of the semiconductor chip and the defective image to extract the defective wiring portion. By classifying the types, wiring failure mode types such as short mode type and disconnection mode type are classified, and the influence of the wiring failure mode type on the semiconductor chip based on the classification result of the wiring failure mode type and the design information. The yield of the semiconductor device is predicted by determining, and based on the yield prediction result, it is determined whether to stop the subsequent manufacturing and discard the semiconductor wafer or to continue the subsequent manufacturing. It

Further, in the defect classification system for semiconductor devices according to the present invention, a layout storing pattern data used for manufacturing a semiconductor chip, layout information thereof, and layout data including wiring function types of respective wirings is stored. A database, a design information database that stores design information that includes criticality determination information according to wiring failure mode types such as short mode types and disconnection mode types, and defect inspection that outputs defect information including defect images A defect classification device that classifies the wiring failure mode type of a defect candidate based on the layout data, the design information, and the defect information, wherein the defect classification device is layout pattern data of the layout data. Extraction of wiring locations that are candidate defects by superimposing the defect image with the defect image By discriminating the wiring function type of wiring of the extracted failure candidates, classifying the defective wiring mode type.

Further, in the defect classifying apparatus for semiconductor devices according to the present invention, means for extracting a wiring position which is a defect candidate by superposing layout pattern data obtained from the layout database and a defect image obtained from the defect inspection apparatus. And a means for classifying the wiring failure mode types such as the short mode type and the disconnection mode type by discriminating the wiring function types of the extracted defect candidate wirings.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing the structure of a defect classification system according to an embodiment of the present invention. The system of this embodiment is mainly configured by a defect classification device 1, a layout database 2, a design information database 3, and a defect inspection device 4, and a defect observation device 5 is combined as necessary. Then, these are connected by the network 6.

The layout database 2 is a database for recording layout data 11 including figures used for manufacturing semiconductor masks and their layout information. The layout data 11 includes wiring layer numbers and type numbers corresponding to wiring functions. (Number indicating the wiring function type) is included.

As the defect inspection device 4, a foreign substance inspection device, a visual inspection device, or the like is used. The foreign matter inspection apparatus is generally an optical type, but the appearance inspection apparatus may be an optical type or a SEM type. The defect information 12 necessary for the defect classification method of the present embodiment includes defect image 12a, defect coordinates, the total number of defects, a normal image 12d for referring to the defect image, and category information discriminated by the defect inspection device 4 (for example, wiring). Information such as foreign matter above the wiring, foreign matter under the wiring, and pattern collapse). In the system of the present embodiment, the defect information 12 may be acquired by the defect inspection device 4, or the defect observation that enables more detailed observation based on the defect coordinates and category information output from the defect inspection device 4. The defect information 12 may be acquired using the device 5. The defect observing device 5 may also be an optical type or an SEM type.

Further, a combination of defective wirings or individual wirings (a wiring failure mode type such as a short mode type or a disconnection mode type represented by a combination of wiring function types or a single wiring function type) and each of them The design information database 3 is a collection of the design information 13 in which the correspondence between the information regarding whether or not the repair is possible, the required number of redundant circuits, and the fatality is described. The design information 13 may be transferred from the designer's terminal to the defect classification device 1 without using the design information database 3, or the operator may directly input the design information 13 using the input device 20 of the defect classification device 1. .

The layout data 11, the defect information 12, and the design information 13 are stored in the data storage unit 2 of the defect classification device 1.
1 and the data calculation unit 2 based on a predetermined defect classification algorithm stored in the program storage unit 23.
In 2, the data is sequentially subjected to a predetermined process to classify the defects, and the classification result is output to the output device 24 as necessary.

The defect classifying apparatus 1 classifies defects by the following method and procedure. FIG. 2 is a flowchart showing the defect classification method according to the present embodiment (note that FIG. 2 is an application example only to defects due to a short circuit for simplification of description).

First, the layout data 11 is loaded into the defect classification device (step 1). Here, the layout data 11 is classified for each wiring layer, that is, for each wiring mask.
May be divided and the layout data 11 of a desired wiring layer may be read (the layout database 11 may store the layout data 11 for each wiring layer). Further, the wiring function is associated with the wiring figure and the position in the layout data 11 so that the wiring function of the figure on the layout can be identified. For example, as shown in FIG. 3, it is necessary to configure the layout data 11 by assigning a wiring layer number and a type number corresponding to the wiring function to each wiring.

Next, the design information 13 defining the relationship between the defect classification criteria, whether or not the wiring failure due to the defect can be repaired, and the lethality of the defect is read (step 2). Assuming that a short circuit is present, the design information 13 includes a short mode classification by type number (a short mode classification represented by a combination of wiring function classifications, which is one of wiring failure mode classifications), as shown in FIG. , And remedy availability information.

Next, the defect information 12 describing the defect image 12a, the defect coordinates, the total number of defects, the normal image 12d and the like which have been inspected and observed in advance are acquired (step 3). Figure 5
As shown in, the defect image 12a includes an image of the defect 30 itself and an image of pattern information around the defect in which the defect 30 has occurred.

Then, in order to extract the image of only the defect 30, the normal image 12d is read (step 4), and the normal image 12d is subtracted from the defect image 12a to extract the difference image 14 of the defect (step). 5).

Next, the difference image 14 of the defect and the layout pattern data 31 in the layout data 11 corresponding to the vicinity of the coordinates where the defect occurs are superposed (step 6). Generally, since the coordinate accuracy of the defect output from the defect inspection apparatus 4 is insufficient, when the layout pattern data 31 is overlaid, a positional deviation occurs. Therefore, as shown in FIG. 6, the defect image 12a
Using these and the layout pattern data 31, these images are corrected for the positional deviation of the coordinates by a general image processing method called pattern matching. A normal image 12d may be used instead of the defect image 12a used at this time. At this time, using one of the coordinates as a reference, the new coordinate at the time of the pattern matching is updated as the other coordinate data, or the positional deviation amount between the defect image 12a and the layout pattern data 31 is calculated. It may be stored and the subsequent processing may be performed.

Next, based on this coordinate correction value, the layout pattern data 31 and the difference image 14 of the defect are superposed, and a pseudo defect having the same shape is superposed on the layout pattern (step 7). For example, when a short circuit is assumed as shown in FIG. 7, when the overlap with the defect exists in two or more wirings on the layout pattern, it can be determined as a short circuit defect.

After confirming whether or not there is an overlap in this way (step 8), if a defect is expected,
Which wiring is short-circuited is discriminated from the additional information (number indicating the wiring function type) of the layout data 11 (step 9). That is, as shown in FIG. 8, it is possible to identify the type number of the wiring that overlaps the defect. Therefore,
As shown in FIG. 9, using the information of the wiring failure mode type in the design information 13 read in step 2, the number of occurrences of short circuits is counted for each short mode type represented by a combination of wiring type numbers. To do. In step 11, it is determined whether or not the processing has been completed for all the defect numbers read in step 3.

After the processing of all the defects is completed, as shown in FIG. 9, whether the repair is possible is defined by "0" and "1".
For each wiring layer, the total number of short-circuit occurrences for each short-mode type (repair availability value of "0") (subtotal in FIG. 9) and the short-circuit occurrence of each short-mode type for which repair availability is "1" The total of the numbers (subtotal in FIG. 9) is obtained, and each subtotal is multiplied by “0” or “1” to obtain a subtotal that cannot be repaired (“1”). It is possible to calculate the number of fatal defects of the wafer. Further, if the lethality is counted by the number of chips, the chip yield in the process can be calculated.

Also, in the case of dummy wiring, FIG.
As shown in 0, it is also possible to determine whether the wiring to be functioning is short-circuited with the dummy wiring or the wirings to be functioning are short-circuited. In other words, the layout data 11 includes a type number (a number indicating a wiring function type) that allows the wiring to be functional (denoted as a logic wiring in FIG. 10) and the dummy wiring to be discriminated from each other. The data 13 includes a short mode type represented by a combination of wiring function types and non-lethalness / lethalness represented by “0” or “1” corresponding to the short mode type. The number of fatal defects of the semiconductor wafer in the process can be calculated by the same method as described above. Similarly, if the fatality is counted by the number of chips,
The chip yield in the process can be calculated.

As described above, the defects are not only classified into the categories of short circuit and disconnection of the wiring, but also the wiring failure such as the short mode type or the disconnection mode type represented by the combination of the wiring function types or the single wiring function type. The true fatality of a defect is determined by the mode type and the fatality determination information (repair availability information and fatality / non-fatal information) corresponding to the mode type, so the degree of influence on the performance of a semiconductor chip is clarified. Can be Therefore, it is possible to calculate the net yield for each process and accurately grasp the process to be taken and the type of the most fatal defect to be taken. Therefore, it is possible to accurately change some of the manufacturing conditions of the extracted problematic process, or to change the manufacturing conditions such as changing the design of a part of the mask used in the extracted problematic process. The feedback to the design can be done accurately. Furthermore, it is possible to accurately predict the yield in the final step based on the yield of semiconductor chips in the inspection step (or up to the inspection step). Therefore, the semiconductor wafers inspected here It is possible to determine whether the production of the product should be continued as it is or should be discarded.

FIG. 11 shows an example of the wafer manufacturing continuation determination. Let Y (n) be the yield calculation value of the current arbitrary process (n process) calculated based on the lethality determination result of the defect according to the present embodiment, and let the yield calculation value from the first process to the (n-1) process be Y (1), Y (2), ..., Y (n−), the current yield calculation value Y (cal) from the initial process to the (n) process is calculated from Y (1) to Y (n). Product.
In addition, the yield Y from the (n + 1) step to the final step
(Est) is a yield prediction value Y (n + 1), Y of each process obtained by performing a prediction by a critical area analysis or the like.
(N + 2), ..., Y (E) is obtained, and this Y (n + 1)
To Y (E). The above current yield calculation value (Y (cal)) and yield prediction value (Y (e)
yield of the final process (Y (to
tal)).

If the number of product chips mounted on one wafer is N and the price per product chip is P, then N.P.
Y (total) is the predicted value of sales, and if this value is less than the manufacturing cost C from the subsequent (n + 1) process to the final process, no profit can be obtained, so the manufacturing of this wafer is stopped, Discard. On the other hand, the predicted value of sales is (n +
1) When it is higher than the manufacturing cost C from the process to the final process, it is possible to judge that the manufacturing is continued, and efficient production is possible.

Next, a method applied to search for a defective portion will be described with reference to FIG. When searching which wiring has a failure based on the result of testing, it may be difficult to narrow down the actual failure from several points (failure candidates) that are considered to have failed. Therefore, as shown in FIG. 12, for each wiring layer, an individual identifier (node number) is given to all the wiring patterns that are independent of each other, and the defects found by the in-line inspection result are given. By adding the node information (shown as a short node in FIG. 12) composed of a combination of the above identifiers or a single identifier, it is possible to specify a failure location that is difficult to narrow down. At this time, it is necessary to add circuit node information corresponding to the layout graphic to the design information database 3.

[0034]

As described above, according to the present invention, it becomes possible to rationally and efficiently proceed the semiconductor production, and it is possible to greatly contribute to the reduction of the manufacturing cost and the development period of a new product. .

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of a defect classification system according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a defect classification method according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of layout pattern data, wiring function types, and the like used in an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing correspondences between short mode types used in one embodiment of the present invention and their remedy availability.

FIG. 5 is an explanatory diagram showing a method of extracting a defect difference image according to an embodiment of the present invention.

FIG. 6 is an explanatory diagram showing pattern matching between a defect image and layout pattern data according to an embodiment of the present invention.

FIG. 7 is an explanatory diagram showing superposition of defect difference images on layout pattern data according to an embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a method of discriminating short-circuited wiring function types according to an embodiment of the present invention.

FIG. 9 is an explanatory diagram showing aggregated data for each short mode according to an embodiment of the present invention.

FIG. 10 is an explanatory diagram showing an application example to a semiconductor wafer having a dummy pattern according to an embodiment of the present invention.

FIG. 11 is an explanatory diagram showing a manufacturing continuation determination method in an intermediate step according to the embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a node information storage system of a shorted wiring according to an embodiment of the present invention.

[Explanation of symbols]

1 Defect classifier 2 layout database 3 Design information database 4 Defect inspection equipment 5 Defect observation device 6 network 11 Layout data 12 Defect information 13 Design information 20 Input device 21 Data storage 22 Data calculator 23 Program Storage 24 Output device

Front page continuation (51) Int.Cl. ⁷ identification code FI theme code (reference) G06T 1/00 305 G06T 7/00 300E 5L096 7/00 300 G01R 31/28 L (72) Inventor Hiroto Okuda Kanagawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi F-term in Hitachi, Ltd. production technology research institute (reference) 2G014 AA02 AA03 AA13 AB21 AB59 AC11 2G051 AA51 AB02 EA12 EA14 EC01 2G132 AA08 AB00 AD15 AF13 AL12 4M106 AA01 BA02 BA04 CA16 CA01 CA41 DA15 CA15 DA15 DH31 DH34 DJ18 DJ20 DJ21 DJ23 DJ40 5B057 AA03 CA12 CB12 CC01 CE08 CH01 CH14 DA03 DA12 DB02 DC33 5L096 BA03 DA02 GA08 HA09 (54) [Title of Invention] Defect classification method of semiconductor device, semiconductor device yield prediction method and manufacturing of semiconductor device Method, semiconductor device defect classification system, semiconductor device classification device, and program and recording medium used therefor

Claims (14)

[Claims] 1. A short mode type and a short mode type are identified by superposing the layout pattern data of a semiconductor chip and a defect image to extract a wiring position which is a defect candidate and discriminating a wiring function type of the extracted defect candidate wiring. A method of classifying defects in a semiconductor device, characterized by classifying wiring failure mode types such as disconnection mode types. 2. A short mode type and a short mode type are selected by superimposing the layout pattern data of the semiconductor chip and the defect image to extract the wiring positions which are the defect candidates and discriminate the wiring function type of the extracted defect candidate wiring. By classifying the wiring failure mode types such as the disconnection mode type and determining the influence of the wiring failure mode types on the semiconductor chip based on the classification result of the wiring failure mode types and the design information, the yield of semiconductor devices can be improved. A method for predicting a yield of a semiconductor device, which comprises predicting. 3. The final product yield according to claim 2, wherein the yield of the final product is predicted from the net yield calculation result for each of the plurality of manufacturing processes and the predicted value of the yield of each manufacturing process after the plurality of manufacturing processes. A method for predicting a yield of a semiconductor device, comprising: 4. A short-mode type and a short-mode type are identified by extracting a wiring position which is a defect candidate by superimposing the layout pattern data of the semiconductor chip and a defect image and discriminating the wiring function type of the extracted defect candidate wiring. It is characterized by classifying wiring failure mode types such as disconnection mode types, extracting problematic processes based on the classification result of the wiring failure mode types, and taking measures against the extracted problematic processes. Manufacturing method of semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the manufacturing conditions of the extracted problematic process are changed. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the design of the extracted problematic process is changed. 7. A short-mode type and a short-mode type are identified by superimposing layout pattern data of a semiconductor chip and a defect image to extract a wiring position that is a defect candidate and discriminating a wiring function type of the extracted defect candidate wiring. By classifying the wiring failure mode types such as the disconnection mode type and determining the influence of the wiring failure mode types on the semiconductor chip based on the classification result of the wiring failure mode types and the design information, the yield of semiconductor devices can be improved. A method of manufacturing a semiconductor device, comprising: making a prediction and determining whether to stop the subsequent manufacturing and discard the semiconductor wafer or to continue the subsequent manufacturing based on the yield prediction result. 8. A layout database storing pattern data used for manufacturing a semiconductor chip, layout information thereof, layout data including wiring function types of respective wirings, short mode type, disconnection mode type, and the like. A design information database that stores design information configured to include fatality determination information corresponding to a wiring failure mode type, a defect inspection device that outputs defect information including a defect image, the layout data, the design information, and the A defect classification system for a semiconductor device, comprising: a defect classification device that classifies the wiring failure mode type of a defect candidate based on defect information, wherein the defect classification device includes layout pattern data of the layout data and the defect image. Wiring points that are candidate defects are extracted by overlapping with It said By discriminating wiring function type, defect classification system for a semiconductor device characterized by classifying the defective wiring mode type of wiring. 9. The method according to claim 8, wherein individual identifiers are assigned to all of the individual wiring patterns that are independent of each other, and at least a defect point determined to be a fatal defect is a combination of the identifiers or a single identifier. A defect classification system for semiconductor devices, which is characterized by adding and managing node information constituted by. 10. A means for extracting a wiring position which is a defect candidate by superimposing layout pattern data obtained from a layout database and a defect image obtained from a defect inspection apparatus, and a wiring function type of the extracted defect candidate wiring. And a means for classifying wiring failure mode types such as a short mode type and a disconnection mode type by discriminating the above. 11. The yield of semiconductor devices according to claim 10, wherein the yield of semiconductor devices is predicted by determining the effect of the wiring failure mode type on the semiconductor chip based on the classification result of the wiring failure mode type and the design information. A defect classification apparatus having means. 12. The method according to claim 10, wherein individual identifiers are assigned to all of the individual wiring patterns that are independent of each other, and at least a defect point determined to be a fatal defect is a combination of the identifiers or a single identifier. A defect classifying apparatus for semiconductor devices, characterized in that the node information is added and managed. 13. The defect classification method for a semiconductor device according to claim 1, the semiconductor device yield prediction method for a semiconductor device according to claim 2, or any one of claims 4 to 7. A program that describes a data collection and data processing algorithm for executing the method for manufacturing a semiconductor device described in. 14. The defect classification method for a semiconductor device according to claim 1, the semiconductor device yield prediction method for a semiconductor device according to claim 2, or any one of claims 4 to 7. A computer-readable recording medium having recorded therein a program for executing the method for manufacturing a semiconductor device according to item 1.