KR20120059559A - 반도체 장치의 형성방법 - Google Patents
반도체 장치의 형성방법 Download PDFInfo
- Publication number
- KR20120059559A KR20120059559A KR1020127007098A KR20127007098A KR20120059559A KR 20120059559 A KR20120059559 A KR 20120059559A KR 1020127007098 A KR1020127007098 A KR 1020127007098A KR 20127007098 A KR20127007098 A KR 20127007098A KR 20120059559 A KR20120059559 A KR 20120059559A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon
- layer
- epitaxial
- wafer
- growing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/15—Diffusion of dopants within, into or out of semiconductor bodies or layers from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
- H10D62/605—Planar doped, e.g. atomic-plane doped or delta-doped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3438—Doping during depositing
- H10P14/3448—Delta-doping
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3822—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US23972909P | 2009-09-03 | 2009-09-03 | |
| US61/239,729 | 2009-09-03 | ||
| US12/873,147 US9230810B2 (en) | 2009-09-03 | 2010-08-31 | System and method for substrate wafer back side and edge cross section seals |
| US12/873,147 | 2010-08-31 | ||
| PCT/US2010/047827 WO2011029010A2 (en) | 2009-09-03 | 2010-09-03 | Method of forming a semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020167008584A Division KR101752112B1 (ko) | 2009-09-03 | 2010-09-03 | 반도체 장치의 형성방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20120059559A true KR20120059559A (ko) | 2012-06-08 |
Family
ID=43623603
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020127007098A Ceased KR20120059559A (ko) | 2009-09-03 | 2010-09-03 | 반도체 장치의 형성방법 |
| KR1020167008584A Active KR101752112B1 (ko) | 2009-09-03 | 2010-09-03 | 반도체 장치의 형성방법 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020167008584A Active KR101752112B1 (ko) | 2009-09-03 | 2010-09-03 | 반도체 장치의 형성방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US9230810B2 (https=) |
| EP (1) | EP2474039B1 (https=) |
| JP (1) | JP6002037B2 (https=) |
| KR (2) | KR20120059559A (https=) |
| CN (1) | CN102598276B (https=) |
| WO (1) | WO2011029010A2 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104810363B (zh) * | 2014-01-26 | 2018-04-17 | 北大方正集团有限公司 | 功率集成器件及其制作方法 |
| US9379185B2 (en) | 2014-04-24 | 2016-06-28 | International Business Machines Corporation | Method of forming channel region dopant control in fin field effect transistor |
| WO2016021020A1 (ja) * | 2014-08-07 | 2016-02-11 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置の製造方法、及び、半導体装置 |
| CN106835269A (zh) * | 2017-03-03 | 2017-06-13 | 上海新傲科技股份有限公司 | 用于氮化物外延生长的叠层基板及其形成方法 |
| JP2019075438A (ja) * | 2017-10-13 | 2019-05-16 | 明広 石田 | 半導体レーザ素子及び半導体レーザ素子の製造方法 |
| CN112595949A (zh) * | 2020-12-28 | 2021-04-02 | 上海超硅半导体有限公司 | 一种晶圆自动测试装置及测试方法 |
| CN120656944A (zh) * | 2024-03-13 | 2025-09-16 | 朗姆研究公司 | 半导体衬底的背面密封 |
| CN118380332B (zh) * | 2024-06-21 | 2024-09-06 | 日月新半导体(威海)有限公司 | 一种集成电路封装体及其制备方法 |
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| JP5124999B2 (ja) | 2006-06-15 | 2013-01-23 | 富士電機株式会社 | 半導体装置およびその製造方法 |
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| JP4564510B2 (ja) * | 2007-04-05 | 2010-10-20 | 株式会社東芝 | 電力用半導体素子 |
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| US9425306B2 (en) * | 2009-08-27 | 2016-08-23 | Vishay-Siliconix | Super junction trench power MOSFET devices |
| JP5227356B2 (ja) | 2010-03-26 | 2013-07-03 | 株式会社エヌ・ティ・ティ・ドコモ | 情報端末および情報入力方法 |
-
2010
- 2010-08-31 US US12/873,147 patent/US9230810B2/en active Active
- 2010-09-03 KR KR1020127007098A patent/KR20120059559A/ko not_active Ceased
- 2010-09-03 EP EP10814561.6A patent/EP2474039B1/en active Active
- 2010-09-03 CN CN201080049358.3A patent/CN102598276B/zh active Active
- 2010-09-03 JP JP2012528090A patent/JP6002037B2/ja active Active
- 2010-09-03 KR KR1020167008584A patent/KR101752112B1/ko active Active
- 2010-09-03 WO PCT/US2010/047827 patent/WO2011029010A2/en not_active Ceased
-
2016
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2013504217A (ja) | 2013-02-04 |
| KR101752112B1 (ko) | 2017-06-28 |
| US9230810B2 (en) | 2016-01-05 |
| CN102598276B (zh) | 2015-05-06 |
| WO2011029010A2 (en) | 2011-03-10 |
| US10546750B2 (en) | 2020-01-28 |
| EP2474039A4 (en) | 2014-01-08 |
| US20110049682A1 (en) | 2011-03-03 |
| EP2474039A2 (en) | 2012-07-11 |
| WO2011029010A3 (en) | 2011-07-21 |
| CN102598276A (zh) | 2012-07-18 |
| JP6002037B2 (ja) | 2016-10-05 |
| EP2474039B1 (en) | 2020-11-04 |
| KR20160042462A (ko) | 2016-04-19 |
| US20160225622A1 (en) | 2016-08-04 |
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