KR20060028686A - 내부도체의 접속구조 및 다층기판 - Google Patents
내부도체의 접속구조 및 다층기판 Download PDFInfo
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- KR20060028686A KR20060028686A KR1020057023490A KR20057023490A KR20060028686A KR 20060028686 A KR20060028686 A KR 20060028686A KR 1020057023490 A KR1020057023490 A KR 1020057023490A KR 20057023490 A KR20057023490 A KR 20057023490A KR 20060028686 A KR20060028686 A KR 20060028686A
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Abstract
Description
Claims (15)
- 절연체 기판내에서 서로 소정 간격을 두고 인접하는 2개소이상의 비아도체와 상기 절연체 기판내에 형성된 라인도체를 접속하는 내부도체의 접속구조에 있어서, 상기 한쪽의 비아도체는 상기 다른쪽의 비아도체로부터 멀어지는 방향으로 연장형성된 연속 비아도체를 포함하고, 또한, 상기 한쪽의 비아도체는 상기 연속 비아도체를 통해 상기 라인도체에 접속되어 이루어지는 것을 특징으로 하는 내부도체의 접속구조.
- 제1항에 있어서, 상기 라인도체의 상기 연속 비아도체와의 접속부, 또는 상기 연속 비아도체의 상기 라인도체와의 접속부는 상대측의 접속부보다 큰 면적을 갖는 접속랜드로서 형성되어 이루어지는 것을 특징으로 하는 내부도체의 접속구조.
- 복수의 절연체층을 적층해서 이루어지는 적층체와, 이 적층체의 한쪽의 주면에 있어서 서로 소정 간격을 두고 인접하는 위치로부터 상기 적층체내로 각각 연장되는 적어도 제1, 제2비아도체와, 제1비아도체에 접속된 제1라인도체를 갖는 다층기판에 있어서, 상기 제1비아도체는 상기 제2비아도체로부터 멀어지는 방향으로 연장형성된 제1연속 비아도체를 포함하고, 또한, 상기 제1비아도체는 상기 제1연속 비아도체를 통해 상기 제1라인도체에 접속되어 이루어지는 것을 특징으로 하는 다층기판.
- 제3항에 있어서, 상기 제1, 제2비아도체와는 소정 간격을 두고 상기 적층체의 한쪽의 주면으로부터 상기 적층체내로 연장되는 제3비아도체를 갖고, 상기 제2비아도체는 상기 제1, 제3비아도체 각각으로부터 멀어지는 방향으로 연장형성된 제2연속 비아도체를 포함하고, 또한, 상기 제2비아도체는 상기 제2연속 비아도체를 통해 제2도체라인에 접속되어 이루어지는 것을 특징으로 하는 다층기판.
- 제4항에 있어서, 상기 제1, 제2연속 비아도체는 서로 다른 절연체층에 형성되어 이루어지는 것을 특징으로 하는 다층기판.
- 제4항 또는 제5항에 있어서, 상기 제1, 제2연속 비아도체는 다른 절연체층보다 얇은 절연체층에 형성되어 이루어지는 것을 특징으로 하는 다층기판.
- 제4항 내지 제6항 중 어느 한 항에 있어서, 상기 제1, 제2연속 비아도체는 각각의 절연체층을 관통하는 것을 특징으로 하는 다층기판.
- 제4항 내지 제6항 중 어느 한 항에 있어서, 상기 제1, 제2연속 비아도체는 각각의 절연체층을 관통하지 않는 것을 특징으로 하는 다층기판.
- 제3항 내지 제8항 중 어느 한 항에 있어서, 상기 제1라인도체의 상기 제1연 속 비아도체와의 접속부, 또는 상기 제1연속 비아도체의 상기 제1라인도체와의 접속부는 상대측의 접속부보다 큰 접속랜드로서 형성되어 이루어지는 것을 특징으로 하는 다층기판.
- 제4항 내지 제9항 중 어느 한 항에 있어서, 상기 제2연속 비아도체의 상기 제2라인도체와의 접속부, 또는 상기 제2라인도체의 상기 제2연속 비아도체와의 접속부는 상대측의 접속부보다 큰 접속랜드로서 형성되어 이루어지는 것을 특징으로 하는 다층기판.
- 제3항 내지 제10항 중 어느 한 항에 있어서, 상기 한쪽의 주면에, 상기 각 비아도체에 각각 접속된 표면전극을 형성한 것을 특징으로 하는 다층기판.
- 제3항 내지 제10항 중 어느 한 항에 있어서, 상기 한쪽의 주면에 전자부품이 탑재되어 있으며, 이 전자부품의 외부단자전극이 상기 주면에 노출된 상기 제1비아도체 및 제2비아도체에 표면전극을 통하지 않고 접속되어 있는 것을 특징으로 하는 다층기판.
- 제3항 내지 제12항 중 어느 한 항에 있어서, 상기 한쪽의 주면측은 마더보드에 접속 가능하게 구성되어 이루어지는 것을 특징으로 하는 다층기판.
- 제3항 내지 제13항 중 어느 한 항에 있어서, 상기 절연체층은 저온 소결 세라믹재료로 이루어지는 것을 특징으로 하는 다층기판.
- 제3항 내지 제14항 중 어느 한 항에 있어서, 상기 각 비아도체 및 각 라인도체는 각각 은 또는 구리를 주성분으로 하는 도전성 재료로 이루어지는 것을 특징으로 하는 다층기판.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2004111976 | 2004-04-06 | ||
JPJP-P-2004-00111976 | 2004-04-06 |
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KR20060028686A true KR20060028686A (ko) | 2006-03-31 |
KR100659521B1 KR100659521B1 (ko) | 2006-12-20 |
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KR1020057023490A KR100659521B1 (ko) | 2004-04-06 | 2005-02-08 | 내부도체의 접속구조 및 다층기판 |
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US (1) | US7652213B2 (ko) |
JP (1) | JP3918101B2 (ko) |
KR (1) | KR100659521B1 (ko) |
CN (1) | CN100502621C (ko) |
DE (1) | DE112005000014T5 (ko) |
TW (1) | TWI265763B (ko) |
WO (1) | WO2005101935A1 (ko) |
Cited By (1)
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KR101229956B1 (ko) * | 2008-03-31 | 2013-02-06 | 프린코 코포레이션 | 다층기판의 응력 평형 방법 및 다층기판 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4748161B2 (ja) * | 2005-07-12 | 2011-08-17 | 株式会社村田製作所 | 多層配線基板及びその製造方法 |
EP2187438A1 (en) * | 2007-12-28 | 2010-05-19 | Ibiden Co., Ltd. | Interposer and manufacturing method of the interposer |
US9930775B2 (en) * | 2009-06-02 | 2018-03-27 | Hsio Technologies, Llc | Copper pillar full metal via electrical circuit structure |
JP4992960B2 (ja) | 2009-12-07 | 2012-08-08 | 株式会社村田製作所 | 高周波モジュール |
US8488329B2 (en) * | 2010-05-10 | 2013-07-16 | International Business Machines Corporation | Power and ground vias for power distribution systems |
CN103444271A (zh) * | 2011-05-12 | 2013-12-11 | 株式会社藤仓 | 贯通布线基板、电子器件封装以及电子部件 |
CN102355798B (zh) * | 2011-10-25 | 2014-04-23 | 中国兵器工业集团第二一四研究所苏州研发中心 | 柱面模块电路板的制作方法以及烧结支架 |
US9440135B2 (en) * | 2012-05-29 | 2016-09-13 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Multilayer electronic structures with integral vias extending in in-plane direction |
TWM521801U (zh) * | 2015-05-29 | 2016-05-11 | Chunghwa Prec Test Tech Co Ltd | 具有高接合強度之多層結構的轉接介面板 |
CN107666770A (zh) * | 2016-07-29 | 2018-02-06 | 鹏鼎控股(深圳)股份有限公司 | 具焊垫的电路板及其制作方法 |
JP6729790B2 (ja) | 2017-03-14 | 2020-07-22 | 株式会社村田製作所 | 高周波モジュール |
IT201700051157A1 (it) * | 2017-05-11 | 2018-11-11 | Technoprobe Spa | Metodo di fabbricazione di un multistrato di una scheda di misura per un’apparecchiatura di test di dispositivi elettronici |
WO2019082714A1 (ja) * | 2017-10-26 | 2019-05-02 | 株式会社村田製作所 | 多層基板、インターポーザおよび電子機器 |
WO2020041605A1 (en) * | 2018-08-22 | 2020-02-27 | Liquid Wire Inc. | Structures with deformable conductors |
US11956898B2 (en) * | 2020-09-23 | 2024-04-09 | Apple Inc. | Three-dimensional (3D) copper in printed circuit boards |
CN115343812B (zh) * | 2022-08-22 | 2023-10-17 | 德阳三环科技有限公司 | 输入输出构件和制备方法及封装基座和光器件 |
Family Cites Families (10)
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JP2680443B2 (ja) | 1989-09-27 | 1997-11-19 | 株式会社東芝 | セラミック配線基板およびその製造方法 |
JP2996510B2 (ja) * | 1990-11-30 | 2000-01-11 | 株式会社日立製作所 | 電子回路基板 |
US5456778A (en) * | 1992-08-21 | 1995-10-10 | Sumitomo Metal Ceramics Inc. | Method of fabricating ceramic circuit substrate |
JPH1174645A (ja) | 1997-08-29 | 1999-03-16 | Sumitomo Kinzoku Electro Device:Kk | 多層セラミック基板の製造方法 |
JP2000353872A (ja) | 1999-06-11 | 2000-12-19 | Denso Corp | 回路基板およびその製造方法 |
JP4592891B2 (ja) | 1999-11-26 | 2010-12-08 | イビデン株式会社 | 多層回路基板および半導体装置 |
TW512653B (en) * | 1999-11-26 | 2002-12-01 | Ibiden Co Ltd | Multilayer circuit board and semiconductor device |
JP2001284811A (ja) | 2000-03-29 | 2001-10-12 | Murata Mfg Co Ltd | 積層型セラミック電子部品およびその製造方法ならびに電子装置 |
JP3407737B2 (ja) * | 2000-12-14 | 2003-05-19 | 株式会社デンソー | 多層基板の製造方法およびその製造方法によって形成される多層基板 |
US6812576B1 (en) * | 2002-05-14 | 2004-11-02 | Applied Micro Circuits Corporation | Fanned out interconnect via structure for electronic package substrates |
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- 2005-02-08 WO PCT/JP2005/001815 patent/WO2005101935A1/ja active Application Filing
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KR101229956B1 (ko) * | 2008-03-31 | 2013-02-06 | 프린코 코포레이션 | 다층기판의 응력 평형 방법 및 다층기판 |
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CN100502621C (zh) | 2009-06-17 |
US20070107933A1 (en) | 2007-05-17 |
DE112005000014T5 (de) | 2006-05-18 |
TWI265763B (en) | 2006-11-01 |
CN1788531A (zh) | 2006-06-14 |
WO2005101935A1 (ja) | 2005-10-27 |
JPWO2005101935A1 (ja) | 2007-08-16 |
KR100659521B1 (ko) | 2006-12-20 |
US7652213B2 (en) | 2010-01-26 |
JP3918101B2 (ja) | 2007-05-23 |
TW200534768A (en) | 2005-10-16 |
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