KR101060906B1 - 다층 ltcc 기판의 제조방법 - Google Patents
다층 ltcc 기판의 제조방법 Download PDFInfo
- Publication number
- KR101060906B1 KR101060906B1 KR1020080083594A KR20080083594A KR101060906B1 KR 101060906 B1 KR101060906 B1 KR 101060906B1 KR 1020080083594 A KR1020080083594 A KR 1020080083594A KR 20080083594 A KR20080083594 A KR 20080083594A KR 101060906 B1 KR101060906 B1 KR 101060906B1
- Authority
- KR
- South Korea
- Prior art keywords
- ceramic
- pattern
- external electrode
- layer
- conductive
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
- H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (7)
- 복수의 세라믹층으로 이루어지며 복수개의 도전성 비아를 구비하고, 최외곽 세라믹층의 두께가 다른 내부의 세라믹층의 두께보다 두꺼운 세라믹 소결체를 마련하는 단계;상기 세라믹 소결체의 상기 최외곽 세라믹층의 도전성 비아 위에 레이저광을 조사하여 상기 최외곽 세라믹층을 관통하지 않는 홈부 패턴을 형성하는 단계;상기 홈부 패턴에 도전성 페이스트를 충전하는 단계;외부 전극 패턴이 형성되도록 상기 도전성 페이스트를 소성하는 단계; 및상기 외부 전극 패턴에 도금층을 형성하는 단계;를 포함하는 다층 LTCC 기판의 제조방법.
- 삭제
- 제1항에 있어서,상기 도전성 페이스트는 Ag, Ag-Pd, Cu 및 Au를 포함하는 그룹으로부터 선택된 금속과 글래스 성분의 혼합물인 것을 특징으로 하는 다층 LTCC 기판의 제조방법.
- 제1항에 있어서,상기 도전성 페이스트의 소성 온도는 상기 세라믹 소결체에 적용된 소성 온도보다 낮은 것을 특징으로 하는 다층 LTCC 기판의 제조방법.
- 삭제
- 제1항에 있어서,상기 외부 전극 패턴은 50㎛ 이하의 선폭을 갖는 것을 특징으로 하는 다층 LTCC 기판의 제조방법.
- 제1항에 있어서,상기 도전성 페이스트를 충전하는 단계는, 스크린 프린팅 기법에 의해 실행되는 것을 특징으로 하는 다층 LTCC 기판의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080083594A KR101060906B1 (ko) | 2008-08-26 | 2008-08-26 | 다층 ltcc 기판의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080083594A KR101060906B1 (ko) | 2008-08-26 | 2008-08-26 | 다층 ltcc 기판의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20100024852A KR20100024852A (ko) | 2010-03-08 |
KR101060906B1 true KR101060906B1 (ko) | 2011-08-30 |
Family
ID=42176586
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020080083594A KR101060906B1 (ko) | 2008-08-26 | 2008-08-26 | 다층 ltcc 기판의 제조방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR101060906B1 (ko) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003282352A (ja) * | 2002-03-27 | 2003-10-03 | Kyocera Corp | 積層セラミックコンデンサの製造方法 |
KR100790695B1 (ko) * | 2006-05-19 | 2008-01-02 | 삼성전기주식회사 | 전자부품 패키지용 세라믹 기판의 제조방법 |
-
2008
- 2008-08-26 KR KR1020080083594A patent/KR101060906B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003282352A (ja) * | 2002-03-27 | 2003-10-03 | Kyocera Corp | 積層セラミックコンデンサの製造方法 |
KR100790695B1 (ko) * | 2006-05-19 | 2008-01-02 | 삼성전기주식회사 | 전자부품 패키지용 세라믹 기판의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20100024852A (ko) | 2010-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4337950B2 (ja) | 回路基板の製造方法 | |
KR101089936B1 (ko) | 다층 세라믹 회로 기판 및 제조방법 | |
US7463475B2 (en) | Multilayer electronic component, electronic device, and method for manufacturing multilayer electronic component | |
JP2005108950A (ja) | セラミックモジュール部品およびその製造方法 | |
JP4463045B2 (ja) | セラミック電子部品及びコンデンサ | |
WO2018042846A1 (ja) | 電子デバイス及び多層セラミック基板 | |
KR100748238B1 (ko) | 무수축 세라믹 기판 및 그 제조방법 | |
KR20090051627A (ko) | 다층 세라믹 기판 및 그의 제조방법 | |
US20160242287A1 (en) | Multilayer substrate and method for manufacturing the same | |
JP2009111394A (ja) | 多層セラミック基板の製造方法 | |
JP6819603B2 (ja) | 多層セラミック基板およびその製造方法 | |
WO2018030192A1 (ja) | セラミック電子部品 | |
KR101805074B1 (ko) | 세라믹 다층회로 기판의 제조방법 | |
KR101060906B1 (ko) | 다층 ltcc 기판의 제조방법 | |
JP7011563B2 (ja) | 回路基板および電子部品 | |
KR100956212B1 (ko) | 다층 세라믹 기판의 제조 방법 | |
JP4429130B2 (ja) | セラミック電子部品の製造方法 | |
JP6418918B2 (ja) | プローブカード用回路基板およびそれを備えたプローブカード | |
JP6750728B2 (ja) | 積層型電子部品および積層型電子部品モジュール | |
JP2011049342A (ja) | 電子部品搭載用基板およびその製造方法 | |
JP4463046B2 (ja) | セラミック電子部品及びコンデンサ | |
JP2006041319A (ja) | 表面実装型多連コンデンサ及びその実装構造 | |
JP2005039071A (ja) | セラミック積層デバイスの製造方法 | |
KR101038891B1 (ko) | 세라믹 기판 및 그의 제조 방법 | |
JP5289874B2 (ja) | セラミック部品の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E90F | Notification of reason for final refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20140701 Year of fee payment: 4 |
|
FPAY | Annual fee payment |
Payment date: 20150707 Year of fee payment: 5 |
|
FPAY | Annual fee payment |
Payment date: 20160701 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20170713 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20180711 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20190604 Year of fee payment: 9 |