KR20010094995A - 반도체 집적회로 - Google Patents

반도체 집적회로 Download PDF

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Publication number
KR20010094995A
KR20010094995A KR1020010015127A KR20010015127A KR20010094995A KR 20010094995 A KR20010094995 A KR 20010094995A KR 1020010015127 A KR1020010015127 A KR 1020010015127A KR 20010015127 A KR20010015127 A KR 20010015127A KR 20010094995 A KR20010094995 A KR 20010094995A
Authority
KR
South Korea
Prior art keywords
data line
potential
precharge
voltage
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020010015127A
Other languages
English (en)
Korean (ko)
Inventor
칸노유스케
이토키요오
Original Assignee
가나이 쓰토무
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가나이 쓰토무
Publication of KR20010094995A publication Critical patent/KR20010094995A/ko
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
KR1020010015127A 2000-03-31 2001-03-23 반도체 집적회로 Ceased KR20010094995A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000101204A JP2001291389A (ja) 2000-03-31 2000-03-31 半導体集積回路
JP2000-101204 2000-03-31

Publications (1)

Publication Number Publication Date
KR20010094995A true KR20010094995A (ko) 2001-11-03

Family

ID=18615290

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010015127A Ceased KR20010094995A (ko) 2000-03-31 2001-03-23 반도체 집적회로

Country Status (4)

Country Link
US (4) US6519195B2 (enExample)
JP (1) JP2001291389A (enExample)
KR (1) KR20010094995A (enExample)
TW (1) TW536711B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8576636B2 (en) 2010-07-16 2013-11-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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US6762951B2 (en) * 2001-11-13 2004-07-13 Hitachi, Ltd. Semiconductor integrated circuit device
JP2001291389A (ja) * 2000-03-31 2001-10-19 Hitachi Ltd 半導体集積回路
US6563743B2 (en) * 2000-11-27 2003-05-13 Hitachi, Ltd. Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy
DE10124753B4 (de) * 2001-05-21 2006-06-08 Infineon Technologies Ag Schaltungsanordnung zum Auslesen und zum Speichern von binären Speicherzellensignalen
JP2003233989A (ja) * 2002-02-07 2003-08-22 Fujitsu Ltd 半導体記憶装置及びプリチャージ方法
US6894231B2 (en) * 2002-03-19 2005-05-17 Broadcom Corporation Bus twisting scheme for distributed coupling and low power
US6809986B2 (en) * 2002-08-29 2004-10-26 Micron Technology, Inc. System and method for negative word line driver circuit
JP2004265944A (ja) * 2003-02-21 2004-09-24 Handotai Rikougaku Kenkyu Center:Kk 半導体記憶装置
US6845059B1 (en) * 2003-06-26 2005-01-18 International Business Machines Corporation High performance gain cell architecture
EP1492126A1 (en) 2003-06-27 2004-12-29 Dialog Semiconductor GmbH Analog or multilevel DRAM cell having natural transistor
US6831866B1 (en) 2003-08-26 2004-12-14 International Business Machines Corporation Method and apparatus for read bitline clamping for gain cell DRAM devices
KR100533384B1 (ko) * 2004-04-12 2005-12-06 주식회사 하이닉스반도체 저진폭 전압구동 글로벌 입출력 라인을 갖는 반도체메모리 장치
US7385865B2 (en) * 2004-12-01 2008-06-10 Intel Corporation Memory circuit
US20060176747A1 (en) * 2005-02-09 2006-08-10 International Business Machines Corporation Circuit for interfacing local bitlines with global bitline
DE102005020808B3 (de) * 2005-05-04 2006-07-20 Micronas Gmbh Nichtflüchtige Speichereinrichtung mit einer Programmier- und Löschkontrolle
US7361872B2 (en) * 2005-08-16 2008-04-22 Graphic Packaging International, Inc. Variable serving size insulated packaging
JP2007058957A (ja) * 2005-08-23 2007-03-08 Toshiba Corp 半導体記憶装置
US7158432B1 (en) * 2005-09-01 2007-01-02 Freescale Semiconductor, Inc. Memory with robust data sensing and method for sensing data
US8077533B2 (en) 2006-01-23 2011-12-13 Freescale Semiconductor, Inc. Memory and method for sensing data in a memory using complementary sensing scheme
JP5181423B2 (ja) 2006-03-20 2013-04-10 ソニー株式会社 半導体メモリデバイスとその動作方法
KR100808589B1 (ko) 2006-04-11 2008-02-29 주식회사 하이닉스반도체 반도체 메모리 장치의 입출력 라인 프리차지 회로
US7606057B2 (en) * 2006-05-31 2009-10-20 Arm Limited Metal line layout in a memory cell
JP4285511B2 (ja) * 2006-07-27 2009-06-24 ソニー株式会社 半導体メモリデバイス
US8009461B2 (en) * 2008-01-07 2011-08-30 International Business Machines Corporation SRAM device, and SRAM device design structure, with adaptable access transistors
US7864600B2 (en) * 2008-06-19 2011-01-04 Texas Instruments Incorporated Memory cell employing reduced voltage
US8339882B2 (en) * 2010-07-12 2012-12-25 Promos Technologies Pte. Ltd. Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM
KR101736383B1 (ko) * 2010-08-03 2017-05-30 삼성전자주식회사 메모리 장치, 이의 프리차지 제어 방법, 및 이를 포함하는 장치들
JP2012119013A (ja) * 2010-11-29 2012-06-21 Toshiba Corp 不揮発性半導体記憶装置
JP2013137853A (ja) * 2011-12-02 2013-07-11 Semiconductor Energy Lab Co Ltd 記憶装置および記憶装置の駆動方法

Citations (6)

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KR900012278A (ko) * 1989-01-13 1990-08-03 가부시끼가이샤 히다찌세이사꾸쇼 반도체 기억장치
KR970012770A (ko) * 1995-08-08 1997-03-29 김광호 불 휘발성 반도체 메모리 장치의 증폭회로
JPH10149677A (ja) * 1996-11-19 1998-06-02 Toshiba Corp ダイナミック型半導体記憶装置
KR19980037417A (ko) * 1996-11-21 1998-08-05 김광호 폴디드 비트라인 구조를 갖는 불휘발성 반도체 메모리 장치의 프로그램방법
JPH11134866A (ja) * 1997-10-27 1999-05-21 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR20000019073A (ko) * 1998-09-08 2000-04-06 윤종용 인접 비트라인간 누화 잡음을 개선한 반도체메모리장치

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US3593037A (en) * 1970-03-13 1971-07-13 Intel Corp Cell for mos random-acess integrated circuit memory
US3706891A (en) * 1971-06-17 1972-12-19 Ibm A. c. stable storage cell
BE788583A (fr) * 1971-09-16 1973-01-02 Intel Corp Cellule a trois lignes pour memoire a circuit integre a acces aleatoir
JPS5154789A (enExample) * 1974-11-09 1976-05-14 Nippon Electric Co
KR950001424B1 (en) 1986-03-28 1995-02-24 Hitachi Ltd 3-transistor dynamic random access memory
JP2615011B2 (ja) * 1986-06-13 1997-05-28 株式会社日立製作所 半導体記憶回路
US4945393A (en) * 1988-06-21 1990-07-31 At&T Bell Laboratories Floating gate memory circuit and apparatus
US4879682A (en) 1988-09-15 1989-11-07 Motorola, Inc. Sense amplifier precharge control
JPH05250875A (ja) * 1992-02-27 1993-09-28 Nec Corp 半導体記憶装置
KR950005095Y1 (ko) * 1992-03-18 1995-06-22 문정환 양방향성 그로벌 비트 라인을 갖는 dram
US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
US6016268A (en) * 1997-02-18 2000-01-18 Richard Mann Three transistor multi-state dynamic memory cell for embedded CMOS logic applications
FR2778012B1 (fr) * 1998-04-28 2001-09-28 Sgs Thomson Microelectronics Dispositif et procede de lecture de cellules de memoire eeprom
KR100619580B1 (ko) * 1999-05-14 2006-09-05 가부시키가이샤 히타치세이사쿠쇼 반도체 집적회로장치
JP2001291389A (ja) * 2000-03-31 2001-10-19 Hitachi Ltd 半導体集積回路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900012278A (ko) * 1989-01-13 1990-08-03 가부시끼가이샤 히다찌세이사꾸쇼 반도체 기억장치
KR970012770A (ko) * 1995-08-08 1997-03-29 김광호 불 휘발성 반도체 메모리 장치의 증폭회로
JPH10149677A (ja) * 1996-11-19 1998-06-02 Toshiba Corp ダイナミック型半導体記憶装置
KR19980037417A (ko) * 1996-11-21 1998-08-05 김광호 폴디드 비트라인 구조를 갖는 불휘발성 반도체 메모리 장치의 프로그램방법
JPH11134866A (ja) * 1997-10-27 1999-05-21 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR20000019073A (ko) * 1998-09-08 2000-04-06 윤종용 인접 비트라인간 누화 잡음을 개선한 반도체메모리장치

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8576636B2 (en) 2010-07-16 2013-11-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
US6519195B2 (en) 2003-02-11
US20030090948A1 (en) 2003-05-15
US6829186B2 (en) 2004-12-07
US20050088886A1 (en) 2005-04-28
JP2001291389A (ja) 2001-10-19
US20040057311A1 (en) 2004-03-25
TW536711B (en) 2003-06-11
US20010048617A1 (en) 2001-12-06
US6614696B2 (en) 2003-09-02

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