TW536711B - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
- Publication number
- TW536711B TW536711B TW090107384A TW90107384A TW536711B TW 536711 B TW536711 B TW 536711B TW 090107384 A TW090107384 A TW 090107384A TW 90107384 A TW90107384 A TW 90107384A TW 536711 B TW536711 B TW 536711B
- Authority
- TW
- Taiwan
- Prior art keywords
- potential
- data line
- semiconductor integrated
- integrated circuit
- memory
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 230000003321 amplification Effects 0.000 claims abstract description 15
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 15
- 230000002079 cooperative effect Effects 0.000 claims description 18
- 230000000875 corresponding effect Effects 0.000 claims description 18
- 238000012546 transfer Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
- 230000001276 controlling effect Effects 0.000 claims 1
- 229910003460 diamond Inorganic materials 0.000 claims 1
- 239000010432 diamond Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 9
- 239000003990 capacitor Substances 0.000 abstract description 8
- 230000006870 function Effects 0.000 abstract description 8
- 230000008569 process Effects 0.000 abstract description 2
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 29
- 239000010410 layer Substances 0.000 description 24
- 230000003071 parasitic effect Effects 0.000 description 15
- 101100481702 Arabidopsis thaliana TMK1 gene Proteins 0.000 description 13
- 230000000694 effects Effects 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 101001063878 Homo sapiens Leukemia-associated protein 1 Proteins 0.000 description 5
- 102100030893 Leukemia-associated protein 1 Human genes 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 101100029846 Oryza sativa subsp. japonica PIP1-1 gene Proteins 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011867 re-evaluation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000101204A JP2001291389A (ja) | 2000-03-31 | 2000-03-31 | 半導体集積回路 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW536711B true TW536711B (en) | 2003-06-11 |
Family
ID=18615290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW090107384A TW536711B (en) | 2000-03-31 | 2001-03-28 | Semiconductor integrated circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (4) | US6519195B2 (enExample) |
| JP (1) | JP2001291389A (enExample) |
| KR (1) | KR20010094995A (enExample) |
| TW (1) | TW536711B (enExample) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6762951B2 (en) * | 2001-11-13 | 2004-07-13 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| JP2001291389A (ja) * | 2000-03-31 | 2001-10-19 | Hitachi Ltd | 半導体集積回路 |
| US6563743B2 (en) * | 2000-11-27 | 2003-05-13 | Hitachi, Ltd. | Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy |
| DE10124753B4 (de) * | 2001-05-21 | 2006-06-08 | Infineon Technologies Ag | Schaltungsanordnung zum Auslesen und zum Speichern von binären Speicherzellensignalen |
| JP2003233989A (ja) * | 2002-02-07 | 2003-08-22 | Fujitsu Ltd | 半導体記憶装置及びプリチャージ方法 |
| US6894231B2 (en) * | 2002-03-19 | 2005-05-17 | Broadcom Corporation | Bus twisting scheme for distributed coupling and low power |
| US6809986B2 (en) * | 2002-08-29 | 2004-10-26 | Micron Technology, Inc. | System and method for negative word line driver circuit |
| JP2004265944A (ja) * | 2003-02-21 | 2004-09-24 | Handotai Rikougaku Kenkyu Center:Kk | 半導体記憶装置 |
| US6845059B1 (en) * | 2003-06-26 | 2005-01-18 | International Business Machines Corporation | High performance gain cell architecture |
| EP1492126A1 (en) | 2003-06-27 | 2004-12-29 | Dialog Semiconductor GmbH | Analog or multilevel DRAM cell having natural transistor |
| US6831866B1 (en) | 2003-08-26 | 2004-12-14 | International Business Machines Corporation | Method and apparatus for read bitline clamping for gain cell DRAM devices |
| KR100533384B1 (ko) * | 2004-04-12 | 2005-12-06 | 주식회사 하이닉스반도체 | 저진폭 전압구동 글로벌 입출력 라인을 갖는 반도체메모리 장치 |
| US7385865B2 (en) * | 2004-12-01 | 2008-06-10 | Intel Corporation | Memory circuit |
| US20060176747A1 (en) * | 2005-02-09 | 2006-08-10 | International Business Machines Corporation | Circuit for interfacing local bitlines with global bitline |
| DE102005020808B3 (de) * | 2005-05-04 | 2006-07-20 | Micronas Gmbh | Nichtflüchtige Speichereinrichtung mit einer Programmier- und Löschkontrolle |
| US7361872B2 (en) * | 2005-08-16 | 2008-04-22 | Graphic Packaging International, Inc. | Variable serving size insulated packaging |
| JP2007058957A (ja) * | 2005-08-23 | 2007-03-08 | Toshiba Corp | 半導体記憶装置 |
| US7158432B1 (en) * | 2005-09-01 | 2007-01-02 | Freescale Semiconductor, Inc. | Memory with robust data sensing and method for sensing data |
| US8077533B2 (en) | 2006-01-23 | 2011-12-13 | Freescale Semiconductor, Inc. | Memory and method for sensing data in a memory using complementary sensing scheme |
| JP5181423B2 (ja) | 2006-03-20 | 2013-04-10 | ソニー株式会社 | 半導体メモリデバイスとその動作方法 |
| KR100808589B1 (ko) | 2006-04-11 | 2008-02-29 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 입출력 라인 프리차지 회로 |
| US7606057B2 (en) * | 2006-05-31 | 2009-10-20 | Arm Limited | Metal line layout in a memory cell |
| JP4285511B2 (ja) * | 2006-07-27 | 2009-06-24 | ソニー株式会社 | 半導体メモリデバイス |
| US8009461B2 (en) * | 2008-01-07 | 2011-08-30 | International Business Machines Corporation | SRAM device, and SRAM device design structure, with adaptable access transistors |
| US7864600B2 (en) * | 2008-06-19 | 2011-01-04 | Texas Instruments Incorporated | Memory cell employing reduced voltage |
| US8339882B2 (en) * | 2010-07-12 | 2012-12-25 | Promos Technologies Pte. Ltd. | Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM |
| WO2012008286A1 (en) | 2010-07-16 | 2012-01-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| KR101736383B1 (ko) * | 2010-08-03 | 2017-05-30 | 삼성전자주식회사 | 메모리 장치, 이의 프리차지 제어 방법, 및 이를 포함하는 장치들 |
| JP2012119013A (ja) * | 2010-11-29 | 2012-06-21 | Toshiba Corp | 不揮発性半導体記憶装置 |
| JP2013137853A (ja) * | 2011-12-02 | 2013-07-11 | Semiconductor Energy Lab Co Ltd | 記憶装置および記憶装置の駆動方法 |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3593037A (en) * | 1970-03-13 | 1971-07-13 | Intel Corp | Cell for mos random-acess integrated circuit memory |
| US3706891A (en) * | 1971-06-17 | 1972-12-19 | Ibm | A. c. stable storage cell |
| BE788583A (fr) * | 1971-09-16 | 1973-01-02 | Intel Corp | Cellule a trois lignes pour memoire a circuit integre a acces aleatoir |
| JPS5154789A (enExample) * | 1974-11-09 | 1976-05-14 | Nippon Electric Co | |
| KR950001424B1 (en) | 1986-03-28 | 1995-02-24 | Hitachi Ltd | 3-transistor dynamic random access memory |
| JP2615011B2 (ja) * | 1986-06-13 | 1997-05-28 | 株式会社日立製作所 | 半導体記憶回路 |
| US4945393A (en) * | 1988-06-21 | 1990-07-31 | At&T Bell Laboratories | Floating gate memory circuit and apparatus |
| US4879682A (en) | 1988-09-15 | 1989-11-07 | Motorola, Inc. | Sense amplifier precharge control |
| JP2837682B2 (ja) * | 1989-01-13 | 1998-12-16 | 株式会社日立製作所 | 半導体記憶装置 |
| JPH05250875A (ja) * | 1992-02-27 | 1993-09-28 | Nec Corp | 半導体記憶装置 |
| KR950005095Y1 (ko) * | 1992-03-18 | 1995-06-22 | 문정환 | 양방향성 그로벌 비트 라인을 갖는 dram |
| US5396452A (en) * | 1993-07-02 | 1995-03-07 | Wahlstrom; Sven E. | Dynamic random access memory |
| KR970012770A (ko) * | 1995-08-08 | 1997-03-29 | 김광호 | 불 휘발성 반도체 메모리 장치의 증폭회로 |
| JP3241280B2 (ja) * | 1996-11-19 | 2001-12-25 | 株式会社東芝 | ダイナミック型半導体記憶装置 |
| KR19980037417A (ko) * | 1996-11-21 | 1998-08-05 | 김광호 | 폴디드 비트라인 구조를 갖는 불휘발성 반도체 메모리 장치의 프로그램방법 |
| US6016268A (en) * | 1997-02-18 | 2000-01-18 | Richard Mann | Three transistor multi-state dynamic memory cell for embedded CMOS logic applications |
| JPH11134866A (ja) * | 1997-10-27 | 1999-05-21 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| FR2778012B1 (fr) * | 1998-04-28 | 2001-09-28 | Sgs Thomson Microelectronics | Dispositif et procede de lecture de cellules de memoire eeprom |
| KR20000019073A (ko) * | 1998-09-08 | 2000-04-06 | 윤종용 | 인접 비트라인간 누화 잡음을 개선한 반도체메모리장치 |
| KR100619580B1 (ko) * | 1999-05-14 | 2006-09-05 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 집적회로장치 |
| JP2001291389A (ja) * | 2000-03-31 | 2001-10-19 | Hitachi Ltd | 半導体集積回路 |
-
2000
- 2000-03-31 JP JP2000101204A patent/JP2001291389A/ja active Pending
-
2001
- 2001-03-23 KR KR1020010015127A patent/KR20010094995A/ko not_active Ceased
- 2001-03-28 TW TW090107384A patent/TW536711B/zh not_active IP Right Cessation
- 2001-03-28 US US09/818,509 patent/US6519195B2/en not_active Expired - Fee Related
-
2002
- 2002-12-23 US US10/325,920 patent/US6614696B2/en not_active Expired - Fee Related
-
2003
- 2003-06-27 US US10/606,957 patent/US6829186B2/en not_active Expired - Fee Related
-
2004
- 2004-11-03 US US10/979,124 patent/US20050088886A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US6519195B2 (en) | 2003-02-11 |
| KR20010094995A (ko) | 2001-11-03 |
| US20030090948A1 (en) | 2003-05-15 |
| US6829186B2 (en) | 2004-12-07 |
| US20050088886A1 (en) | 2005-04-28 |
| JP2001291389A (ja) | 2001-10-19 |
| US20040057311A1 (en) | 2004-03-25 |
| US20010048617A1 (en) | 2001-12-06 |
| US6614696B2 (en) | 2003-09-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |