JP2001291389A - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JP2001291389A
JP2001291389A JP2000101204A JP2000101204A JP2001291389A JP 2001291389 A JP2001291389 A JP 2001291389A JP 2000101204 A JP2000101204 A JP 2000101204A JP 2000101204 A JP2000101204 A JP 2000101204A JP 2001291389 A JP2001291389 A JP 2001291389A
Authority
JP
Japan
Prior art keywords
data line
potential
voltage
precharge
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000101204A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001291389A5 (enExample
Inventor
Yusuke Sugano
雄介 菅野
Kiyoo Ito
清男 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000101204A priority Critical patent/JP2001291389A/ja
Priority to KR1020010015127A priority patent/KR20010094995A/ko
Priority to US09/818,509 priority patent/US6519195B2/en
Priority to TW090107384A priority patent/TW536711B/zh
Publication of JP2001291389A publication Critical patent/JP2001291389A/ja
Priority to US10/325,920 priority patent/US6614696B2/en
Priority to US10/606,957 priority patent/US6829186B2/en
Priority to US10/979,124 priority patent/US20050088886A1/en
Publication of JP2001291389A5 publication Critical patent/JP2001291389A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
JP2000101204A 2000-03-31 2000-03-31 半導体集積回路 Pending JP2001291389A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2000101204A JP2001291389A (ja) 2000-03-31 2000-03-31 半導体集積回路
KR1020010015127A KR20010094995A (ko) 2000-03-31 2001-03-23 반도체 집적회로
US09/818,509 US6519195B2 (en) 2000-03-31 2001-03-28 Semiconductor integrated circuit
TW090107384A TW536711B (en) 2000-03-31 2001-03-28 Semiconductor integrated circuit
US10/325,920 US6614696B2 (en) 2000-03-31 2002-12-23 Semiconductor device having memory cells coupled to read and write data lines
US10/606,957 US6829186B2 (en) 2000-03-31 2003-06-27 Semiconductor integrated circuit
US10/979,124 US20050088886A1 (en) 2000-03-31 2004-11-03 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000101204A JP2001291389A (ja) 2000-03-31 2000-03-31 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006191467A Division JP4338045B2 (ja) 2006-07-12 2006-07-12 半導体集積回路

Publications (2)

Publication Number Publication Date
JP2001291389A true JP2001291389A (ja) 2001-10-19
JP2001291389A5 JP2001291389A5 (enExample) 2005-02-03

Family

ID=18615290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000101204A Pending JP2001291389A (ja) 2000-03-31 2000-03-31 半導体集積回路

Country Status (4)

Country Link
US (4) US6519195B2 (enExample)
JP (1) JP2001291389A (enExample)
KR (1) KR20010094995A (enExample)
TW (1) TW536711B (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007058957A (ja) * 2005-08-23 2007-03-08 Toshiba Corp 半導体記憶装置
JP2007257682A (ja) * 2006-03-20 2007-10-04 Sony Corp 半導体メモリデバイスとその動作方法
KR100793671B1 (ko) * 2002-02-07 2008-01-10 후지쯔 가부시끼가이샤 반도체 기억 장치 및 프리차지 방법
JP2008034007A (ja) * 2006-07-27 2008-02-14 Sony Corp 半導体メモリデバイス
KR100808589B1 (ko) 2006-04-11 2008-02-29 주식회사 하이닉스반도체 반도체 메모리 장치의 입출력 라인 프리차지 회로
WO2012008286A1 (en) * 2010-07-16 2012-01-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2017120683A (ja) * 2011-12-02 2017-07-06 株式会社半導体エネルギー研究所 記憶装置の駆動方法

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6762951B2 (en) * 2001-11-13 2004-07-13 Hitachi, Ltd. Semiconductor integrated circuit device
JP2001291389A (ja) * 2000-03-31 2001-10-19 Hitachi Ltd 半導体集積回路
US6563743B2 (en) * 2000-11-27 2003-05-13 Hitachi, Ltd. Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy
DE10124753B4 (de) * 2001-05-21 2006-06-08 Infineon Technologies Ag Schaltungsanordnung zum Auslesen und zum Speichern von binären Speicherzellensignalen
US6894231B2 (en) * 2002-03-19 2005-05-17 Broadcom Corporation Bus twisting scheme for distributed coupling and low power
US6809986B2 (en) * 2002-08-29 2004-10-26 Micron Technology, Inc. System and method for negative word line driver circuit
JP2004265944A (ja) * 2003-02-21 2004-09-24 Handotai Rikougaku Kenkyu Center:Kk 半導体記憶装置
US6845059B1 (en) * 2003-06-26 2005-01-18 International Business Machines Corporation High performance gain cell architecture
EP1492126A1 (en) 2003-06-27 2004-12-29 Dialog Semiconductor GmbH Analog or multilevel DRAM cell having natural transistor
US6831866B1 (en) 2003-08-26 2004-12-14 International Business Machines Corporation Method and apparatus for read bitline clamping for gain cell DRAM devices
KR100533384B1 (ko) * 2004-04-12 2005-12-06 주식회사 하이닉스반도체 저진폭 전압구동 글로벌 입출력 라인을 갖는 반도체메모리 장치
US7385865B2 (en) * 2004-12-01 2008-06-10 Intel Corporation Memory circuit
US20060176747A1 (en) * 2005-02-09 2006-08-10 International Business Machines Corporation Circuit for interfacing local bitlines with global bitline
DE102005020808B3 (de) * 2005-05-04 2006-07-20 Micronas Gmbh Nichtflüchtige Speichereinrichtung mit einer Programmier- und Löschkontrolle
US7361872B2 (en) * 2005-08-16 2008-04-22 Graphic Packaging International, Inc. Variable serving size insulated packaging
US7158432B1 (en) * 2005-09-01 2007-01-02 Freescale Semiconductor, Inc. Memory with robust data sensing and method for sensing data
US8077533B2 (en) 2006-01-23 2011-12-13 Freescale Semiconductor, Inc. Memory and method for sensing data in a memory using complementary sensing scheme
US7606057B2 (en) * 2006-05-31 2009-10-20 Arm Limited Metal line layout in a memory cell
US8009461B2 (en) * 2008-01-07 2011-08-30 International Business Machines Corporation SRAM device, and SRAM device design structure, with adaptable access transistors
US7864600B2 (en) * 2008-06-19 2011-01-04 Texas Instruments Incorporated Memory cell employing reduced voltage
US8339882B2 (en) * 2010-07-12 2012-12-25 Promos Technologies Pte. Ltd. Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM
KR101736383B1 (ko) * 2010-08-03 2017-05-30 삼성전자주식회사 메모리 장치, 이의 프리차지 제어 방법, 및 이를 포함하는 장치들
JP2012119013A (ja) * 2010-11-29 2012-06-21 Toshiba Corp 不揮発性半導体記憶装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3593037A (en) * 1970-03-13 1971-07-13 Intel Corp Cell for mos random-acess integrated circuit memory
US3706891A (en) * 1971-06-17 1972-12-19 Ibm A. c. stable storage cell
BE788583A (fr) * 1971-09-16 1973-01-02 Intel Corp Cellule a trois lignes pour memoire a circuit integre a acces aleatoir
JPS5154789A (enExample) * 1974-11-09 1976-05-14 Nippon Electric Co
KR950001424B1 (en) 1986-03-28 1995-02-24 Hitachi Ltd 3-transistor dynamic random access memory
JP2615011B2 (ja) * 1986-06-13 1997-05-28 株式会社日立製作所 半導体記憶回路
US4945393A (en) * 1988-06-21 1990-07-31 At&T Bell Laboratories Floating gate memory circuit and apparatus
US4879682A (en) 1988-09-15 1989-11-07 Motorola, Inc. Sense amplifier precharge control
JP2837682B2 (ja) * 1989-01-13 1998-12-16 株式会社日立製作所 半導体記憶装置
JPH05250875A (ja) * 1992-02-27 1993-09-28 Nec Corp 半導体記憶装置
KR950005095Y1 (ko) * 1992-03-18 1995-06-22 문정환 양방향성 그로벌 비트 라인을 갖는 dram
US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
KR970012770A (ko) * 1995-08-08 1997-03-29 김광호 불 휘발성 반도체 메모리 장치의 증폭회로
JP3241280B2 (ja) * 1996-11-19 2001-12-25 株式会社東芝 ダイナミック型半導体記憶装置
KR19980037417A (ko) * 1996-11-21 1998-08-05 김광호 폴디드 비트라인 구조를 갖는 불휘발성 반도체 메모리 장치의 프로그램방법
US6016268A (en) * 1997-02-18 2000-01-18 Richard Mann Three transistor multi-state dynamic memory cell for embedded CMOS logic applications
JPH11134866A (ja) * 1997-10-27 1999-05-21 Matsushita Electric Ind Co Ltd 半導体記憶装置
FR2778012B1 (fr) * 1998-04-28 2001-09-28 Sgs Thomson Microelectronics Dispositif et procede de lecture de cellules de memoire eeprom
KR20000019073A (ko) * 1998-09-08 2000-04-06 윤종용 인접 비트라인간 누화 잡음을 개선한 반도체메모리장치
KR100619580B1 (ko) * 1999-05-14 2006-09-05 가부시키가이샤 히타치세이사쿠쇼 반도체 집적회로장치
JP2001291389A (ja) * 2000-03-31 2001-10-19 Hitachi Ltd 半導体集積回路

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100793671B1 (ko) * 2002-02-07 2008-01-10 후지쯔 가부시끼가이샤 반도체 기억 장치 및 프리차지 방법
JP2007058957A (ja) * 2005-08-23 2007-03-08 Toshiba Corp 半導体記憶装置
JP2007257682A (ja) * 2006-03-20 2007-10-04 Sony Corp 半導体メモリデバイスとその動作方法
US7558134B2 (en) 2006-03-20 2009-07-07 Sony Corporation Semiconductor memory device and its operation method
KR100808589B1 (ko) 2006-04-11 2008-02-29 주식회사 하이닉스반도체 반도체 메모리 장치의 입출력 라인 프리차지 회로
JP2008034007A (ja) * 2006-07-27 2008-02-14 Sony Corp 半導体メモリデバイス
US7486571B2 (en) 2006-07-27 2009-02-03 Sony Corporation Semiconductor memory device
WO2012008286A1 (en) * 2010-07-16 2012-01-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8576636B2 (en) 2010-07-16 2013-11-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2017120683A (ja) * 2011-12-02 2017-07-06 株式会社半導体エネルギー研究所 記憶装置の駆動方法

Also Published As

Publication number Publication date
US6519195B2 (en) 2003-02-11
KR20010094995A (ko) 2001-11-03
US20030090948A1 (en) 2003-05-15
US6829186B2 (en) 2004-12-07
US20050088886A1 (en) 2005-04-28
US20040057311A1 (en) 2004-03-25
TW536711B (en) 2003-06-11
US20010048617A1 (en) 2001-12-06
US6614696B2 (en) 2003-09-02

Similar Documents

Publication Publication Date Title
JP2001291389A (ja) 半導体集積回路
US7969765B2 (en) Sense amplifier for semiconductor memory device
KR900008936B1 (ko) Cmos 다이내믹램
KR100887333B1 (ko) 반도체기억장치
JP2611504B2 (ja) 半導体メモリ
JP3781270B2 (ja) 半導体集積回路装置
US8520449B2 (en) Semiconductor device and control method thereof
US9177619B2 (en) Semiconductor device having hierarchical bit line structure
JPH04370596A (ja) 高速センシング動作を実行するセンスアンプ
JPWO2000070682A1 (ja) 半導体集積回路装置
JP2007042172A (ja) 半導体メモリ装置
JPH10302469A (ja) 半導体記憶装置
US6292417B1 (en) Memory device with reduced bit line pre-charge voltage
JP3636233B2 (ja) ワードドライバ回路及びそれを利用したメモリ回路
US20010012214A1 (en) Semiconductor memory device
US7733681B2 (en) Ferroelectric memory with amplification between sub bit-line and main bit-line
JP2019109954A (ja) 半導体記憶装置
JP2003257181A (ja) 半導体装置
US6690198B2 (en) Repeater with reduced power consumption
JP2004171742A (ja) 半導体装置
US5574696A (en) Dynamic ram device having high read operation speed
JP4338045B2 (ja) 半導体集積回路
US6219269B1 (en) Semiconductor memory device capable of improving read operation speed
CN100541660C (zh) 半导体存储器件
JP2001014852A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040227

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040227

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20040227

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060517

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060712

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070124

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070523