KR101338841B1 - 에칭 프로세스를 위한 안정화된 포토레지스트 구조 - Google Patents

에칭 프로세스를 위한 안정화된 포토레지스트 구조 Download PDF

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Publication number
KR101338841B1
KR101338841B1 KR1020137001215A KR20137001215A KR101338841B1 KR 101338841 B1 KR101338841 B1 KR 101338841B1 KR 1020137001215 A KR1020137001215 A KR 1020137001215A KR 20137001215 A KR20137001215 A KR 20137001215A KR 101338841 B1 KR101338841 B1 KR 101338841B1
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South Korea
Prior art keywords
mask
layer
forming
etching
sidewall
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR1020137001215A
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English (en)
Korean (ko)
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KR20130025942A (ko
Inventor
에스 엠 레자 사드자디
에릭 에이 허드슨
피터 시리글리아노
김지수
지쑹 후앙
Original Assignee
램 리써치 코포레이션
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Priority claimed from US11/076,087 external-priority patent/US7241683B2/en
Application filed by 램 리써치 코포레이션 filed Critical 램 리써치 코포레이션
Publication of KR20130025942A publication Critical patent/KR20130025942A/ko
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Publication of KR101338841B1 publication Critical patent/KR101338841B1/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor

Landscapes

  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020137001215A 2005-03-08 2006-03-02 에칭 프로세스를 위한 안정화된 포토레지스트 구조 Expired - Fee Related KR101338841B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/076,087 US7241683B2 (en) 2005-03-08 2005-03-08 Stabilized photoresist structure for etching process
US11/076,087 2005-03-08
US11/223,363 US7491647B2 (en) 2005-03-08 2005-09-09 Etch with striation control
US11/223,363 2005-09-09
PCT/US2006/007643 WO2006096528A2 (en) 2005-03-08 2006-03-02 Stabilized photoresist structure for etching process

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020077022854A Division KR101274382B1 (ko) 2005-03-08 2006-03-02 에칭 프로세스를 위한 안정화된 포토레지스트 구조

Publications (2)

Publication Number Publication Date
KR20130025942A KR20130025942A (ko) 2013-03-12
KR101338841B1 true KR101338841B1 (ko) 2013-12-06

Family

ID=36782308

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020137001215A Expired - Fee Related KR101338841B1 (ko) 2005-03-08 2006-03-02 에칭 프로세스를 위한 안정화된 포토레지스트 구조
KR1020077022854A Expired - Fee Related KR101274382B1 (ko) 2005-03-08 2006-03-02 에칭 프로세스를 위한 안정화된 포토레지스트 구조

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020077022854A Expired - Fee Related KR101274382B1 (ko) 2005-03-08 2006-03-02 에칭 프로세스를 위한 안정화된 포토레지스트 구조

Country Status (8)

Country Link
US (2) US7491647B2 (https=)
EP (1) EP1856717A2 (https=)
JP (2) JP5070196B2 (https=)
KR (2) KR101338841B1 (https=)
IL (1) IL185743A (https=)
SG (1) SG144148A1 (https=)
TW (1) TWI396938B (https=)
WO (1) WO2006096528A2 (https=)

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US20090191711A1 (en) * 2008-01-30 2009-07-30 Ying Rui Hardmask open process with enhanced cd space shrink and reduction
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JP5260356B2 (ja) 2009-03-05 2013-08-14 東京エレクトロン株式会社 基板処理方法
JP5662079B2 (ja) * 2010-02-24 2015-01-28 東京エレクトロン株式会社 エッチング処理方法
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CN105493255B (zh) 2013-08-27 2021-04-20 东京毅力科创株式会社 用于横向裁剪硬掩模的方法
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US9852924B1 (en) * 2016-08-24 2017-12-26 Lam Research Corporation Line edge roughness improvement with sidewall sputtering
JP6877290B2 (ja) * 2017-08-03 2021-05-26 東京エレクトロン株式会社 被処理体を処理する方法
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
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JP7323409B2 (ja) * 2019-10-01 2023-08-08 東京エレクトロン株式会社 基板処理方法、及び、プラズマ処理装置
JP2021174902A (ja) * 2020-04-27 2021-11-01 東京エレクトロン株式会社 処理方法及び基板処理装置
JP7320554B2 (ja) * 2021-04-27 2023-08-03 株式会社アルバック エッチング方法
CN120809574B (zh) * 2025-09-16 2025-11-21 上海邦芯半导体科技有限公司 硬掩膜刻蚀方法及刻蚀设备

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Also Published As

Publication number Publication date
IL185743A (en) 2010-12-30
EP1856717A2 (en) 2007-11-21
TW200702900A (en) 2007-01-16
WO2006096528A3 (en) 2006-12-07
US7491647B2 (en) 2009-02-17
IL185743A0 (en) 2008-01-06
JP5070196B2 (ja) 2012-11-07
SG144148A1 (en) 2008-07-29
KR20070116076A (ko) 2007-12-06
JP2012151510A (ja) 2012-08-09
JP2008538857A (ja) 2008-11-06
US20090121324A1 (en) 2009-05-14
WO2006096528A2 (en) 2006-09-14
KR20130025942A (ko) 2013-03-12
US20060194439A1 (en) 2006-08-31
KR101274382B1 (ko) 2013-06-14
TWI396938B (zh) 2013-05-21

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