TWI396938B - 形成特徵於蝕刻層中之方法及裝置 - Google Patents

形成特徵於蝕刻層中之方法及裝置 Download PDF

Info

Publication number
TWI396938B
TWI396938B TW095107616A TW95107616A TWI396938B TW I396938 B TWI396938 B TW I396938B TW 095107616 A TW095107616 A TW 095107616A TW 95107616 A TW95107616 A TW 95107616A TW I396938 B TWI396938 B TW I396938B
Authority
TW
Taiwan
Prior art keywords
mask
sidewall
layer
photoresist
gas
Prior art date
Application number
TW095107616A
Other languages
English (en)
Chinese (zh)
Other versions
TW200702900A (en
Inventor
沙加地 史
西瑞葛利諾 彼得
金知洙
黃興頌
哈德森 艾瑞克
Original Assignee
泛林股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/076,087 external-priority patent/US7241683B2/en
Application filed by 泛林股份有限公司 filed Critical 泛林股份有限公司
Publication of TW200702900A publication Critical patent/TW200702900A/zh
Application granted granted Critical
Publication of TWI396938B publication Critical patent/TWI396938B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
TW095107616A 2005-03-08 2006-03-07 形成特徵於蝕刻層中之方法及裝置 TWI396938B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/076,087 US7241683B2 (en) 2005-03-08 2005-03-08 Stabilized photoresist structure for etching process
US11/223,363 US7491647B2 (en) 2005-03-08 2005-09-09 Etch with striation control

Publications (2)

Publication Number Publication Date
TW200702900A TW200702900A (en) 2007-01-16
TWI396938B true TWI396938B (zh) 2013-05-21

Family

ID=36782308

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095107616A TWI396938B (zh) 2005-03-08 2006-03-07 形成特徵於蝕刻層中之方法及裝置

Country Status (8)

Country Link
US (2) US7491647B2 (https=)
EP (1) EP1856717A2 (https=)
JP (2) JP5070196B2 (https=)
KR (2) KR101274382B1 (https=)
IL (1) IL185743A (https=)
SG (1) SG144148A1 (https=)
TW (1) TWI396938B (https=)
WO (1) WO2006096528A2 (https=)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7273815B2 (en) * 2005-08-18 2007-09-25 Lam Research Corporation Etch features with reduced line edge roughness
US7682516B2 (en) * 2005-10-05 2010-03-23 Lam Research Corporation Vertical profile fixing
US7264743B2 (en) * 2006-01-23 2007-09-04 Lam Research Corporation Fin structure formation
US7491343B2 (en) * 2006-09-14 2009-02-17 Lam Research Corporation Line end shortening reduction during etch
US7309646B1 (en) * 2006-10-10 2007-12-18 Lam Research Corporation De-fluoridation process
US7902073B2 (en) * 2006-12-14 2011-03-08 Lam Research Corporation Glue layer for hydrofluorocarbon etch
US8283255B2 (en) * 2007-05-24 2012-10-09 Lam Research Corporation In-situ photoresist strip during plasma etching of active hard mask
US7981812B2 (en) * 2007-07-08 2011-07-19 Applied Materials, Inc. Methods for forming ultra thin structures on a substrate
US20100330805A1 (en) * 2007-11-02 2010-12-30 Kenny Linh Doan Methods for forming high aspect ratio features on a substrate
US20090191711A1 (en) * 2008-01-30 2009-07-30 Ying Rui Hardmask open process with enhanced cd space shrink and reduction
KR101025741B1 (ko) * 2008-09-02 2011-04-04 주식회사 하이닉스반도체 수직 채널 트랜지스터의 활성필라 제조방법
JP5260356B2 (ja) * 2009-03-05 2013-08-14 東京エレクトロン株式会社 基板処理方法
US9373521B2 (en) 2010-02-24 2016-06-21 Tokyo Electron Limited Etching processing method
JP5662079B2 (ja) * 2010-02-24 2015-01-28 東京エレクトロン株式会社 エッチング処理方法
US8304262B2 (en) * 2011-02-17 2012-11-06 Lam Research Corporation Wiggling control for pseudo-hardmask
KR101867998B1 (ko) * 2011-06-14 2018-06-15 삼성전자주식회사 패턴 형성 방법
WO2013145509A1 (ja) * 2012-03-27 2013-10-03 シャープ株式会社 ウエハ処理方法、ウエハ処理装置および半導体発光素子の製造方法
KR20160044545A (ko) 2013-08-27 2016-04-25 도쿄엘렉트론가부시키가이샤 하드마스크를 측면으로 트리밍하기 위한 방법
US9269587B2 (en) 2013-09-06 2016-02-23 Applied Materials, Inc. Methods for etching materials using synchronized RF pulses
GB201322931D0 (en) * 2013-12-23 2014-02-12 Spts Technologies Ltd Method of etching
US9659771B2 (en) * 2015-06-11 2017-05-23 Applied Materials, Inc. Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning
US9922839B2 (en) * 2015-06-23 2018-03-20 Lam Research Corporation Low roughness EUV lithography
US9852924B1 (en) * 2016-08-24 2017-12-26 Lam Research Corporation Line edge roughness improvement with sidewall sputtering
JP6877290B2 (ja) * 2017-08-03 2021-05-26 東京エレクトロン株式会社 被処理体を処理する方法
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
US10734238B2 (en) * 2017-11-21 2020-08-04 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for critical dimension control
US11114306B2 (en) 2018-09-17 2021-09-07 Applied Materials, Inc. Methods for depositing dielectric material
JP7323409B2 (ja) * 2019-10-01 2023-08-08 東京エレクトロン株式会社 基板処理方法、及び、プラズマ処理装置
JP2021174902A (ja) * 2020-04-27 2021-11-01 東京エレクトロン株式会社 処理方法及び基板処理装置
JP7320554B2 (ja) * 2021-04-27 2023-08-03 株式会社アルバック エッチング方法
CN120809574B (zh) * 2025-09-16 2025-11-21 上海邦芯半导体科技有限公司 硬掩膜刻蚀方法及刻蚀设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025255A (en) * 1998-06-25 2000-02-15 Vanguard International Semiconductor Corporation Two-step etching process for forming self-aligned contacts
TW538449B (en) * 2001-01-16 2003-06-21 Osram Opto Semiconductors Gmbh Method to form an etching-mask
TWI224557B (en) * 1999-04-26 2004-12-01 United Microelectronics Corp Etching process for low-k organic film

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3437863B2 (ja) 1993-01-18 2003-08-18 株式会社半導体エネルギー研究所 Ｍｉｓ型半導体装置の作製方法
JPS5378170A (en) 1976-12-22 1978-07-11 Toshiba Corp Continuous processor for gas plasma etching
US4414059A (en) 1982-12-09 1983-11-08 International Business Machines Corporation Far UV patterning of resist materials
JPS6313334A (ja) 1986-07-04 1988-01-20 Hitachi Ltd ドライエツチング方法
KR900007687B1 (ko) 1986-10-17 1990-10-18 가부시기가이샤 히다찌세이사꾸쇼 플라즈마처리방법 및 장치
JPH0219852A (ja) * 1988-07-07 1990-01-23 Matsushita Electric Ind Co Ltd レジスト処理方法
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
US5273609A (en) 1990-09-12 1993-12-28 Texas Instruments Incorporated Method and apparatus for time-division plasma chopping in a multi-channel plasma processing equipment
DE4241045C1 (de) 1992-12-05 1994-05-26 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silicium
US5296410A (en) 1992-12-16 1994-03-22 Samsung Electronics Co., Ltd. Method for separating fine patterns of a semiconductor device
JPH07226397A (ja) 1994-02-10 1995-08-22 Tokyo Electron Ltd エッチング処理方法
DE4317623C2 (de) 1993-05-27 2003-08-21 Bosch Gmbh Robert Verfahren und Vorrichtung zum anisotropen Plasmaätzen von Substraten und dessen Verwendung
US5562801A (en) 1994-04-28 1996-10-08 Cypress Semiconductor Corporation Method of etching an oxide layer
JPH0936089A (ja) 1995-07-19 1997-02-07 Toshiba Corp アッシング方法及びその装置
GB9616225D0 (en) 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
EP0822582B1 (en) 1996-08-01 2003-10-01 Surface Technology Systems Plc Method of etching substrates
DE19641288A1 (de) 1996-10-07 1998-04-09 Bosch Gmbh Robert Verfahren zum anisotropen Plasmaätzen verschiedener Substrate
US5882535A (en) 1997-02-04 1999-03-16 Micron Technology, Inc. Method for forming a hole in a semiconductor device
DE19706682C2 (de) 1997-02-20 1999-01-14 Bosch Gmbh Robert Anisotropes fluorbasiertes Plasmaätzverfahren für Silizium
US6153490A (en) 1997-07-01 2000-11-28 Texas Instruments Incorporated Method for forming integrated circuit capacitor and memory
DE19730644C1 (de) 1997-07-17 1998-11-19 Bosch Gmbh Robert Verfahren zum Erkennen des Übergangs unterschiedlicher Materialien in Halbleiterstrukturen bei einer anisotropen Tiefenätzung
US6187685B1 (en) 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
DE19734278C1 (de) 1997-08-07 1999-02-25 Bosch Gmbh Robert Vorrichtung zum anisotropen Ätzen von Substraten
DE19736370C2 (de) 1997-08-21 2001-12-06 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silizium
US5942446A (en) 1997-09-12 1999-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer
US6074959A (en) 1997-09-19 2000-06-13 Applied Materials, Inc. Method manifesting a wide process window and using hexafluoropropane or other hydrofluoropropanes to selectively etch oxide
US5849639A (en) 1997-11-26 1998-12-15 Lucent Technologies Inc. Method for removing etching residues and contaminants
KR100520148B1 (ko) 1997-12-31 2006-05-12 주식회사 하이닉스반도체 신규한바이시클로알켄유도체와이를이용한포토레지스트중합체및이중합체를함유한포토레지스트조성물
US6387287B1 (en) 1998-03-27 2002-05-14 Applied Materials, Inc. Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window
US6071822A (en) 1998-06-08 2000-06-06 Plasma-Therm, Inc. Etching process for producing substantially undercut free silicon on insulator structures
US6211092B1 (en) 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
US6406995B1 (en) 1998-09-30 2002-06-18 Intel Corporation Pattern-sensitive deposition for damascene processing
US6100200A (en) 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6316169B1 (en) 1999-06-25 2001-11-13 Lam Research Corporation Methods for reducing profile variation in photoresist trimming
US6235453B1 (en) 1999-07-07 2001-05-22 Advanced Micro Devices, Inc. Low-k photoresist removal process
KR100327346B1 (ko) 1999-07-20 2002-03-06 윤종용 선택적 폴리머 증착을 이용한 플라즈마 식각방법 및 이를이용한 콘택홀 형성방법
US6368974B1 (en) 1999-08-02 2002-04-09 United Microelectronics Corp. Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching
WO2001029879A2 (en) 1999-10-20 2001-04-26 Mattson Technology, Inc. Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
US6326307B1 (en) 1999-11-15 2001-12-04 Appllied Materials, Inc. Plasma pretreatment of photoresist in an oxide etch process
US6569774B1 (en) 2000-08-31 2003-05-27 Micron Technology, Inc. Method to eliminate striations and surface roughness caused by dry etch
US6403491B1 (en) 2000-11-01 2002-06-11 Applied Materials, Inc. Etch method using a dielectric etch chamber with expanded process window
DE10059836A1 (de) 2000-12-01 2002-06-13 Infineon Technologies Ag Verfahren zur Strukturierung dielektrischer Schichten
TW502300B (en) * 2001-09-28 2002-09-11 Macronix Int Co Ltd Method of reducing pattern spacing or opening dimension
US6656282B2 (en) 2001-10-11 2003-12-02 Moohan Co., Ltd. Atomic layer deposition apparatus and process using remote plasma
US6750150B2 (en) 2001-10-18 2004-06-15 Macronix International Co., Ltd. Method for reducing dimensions between patterns on a photoresist
KR100448714B1 (ko) 2002-04-24 2004-09-13 삼성전자주식회사 다층 나노라미네이트 구조를 갖는 반도체 장치의 절연막및 그의 형성방법
US6713396B2 (en) * 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6924191B2 (en) 2002-06-20 2005-08-02 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor
JP3878577B2 (ja) * 2003-06-06 2007-02-07 株式会社東芝 半導体装置の製造方法
US7169695B2 (en) 2002-10-11 2007-01-30 Lam Research Corporation Method for forming a dual damascene structure
US6833325B2 (en) 2002-10-11 2004-12-21 Lam Research Corporation Method for plasma etching performance enhancement
US7090967B2 (en) 2002-12-30 2006-08-15 Infineon Technologies Ag Pattern transfer in device fabrication
US6780708B1 (en) 2003-03-05 2004-08-24 Advanced Micro Devices, Inc. Method of forming core and periphery gates including two critical masking steps to form a hard mask in a core region that includes a critical dimension less than achievable at a resolution limit of lithography
US7294580B2 (en) * 2003-04-09 2007-11-13 Lam Research Corporation Method for plasma stripping using periodic modulation of gas chemistry and hydrocarbon addition
US6916746B1 (en) 2003-04-09 2005-07-12 Lam Research Corporation Method for plasma etching using periodic modulation of gas chemistry
US7250371B2 (en) * 2003-08-26 2007-07-31 Lam Research Corporation Reduction of feature critical dimensions
JP4538209B2 (ja) 2003-08-28 2010-09-08 株式会社日立ハイテクノロジーズ 半導体装置の製造方法
US7298004B2 (en) 2004-11-30 2007-11-20 Infineon Technologies Ag Charge-trapping memory cell and method for production
US20060134917A1 (en) * 2004-12-16 2006-06-22 Lam Research Corporation Reduction of etch mask feature critical dimensions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025255A (en) * 1998-06-25 2000-02-15 Vanguard International Semiconductor Corporation Two-step etching process for forming self-aligned contacts
TWI224557B (en) * 1999-04-26 2004-12-01 United Microelectronics Corp Etching process for low-k organic film
TW538449B (en) * 2001-01-16 2003-06-21 Osram Opto Semiconductors Gmbh Method to form an etching-mask

Also Published As

Publication number Publication date
US7491647B2 (en) 2009-02-17
TW200702900A (en) 2007-01-16
JP5070196B2 (ja) 2012-11-07
US20060194439A1 (en) 2006-08-31
KR101338841B1 (ko) 2013-12-06
US20090121324A1 (en) 2009-05-14
IL185743A0 (en) 2008-01-06
WO2006096528A3 (en) 2006-12-07
JP2012151510A (ja) 2012-08-09
IL185743A (en) 2010-12-30
KR20070116076A (ko) 2007-12-06
KR101274382B1 (ko) 2013-06-14
WO2006096528A2 (en) 2006-09-14
SG144148A1 (en) 2008-07-29
JP2008538857A (ja) 2008-11-06
EP1856717A2 (en) 2007-11-21
KR20130025942A (ko) 2013-03-12

Similar Documents

Publication Publication Date Title
TWI396938B (zh) 形成特徵於蝕刻層中之方法及裝置
CN100530541C (zh) 用于蚀刻工艺的稳定的光致抗蚀剂结构
CN100568458C (zh) 使用多个掩模步骤减小临界尺寸的方法
JP5081917B2 (ja) フッ素除去プロセス
CN101595551B (zh) 临界尺寸减小及粗糙度控制
TWI388008B (zh) 遮罩修整
CN100543946C (zh) 蚀刻掩模特征临界尺寸的减小
KR101516455B1 (ko) Ａｒｌ 에칭을 이용한 마스크 트리밍
JP2013016844A (ja) 均一性を制御したエッチング
TWI424490B (zh) 垂直輪廓修正

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees