KR101123377B1 - 화학 기계적 연마 평탄화를 위한 이중 실리콘 게이트 층을구비한 ｆｉｎｆｅｔ - Google Patents

화학 기계적 연마 평탄화를 위한 이중 실리콘 게이트 층을구비한 ｆｉｎｆｅｔ Download PDF

Info

Publication number
KR101123377B1
KR101123377B1 KR1020057023790A KR20057023790A KR101123377B1 KR 101123377 B1 KR101123377 B1 KR 101123377B1 KR 1020057023790 A KR1020057023790 A KR 1020057023790A KR 20057023790 A KR20057023790 A KR 20057023790A KR 101123377 B1 KR101123377 B1 KR 101123377B1
Authority
KR
South Korea
Prior art keywords
layer
gate
fin
gate structure
planarization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020057023790A
Other languages
English (en)
Korean (ko)
Other versions
KR20060013570A (ko
Inventor
크리쉬나쉬리 아츄싼
쉬블리 에스. 아메드
하이홍 왕
빈 유
Original Assignee
글로벌파운드리즈 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 글로벌파운드리즈 인크. filed Critical 글로벌파운드리즈 인크.
Publication of KR20060013570A publication Critical patent/KR20060013570A/ko
Application granted granted Critical
Publication of KR101123377B1 publication Critical patent/KR101123377B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0243—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020057023790A 2003-06-12 2004-06-05 화학 기계적 연마 평탄화를 위한 이중 실리콘 게이트 층을구비한 ｆｉｎｆｅｔ Expired - Fee Related KR101123377B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/459,579 US6756643B1 (en) 2003-06-12 2003-06-12 Dual silicon layer for chemical mechanical polishing planarization
US10/459,579 2003-06-12
PCT/US2004/017725 WO2004112146A1 (en) 2003-06-12 2004-06-05 Finfet with dual silicon gate layer for chemical mechanical polishing planarization

Publications (2)

Publication Number Publication Date
KR20060013570A KR20060013570A (ko) 2006-02-10
KR101123377B1 true KR101123377B1 (ko) 2012-03-27

Family

ID=32508107

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057023790A Expired - Fee Related KR101123377B1 (ko) 2003-06-12 2004-06-05 화학 기계적 연마 평탄화를 위한 이중 실리콘 게이트 층을구비한 ｆｉｎｆｅｔ

Country Status (8)

Country Link
US (3) US6756643B1 (enExample)
JP (1) JP2007500952A (enExample)
KR (1) KR101123377B1 (enExample)
CN (1) CN100477258C (enExample)
DE (1) DE112004001030B4 (enExample)
GB (1) GB2418534B (enExample)
TW (1) TWI338328B (enExample)
WO (1) WO2004112146A1 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091068B1 (en) * 2002-12-06 2006-08-15 Advanced Micro Devices, Inc. Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
US7192876B2 (en) * 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization
US7087506B2 (en) * 2003-06-26 2006-08-08 International Business Machines Corporation Method of forming freestanding semiconductor layer
US7224029B2 (en) * 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
US7701018B2 (en) * 2004-03-19 2010-04-20 Nec Corporation Semiconductor device and method for manufacturing same
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7388257B2 (en) * 2004-09-01 2008-06-17 International Business Machines Corporation Multi-gate device with high k dielectric for channel top surface
KR100678476B1 (ko) 2005-04-21 2007-02-02 삼성전자주식회사 씬 바디의 활성 영역 상에 적어도 두 개의 게이트 실리콘 패턴들을 갖는 더블 게이트 트랜지스터들 및 그 형성방법들
KR100657824B1 (ko) 2005-12-27 2006-12-14 주식회사 하이닉스반도체 핀 트랜지스터 및 그 제조 방법
CN101490822B (zh) * 2006-07-11 2011-03-16 Nxp股份有限公司 半导体器件及其制造方法
US8203182B2 (en) * 2007-03-14 2012-06-19 Nxp B.V. FinFET with two independent gates and method for fabricating the same
JP5371144B2 (ja) * 2007-06-29 2013-12-18 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の作製方法、並びに電子機器
US20090050975A1 (en) * 2007-08-21 2009-02-26 Andres Bryant Active Silicon Interconnect in Merged Finfet Process
US8497210B2 (en) 2010-10-04 2013-07-30 International Business Machines Corporation Shallow trench isolation chemical mechanical planarization
CN102479701B (zh) * 2010-11-30 2015-06-24 中国科学院微电子研究所 化学机械平坦化方法和后金属栅的制作方法
US8252689B2 (en) 2010-11-30 2012-08-28 Institute of Microelectronics, Chinese Academy of Sciences Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process
US20130189841A1 (en) * 2012-01-20 2013-07-25 Applied Materials, Inc. Engineering dielectric films for cmp stop
US9647066B2 (en) 2012-04-24 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy FinFET structure and method of making same
CN103426757B (zh) * 2012-05-15 2016-01-06 中芯国际集成电路制造(上海)有限公司 Ω形鳍式场效应晶体管的形成方法
CN103489780B (zh) * 2012-06-13 2016-02-17 中芯国际集成电路制造(上海)有限公司 鳍式场效应管基体的形成方法及鳍式场效应管
CN104008967B (zh) * 2013-02-25 2017-06-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9087796B2 (en) 2013-02-26 2015-07-21 International Business Machines Corporation Semiconductor fabrication method using stop layer
KR20150021811A (ko) * 2013-08-21 2015-03-03 삼성전자주식회사 반도체 소자의 제조방법
US20150200111A1 (en) * 2014-01-13 2015-07-16 Globalfoundries Inc. Planarization scheme for finfet gate height uniformity control
US9472572B2 (en) * 2014-05-06 2016-10-18 Globalfoundries Inc. Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins
CN105161418B (zh) * 2014-06-12 2019-04-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
US9773871B2 (en) * 2015-11-16 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
KR102647695B1 (ko) * 2016-08-12 2024-03-14 삼성디스플레이 주식회사 트랜지스터 표시판 및 그 제조 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010036731A1 (en) * 1999-12-09 2001-11-01 Muller K. Paul L. Process for making planarized silicon fin device
US20020130354A1 (en) * 2001-03-13 2002-09-19 National Inst. Of Advanced Ind. Science And Tech. Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260647A (ja) * 1993-03-04 1994-09-16 Sony Corp Ｘｍｏｓトランジスタの作製方法
JP2823819B2 (ja) * 1994-06-27 1998-11-11 松下電器産業株式会社 半導体装置およびその製造方法
JP3607431B2 (ja) * 1996-09-18 2005-01-05 株式会社東芝 半導体装置およびその製造方法
JP4389359B2 (ja) * 2000-06-23 2009-12-24 日本電気株式会社 薄膜トランジスタ及びその製造方法
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6787439B2 (en) * 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010036731A1 (en) * 1999-12-09 2001-11-01 Muller K. Paul L. Process for making planarized silicon fin device
US20020130354A1 (en) * 2001-03-13 2002-09-19 National Inst. Of Advanced Ind. Science And Tech. Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same

Also Published As

Publication number Publication date
TWI338328B (en) 2011-03-01
US20050056845A1 (en) 2005-03-17
US6982464B2 (en) 2006-01-03
DE112004001030B4 (de) 2008-09-25
CN100477258C (zh) 2009-04-08
US6812076B1 (en) 2004-11-02
TW200503095A (en) 2005-01-16
WO2004112146A1 (en) 2004-12-23
KR20060013570A (ko) 2006-02-10
GB0524314D0 (en) 2006-01-04
GB2418534B (en) 2007-01-31
JP2007500952A (ja) 2007-01-18
GB2418534A (en) 2006-03-29
DE112004001030T5 (de) 2006-06-01
US6756643B1 (en) 2004-06-29
CN1806340A (zh) 2006-07-19

Similar Documents

Publication Publication Date Title
KR101123377B1 (ko) 화학 기계적 연마 평탄화를 위한 이중 실리콘 게이트 층을구비한 ｆｉｎｆｅｔ
KR101062986B1 (ko) Ｆｉｎｆｅｔ내의 게이트 영역의 다단계 화학 기계 연마
US6764884B1 (en) Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
KR100993937B1 (ko) Ｕ-형태의 게이트 구조를 가지는 반도체 디바이스
US7432557B1 (en) FinFET device with multiple channels
KR100817949B1 (ko) 반도체 디바이스, 반도체 디바이스 제조 방법 및 비평면 트랜지스터 제조 방법
US6027998A (en) Method for fully planarized conductive line for a stack gate
KR100874960B1 (ko) 고 이동도 반도체 어셈블리, 고 이동도 반도체 기판 및 고이동도 반도체 어셈블리의 제조 방법
KR101735976B1 (ko) 트랜지스터 게이트용 캡핑 유전체 구조를 형성하는 방법
KR101707720B1 (ko) 장치, 소자 및 그 제조 방법
US7892911B2 (en) Metal gate electrodes for replacement gate integration scheme
US20040126975A1 (en) Double gate semiconductor device having separate gates
TWI744006B (zh) 記憶體元件及其製造方法
US20050056881A1 (en) Dummy pattern for silicide gate electrode
KR20050096156A (ko) 좁은 핀 ｆｉｎｆｅｔ
KR20050118717A (ko) ＦｉｎＦＥＴ 디바이스 구조의 형성 방법
JP7018963B2 (ja) Ｖｆｅｔアーキテクチャ内の超長チャネル・デバイス
US11942375B2 (en) Structure and formation method of semiconductor device with fin structures
CN110571333B (zh) 一种无掺杂晶体管器件制作方法
US6876042B1 (en) Additional gate control for a double-gate MOSFET
US11810812B2 (en) Single diffusion cut for gate structures
JP2023554273A (ja) 局所化された金属シリサイドを含むラップ・アラウンド・コンタクト
CN102646588A (zh) 一种半导体器件的制作方法
JP2001085512A (ja) 半導体装置及び半導体装置の製造方法

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20150130

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20160127

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20170228

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20170228

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000