CN100477258C - 用于化学机械研磨平面化的双硅层鳍状场效应晶体管 - Google Patents
用于化学机械研磨平面化的双硅层鳍状场效应晶体管 Download PDFInfo
- Publication number
- CN100477258C CN100477258C CNB2004800161347A CN200480016134A CN100477258C CN 100477258 C CN100477258 C CN 100477258C CN B2004800161347 A CNB2004800161347 A CN B2004800161347A CN 200480016134 A CN200480016134 A CN 200480016134A CN 100477258 C CN100477258 C CN 100477258C
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- layer
- semiconductor device
- fin structure
- gate
- fin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
- H10D30/0243—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6733—Multi-gate TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H10D30/6739—Conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/459,579 US6756643B1 (en) | 2003-06-12 | 2003-06-12 | Dual silicon layer for chemical mechanical polishing planarization |
| US10/459,579 | 2003-06-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1806340A CN1806340A (zh) | 2006-07-19 |
| CN100477258C true CN100477258C (zh) | 2009-04-08 |
Family
ID=32508107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800161347A Expired - Fee Related CN100477258C (zh) | 2003-06-12 | 2004-06-05 | 用于化学机械研磨平面化的双硅层鳍状场效应晶体管 |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US6756643B1 (enExample) |
| JP (1) | JP2007500952A (enExample) |
| KR (1) | KR101123377B1 (enExample) |
| CN (1) | CN100477258C (enExample) |
| DE (1) | DE112004001030B4 (enExample) |
| GB (1) | GB2418534B (enExample) |
| TW (1) | TWI338328B (enExample) |
| WO (1) | WO2004112146A1 (enExample) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7091068B1 (en) * | 2002-12-06 | 2006-08-15 | Advanced Micro Devices, Inc. | Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices |
| US7192876B2 (en) * | 2003-05-22 | 2007-03-20 | Freescale Semiconductor, Inc. | Transistor with independent gate structures |
| US6756643B1 (en) * | 2003-06-12 | 2004-06-29 | Advanced Micro Devices, Inc. | Dual silicon layer for chemical mechanical polishing planarization |
| US7087506B2 (en) * | 2003-06-26 | 2006-08-08 | International Business Machines Corporation | Method of forming freestanding semiconductor layer |
| US7224029B2 (en) * | 2004-01-28 | 2007-05-29 | International Business Machines Corporation | Method and structure to create multiple device widths in FinFET technology in both bulk and SOI |
| JPWO2005091374A1 (ja) * | 2004-03-19 | 2008-02-07 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| KR100541657B1 (ko) * | 2004-06-29 | 2006-01-11 | 삼성전자주식회사 | 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터 |
| US7388257B2 (en) * | 2004-09-01 | 2008-06-17 | International Business Machines Corporation | Multi-gate device with high k dielectric for channel top surface |
| KR100678476B1 (ko) | 2005-04-21 | 2007-02-02 | 삼성전자주식회사 | 씬 바디의 활성 영역 상에 적어도 두 개의 게이트 실리콘 패턴들을 갖는 더블 게이트 트랜지스터들 및 그 형성방법들 |
| KR100657824B1 (ko) | 2005-12-27 | 2006-12-14 | 주식회사 하이닉스반도체 | 핀 트랜지스터 및 그 제조 방법 |
| WO2008007331A2 (en) * | 2006-07-11 | 2008-01-17 | Nxp B.V. | Semiconductor devices and methods of manufacture thereof |
| US8203182B2 (en) * | 2007-03-14 | 2012-06-19 | Nxp B.V. | FinFET with two independent gates and method for fabricating the same |
| JP5371144B2 (ja) * | 2007-06-29 | 2013-12-18 | 株式会社半導体エネルギー研究所 | 半導体装置及び半導体装置の作製方法、並びに電子機器 |
| US20090050975A1 (en) * | 2007-08-21 | 2009-02-26 | Andres Bryant | Active Silicon Interconnect in Merged Finfet Process |
| US8497210B2 (en) | 2010-10-04 | 2013-07-30 | International Business Machines Corporation | Shallow trench isolation chemical mechanical planarization |
| CN102479701B (zh) * | 2010-11-30 | 2015-06-24 | 中国科学院微电子研究所 | 化学机械平坦化方法和后金属栅的制作方法 |
| US8252689B2 (en) | 2010-11-30 | 2012-08-28 | Institute of Microelectronics, Chinese Academy of Sciences | Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process |
| US20130189841A1 (en) * | 2012-01-20 | 2013-07-25 | Applied Materials, Inc. | Engineering dielectric films for cmp stop |
| US9647066B2 (en) | 2012-04-24 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy FinFET structure and method of making same |
| CN103426757B (zh) * | 2012-05-15 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Ω形鳍式场效应晶体管的形成方法 |
| CN103489780B (zh) * | 2012-06-13 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应管基体的形成方法及鳍式场效应管 |
| CN104008967B (zh) * | 2013-02-25 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
| US9087796B2 (en) | 2013-02-26 | 2015-07-21 | International Business Machines Corporation | Semiconductor fabrication method using stop layer |
| KR20150021811A (ko) * | 2013-08-21 | 2015-03-03 | 삼성전자주식회사 | 반도체 소자의 제조방법 |
| US20150200111A1 (en) * | 2014-01-13 | 2015-07-16 | Globalfoundries Inc. | Planarization scheme for finfet gate height uniformity control |
| US9472572B2 (en) * | 2014-05-06 | 2016-10-18 | Globalfoundries Inc. | Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins |
| CN105161418B (zh) * | 2014-06-12 | 2019-04-09 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法和电子装置 |
| US9773871B2 (en) | 2015-11-16 | 2017-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor and method for fabricating the same |
| KR102647695B1 (ko) * | 2016-08-12 | 2024-03-14 | 삼성디스플레이 주식회사 | 트랜지스터 표시판 및 그 제조 방법 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010036731A1 (en) * | 1999-12-09 | 2001-11-01 | Muller K. Paul L. | Process for making planarized silicon fin device |
| US20020130354A1 (en) * | 2001-03-13 | 2002-09-19 | National Inst. Of Advanced Ind. Science And Tech. | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same |
| US20020177263A1 (en) * | 2001-05-24 | 2002-11-28 | International Business Machines Corporation | Damascene double-gate MOSFET with vertical channel regions |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06260647A (ja) * | 1993-03-04 | 1994-09-16 | Sony Corp | Xmosトランジスタの作製方法 |
| JP2823819B2 (ja) * | 1994-06-27 | 1998-11-11 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
| JP3607431B2 (ja) * | 1996-09-18 | 2005-01-05 | 株式会社東芝 | 半導体装置およびその製造方法 |
| JP4389359B2 (ja) * | 2000-06-23 | 2009-12-24 | 日本電気株式会社 | 薄膜トランジスタ及びその製造方法 |
| JP3543117B2 (ja) * | 2001-03-13 | 2004-07-14 | 独立行政法人産業技術総合研究所 | 二重ゲート電界効果トランジスタ |
| US6689650B2 (en) * | 2001-09-27 | 2004-02-10 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
| US20030151077A1 (en) * | 2002-02-13 | 2003-08-14 | Leo Mathew | Method of forming a vertical double gate semiconductor device and structure thereof |
| US6642090B1 (en) * | 2002-06-03 | 2003-11-04 | International Business Machines Corporation | Fin FET devices from bulk semiconductor and method for forming |
| US6787439B2 (en) * | 2002-11-08 | 2004-09-07 | Advanced Micro Devices, Inc. | Method using planarizing gate material to improve gate critical dimension in semiconductor devices |
| US6611029B1 (en) * | 2002-11-08 | 2003-08-26 | Advanced Micro Devices, Inc. | Double gate semiconductor device having separate gates |
| US6645797B1 (en) * | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
| US6756643B1 (en) * | 2003-06-12 | 2004-06-29 | Advanced Micro Devices, Inc. | Dual silicon layer for chemical mechanical polishing planarization |
-
2003
- 2003-06-12 US US10/459,579 patent/US6756643B1/en not_active Expired - Lifetime
-
2004
- 2004-01-08 US US10/752,691 patent/US6812076B1/en not_active Expired - Fee Related
- 2004-06-05 DE DE112004001030T patent/DE112004001030B4/de not_active Expired - Fee Related
- 2004-06-05 CN CNB2004800161347A patent/CN100477258C/zh not_active Expired - Fee Related
- 2004-06-05 WO PCT/US2004/017725 patent/WO2004112146A1/en not_active Ceased
- 2004-06-05 JP JP2006533565A patent/JP2007500952A/ja not_active Ceased
- 2004-06-05 GB GB0524314A patent/GB2418534B/en not_active Expired - Fee Related
- 2004-06-05 KR KR1020057023790A patent/KR101123377B1/ko not_active Expired - Fee Related
- 2004-06-10 TW TW093116645A patent/TWI338328B/zh not_active IP Right Cessation
- 2004-10-29 US US10/975,473 patent/US6982464B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010036731A1 (en) * | 1999-12-09 | 2001-11-01 | Muller K. Paul L. | Process for making planarized silicon fin device |
| US20020130354A1 (en) * | 2001-03-13 | 2002-09-19 | National Inst. Of Advanced Ind. Science And Tech. | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same |
| US20020177263A1 (en) * | 2001-05-24 | 2002-11-28 | International Business Machines Corporation | Damascene double-gate MOSFET with vertical channel regions |
Non-Patent Citations (1)
| Title |
|---|
| 自对准双栅MOSFET的结构与工艺实现. 钱莉,李伟华.电子器件,第25卷第3期. 2002 * |
Also Published As
| Publication number | Publication date |
|---|---|
| DE112004001030B4 (de) | 2008-09-25 |
| TWI338328B (en) | 2011-03-01 |
| JP2007500952A (ja) | 2007-01-18 |
| GB2418534A (en) | 2006-03-29 |
| GB0524314D0 (en) | 2006-01-04 |
| KR20060013570A (ko) | 2006-02-10 |
| KR101123377B1 (ko) | 2012-03-27 |
| US6812076B1 (en) | 2004-11-02 |
| GB2418534B (en) | 2007-01-31 |
| CN1806340A (zh) | 2006-07-19 |
| US6756643B1 (en) | 2004-06-29 |
| WO2004112146A1 (en) | 2004-12-23 |
| DE112004001030T5 (de) | 2006-06-01 |
| US20050056845A1 (en) | 2005-03-17 |
| TW200503095A (en) | 2005-01-16 |
| US6982464B2 (en) | 2006-01-03 |
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| Date | Code | Title | Description |
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| C06 | Publication | ||
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: GLOBALFOUNDRIES SEMICONDUCTORS CO., LTD Free format text: FORMER OWNER: ADVANCED MICRO DEVICES CORPORATION Effective date: 20100722 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA STATE, THE USA TO: GRAND CAYMAN ISLAND, BRITISH CAYMAN ISLANDS |
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| TR01 | Transfer of patent right |
Effective date of registration: 20100722 Address after: Grand Cayman, Cayman Islands Patentee after: Globalfoundries Semiconductor Inc. Address before: American California Patentee before: Advanced Micro Devices Inc. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090408 Termination date: 20160605 |
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| CF01 | Termination of patent right due to non-payment of annual fee |