Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/32115—Planarisation
  • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
  • H10D30/0243—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6733—Multi-gate TFTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
  • H10D30/6739—Conductor-insulator-semiconductor electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Definitions

• the present invention relates to semiconductor devices and methods of manufacturing semiconductor devices.
• the present invention has particular applicability to double-gate devices.
• MOSFETs planar metal oxide semiconductor field effect transistors
• problems associated with short channel effects such as excessive leakage between the source and drain, become increasingly difficult to overcome.
• mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
• Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs.
• the double-gate MOSFETs offer better characteristics than the conventional bulk silicon MOSFETs. These improvements arise because the double- gate MOSFET has a gate electrode on both sides of the channel, rather than only on one side as in conventional MOSFETs. When there are two gates, the electric field generated by the drain is better screened from the source end of the channel. Also, two gates can control roughly twice as much current as a single gate, resulting in a stronger switching signal.
• a FinFET is a recent double-gate structure that exhibits good short channel behavior.
• a FinFET includes a channel formed in a vertical fin.
• the FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
• Implementations consistent with the present invention provide a double-gate MOSFET having a dual polysilicon layer over the gate area that is used to enhance chemical mechanical polishing (CMP) planarization of the polysilicon.
• CMP chemical mechanical polishing
• One implementation consistent with the invention provides a method of manufacturing a semiconductor device.
• the method includes forming a fin structure on an insulator and forming a gate structure over at least a portion of the fin structure and a portion of the insulator.
• the gate structure includes a first layer and a second layer formed over the first layer.
• the method further includes planarizing the gate structure by performing a chemical-mechanical polishing (CMP) of the gate structure.
• CMP chemical-mechanical polishing
• the planarization rate of the first layer of the gate structure may be slower than that of the second layer of the gate structure.
• the planarization continues until the first layer is exposed in an area over the fin.
• An alternate implementation consistent with the invention is directed to a semiconductor device.
• the device includes a fin structure formed over an insulator.
• the fin structure includes first and second ends.
• At least a portion of the fin structure acts as a channel in the semiconductor device.
• An amorphous silicon layer is formed over at least a portion of the fin structure.
• a polysilicon layer is formed around at least the portion of the amorphous silicon layer. The amorphous silicon layer protrudes through the polysilicon layer in an area over the fin structure.
• a source region is connected to the first end of the fin structure.
• a drain region is connected to the second end of the fin structure.
• Fig. 1 is a diagram illustrating the cross-section of an exemplary semiconductor device
• Fig. 2A is a diagram illustrating the top view of a fin structure formed on the semiconductor device shown in Fig. 1
• Fig. 2B is a diagram illustrating a cross-section along line A-A' in Fig. 2A;
• Fig. 3 is a diagram illustrating a cross-section of a gate dielectric layer formed on the fin shown in Fig. 2B;
• Fig. 4 is a diagram illustrating a cross-section showing gate material layers deposited over the fin shown in Fig. 3;
• Fig. 5 is a diagram illustrating a cross-section showing the gate material layers of Fig. 4 after an initial planarization;
• Fig. 6 is a diagram illustrating a cross-section showing the gate material layers of Fig. 5 after further planarization
• Fig. 7 is a diagram schematically illustrating a top view of a FinFET showing a gate structure patterned from the gate material shown in Fig. 6;
• Fig. 8 is a diagram illustrating a cross-section showing dummy fins
• Fig. 9 is a diagram conceptually illustrating an array of lines, including dummy structures, on a semiconductor device
• Fig. 10 is a diagram conceptually illustrating an alternate dummy structure on a semiconductor device.
• Figs. 11-14 are diagrams illustrating cross-sections that show the formation of vias.
• FIG. 1 illustrates the cross-section of a semiconductor device 100 formed in accordance with an embodiment of the present invention.
• semiconductor device 100 may include a silicon on insulator (SOI) structure that includes a silicon substrate 110, a buried oxide layer 120 and a silicon layer 130 formed on the buried oxide layer 120. Buried oxide layer 120 and silicon layer 130 may be formed on substrate 110 in a conventional manner.
• SOI silicon on insulator
• buried oxide layer 120 may include a silicon oxide and may have a thickness ranging from about 1000 A to about 3000 A.
• Silicon layer 130 may include monocrystalline or polycrystalline silicon. Silicon layer 130 is used to form a fin structure for a double-gate transistor device, as described in more detail below.
• substrate 110 and layer 130 may include other semiconducting materials, such as germanium, or combinations of semiconducting materials, such as silicon-germanium.
• Buried oxide layer 120 may also include other dielectric materials.
• a dielectric layer 140 such as a silicon nitride layer or a silicon oxide layer (e.g., SiO 2 ), may be formed over silicon layer 130 to act as a protective cap during subsequent etching processes.
• dielectric layer 140 may be grown to a thickness ranging from about 150 A to about 700 A.
• a photoresist material may be deposited and patterned to form a photoresist mask 150 for subsequent processing.
• the photoresist may be deposited and patterned in any conventional manner.
• silicon layer 130 may be etched in a conventional manner, with the etching terminating on buried oxide layer 120 to form a fin.
• source and drain regions may be formed adjacent the respective ends of the fin.
• a layer of silicon, germanium or combination of silicon and germanium may be deposited, patterned and etched in a conventional manner to form source and drain regions.
• silicon layer 130 may be patterned and etched to form source and drain regions simultaneously with the fin.
• Fig. 2A schematically illustrates the top view of a fin structure on semiconductor device 100 formed in such a manner.
• Source region 220 and drain region 230 may be formed adjacent the ends of fin structure 210 on buried oxide layer 120, according to an exemplary embodiment of the present invention.
• Fig. 2B is a cross-section along line A-A' in Fig. 2A illustrating the formation of fin structure 210.
• dielectric layer 140 and silicon layer 130 may be etched to form fin structure 210 comprising a silicon fin 130 with a dielectric cap 140.
• Fig. 3 is a cross-section illustrating the formation of a gate dielectric layer and gate material over fin structure 210 in accordance with an exemplary embodiment of the present invention.
• a dielectric layer may be formed on the exposed side surfaces of silicon fin 130.
• a thin oxide film 310 may be thermally grown on fin 130, as illustrated in Fig. 3.
• the oxide film 310 may be grown to a thickness of about 50 A to about 100 A and may be formed on the exposed side surfaces of fin 130.
• Gate material layer(s) may be deposited over semiconductor device 100 after formation of the oxide film 310.
• the gate material layers may include a thin layer of amorphous silicon 420 followed by a layer of undoped polysilicon 425.
• Layers 420 and 425 may be deposited using conventional chemical vapor deposition (CVD) or other well known techniques.
• Amorphous silicon layer 420 may be deposited to a thickness of approximately 300 A. More particularly, amorphous silicon layer 420 may be deposited to a thickness ranging from about 200 A to 600 A.
• Polysilicon layer 425 may be deposited to a thickness ranging from about 200 A to 1000 A. The thicknesses will vary depending on the fin or stack height.
• Layers 420 and 425, and in particular, layer 425, may next be planarized.
• gate material layers 420 and 425 may be planarized in a planarization process that takes advantage of the different polishing rates of amorphous silicon layer 420 and polysilicon layer 425. More specifically, by using the differences between polishing rates of the amorphous silicon layer 420 and polysilicon layer 425, a controlled amount of amorphous layer 420 can be retained on fin 210.
• CMP is one know planarization technique that may be used to planarize a semiconductor surface.
• CMP processing a wafer is placed face down on a rotating platen. The wafer, held in place by a carrier, rotates in the same direction of the platen.
• On the surface of the platen is a polishing pad on which there is a polishing slurry.
• the slurry may include a colloidal solution of silica particles in a carrier solution.
• the chemical composition and pH of the slurry affects the performance of the CMP process.
• the particular slurry is chosen to have a low rate of polishing for amorphous silicon as compared to polysilicon. Slurries for CMP are well known in the art and are generally available.
• the pH of the slurry may vary from 7 - 12.
• the removal rates can be varied from 50 A/min to 2000 A/min for a-Si and 500 A/min to 6000 A/min for poly Si.
• Fig. 5 is a cross-section illustrating the planarizing of the gate material layers 420 and 425 after an initial period of planarization has been completed.
• polysilicon layer 425 has initially been planarized such that the extrusion of polysilicon layer 425 above fin 210 has been reduced.
• Fig. 6 illustrates semiconductor device 100 after further CMP processing. At this point, the upper surface of amorphous silicon layer 420 may be exposed in the area above fin 210. Because the CMP process has a relatively slow rate of polishing for amorphous silicon layer 420 compared to polysilicon layer 425, amorphous silicon layer 420 effectively acts as an automatic stop layer and will remain as a protective layer over fin 210.
• amorphous silicon layer 420 may also be removed during the CMP. In this manner, amorphous silicon layer 420 may be used as a protective stopping layer for fin 210 when planarizing gate layer 420 and 425.
• the final thickness of amorphous silicon layer 420 extending above fin 210, shown in Fig. 6 as distance I 1 may be, for example, approximately 300 A.
• Fig. 7 schematically illustrates the top view of semiconductor device 100 illustrating a gate structure 710 patterned from gate material layers 420 and 425.
• Gate structure 710 may be patterned and etched after the CMP process is completed. Gate structure 710 extends across a channel region of the fin 210. Gate structure 710 may include a gate portion proximate to the sides of the fin 210 and a larger electrode portion spaced apart from the fin 210. The electrode portion of gate structure 710 may provide an accessible electrical contact for biasing or otherwise controlling the gate portion.
• the source/drain regions 220 and 230 may then be doped.
• n-type or p-type impurities may be implanted in source/drain regions 220 and 230.
• the particular implantation dosages and energies may be selected based on the particular end device requirements.
• One of ordinary skill in this art would be able to optimize the source/drain implantation process based on the circuit requirements and such acts are not disclosed herein in order not to unduly obscure the thrust of the present invention.
• side wall spacers (not shown) may optionally be formed prior to the source/drain ion implantation to control the location of the source/drain junctions based on the particular circuit requirements.
• Activation annealing may then be performed to activate the source/drain regions 220 and 230.
• Fig. 8 is a cross-sectional diagram illustrating dummy fins. Fig. 8 is generally similar to the cross- section shown in Fig. 4, except in Fig. 8, dummy fins 801 and 802 have been formed next to the actual fin 810. Dummy fins 801and 802 do not play a role in the final operation of the FinFET. However, by placing fins 801 and 802 next to fin 810, gate material layer 820 may form a more uniform distribution when it is initially deposited.
• dummy fins 801 and 802 cause the low point in layer 820 to be higher in the areas adjacent fin 810 than if dummy fins 801 and 802 were not present.
• layer 820 starts off more uniform than without dummy fins 801 and 802. This can lead to better uniformity after planarization.
• Fig. 9 is a diagram conceptually illustrating an array of lines (e.g., fins) on a semiconductor device.
• Lines 901 may represent fins that are actually used in the FinFETs.
• Lines 902 represent dummy fins at the ends of lines 901. Dummy fins 902 help to compensate for erosion effects caused by the CMP process, thus potentially yielding a more uniform planarized surface.
• Fig. 10 is a diagram conceptually illustrating an alternate implementation of a dummy structure.
• Lines 1001 may be similar to lines 901, and represent actual structures used in the final semiconductor device. Dummy lines 901, however, are replaced by dummy structure 1002.
• Dummy structure 1002 encompasses more area than dummy lines 902 and may provide better uniformity during planarization. In particular, by encapsulating the pattern of lines 1001, dummy structure 1002 may protect and prevent lines 1001 from nonuniform polishing.
• the dimension of dummy structure 1002, such as length I 2 may depend on the overall pattern density being used on the semiconductor device.
• CMP induced detrimental effects for metal gate integration layers may be reduced.
• Interlayer dielectric (ILD) layers may be used in semiconductor devices when creating vertically stacked layers of semiconductor logic. As shown in Fig. 11, an ILD layer 1101 may be used to separate a first semiconductor logic layer 1102 from a second semiconductor logic layer that will later be formed above ILD layer 1101. Layer 1102 is not shown in detail in Fig. 11, but may include, for example, numerous interconnected FinFETs that perform one or more logic functions.
• ILD Interlayer dielectric
• Vias 1103 may be patterned in ILD layer 1101 by application of resist 1104. Vias 1103 may be filled (shown in Figs. 12-14) with a conducting material that allows the layers to communicate with one another.
• Implantation material 1205 may include silicon (Si) or Palladium (Pd) that function as activators for the subsequently deposited metal. Other materials that function as activators for electroless deposition of metals may be used.
• resist 1104 may be removed and a metal 1406 may then be selectively deposited.
• Metal 1406 may be deposited through selective electroless deposition and may include metals such as cobalt (Co), nickel (Ni), or tungsten (W) or their alloys.
• the metal 140 may be deposited only on the areas cultivated with implantation material 1205 (i.e., the activated surfaces of via 1103). Accordingly, via 1103 is filled with a conducting metal. This process tends to prevent CMP induced dishing or other detrimental effects.
• the multiple gate layers may include a thin amorphous silicon layer that acts as an automated planarization stop layer during the CMP process.
• numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention.
• the present invention can be practiced without resorting to the specific details set forth herein.
• well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention.
• the dielectric and conductive layers used in manufacturing a semiconductor device in accordance with the present invention can be deposited by conventional deposition techniques.
• metallization techniques such as various types of chemical vapor deposition (CVD) processes, including low pressure chemical vapor deposition (LPCVD) and enhanced chemical vapor deposition (ECVD) can be employed.
• CVD chemical vapor deposition
• LPCVD low pressure chemical vapor deposition
• ECVD enhanced chemical vapor deposition
• the present invention is applicable in the manufacturing of semiconductor devices and particularly in semiconductor devices with design features of 100 nm and below, resulting in increased transistor and circuit speeds and improved reliability.
• the present invention is applicable to the formation of any of various types of semiconductor devices, and hence, details have not been set forth in order to avoid obscuring the thrust of the present invention.
• conventional photolithographic and etching techniques are employed and, hence, the details of such techniques have not been set forth herein in detail.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Power Engineering (AREA)
• Thin Film Transistor (AREA)
• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Mechanical Treatment Of Semiconductor (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=32508107

Family Applications (1)

Country Status (8)

Cited By (1)

Families Citing this family (28)

Citations (4)

Family Cites Families (11)

• 2003
  • 2003-06-12 US US10/459,579 patent/US6756643B1/en not_active Expired - Lifetime
• 2004
  • 2004-01-08 US US10/752,691 patent/US6812076B1/en not_active Expired - Fee Related
  • 2004-06-05 KR KR1020057023790A patent/KR101123377B1/ko not_active Expired - Fee Related
  • 2004-06-05 JP JP2006533565A patent/JP2007500952A/ja not_active Ceased
  • 2004-06-05 WO PCT/US2004/017725 patent/WO2004112146A1/en not_active Ceased
  • 2004-06-05 DE DE112004001030T patent/DE112004001030B4/de not_active Expired - Fee Related
  • 2004-06-05 CN CNB2004800161347A patent/CN100477258C/zh not_active Expired - Fee Related
  • 2004-06-05 GB GB0524314A patent/GB2418534B/en not_active Expired - Fee Related
  • 2004-06-10 TW TW093116645A patent/TWI338328B/zh not_active IP Right Cessation
  • 2004-10-29 US US10/975,473 patent/US6982464B2/en not_active Expired - Fee Related

Patent Citations (4)

Also Published As

Similar Documents

Legal Events