KR101054238B1 - 웨이퍼 코팅 및 싱귤레이션 방법 - Google Patents

웨이퍼 코팅 및 싱귤레이션 방법 Download PDF

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Publication number
KR101054238B1
KR101054238B1 KR1020057004220A KR20057004220A KR101054238B1 KR 101054238 B1 KR101054238 B1 KR 101054238B1 KR 1020057004220 A KR1020057004220 A KR 1020057004220A KR 20057004220 A KR20057004220 A KR 20057004220A KR 101054238 B1 KR101054238 B1 KR 101054238B1
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South Korea
Prior art keywords
wafer
integrated circuit
delete delete
underfill material
front side
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Expired - Fee Related
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KR1020057004220A
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English (en)
Korean (ko)
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KR20050054933A (ko
Inventor
징 콰이
제니스 댄버
토마스즈 클로소와크
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프리스케일 세미컨덕터, 인크.
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/014Manufacture or treatment using batch processing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/012Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/013Manufacture or treatment of die-attach connectors
    • H10W72/01331Manufacture or treatment of die-attach connectors using blanket deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/853On the same surface
    • H10W72/856Bump connectors and die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body

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  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Wire Bonding (AREA)
KR1020057004220A 2002-09-11 2003-09-05 웨이퍼 코팅 및 싱귤레이션 방법 Expired - Fee Related KR101054238B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/241,265 US6649445B1 (en) 2002-09-11 2002-09-11 Wafer coating and singulation method
US10/241,265 2002-09-11
PCT/US2003/027964 WO2004034422A2 (en) 2002-09-11 2003-09-05 Wafer coating and singulation method

Publications (2)

Publication Number Publication Date
KR20050054933A KR20050054933A (ko) 2005-06-10
KR101054238B1 true KR101054238B1 (ko) 2011-08-08

Family

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KR1020057004220A Expired - Fee Related KR101054238B1 (ko) 2002-09-11 2003-09-05 웨이퍼 코팅 및 싱귤레이션 방법

Country Status (6)

Country Link
US (1) US6649445B1 (https=)
JP (1) JP2005538572A (https=)
KR (1) KR101054238B1 (https=)
CN (1) CN100416768C (https=)
AU (1) AU2003296904A1 (https=)
WO (1) WO2004034422A2 (https=)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6352881B1 (en) 1999-07-22 2002-03-05 National Semiconductor Corporation Method and apparatus for forming an underfill adhesive layer
US6794751B2 (en) * 2001-06-29 2004-09-21 Intel Corporation Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies
DE10202881B4 (de) * 2002-01-25 2007-09-20 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterchips mit einer Chipkantenschutzschicht, insondere für Wafer Level Packaging Chips
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US7423337B1 (en) 2002-08-19 2008-09-09 National Semiconductor Corporation Integrated circuit device package having a support coating for improved reliability during temperature cycling
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
JP2004221125A (ja) * 2003-01-09 2004-08-05 Sharp Corp 半導体装置及びその製造方法
US7301222B1 (en) 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
JP2004288816A (ja) * 2003-03-20 2004-10-14 Seiko Epson Corp 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
US20040235272A1 (en) * 2003-05-23 2004-11-25 Howard Gregory E. Scribe street width reduction by deep trench and shallow saw cut
US6890836B2 (en) * 2003-05-23 2005-05-10 Texas Instruments Incorporated Scribe street width reduction by deep trench and shallow saw cut
DE10333841B4 (de) * 2003-07-24 2007-05-10 Infineon Technologies Ag Verfahren zur Herstellung eines Nutzens mit in Zeilen und Spalten angeordneten Halbleiterbauteilpositionen und Verfahren zur Herstellung eines Halbleiterbauteils
TWI231534B (en) * 2003-12-11 2005-04-21 Advanced Semiconductor Eng Method for dicing a wafer
US7282375B1 (en) 2004-04-14 2007-10-16 National Semiconductor Corporation Wafer level package design that facilitates trimming and testing
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7354800B2 (en) 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
KR100660868B1 (ko) * 2005-07-06 2006-12-26 삼성전자주식회사 칩의 배면이 몰딩된 반도체 패키지 및 그의 제조방법
US7273768B2 (en) * 2005-08-30 2007-09-25 Mutual-Pak Technology Co. Ltd. Wafer-level package and IC module assembly method for the wafer-level package
US7456088B2 (en) 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7768125B2 (en) * 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
JP2007214268A (ja) * 2006-02-08 2007-08-23 Seiko Instruments Inc 半導体装置の製造方法
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
JP4791843B2 (ja) * 2006-02-14 2011-10-12 株式会社ディスコ 接着フィルム付きデバイスの製造方法
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface
JP5275553B2 (ja) * 2006-06-27 2013-08-28 スリーエム イノベイティブ プロパティズ カンパニー 分割チップの製造方法
US7482251B1 (en) * 2006-08-10 2009-01-27 Impinj, Inc. Etch before grind for semiconductor die singulation
US9111950B2 (en) * 2006-09-28 2015-08-18 Philips Lumileds Lighting Company, Llc Process for preparing a semiconductor structure for mounting
JP5091600B2 (ja) 2006-09-29 2012-12-05 三洋電機株式会社 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP4933233B2 (ja) 2006-11-30 2012-05-16 株式会社ディスコ ウエーハの加工方法
JP4345808B2 (ja) * 2006-12-15 2009-10-14 エルピーダメモリ株式会社 半導体装置の製造方法
KR100842505B1 (ko) * 2006-12-19 2008-07-01 동부일렉트로닉스 주식회사 웨이퍼 백면의 메탈 증착공정
TWI364793B (en) * 2007-05-08 2012-05-21 Mutual Pak Technology Co Ltd Package structure for integrated circuit device and method of the same
US7727875B2 (en) * 2007-06-21 2010-06-01 Stats Chippac, Ltd. Grooving bumped wafer pre-underfill system
US7838424B2 (en) * 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US20090155981A1 (en) * 2007-12-13 2009-06-18 Ayotte Stephen P Method and apparatus for singulating integrated circuit chips
US7824962B2 (en) * 2008-01-29 2010-11-02 Infineon Technologies Ag Method of integrated circuit fabrication
CN101521164B (zh) * 2008-02-26 2011-01-05 上海凯虹科技电子有限公司 引线键合芯片级封装方法
JP5436827B2 (ja) * 2008-03-21 2014-03-05 日立化成株式会社 半導体装置の製造方法
US8058150B2 (en) * 2008-07-10 2011-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Particle free wafer separation
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
JP2010192867A (ja) * 2009-01-20 2010-09-02 Renesas Electronics Corp 半導体集積回路装置および半導体集積回路装置の製造方法
US7776649B1 (en) * 2009-05-01 2010-08-17 Powertech Technology Inc. Method for fabricating wafer level chip scale packages
CN101941181B (zh) * 2009-07-03 2012-10-17 日月光半导体制造股份有限公司 晶圆的研磨方法
CN102237307A (zh) * 2010-04-27 2011-11-09 瑞鼎科技股份有限公司 集成电路晶圆切割方法
US9224647B2 (en) 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US8993377B2 (en) 2010-09-29 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of bonding different size semiconductor die at the wafer level
US8652935B2 (en) 2010-12-16 2014-02-18 Tessera, Inc. Void-free wafer bonding using channels
US20120273935A1 (en) * 2011-04-29 2012-11-01 Stefan Martens Semiconductor Device and Method of Making a Semiconductor Device
JP5888995B2 (ja) 2012-01-16 2016-03-22 三菱電機株式会社 半導体装置およびその製造方法
US8940618B2 (en) * 2012-03-13 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for cutting semiconductor wafers
CN102825541B (zh) * 2012-09-10 2014-12-10 豪威科技(上海)有限公司 晶圆减薄方法
US9631065B2 (en) * 2013-03-12 2017-04-25 Intel Corporation Methods of forming wafer level underfill materials and structures formed thereby
US9508623B2 (en) 2014-06-08 2016-11-29 UTAC Headquarters Pte. Ltd. Semiconductor packages and methods of packaging semiconductor devices
JP5967629B2 (ja) 2014-11-17 2016-08-10 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation 回路モジュール及びその製造方法
US9466585B1 (en) * 2015-03-21 2016-10-11 Nxp B.V. Reducing defects in wafer level chip scale package (WLCSP) devices
JP2017054888A (ja) * 2015-09-08 2017-03-16 株式会社ディスコ ウエーハの加工方法
US11037904B2 (en) 2015-11-24 2021-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Singulation and bonding methods and structures formed thereby
JP6608694B2 (ja) * 2015-12-25 2019-11-20 株式会社ディスコ ウエーハの加工方法
JP6523999B2 (ja) * 2016-03-14 2019-06-05 東芝メモリ株式会社 半導体装置およびその製造方法
DE102016116499B4 (de) * 2016-09-02 2022-06-15 Infineon Technologies Ag Verfahren zum Bilden von Halbleiterbauelementen und Halbleiterbauelemente
JP6767814B2 (ja) * 2016-09-05 2020-10-14 株式会社ディスコ パッケージデバイスチップの製造方法
JP6746224B2 (ja) * 2016-11-18 2020-08-26 株式会社ディスコ デバイスチップパッケージの製造方法
US10529671B2 (en) 2016-12-13 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10510709B2 (en) * 2017-04-20 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package and manufacturing method thereof
CN109102772B (zh) * 2017-06-20 2023-11-21 昆山国显光电有限公司 驱动电路板和显示装置
JP6976650B2 (ja) * 2017-09-08 2021-12-08 株式会社ディスコ ウェーハの加工方法
JP7058904B2 (ja) * 2017-09-08 2022-04-25 株式会社ディスコ ウェーハの加工方法
JP7013085B2 (ja) * 2017-09-08 2022-01-31 株式会社ディスコ ウェーハの加工方法
JP7013084B2 (ja) * 2017-09-08 2022-01-31 株式会社ディスコ ウェーハの加工方法
JP6918418B2 (ja) * 2017-09-08 2021-08-11 株式会社ディスコ ウェーハの加工方法
JP7118522B2 (ja) * 2017-09-19 2022-08-16 株式会社ディスコ ウェーハの加工方法
JP7118521B2 (ja) * 2017-09-19 2022-08-16 株式会社ディスコ ウェーハの加工方法
KR102506698B1 (ko) * 2018-02-19 2023-03-07 에스케이하이닉스 주식회사 보강용 탑 다이를 포함하는 반도체 패키지 제조 방법
KR102243674B1 (ko) * 2019-10-28 2021-04-23 주식회사 루츠 세라믹칩 제조방법
JP7614781B2 (ja) * 2020-10-19 2025-01-16 日東電工株式会社 半導体装置の製造方法
US11908831B2 (en) 2020-10-21 2024-02-20 Stmicroelectronics Pte Ltd Method for manufacturing a wafer level chip scale package (WLCSP)
CN115833769B (zh) * 2022-11-28 2023-09-05 北京超材信息科技有限公司 声表面波器件的制造方法、声表面波器件以及射频模组
TWI887972B (zh) * 2024-01-22 2025-06-21 頎邦科技股份有限公司 封裝構造及其製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332520A (ja) 2000-05-23 2001-11-30 Amkor Technology Inc シート状樹脂組成物及びそれを用いた半導体装置の製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128746A (en) 1990-09-27 1992-07-07 Motorola, Inc. Adhesive and encapsulant material with fluxing properties
JP3376203B2 (ja) 1996-02-28 2003-02-10 株式会社東芝 半導体装置とその製造方法及びこの半導体装置を用いた実装構造体とその製造方法
JP3137322B2 (ja) * 1996-07-12 2001-02-19 富士通株式会社 半導体装置の製造方法及び半導体装置製造用金型及び半導体装置
JP2001510944A (ja) 1997-07-21 2001-08-07 アギラ テクノロジーズ インコーポレイテッド 半導体フリップチップ・パッケージおよびその製造方法
US6184109B1 (en) * 1997-07-23 2001-02-06 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
JPH11111646A (ja) * 1997-10-02 1999-04-23 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
US6323062B1 (en) 1998-04-27 2001-11-27 Alpha Metals, Inc. Wafer coating method for flip chips
US6265776B1 (en) * 1998-04-27 2001-07-24 Fry's Metals, Inc. Flip chip with integrated flux and underfill
JP3516592B2 (ja) * 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6168972B1 (en) 1998-12-22 2001-01-02 Fujitsu Limited Flip chip pre-assembly underfill process
JP3330890B2 (ja) * 1999-01-12 2002-09-30 沖電気工業株式会社 樹脂封止型半導体装置及びその製造方法
US6194788B1 (en) 1999-03-10 2001-02-27 Alpha Metals, Inc. Flip chip with integrated flux and underfill
JP3423245B2 (ja) * 1999-04-09 2003-07-07 沖電気工業株式会社 半導体装置及びその実装方法
US6352881B1 (en) * 1999-07-22 2002-03-05 National Semiconductor Corporation Method and apparatus for forming an underfill adhesive layer
JP2001127206A (ja) * 1999-08-13 2001-05-11 Citizen Watch Co Ltd チップスケールパッケージの製造方法及びicチップの製造方法
JP3455762B2 (ja) * 1999-11-11 2003-10-14 カシオ計算機株式会社 半導体装置およびその製造方法
US6524890B2 (en) * 1999-11-17 2003-02-25 Denso Corporation Method for manufacturing semiconductor device having element isolation structure
JP2001176899A (ja) * 1999-12-21 2001-06-29 Sanyo Electric Co Ltd 半導体装置の製造方法
US6528393B2 (en) * 2000-06-13 2003-03-04 Advanced Semiconductor Engineering, Inc. Method of making a semiconductor package by dicing a wafer from the backside surface thereof
JP2002016022A (ja) * 2000-06-29 2002-01-18 Toshiba Corp 半導体装置の製造方法
JP2002100709A (ja) * 2000-09-21 2002-04-05 Hitachi Ltd 半導体装置及びその製造方法
US6506681B2 (en) 2000-12-06 2003-01-14 Micron Technology, Inc. Thin flip—chip method
JP4330821B2 (ja) * 2001-07-04 2009-09-16 株式会社東芝 半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332520A (ja) 2000-05-23 2001-11-30 Amkor Technology Inc シート状樹脂組成物及びそれを用いた半導体装置の製造方法

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JP2005538572A (ja) 2005-12-15
KR20050054933A (ko) 2005-06-10
WO2004034422A3 (en) 2004-08-26
WO2004034422A2 (en) 2004-04-22
US6649445B1 (en) 2003-11-18
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