CN101350322A - 形成集成电路结构的方法 - Google Patents

形成集成电路结构的方法 Download PDF

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Publication number
CN101350322A
CN101350322A CNA2008100955784A CN200810095578A CN101350322A CN 101350322 A CN101350322 A CN 101350322A CN A2008100955784 A CNA2008100955784 A CN A2008100955784A CN 200810095578 A CN200810095578 A CN 200810095578A CN 101350322 A CN101350322 A CN 101350322A
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chip
primer
wafer
integrated circuit
circuit structure
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CN101350322B (zh
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李建勋
赵智杰
宋明忠
郭祖宽
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种封装及形成集成电路结构的方法，包括提供其表面上具有接合导体的晶圆，并涂抹混合底胶至晶圆的表面上。混合底胶包括底胶材料及助熔剂材料。在涂抹混合底胶的步骤后，将芯片接合至晶圆上，且使得芯片上的焊料凸块与接合导体连接。本发明能够减小接合在晶圆上的芯片间的距离，节省晶圆范围，并减少工艺时间。

Description

形成集成电路结构的方法
技术领域
本发明涉及集成电路工艺，且特别涉及芯片-晶圆(die-to-wafer)接合工艺。
背景技术
中介层(interposer)可用在集成电路的封装，一般是用来形成半导体芯片与封装元件间的连接。例如，当半导体芯片上的接合焊盘(bonding pad)非常密集时，会造成封装工艺的困难。因此，便可用中介层来增加半导体芯片的间距。
图1显示将芯片12及14接合至中介层晶圆10上的工艺剖面图。中介层晶圆10包括铜柱16(copper post)，其连接至接合焊盘19，并进一步连接至焊球20。芯片12及14通过焊料凸块1 8设置在铜柱16上。
通常，接合工艺包括将多个焊料凸块18预先设置在芯片12及14上，涂抹助熔剂(flux)至铜柱16，然后将芯片12及14接合至中介层晶圆10上，其中焊料凸块18朝着铜柱16放置。将焊料凸块18与铜柱16回焊接合后，将底胶22涂至芯片12及14与下面的中介层晶圆10之间的间隙中。在传统的工艺中，是利用底胶分配器24(包括注射针26)通过间隙28(及芯片12、14与其他邻近芯片之间的间隙)将底胶22涂至中介层晶圆10上。底胶随后会因毛细管效应被吸入多个焊料凸块18间的间隙。
传统的接合工艺有一些缺点。为了不浪费中介层晶圆的空间，间隙28的宽度W1是越小越好。但是，随着间隙28的宽度W1的缩小，要通过间隙28来涂抹底胶将更为困难。这个问题随着芯片尺寸的缩小化更为严重。通常，间隙28的宽度W1需要大于约1毫米。
此外，传统工艺在焊料凸块18回焊后的清理(cleaning)工艺也有执行上的困难。不希望得到的物质(例如剩余的助熔剂)必须被清除掉。然而，随着宽度W1及中介层晶圆10与芯片12、14间的宽度W2的不断缩小，清理工艺也不断地变得更困难。因此，业界亟需新的接合工艺。
发明内容
本发明提供一种形成集成电路结构的方法，包括提供其表面上具有接合导体的晶圆，并涂抹混合底胶至晶圆的表面上。混合底胶包括底胶材料及助熔剂材料。然后在涂抹混合底胶的步骤后，将芯片接合至晶圆上，且使得芯片上的焊料凸块与接合导体连接。
上述形成集成电路结构的方法中，该接合芯片的步骤可包括：将该芯片与该晶圆对齐，并将该芯片压向该混合底胶，直到该芯片上的焊料凸块穿过该混合底胶并与该接合导体接触；回焊该焊料凸块；以及固化该混合底胶。
上述形成集成电路结构的方法中，在回焊该焊料凸块后，可涂抹该混合底胶至该芯片上，并将额外的芯片接合至该芯片上。
上述形成集成电路结构的方法中，该混合底胶可填充在具有相同深度的该芯片与邻近芯片间的间隙中，且其中该混合底胶的顶表面高于该芯片的顶表面。
上述形成集成电路结构的方法中，该混合底胶可在固化前实质上无法流动。
上述形成集成电路结构的方法中，该助熔剂材料可为疏水性的。
上述形成集成电路结构的方法中，该混合底胶可只分配在该晶圆中的芯片上，且在该芯片间的切割线实质上不具有该混合底胶。
上述形成集成电路结构的方法中，该涂抹混合底胶的步骤可包括：贴上模板遮罩至该晶圆上，其中该模板遮罩中的开口露出该晶圆上的芯片；将该混合底胶涂至该开口中；除去该模板遮罩上的过量的混合底胶；以及除去该模板遮罩。
上述形成集成电路结构的方法中，该晶圆可为中介层晶圆。
上述形成集成电路结构的方法中，该晶圆可为半导体晶圆，包括有源电路，且其中该接合导体包括接合焊盘。
上述形成集成电路结构的方法中，在该涂抹混合底胶的步骤之后而在该接合芯片的步骤之前，至少部分的该接合导体可埋在该混合底胶中。
上述形成集成电路结构的方法中，在该涂抹混合底胶的步骤之后而在该接合芯片的步骤之前，全部的该接合导体可埋在该混合底胶中。
本发明还提供一种形成集成电路结构的方法，包括提供包含接合导体在其上的晶圆，及提供包含焊料凸块在其上的芯片。将混合底胶涂至晶圆上，其中至少部分的接合导体被埋在混合底胶中。将芯片与晶圆对齐，并将芯片压向混合底胶，以使得芯片上的焊料凸块穿过混合底胶而与接合导体接触。然后回焊焊料凸块，及接着固化混合底胶。
本发明又提供一种形成集成电路结构的方法，包括提供包含接合导体在其上的晶圆，及各包含焊料凸块在其上的第一及第二芯片。将混合底胶涂至晶圆上，其中接合导体被埋在混合底胶中。将第一及第二芯片与晶圆对齐，并压向混合底胶，以使得第一及第二芯片上的焊料凸块穿过混合底胶而与接合导体接触。第一及第二芯片间的晶圆区域优选不具有混合底胶。此方法还包括焊料凸块的回焊及混合底胶的固化。
本发明的优点包括减小接合在晶圆上的芯片间的距离，可节省晶圆范围，并减少工艺时间。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，以下特举出优选实施例并配合附图进行详细说明。
附图说明
图1显示将半导体芯片接合至中介层晶圆的习知工艺的剖面图。
图2A-图6显示本发明一实施例的一系列工艺剖面图，其中使用包含助熔剂的混合底胶将半导体芯片接合至晶圆。
图7A-图8显示堆叠更多的芯片至图6所示的结构的过程。
其中，附图标记说明如下：
12、14～接合芯片；10～中介层晶圆；16～铜柱；19、38、56～接合焊盘；22～底胶；20～焊球；18、52、62～焊料凸块；24～底胶分配器；26～注射针；28～间隙；W1、W2、W3～宽度；30～晶圆；33、50、60～芯片；32～基底材料；34～铜柱；36～凸块(或焊球)；40～背面；44、64～混合底胶；46～模板遮罩；54～接合头；58～区域。
具体实施方式
以下将配合附图说明本发明的实施例将芯片接合至晶圆上的方法。在以下各种实施例，相似的元件符号用来标示相似的元件。
请参照图2A，先提供晶圆30。在一个实施例中，晶圆30是中介层晶圆，包括基底材料32及形成于其中的铜柱34。在优选实施例中，基底材料32包括硅。在另一实施例中，基底材料32包括其他常用的半导体材料或介电材料，例如有机材料及陶瓷。每一个铜柱34均具有埋入基底材料32的第一端，及连接至凸块36(或焊球36)的第二端。铜柱34的第一端依照半导体芯片的接合焊盘排列(未示于图中)，在随后工艺中，接合焊盘将接合至中介层晶圆30。
在另一实施例中，如图2B所示，晶圆30是半导体晶圆，包括数个半导体芯片，半导体芯片可包括集成电路。因此，随后的接合工艺常称作芯片-晶圆接合(die-to-wafer bonding)。接合焊盘38形成于晶圆30上，并连接至集成电路。为了简化叙述，图2A及图2B只显示晶圆30中的两个芯片33。
请参照图3，使得中介层晶圆30的背面40变薄直到露出铜柱34的第一端。然后实施蚀刻工艺以进一步使基底材料32的背面40凹陷，使得铜柱34的顶端部分突出背面40。
请参照图4A，涂抹混合底胶44(包括助熔剂与底胶)至晶圆30上。如本领域技术人员所知，当固化时，底胶具有保护焊料凸块免于应力伤害的功能，而助熔剂可增进金属的融合，所以可增进焊料凸块的回焊工艺。混合底胶44优选是环氧材料，可包括树脂。可进一步将硅胶加入混合底胶44。混合底胶44中的底胶优选是可快速固化的。在一个实施例中，底胶的固化可在少于约十分钟之内完成。
混合底胶44中的助熔剂优选包括比传统助熔剂(与底胶分离者)更少量的活化剂(activator)。在另一实施例中，混合底胶44中的助熔剂包括具有比传统助熔剂强度小的活化剂，例如Co2+、Co3+及其相似物。在一个实施例中，助熔剂包括少于约1％的活化剂。因此，在接合工艺后，不需除去助熔剂。混合底胶44中的助熔剂优选是疏水性的。其好处是既然疏水性的助熔剂将留在最终结构中，助熔剂将不会吸收水气，特别是底胶中的水气。因此，将可消除由水气造成对最终集成电路结构效能的可能的不利影响。
在优选实施例中，混合底胶44具有高粘度，因此可减低流动性。当将混合底胶涂至中介层晶圆30时，混合底胶44更优选是实质上无法流动的。在一个实施例中，混合底胶44的粘度大于约3000cps至约8000cps。因此，在涂抹之后，混合底胶44将实质上留在原涂抹处，而不会流到晶圆30的其他位置。另一方面，粘度也最好不能太大，以便在随后的接合工艺中，只需施加一点力量即可使得焊料凸块压穿混合底胶44。在一个实施例中，混合底胶44包括硬化剂、氧化硅、环氧基材料、或前述的组合，而混合底胶44中的助熔剂包括松脂(rosin)、松香酸(abietic acid)、辛二酸(suberic acid)、或前述的组合。
在第一实施例中，如图4A所示，只将混合底胶44涂于芯片33上，而不将混合底胶44涂抹于芯片33间的区域(例如切割线)上。在第二实施例中，如图4B所示，放置模板遮罩46于中介层晶圆30上，其中模板遮罩46包括数个开口，通过这些开口露出每个芯片33。然后将混合底胶44涂至开口中。除去多余的混合底胶44，例如以刮刀消除，使得混合底胶44只留在开口中。然后除去模板遮罩46。在优选实施例中，芯片33间的切割线由模板遮罩46所遮蔽，所以没有混合底胶44会涂抹于其上。混合底胶44优选覆盖全部的铜柱34(或图2B中的接合焊盘38)。控制混合底胶44的优选涂抹量使得在随后将芯片接合至晶圆30期间，没有实质溢流发生。
在第三实施例中，涂抹混合底胶44使成为实质平坦的涂层，如图4C所示。混合底胶44的厚度优选是实质上接近随后所接合的焊料凸块的高度。请注意图4A、图4B、及图4C所示的实施例中，至少一些铜柱34(或假如晶圆30是半导体晶圆时，如图2B所示的接合焊盘38)，或可能是全部的铜柱34，埋在混合底胶44中。
请参照图5，先准备芯片50。芯片50优选包括集成电路形成于其中。将焊料凸块52预先设置在芯片50的表面上，并连接至芯片50中的集成电路。接合头54用以转移芯片50使覆盖并对齐至其中一个芯片33。随后将芯片50压向中介层晶圆30，使得焊料凸块52穿过混合底胶44直到与铜柱34(或假如晶圆30是半导体晶圆时，如图2B所示的接合焊盘38)接触。假如混合底胶44从芯片33与芯片50间的间隙溢流，多余的混合底胶44可能向旁边挤压。优选的是，假如芯片50与其邻近芯片间的间隙够宽，例如具有大于约300微米的宽度W3(见图6)，则可涂抹较多混合底胶44，而多余的混合底胶材料将从间隙中被挤出。否则，混合底胶44的涂抹量需要仔细地控制以确定不会有多余的溢流。
请参照图6，假如仔细地涂抹混合底胶44而只覆盖铜柱34，且没有溢流发生，混合底胶44可只被限制在芯片50与其对应的下方芯片33间的重叠区域中，而区域58(于多个芯片50间的间隙露出)可能没有涂抹到混合底胶44。这与使用传统底胶-涂抹(underfill-dispensing)方法所形成的结构不同，在传统结构中底胶是通过多个芯片50间的间隙来涂抹的，所以区域58会涂抹到底胶。在放置全部芯片50到晶圆30上后，执行回焊工艺，以便焊料凸块52与下方的铜柱34接合(或图2B的接合焊盘38)。
然后执行固化工艺来固化混合底胶44中的底胶。在优选实施例中，底胶是可快速固化的，因此固化工艺可在少于十分钟内完成。在固化工艺后，不需要助熔剂除去步骤。
在以上所讨论的实施例中，将芯片接合至晶圆30上之前，将焊料凸块预先设置至晶圆30上。本领域技术人员可了解焊料凸块52可在将芯片50接合至晶圆30上之前，先预设置至晶圆30上。因此，混合底胶44会掩埋至少一些焊料凸块。
图7A至图8显示堆叠更多的芯片至芯片50上的过程。为了堆叠更多芯片，芯片50优选具有接合焊盘56，其位于焊料凸块52所在位置的另一边上。芯片50可进一步包括穿硅介层窗(未示于图中)。然后使用与图4A至图4C所示大抵相同的方法将混合底胶涂至芯片50上。例如在图7A中，将混合底胶64涂在每个芯片50上。在图7B中，混合底胶64均匀地覆盖，并填充在多个芯片50间的间隙。混合底胶64可包括与混合底胶44大抵相同的成分。
图8显示将芯片60接合至芯片50。焊料凸块62优选预先设置至芯片60上。然后使用与以上所讨论大抵相同的方法来将芯片60接合至芯片50上。接着执行回焊及固化工艺。
本发明的实施例具有数个优点。既然混合底胶44是在将芯片接合至晶圆前涂抹的，芯片间的空间可减小而不会在随后的底胶涂抹及助熔剂除去工艺中造成困难。这对于形成下一世代的集成电路是特别有利的。此外，将助熔剂的涂抹及底胶的涂抹整合成一个步骤，可减少工艺时间。
虽然本发明已以数个优选实施例公开如上，然而其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与修改，因此本发明的保护范围应以所附权利要求范围为准。

Claims (12)

1.一种形成集成电路结构的方法，包括以下步骤：
提供晶圆，其表面具有接合导体；
涂抹混合底胶至该晶圆的表面上，其中该混合底胶包括底胶材料及助熔剂材料；以及
在该涂抹混合底胶的步骤后，将芯片接合在该晶圆上，且使得该芯片上的焊料凸块与该接合导体连接。
2.如权利要求1所述的形成集成电路结构的方法，其中该接合芯片的步骤包括：
将该芯片与该晶圆对齐，并将该芯片压向该混合底胶，直到该芯片上的焊料凸块穿过该混合底胶并与该接合导体接触；
回焊该焊料凸块；以及
固化该混合底胶。
3.如权利要求2所述的形成集成电路结构的方法，其中在回焊该焊料凸块后，涂抹该混合底胶至该芯片上，并将额外的芯片接合至该芯片上。
4.如权利要求3所述的形成集成电路结构的方法，其中该混合底胶填充在具有相同深度的该芯片与邻近芯片间的间隙中，而其中该混合底胶的顶表面高于该芯片的顶表面。
5.如权利要求1所述的形成集成电路结构的方法，其中该混合底胶在固化前，是实质上无法流动的。
6.如权利要求1所述的形成集成电路结构的方法，其中该助熔剂材料是疏水性的。
7.如权利要求1所述的形成集成电路结构的方法，其中该混合底胶只分配在该晶圆中的芯片上，而其中在该芯片间的切割线实质上不具有该混合底胶。
8.如权利要求7所述的形成集成电路结构的方法，其中该涂抹混合底胶的步骤包括：
贴上模板遮罩至该晶圆上，其中该模板遮罩中的开口露出该晶圆上的芯片；
将该混合底胶涂至该开口中；
除去该模板遮罩上的过量的混合底胶；以及
除去该模板遮罩。
9.如权利要求1所述的形成集成电路结构的方法，其中该晶圆是中介层晶圆。
10.如权利要求1所述的形成集成电路结构的方法，其中该晶圆是半导体晶圆，包括有源电路，且其中该接合导体包括接合焊盘。
11.如权利要求1所述的形成集成电路结构的方法，其中在该涂抹混合底胶的步骤之后而在该接合芯片的步骤之前，至少部分的该接合导体埋在该混合底胶中。
12.如权利要求1所述的形成集成电路结构的方法，其中在该涂抹混合底胶的步骤之后而在该接合芯片的步骤之前，全部的该接合导体埋在该混合底胶中。
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