KR101010159B1 - 얇은 언더필 및 두꺼운 솔더 마스크를 가지는 플립-칩어셈블리 - Google Patents
얇은 언더필 및 두꺼운 솔더 마스크를 가지는 플립-칩어셈블리 Download PDFInfo
- Publication number
- KR101010159B1 KR101010159B1 KR1020057018230A KR20057018230A KR101010159B1 KR 101010159 B1 KR101010159 B1 KR 101010159B1 KR 1020057018230 A KR1020057018230 A KR 1020057018230A KR 20057018230 A KR20057018230 A KR 20057018230A KR 101010159 B1 KR101010159 B1 KR 101010159B1
- Authority
- KR
- South Korea
- Prior art keywords
- flip chip
- underfill material
- underfill
- active surface
- delete delete
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
- H01L2224/81011—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/402,631 | 2003-03-28 | ||
| US10/402,631 US6774497B1 (en) | 2003-03-28 | 2003-03-28 | Flip-chip assembly with thin underfill and thick solder mask |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20050118694A KR20050118694A (ko) | 2005-12-19 |
| KR101010159B1 true KR101010159B1 (ko) | 2011-01-20 |
Family
ID=32825058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020057018230A Expired - Lifetime KR101010159B1 (ko) | 2003-03-28 | 2004-03-24 | 얇은 언더필 및 두꺼운 솔더 마스크를 가지는 플립-칩어셈블리 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6774497B1 (enExample) |
| JP (1) | JP4703556B2 (enExample) |
| KR (1) | KR101010159B1 (enExample) |
| MY (1) | MY136290A (enExample) |
| TW (1) | TWI340442B (enExample) |
| WO (1) | WO2004086845A2 (enExample) |
Families Citing this family (114)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090111206A1 (en) | 1999-03-30 | 2009-04-30 | Daniel Luch | Collector grid, electrode structures and interrconnect structures for photovoltaic arrays and methods of manufacture |
| US7507903B2 (en) | 1999-03-30 | 2009-03-24 | Daniel Luch | Substrate and collector grid structures for integrated series connected photovoltaic arrays and process of manufacture of such arrays |
| US8138413B2 (en) | 2006-04-13 | 2012-03-20 | Daniel Luch | Collector grid and interconnect structures for photovoltaic arrays and modules |
| US8222513B2 (en) | 2006-04-13 | 2012-07-17 | Daniel Luch | Collector grid, electrode structures and interconnect structures for photovoltaic arrays and methods of manufacture |
| US8664030B2 (en) | 1999-03-30 | 2014-03-04 | Daniel Luch | Collector grid and interconnect structures for photovoltaic arrays and modules |
| US8198696B2 (en) | 2000-02-04 | 2012-06-12 | Daniel Luch | Substrate structures for integrated series connected photovoltaic arrays and process of manufacture of such arrays |
| US6916684B2 (en) * | 2003-03-18 | 2005-07-12 | Delphi Technologies, Inc. | Wafer-applied underfill process |
| TWI241675B (en) * | 2003-08-18 | 2005-10-11 | Siliconware Precision Industries Co Ltd | Chip carrier for semiconductor chip |
| TWI236105B (en) * | 2003-10-24 | 2005-07-11 | Advanced Semiconductor Eng | Manufacturing method for ball grid array package |
| US8853001B2 (en) * | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
| TWI358776B (en) * | 2003-11-08 | 2012-02-21 | Chippac Inc | Flip chip interconnection pad layout |
| USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| KR101237172B1 (ko) | 2003-11-10 | 2013-02-25 | 스태츠 칩팩, 엘티디. | 범프-온-리드 플립 칩 인터커넥션 |
| US8350384B2 (en) * | 2009-11-24 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
| US7901983B2 (en) * | 2004-11-10 | 2011-03-08 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US20070105277A1 (en) | 2004-11-10 | 2007-05-10 | Stats Chippac Ltd. | Solder joint flip chip interconnection |
| US8674500B2 (en) | 2003-12-31 | 2014-03-18 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US7659633B2 (en) | 2004-11-10 | 2010-02-09 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| US8129841B2 (en) * | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| US8026128B2 (en) * | 2004-11-10 | 2011-09-27 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
| US20060216860A1 (en) | 2005-03-25 | 2006-09-28 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
| US8076232B2 (en) | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| US8574959B2 (en) * | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
| US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| US20080290509A1 (en) * | 2003-12-02 | 2008-11-27 | United Test And Assembly Center | Chip Scale Package and Method of Assembling the Same |
| US7902678B2 (en) * | 2004-03-29 | 2011-03-08 | Nec Corporation | Semiconductor device and manufacturing method thereof |
| US20050224951A1 (en) * | 2004-03-31 | 2005-10-13 | Daewoong Suh | Jet-dispensed stress relief layer in contact arrays, and processes of making same |
| US7244634B2 (en) | 2004-03-31 | 2007-07-17 | Intel Corporation | Stress-relief layer and stress-compensation collar in contact arrays, and processes of making same |
| TWI230989B (en) * | 2004-05-05 | 2005-04-11 | Megic Corp | Chip bonding method |
| US20060157534A1 (en) * | 2004-08-06 | 2006-07-20 | Tessera, Inc. | Components with solder masks |
| US7838868B2 (en) * | 2005-01-20 | 2010-11-23 | Nanosolar, Inc. | Optoelectronic architecture having compound conducting substrate |
| US7732229B2 (en) * | 2004-09-18 | 2010-06-08 | Nanosolar, Inc. | Formation of solar cells with conductive barrier layers and foil substrates |
| FR2875995B1 (fr) * | 2004-09-24 | 2014-10-24 | Oberthur Card Syst Sa | Procede de montage d'un composant electronique sur un support, de preference mou, et entite electronique ainsi obtenue, telle q'un passeport |
| US20060099790A1 (en) * | 2004-10-26 | 2006-05-11 | Cheng-Yuan Lin | Method of implanting at least one solder bump on a printed circuit board |
| US8927315B1 (en) | 2005-01-20 | 2015-01-06 | Aeris Capital Sustainable Ip Ltd. | High-throughput assembly of series interconnected solar cells |
| US7148560B2 (en) * | 2005-01-25 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | IC chip package structure and underfill process |
| US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
| US20060255473A1 (en) | 2005-05-16 | 2006-11-16 | Stats Chippac Ltd. | Flip chip interconnect solder mask |
| US9258904B2 (en) * | 2005-05-16 | 2016-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
| US20060255476A1 (en) * | 2005-05-16 | 2006-11-16 | Kuhlman Frederick F | Electronic assembly with controlled solder joint thickness |
| US7371673B2 (en) * | 2005-05-17 | 2008-05-13 | Texas Instruments Incorporated | Method and apparatus for attaching an IC package to a PCB assembly |
| WO2006134891A1 (ja) * | 2005-06-16 | 2006-12-21 | Senju Metal Industry Co., Ltd. | モジュール基板のはんだ付け方法 |
| US20070026575A1 (en) * | 2005-06-24 | 2007-02-01 | Subramanian Sankara J | No flow underfill device and method |
| US20070149001A1 (en) * | 2005-12-22 | 2007-06-28 | Uka Harshad K | Flexible circuit |
| US20070238222A1 (en) * | 2006-03-28 | 2007-10-11 | Harries Richard J | Apparatuses and methods to enhance passivation and ILD reliability |
| US9865758B2 (en) | 2006-04-13 | 2018-01-09 | Daniel Luch | Collector grid and interconnect structures for photovoltaic arrays and modules |
| US9006563B2 (en) | 2006-04-13 | 2015-04-14 | Solannex, Inc. | Collector grid and interconnect structures for photovoltaic arrays and modules |
| US8729385B2 (en) | 2006-04-13 | 2014-05-20 | Daniel Luch | Collector grid and interconnect structures for photovoltaic arrays and modules |
| US9236512B2 (en) | 2006-04-13 | 2016-01-12 | Daniel Luch | Collector grid and interconnect structures for photovoltaic arrays and modules |
| US8884155B2 (en) | 2006-04-13 | 2014-11-11 | Daniel Luch | Collector grid and interconnect structures for photovoltaic arrays and modules |
| US8822810B2 (en) | 2006-04-13 | 2014-09-02 | Daniel Luch | Collector grid and interconnect structures for photovoltaic arrays and modules |
| US20070269930A1 (en) * | 2006-05-19 | 2007-11-22 | Texas Instruments Incorporated | Methodology to control underfill fillet size, flow-out and bleed in flip chips (FC), chip scale packages (CSP) and ball grid arrays (BGA) |
| US7626262B2 (en) * | 2006-06-14 | 2009-12-01 | Infineon Technologies Ag | Electrically conductive connection, electronic component and method for their production |
| US7713782B2 (en) * | 2006-09-22 | 2010-05-11 | Stats Chippac, Inc. | Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps |
| US9847309B2 (en) | 2006-09-22 | 2017-12-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate |
| DE102006059127A1 (de) | 2006-09-25 | 2008-03-27 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Anordnung optoelektronischer Bauelemente und Anordnung optoelektronischer Bauelemente |
| KR100780694B1 (ko) * | 2006-11-29 | 2007-11-30 | 주식회사 하이닉스반도체 | 플립 칩 패키지 |
| EP2092553A1 (en) * | 2006-12-08 | 2009-08-26 | Henkel AG & Co. KGaA | Process for coating a bumped semiconductor wafer |
| US20100007018A1 (en) * | 2006-12-08 | 2010-01-14 | Derek Wyatt | Process for coating a bumped semiconductor wafer |
| WO2008073432A2 (en) * | 2006-12-11 | 2008-06-19 | Fry's Metals, Inc. | No flow underfill process, composition, and reflow carrier |
| US8178392B2 (en) * | 2007-05-18 | 2012-05-15 | Stats Chippac Ltd. | Electronic system with expansion feature |
| JP5169171B2 (ja) * | 2007-11-26 | 2013-03-27 | パナソニック株式会社 | 電子部品の接合方法 |
| JP2009200338A (ja) * | 2008-02-22 | 2009-09-03 | Renesas Technology Corp | 半導体装置の製造方法 |
| US8349721B2 (en) * | 2008-03-19 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding |
| US7759137B2 (en) * | 2008-03-25 | 2010-07-20 | Stats Chippac, Ltd. | Flip chip interconnection structure with bump on partial pad and method thereof |
| US9345148B2 (en) | 2008-03-25 | 2016-05-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad |
| US20090250814A1 (en) * | 2008-04-03 | 2009-10-08 | Stats Chippac, Ltd. | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof |
| TWI393197B (zh) * | 2008-07-16 | 2013-04-11 | Chipmos Technoligies Inc | 晶片封裝 |
| US7897502B2 (en) * | 2008-09-10 | 2011-03-01 | Stats Chippac, Ltd. | Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers |
| US8198186B2 (en) | 2008-12-31 | 2012-06-12 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
| US8659172B2 (en) * | 2008-12-31 | 2014-02-25 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material with solder mask patch |
| US20100237500A1 (en) * | 2009-03-20 | 2010-09-23 | Stats Chippac, Ltd. | Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site |
| US8247243B2 (en) | 2009-05-22 | 2012-08-21 | Nanosolar, Inc. | Solar cell interconnection |
| US8039384B2 (en) | 2010-03-09 | 2011-10-18 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces |
| US8409978B2 (en) | 2010-06-24 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe |
| KR101692702B1 (ko) | 2010-07-01 | 2017-01-18 | 삼성전자주식회사 | 반도체 패키지 및 이를 제조하는 방법 |
| US8492197B2 (en) | 2010-08-17 | 2013-07-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
| US8228682B1 (en) | 2010-08-20 | 2012-07-24 | Xilinx, Inc. | Electronic assembly with trenches for underfill material |
| US8435834B2 (en) | 2010-09-13 | 2013-05-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP |
| TWI527178B (zh) * | 2010-12-15 | 2016-03-21 | 史達晶片有限公司 | 在無焊料遮罩的回焊期間的導電凸塊材料的自我局限的半導體裝置和方法 |
| JP2013048205A (ja) * | 2011-07-25 | 2013-03-07 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
| TWI536617B (zh) * | 2012-02-17 | 2016-06-01 | 鴻海精密工業股份有限公司 | 發光二極體燈條及其製造方法 |
| US9941176B2 (en) * | 2012-05-21 | 2018-04-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective solder bump formation on wafer |
| WO2013177541A1 (en) * | 2012-05-25 | 2013-11-28 | Applied Materials, Inc. | Polymer hot-wire chemical vapor deposition in chip scale packaging |
| US8802556B2 (en) | 2012-11-14 | 2014-08-12 | Qualcomm Incorporated | Barrier layer on bump and non-wettable coating on trace |
| US8994191B2 (en) * | 2013-01-21 | 2015-03-31 | Advanced Micro Devices (Shanghai) Co. Ltd. | Die-die stacking structure and method for making the same |
| US9673065B2 (en) * | 2013-07-18 | 2017-06-06 | Texas Instruments Incorporated | Semiconductor substrate having stress-absorbing surface layer |
| CN104347532B (zh) * | 2013-07-31 | 2017-08-04 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
| US9515006B2 (en) | 2013-09-27 | 2016-12-06 | Freescale Semiconductor, Inc. | 3D device packaging using through-substrate posts |
| US9508701B2 (en) | 2013-09-27 | 2016-11-29 | Freescale Semiconductor, Inc. | 3D device packaging using through-substrate pillars |
| US9508702B2 (en) | 2013-09-27 | 2016-11-29 | Freescale Semiconductor, Inc. | 3D device packaging using through-substrate posts |
| KR101550412B1 (ko) | 2014-08-13 | 2015-09-09 | 한국생산기술연구원 | 범프형성방법 |
| WO2017111786A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | No-flow adhesive for second and third level interconnects |
| US10160066B2 (en) * | 2016-11-01 | 2018-12-25 | GM Global Technology Operations LLC | Methods and systems for reinforced adhesive bonding using solder elements and flux |
| US9978707B1 (en) * | 2017-03-23 | 2018-05-22 | Delphi Technologies, Inc. | Electrical-device adhesive barrier |
| US10763131B2 (en) * | 2017-11-17 | 2020-09-01 | Micron Technology, Inc. | Semiconductor device with a multi-layered encapsulant and associated systems, devices, and methods |
| CN108901144A (zh) * | 2018-07-17 | 2018-11-27 | 天津瑞爱恩科技有限公司 | 增强印刷线路板软硬板组合强度的方法 |
| CN108966522A (zh) * | 2018-07-17 | 2018-12-07 | 天津瑞爱恩科技有限公司 | Qfn芯片焊点加固方法和元件焊点强化方法 |
| CN109181406A (zh) * | 2018-09-20 | 2019-01-11 | 何治伟 | 一种高催化效率型光固化白色阻焊油墨材料的制备方法 |
| KR102177853B1 (ko) * | 2019-05-30 | 2020-11-11 | 서울대학교 산학협력단 | 플렉서블 기판에서의 납땜 방법 |
| CN110707053A (zh) * | 2019-11-13 | 2020-01-17 | 东莞市新懿电子材料技术有限公司 | 一种芯片封装结构及芯片封装方法 |
| US11616027B2 (en) | 2019-12-17 | 2023-03-28 | Analog Devices International Unlimited Company | Integrated circuit packages to minimize stress on a semiconductor die |
| CN114051647B (zh) | 2020-01-29 | 2023-02-03 | 株式会社村田制作所 | 带电极的无源部件和带电极的无源部件的集合体 |
| KR20210114197A (ko) * | 2020-03-10 | 2021-09-23 | 엘지이노텍 주식회사 | 인쇄회로기판 |
| KR20220104388A (ko) * | 2021-01-18 | 2022-07-26 | 엘지이노텍 주식회사 | 반도체 패키지 및 그 제조방법 |
| DE102021113721A1 (de) * | 2021-05-27 | 2022-12-01 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur herstellung eines trägers, verfahren zur herstellung eines elektrischen bauteils, träger und elektrisches bauelement |
| US12431456B2 (en) * | 2021-07-12 | 2025-09-30 | Changxin Memory Technologies, Inc. | Package structure including a first non-conductive layer having a greater melt viscosity than a second non-conductive layer and method for fabricating the package structure |
| CN113923865B (zh) * | 2021-09-13 | 2023-08-22 | 华为技术有限公司 | 一种电子组件和电子设备 |
| US11935855B2 (en) | 2021-11-24 | 2024-03-19 | Advanced Semiconductor Engineering, Inc. | Electronic package structure and method for manufacturing the same |
| CN116153871A (zh) * | 2022-11-21 | 2023-05-23 | 昆明物理研究所 | 一种芯片封装中用底部填充胶及倒装焊接封装方法 |
| CN115881655A (zh) * | 2023-02-16 | 2023-03-31 | 成都频岢微电子有限公司 | 一种射频前端模组封装工艺结构 |
| JP2025040559A (ja) | 2023-09-12 | 2025-03-25 | 日亜化学工業株式会社 | 発光装置 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190940B1 (en) | 1999-01-21 | 2001-02-20 | Lucent Technologies Inc. | Flip chip assembly of semiconductor IC chips |
| US6265776B1 (en) | 1998-04-27 | 2001-07-24 | Fry's Metals, Inc. | Flip chip with integrated flux and underfill |
| US6410415B1 (en) | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3376203B2 (ja) | 1996-02-28 | 2003-02-10 | 株式会社東芝 | 半導体装置とその製造方法及びこの半導体装置を用いた実装構造体とその製造方法 |
| JPH10242211A (ja) * | 1996-12-24 | 1998-09-11 | Nitto Denko Corp | 半導体装置の製法 |
| DE1025587T1 (de) | 1997-07-21 | 2001-02-08 | Aguila Technologies, Inc. | Halbleiter-flipchippackung und herstellungsverfahren dafür |
| US6324069B1 (en) * | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
| US6228678B1 (en) * | 1998-04-27 | 2001-05-08 | Fry's Metals, Inc. | Flip chip with integrated mask and underfill |
| JP2000260819A (ja) * | 1999-03-10 | 2000-09-22 | Toshiba Corp | 半導体装置の製造方法 |
| US6194788B1 (en) | 1999-03-10 | 2001-02-27 | Alpha Metals, Inc. | Flip chip with integrated flux and underfill |
| US6271107B1 (en) * | 1999-03-31 | 2001-08-07 | Fujitsu Limited | Semiconductor with polymeric layer |
| US6294840B1 (en) * | 1999-11-18 | 2001-09-25 | Lsi Logic Corporation | Dual-thickness solder mask in integrated circuit package |
| US6700209B1 (en) | 1999-12-29 | 2004-03-02 | Intel Corporation | Partial underfill for flip-chip electronic packages |
| US6507118B1 (en) * | 2000-07-14 | 2003-01-14 | 3M Innovative Properties Company | Multi-metal layer circuit |
| JP4609617B2 (ja) * | 2000-08-01 | 2011-01-12 | 日本電気株式会社 | 半導体装置の実装方法及び実装構造体 |
-
2003
- 2003-03-28 US US10/402,631 patent/US6774497B1/en not_active Expired - Lifetime
-
2004
- 2004-03-24 KR KR1020057018230A patent/KR101010159B1/ko not_active Expired - Lifetime
- 2004-03-24 WO PCT/US2004/008939 patent/WO2004086845A2/en not_active Ceased
- 2004-03-24 JP JP2006507512A patent/JP4703556B2/ja not_active Expired - Lifetime
- 2004-03-29 TW TW093108546A patent/TWI340442B/zh not_active IP Right Cessation
- 2004-03-29 MY MYPI20041116A patent/MY136290A/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6265776B1 (en) | 1998-04-27 | 2001-07-24 | Fry's Metals, Inc. | Flip chip with integrated flux and underfill |
| US6190940B1 (en) | 1999-01-21 | 2001-02-20 | Lucent Technologies Inc. | Flip chip assembly of semiconductor IC chips |
| US6410415B1 (en) | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2004086845A2 (en) | 2004-10-14 |
| US6774497B1 (en) | 2004-08-10 |
| WO2004086845A3 (en) | 2005-05-19 |
| JP2006521703A (ja) | 2006-09-21 |
| JP4703556B2 (ja) | 2011-06-15 |
| TW200503222A (en) | 2005-01-16 |
| KR20050118694A (ko) | 2005-12-19 |
| TWI340442B (en) | 2011-04-11 |
| MY136290A (en) | 2008-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101010159B1 (ko) | 얇은 언더필 및 두꺼운 솔더 마스크를 가지는 플립-칩어셈블리 | |
| US6821878B2 (en) | Area-array device assembly with pre-applied underfill layers on printed wiring board | |
| US10515918B2 (en) | Methods of fluxless micro-piercing of solder balls, and resulting devices | |
| JP2662190B2 (ja) | 電子素子アセンブリおよび再加工方法 | |
| US6610559B2 (en) | Integrated void-free process for assembling a solder bumped chip | |
| CN100373597C (zh) | 集成电路封装结构及底部填充胶工艺 | |
| US6294840B1 (en) | Dual-thickness solder mask in integrated circuit package | |
| JP5510795B2 (ja) | 電子部品の実装構造、電子部品の実装方法、並びに電子部品実装用基板 | |
| US7081405B2 (en) | Package module for an IC device and method of forming the same | |
| US7180007B2 (en) | Electronic circuit device and its manufacturing method | |
| US20050263887A1 (en) | Circuit carrier and fabrication method thereof | |
| CN100576476C (zh) | 芯片埋入半导体封装基板结构及其制法 | |
| US20200251436A1 (en) | Semiconductor device package with improved die pad and solder mask design | |
| US7059048B2 (en) | Wafer-level underfill process making use of sacrificial contact pad protective material | |
| US6259155B1 (en) | Polymer enhanced column grid array | |
| US20090211798A1 (en) | Pga type wiring board and method of manufacturing the same | |
| KR102380834B1 (ko) | 인쇄회로기판, 반도체 패키지 및 이들의 제조방법 | |
| US8168525B2 (en) | Electronic part mounting board and method of mounting the same | |
| KR20030085449A (ko) | 개량된 플립 칩 패키지 | |
| US20020066523A1 (en) | Attaching devices using polymers | |
| JP4593444B2 (ja) | 電子部品実装構造体の製造方法 | |
| KR19980070399A (ko) | 플립칩 부착물 | |
| JPH11145320A (ja) | 半導体装置及びその製造方法 | |
| KR20060058259A (ko) | 플립칩의 실장구조 및 그 실장방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20050927 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20090324 Comment text: Request for Examination of Application |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20101025 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20110114 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20110114 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| FPAY | Annual fee payment |
Payment date: 20131227 Year of fee payment: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20131227 Start annual number: 4 End annual number: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20141226 Year of fee payment: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20141226 Start annual number: 5 End annual number: 5 |
|
| FPAY | Annual fee payment |
Payment date: 20151228 Year of fee payment: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20151228 Start annual number: 6 End annual number: 6 |
|
| FPAY | Annual fee payment |
Payment date: 20170102 Year of fee payment: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20170102 Start annual number: 7 End annual number: 7 |
|
| FPAY | Annual fee payment |
Payment date: 20180110 Year of fee payment: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20180110 Start annual number: 8 End annual number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20190102 Year of fee payment: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20190102 Start annual number: 9 End annual number: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20200102 Year of fee payment: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20200102 Start annual number: 10 End annual number: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20210108 Start annual number: 11 End annual number: 11 |
|
| PC1801 | Expiration of term |
Termination date: 20240924 Termination category: Expiration of duration |