Classifications

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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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Definitions

• This invention relates generally to semiconductor wafer processing and integrated circuit packaging.
• the invention relates to bumped semiconductor wafers with wafer-applied underfill, flip chips and flip-chip assemblies, and a method of manufacturing a semiconductor wafer, a flip-chip, or a flip-chip module with a conjoined underfill and solder mask layer.
• Underfill materials are typically applied between the surface of the IC and the PWB.
• the underfill is applied at one or more edges of the flip-chip bonded die and capillary action wicks the fluid under the die. During this process, the entire die surface is coated with the underfill.
• the underfill may be applied to the PWB prior to die placement.
• solder reflow the underfill liquefies and wets the die site on the PCB and the die surface at the bottom and on the edges of the die.
• the capillary flow technology uses underfill encapsulant material of a suitable polymer in the void between the chip and the substrate.
• the underfill material is typically dispensed around two adjacent sides of the semiconductor chip, with the underfill material flowing by capillary action to fill the gap between the chip and the substrate. Baking or heat treatment then hardens the underfill material.
• the underfill encapsulant needs to adhere well to the chip and the substrate to improve the solder joint integrity.
• Underfilling the chip with a subsequently cured encapsulant typically reduces solder joint cracking caused by a thermal expansion mismatch between the chip and the substrate.
• the cured encapsulant reduces the level of stresses on the solder joints, induced by differential expansion and contraction.
• An example of an underfill material being applied around the periphery of a flip-chip assembly and partially wicked into the interior region is described by Raiser, et al., in U.S. patent 6,365,441, "Partial Underfill for Flip Chip Electronic Packages" issued April 2, 2002.
• Underfilling methods may use an underfill layer on the die surface and flux applied to a PCB.
• Yamaji presents an underfill on the surface of a chip and top ends of the bumps, with the flux on the mounting substrate, as described in U.S. patent 5,925,936, "Semiconductor Device for Face Down Bonding to a Mounting Substrate and a Method of Manufacturing the Same” issued July 20, 1999.
• Capote and others disclose a simplified process for flip-chip attachment to a substrate, which pre-coats the bumped IC chip with an encapsulant underfill material, as described in U.S. patent 6,121,689, "Semiconductor Flip-Chip Package and Method for the Fabrication Thereof” issued September 19, 2000.
• the encapsulant encases the bumps that extend.from contacts on the surface of the chip to the pads of the substrate.
• a semiconductor wafer with an array of integrated circuits is coated with underfill material that is approximately the same height as the bumps of a die, before the bumped chips are soldered to a substrate.
• This thick coating may result in the interference with solder joint formation between the bumps and pads on the electrical substrate.
• the close proximity of the underfill to the bump-pad interface can create a physical barrier to consistent, reliable soldering.
• This approach relies solely on the pre-applied underfill material to fill the gap between the chip and the substrate.
• the thickness of the underfill-material coating which is approximately the same height as the bumps of the die, can result in problems during the placement of the die.
• the thick underfill coating may alter the size and shape of the exposed area of the tops of the solder bumps. These tops may be used as locating features for placement. With coated chips, the exposed area above the bumps is random and the bump diameter may be hard to define, making it difficult to inspect and register the coated parts prior to placement. However, when thinner coatings are used, the volume of pre-applied underfill material is insufficient to fill the gap between the chip and the substrate.
• the packaging technology would allow the flip chips to be bonded effectively to a substrate, with highly reliable electrical interconnections and protective underfill material for secure die bonding, stress relief for the bumps and effective environmental protection. Furthermore, the technology would not require pre-coating material up to the top of the solder bumps, would eliminate bump-recognition challenges, and would eliminate an additional tack step typically needed to maintain alignment. Flexibility to apply an optional flux layer before or after bulk epoxy coatings is also desirable.
• a bumped flip chip is provided that includes an active surface and a plurality of connective bumps extending from the active surface, each connective bump including a side region.
• a thin layer of an underfill material is applied to the active surface of the flip chip and to a portion of the side regions of the connective bumps.
• the flip chip is positioned on the electrical substrate that includes a thick layer of a solder mask disposed on the electrical substrate. The flip chip is heated to electrically connect the flip chip to the electrical substrate, wherein the underfill material and the solder mask combine to form a stress-relief layer when the flip chip is electrically connected to the electrical substrate.
• the flip-chip assembly comprises a bumped flip chip with an active surface and a plurality of connective bumps extending from the active surface.
• a thin layer of an underfill material is disposed on the active surface of the flip chip and on a portion of a side region of the connective bumps.
• the bumped flip chip is electrically connected to an electrical substrate that includes a thick layer of a solder mask, the solder mask and the underfill material combining to form a stress- relief layer.
• a bumped semiconductor wafer including an active surface and a plurality of connective bumps extending from the active surface is provided.
• An underfill material is applied to the active surface of the semiconductor wafer and a portion of a side region of the connective bumps, wherein the underfill material extends from the active surface to a thickness between nominally 20 percent and 60 percent of a connective bump height.
• the underfill material is heated to flow around the connective bumps.
• FIG. 1 illustrates a cross-sectional view of a bumped flip chip, in accordance with one embodiment of the current invention
• FIG.2a illustrates a cross-sectional view of a bumped flip chip and an electrical substrate with a solder mask prior to attachment, in accordance with one embodiment of the current invention
• FIG. 2b illustrates a cross-sectional view of a bumped flip chip and an electrical substrate with a solder mask after attachment, in accordance with one embodiment of the current invention
• FIG. 3 illustrates a flow diagram of a method for attaching a flip chip to an electrical substrate, in accordance with one embodiment of the current invention
• FIG.4 illustrates a bumped semiconductor wafer with wafer-applied underfill, in accordance with one embodiment of the current invention.
• FIG. 5 illustrates a flow diagram for a wafer-applied underfill process, in accordance with one embodiment of the current invention.
• FIG. 1 shows a cross-sectional view of a bumped flip chip, in accordance with one embodiment of the present invention at 100.
• Bumped flip chip 100 includes a semiconductor substrate 110 with an active surface 112, and a plurality of connective bumps 120 with side regions 122 extending from active surface 112.
• Bumped flip chip 100 includes an underfill material 130 applied to active surface 112 and to a portion of side regions 122 of connective bumps 120.
• Bumped flip chip 100 may contain a multitude of active components, passive components, or any combination thereof. Bumped flip chip 100 may contain electronic components such as resistors, capacitors, and transistors. These components may be integrated into bumped flip chip 100, which may contain one or more integrated circuits. Bumped flip chip 100 may include a set of electrical interconnect traces and flip-chip pads 114.
• Semiconductor substrate 110 typically contains active and passive electronic devices such as transistors, capacitors and resistors forming one or more integrated circuits on active surface 112 of semiconductor substrate 110. External connections to the integrated circuit are made through metal traces and pads 114 that are part of active surface 112. For clarity, dielectric layers, passivation layers, metal interconnect layers and contacts that form the interconnections to the integrated circuit are not illustrated.
• Semiconductor substrate 110 may be, for example, a silicon substrate, a gallium-arsenide substrate, or other electronic or optoelectronic substrate as is currently known in the art.
• a flux layer 124 may be positioned on a top region of connective bumps 120.
• Flux layer 124 may include acidic components, for example, which remove oxides from the solder bumps or solder balls when melting or reflowing the bumps to an electrical substrate.
• Flux layer 124 may be located only on the tops of the bumps, or may cover the bumps and underfill material 130 by using, for example, a spraying or a dipping technique.
• Underfill material 130 is disposed on active surface 112. Underfill material 130 provides a coating to protect the traces and pads of bumped flip chip 100 and to offer strain or stress relief for the solder bumps or solder balls when the flip chip is electrically connected to an electrical substrate such as a printed wiring board. Underfill material 130 supplies additional bonding strength for the die attach. Underfill material 130 also provides stress relief at the solder ball interfaces during temperature excursions of the flip-chip assembly, and provides environmental protection from moisture, particles, and other contamination that may degrade the performance of the flip chip.
• Underfill material 130 typically covers at least a portion of side regions 122 of connective bumps 120.
• underfill material 130 extends from active surface 112 of semiconductor substrate 110 to a thickness, for example, between nominally 20 percent and 60 percent of the height of a connective bump.
• the thickness of underfill material 130 may be selected in coordination with the thickness of a solder mask to provide proper underfill material flow and to control fillets of underfill material around at least a portion of the edges of bumped flip chip 100 when assembled.
• Underfill material 130 includes curable components that allow underfill material 130 to be pliable and formable during processing, yet to be hard and chemically resistant when bumped flip chip 100 is secured to an electrical substrate.
• Underfill material 130 may comprise a filled epoxy, such as a one- or two-part epoxy that contains insulating microspheres to separate bumped flip chip 100 from an electrical substrate during die attach processes. Fillers may be added to the selective underfill material to improve thermal expansion characteristics of the underfill material.
• Underfill material 130 may include, for example, an epoxy, a thermoplastic material, a thermoset material, polyimide, polyurethane, a polymeric material, a filled epoxy, a filled thermoplastic material, a filled thermoset material, filled polyimide, filled polyurethane, a filled polymeric material, a fluxing underfill, or a suitable underfill compound.
• FIG.2a and FIG.2b illustrate a cross-sectional view of a bumped flip chip and an electrical substrate with a solder mask prior to and after attachment, in accordance with one embodiment of the present invention at 200.
• Flip-chip assembly 200 includes a bumped flip chip 210 and an electrical substrate 240.
• Bumped flip chip 210 includes an active surface 212 and a plurality of connective bumps 220 extending from active surface 212.
• Bumped flip chip 210 also includes a thin layer of an underfill material 230 disposed on active surface 212 of bumped flip chip 210.
• Electrical substrate 240 includes a thick layer of a solder mask 250 disposed on electrical substrate 240.
• Connective bumps 220 may comprise at least one solder bump or at least one solder ball on the active surface of bumped flip chip 210.
• Connective bumps 220 have a side region 222.
• Connective bumps 220 are connected to pads 214 on active surface 212 of bumped flip chip 210.
• Underfill material 230 comprises a material such as an epoxy, a thermoplastic material, a thermoset material, polyimide, polyurethane, a polymeric material, a filled epoxy, a filled thermoplastic material, a filled thermoset material, filled polyimide, filled polyurethane, a filled polymeric material, a fluxing underfill, or a suitable underfill compound. Underfill material 230 may be disposed on a portion of a side region of connective bumps 220.
• solder mask 250 has a thickness of 3.5 mils or 78 percent of the r initial bump height.
• Underfill material 230 flows into and fills cavities around connective bumps 220 during assembly in this non-solder mask defined pad.
• the thickness of underfill material 230 is 2.1 mils or 47 percent of the initial bump height.
• the thickness of underfill material 230 is 2.3 mils or 51 percent of the initial bump height.
• the thickness of underfill material 230 is 2.7 mils or 60 percent of the initial bump height.
• a bumped flip chip is provided, as seen at block 310.
• the flip chip includes an active surface and a plurality of connective bumps extending from the active surface.
• Each connective bump includes a side region.
• the connective bumps may comprise at least one solder bump or at least one solder ball on the active surface of the flip chip.
• a thin layer of an underfill material is applied to the active surface of the flip chip and to a portion of the side regions of the connective bumps, as seen at block 320.
• the underfill material may be applied, for example, using a screen.
• the screen typically has features such as cutouts and windows to allow underfill material to be applied through the screen and onto the bumped flip chip.
• the screen may be aligned to the bumped flip chip or to an array of bumped flip chips on a semiconductor wafer.
• the underfill material may be in the form of a viscous liquid, paste, gel, suspension, or slurry such that the underfill material can be applied through the screen.
• the underfill material may then be dried and stabilized, partially cured, or otherwise solidified.
• the underfill material is often dried to remove the majority or all of the solvents from the underfill material. After application and prior to drying, the underfill material may be removed from an upper portion of the connective bumps as needed, such as with a squeegee or other wiping tool.
• the underfill material is applied by positioning a patterned mask against the active surface of the flip chip, and dispensing the underfill material through the patterned mask.
• the patterned mask often comprises a fine- mesh screen with one or more barrier features on the screen.
• the barrier features may include features that cover, for example, connective bumps and locations where no underfill material is desired.
• the patterned mask may include barrier features over the streets when wafer-level underfill is applied.
• the patterned mask may be a stencil with holes and other features punched or formed in a sheet of material such as plastic or metal.
• the die-cut film or patterned underfill film of one exemplary embodiment is aligned to the bumped flip chip, positioned against the bumped surface of the flip chip, and pressed onto the flip chip while heating to adhere the underfill material to the flip chip.
• the backing layer then can be removed.
• the region between the patterned underfill film and the flip chip is pumped out to remove any air, and then the underfill material is heated with the flip chip to adhere the selective underfill to the flip chip.
• the underfill material may extend, for example, from the active surface of the flip chip to a thickness between nominally 20 percent and 60 percent of a connective bump height, allowing the underfill material to combine with the solder mask on the electrical substrate to provide a stress-relief layer.
• the stress-relief layer serves as and comprises a moisture-penetration barrier.
• the underfill material is applied usually to at least a portion of the side regions of the connective bumps.
• the underfill material is heat-treated in a processing sometimes referred to as b- staging.
• the underfill material is heated to flow the underfill material around the solder bumps.
• the temperature and time for heat-treating and the viscosity of the underfill material may be selected such that the underfill material flows adequately around the bumps.
• the underfill material may be heated to a predefined temperature to drive out the remaining solvents and to solidify the material, allowing a small degree of cross-linking.
• Underfill materials based on epoxies and other polymeric materials are typically heated to an underfill- material staging temperature to dry the underfill material such that the underfill material is no longer tacky.
• the underfill material may be dried and remain uncured or be partially cured after the heating step.
• the underfill-material staging temperature may be between, for example, 80 degrees centigrade and 150 degrees centigrade.
• the heat-treatment step is often done in a controlled environment such as air, nitrogen, or vacuum. Staging temperatures are typically sustained for thirty minutes to over two hours.
• a flux layer is applied to the flip chip, as seen at block 330.
• the flux layer is applied to at least a top portion of the connective bumps.
• the flux layer may be applied, for example, by using a stencil, a screen with features, or a patterned mask.
• the flux layer may be applied to the connective bumps by dispensing a flux material through the stencil, screen or patterned mask and drying it.
• the flux layer may be applied by spraying the active side of the flip chip or a select area of the electrical substrate.
• the flux layer may be applied by dipping the bumped flip chip into a flux bath or flux solution and then dried.
• the flux layer may comprise, for example, a fluxing underfill or a flux with properties that will not interfere with formation of a bond between the underfill material and the solder mask.
• Flux may be included in the underfill material such as when fluxing underfill material is used. Volatile compounds would not be emitted, for example, during reflow of the "solvent-free" solder flux.
• Examples of fluxing underfills include Dexter FF 2200 or Loctite 3594.
• An example of an epoxy flip-chip flux is PK-001 manufactured by.Indium Corporation of America of Clinton, NY.
• the flux layer may be applied prior to application of the underfill material.
• Flux may be omitted entirely, for example, when metals are selected for the connective bumps and the pads on the electrical substrate that do not require solder flux such as non-oxidizing noble metal bumps. In another example, flux may be omitted for bumps that are thermosonically bonded to the electrical substrate pads.
• the flip chip is positioned on the electrical substrate, as seen at block 340. The thinner underfill material allows for cleaner bumps and improved vision recognition when the bumped flip chips are robotically placed.
• the electrical substrate includes a thick layer of a solder mask disposed on the electrical substrate. The bumps are retained in the desired position during the placement stage, in part by positioning the bumps into corresponding holes in the solder mask.
• FIG.5 shows a flow diagram for a wafer-applied underfill process, in accordance with one embodiment of the present invention at 500.
• Wafer-applied underfill process 500 includes steps to apply underfill material to a bumped semiconductor wafer.
• the underfill material may be applied by aligning a patterned underfill film to the bumped semiconductor wafer.
• the patterned underfill film often includes a backing layer, an underfill material disposed on the backing layer, and at least one open feature in the underfill material corresponding to the plurality of connective bumps.
• the patterned underfill film may be laminated to the bumped semiconductor wafer, such as by pressing the patterned underfill film against the bumped semiconductor wafer when the patterned underfill film and the bumped semiconductor wafer are at a lamination temperature.
• a typical lamination temperature is between 60 degrees centigrade and 100 degrees centigrade, for example.
• the patterned underfill film may be pressed with a hot roller, with a press, or with any suitable pressing mechanism.
• the patterned underfill film may be laminated by pumping out a region between the patterned underfill film and the bumped semiconductor wafer to remove trapped air and to firmly hold the patterned underfill film against the bumped semiconductor wafer, and by heating the patterned underfill film and the bumped semiconductor wafer to a lamination temperature.
• the bumped semiconductor wafer and the patterned underfill film is heated to a lamination temperature usually between 60 degrees centigrade and 100 degrees centigrade.
• the backing layer is removed from the patterned underfill film, and the underfill material layer remains laminated to the bumped semiconductor wafer.
• the backing layer may be removed by peeling back or otherwise separating it from the underfill material and the bumped semiconductor wafer.
• a flux layer is often applied to the connective bumps, as seen at block 530.
• the flux layer may be applied to at least a top portion of the connective bumps.
• a screen, stencil, or patterned mask is used to apply the flux layer to the tops of the bumps.
• the flux can be sprayed onto the bumps and the wafer.
• the flux is applied by dipping the semiconductor wafer into a flux solution and then drying the flux solution to leave a thin layer of flux on the solder bumps or solder balls.
• the flux is included within the underfill material.
• the flux layer may be applied after the underfill material is applied, as illustrated.
• the flux layer may be applied prior to underfill application.
• the flux layer may be applied after the application of underfill material as illustrated.
• the flux layer may be applied before the application of the underfill material.
• the semiconductor wafer with the underfill material is heated to flow the underfill material around the connective bumps, as seen at block 540.
• the underfill material may be heated to or above an underfill-material staging temperature.
• the staging temperature is selected to drive off and evaporate any remaining solvents from within the underfill material.
• the underfill material can be dried, for example, until it is no longer tacky or has a desired level of tackiness. During this heat treatment, the underfill may become partially cross- linked or partially cured.
• the underfill-material staging temperature is typically between 80 degrees centigrade and 150 degrees centigrade. Drying times may be between two minutes and twenty minutes or longer. The underfill material may partially cure during this step. The underfill material usually is softened and flows to provide good adhesion and coverage of the side regions of the bumps. Typically when staging cycles are used, the cycles are greater than ten minutes to over two hours at a temperature up to 150 degrees centigrade or higher in an air, nitrogen, or other controlled environment.
• the semiconductor wafer with the underfill material is diced, as seen at block 550.
• the semiconductor wafer may be diced to form individual bumped flip chips using a dicing saw or similar equipment available in the semiconductor industry for dicing wafers.
• the dicing is accomplished typically by attaching the semiconductor wafer to an adhesive backing material and then cutting the wafer along scribe lines between the bumped die.
• the bumped die are then removed and may be placed onto tape and reel, into waffle packs, or in other suitable media for storage and shipping.
• the flip chips have bumps and thin underfill material that are suitable for attachment to printed wiring boards and other electrical substrates in flip-chip assemblies.
• dicing is typically performed after bumping and the application of wafer- applied underfill, dicing can be done prior to application of the underfill material, for example, or before application of the flux layer.

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• 2003
  • 2003-03-28 US US10/402,631 patent/US6774497B1/en not_active Expired - Lifetime
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