WO2008073432A2 - No flow underfill process, composition, and reflow carrier - Google Patents

No flow underfill process, composition, and reflow carrier

Info

Publication number
WO2008073432A2
WO2008073432A2 PCT/US2007/025337 US2007025337W WO2008073432A2 WO 2008073432 A2 WO2008073432 A2 WO 2008073432A2 US 2007025337 W US2007025337 W US 2007025337W WO 2008073432 A2 WO2008073432 A2 WO 2008073432A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
electronic device
reflow
integrated circuit
mechanical pressure
Prior art date
Application number
PCT/US2007/025337
Other languages
French (fr)
Other versions
WO2008073432A3 (en
Inventor
Martin Sobczak
Mark Wilson
Michaels A. Previti
Senthil Kanagavel
Original Assignee
Fry's Metals, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fry's Metals, Inc. filed Critical Fry's Metals, Inc.
Publication of WO2008073432A2 publication Critical patent/WO2008073432A2/en
Publication of WO2008073432A3 publication Critical patent/WO2008073432A3/en

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    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Definitions

  • the present invention generally relates to the packaging of semiconductor integrated circuit devices, and more specifically to a no-flow underfill process and apparatus for preparing packaged area array and flip chip assemblies.
  • a semiconductor integrated circuit device i.e., a microchip, silicon chip, or simply chip
  • the package is then mounted onto a printed circuit board (PCB) in a manner which achieves electrical interconnection between the integrated circuit device and the PCB.
  • PCB printed circuit board
  • the original configuration comprised an IC die in a package substrate with the active side facing away from the substrate. Wires were then bonded to pads on the IC die to make the first level connection to the package substrate.
  • This technology is generally referred to as "wire bonded interconnect.”
  • the die is typically encapsulated with mold compound, typically a plastic, ceramic, or epoxy. Wire bonded interconnect can also be utilized for second level interconnect connecting the package to the PCB.
  • solder is reflowed on an integrated circuit device pad forming a solder bump.
  • the package substrate has a matching pad corresponding to the bump on the die.
  • the die is placed with the active side facing toward the package substrate, the bump and pad are aligned, and the assembly is reflowed again so that the solder-pad interconnect is formed on the package substrate side.
  • This technology is generally referred to as "flip chip” because the active side faces the substrate.
  • the solder bump self-aligns with the pad or substrate metallization and during liquidus, and gravity assists in the "collapse" of the solder bump to form the interconnect.
  • interconnect Interconnection from the integrated circuit device to the package substrate is the first level interconnect, typically flip chip or WLCSP.
  • Second level interconnect describes interconnection from the package substrate to a board.
  • the standoff height and pitch in second level interconnect is generally larger allowing solder balls to be used.
  • Devices that are grouped into this category include BGA and CSP packages.
  • the process for attaching area array devices may vary depending on configuration and reliability requirements.
  • a conventional flip chip assembly process employing capillary underfill may have the following steps:
  • Dispense underfill composition typically by capillary action
  • the substrate passes from one operation to the next in a carrier or "boat.”
  • the boat serves several purposes including confining the substrate, acting as a shuttle from one operation to the next, and inventory control.
  • Underfill of area array devices is required to enable sufficient reliability performance of the chip package. Ideally, no underfill would be needed to meet reliability targets, which is the case for some BGA devices. However, the smaller pitch, smaller gap height, and large CTE mismatch between the device and the package substrate in flip chip assemblies necessitate use of an underfill. Additionally, underfill of area array devices is utilized to ensure assemblies meet the reliability requirements of hand held electronics, primarily drop-shock, even for BGA packages. However, the capillary underfill operation adds significant time to the area array assembly process.
  • No-flow underfill is an attractive alternative to conventional capillary underfill in that it enables a significant reduction in assembly steps and enables stress reduction after assembly.
  • No- flow underfill combines the functions of the flux and the underfill into one system.
  • a typical no-flow underfill area assembly process may have the following steps:
  • thermocompression bonding TAB
  • TCB a heated head applies pressure and heat to the die, sometimes with heat from the bottom of the package substrate on the side opposite the IC die to reflow the solder and to provide enough pressure to overcome the buoyancy effect of the no-flow underfill.
  • the die can be placed and heated to interconnect at time of placement.
  • a second version involves placing the die in one operation then shuttling to a bonding station where heat is employed to interconnect.
  • the disadvantage of thermocompression bonding is primarily due to the complexity of the alignment and bonding operations resulting in yield loss. Yield loss can be attributed to misalignment, incomplete wetting of the solder, or material entrapment at either the placement or the bonding step.
  • TCB equipment In addition, capital equipment is required that is not typically found on conventional area array assembly lines. Due to the complexity of the equipment, it is highly engineered and therefore rather expensive. Manufacturers of TCB equipment include Toray, Panasonic, and Grohmann Engineering. The complexity and cost of the TCB equipment is high, especially in the context of high volume manufacturing (HVM). Accordingly, a need exists for an alternative method to apply pressure during the reflow process.
  • HVM high volume manufacturing
  • the invention is directed to a method for forming an electrical interconnection between an active surface of a semiconductor integrated circuit device and a surface of an electronic device substrate, the method comprising applying pressure between the device and the substrate during reflow to enhance collapse of the reflowed solder bump and form an electrical interconnection between the active surface of the electronic device substrate and the active surface of the semiconductor integrated circuit device.
  • the invention is directed to a reflow carrier apparatus for carrying an electronic device substrate and an electronic device in a reflow oven during attachment of the device to the substrate, the carrier comprising a carrier surface and a mechanical pressure device for applying pressure between the electronic device and the electronic device substrate.
  • FIG. 1 is a top down view of a carrier boat equipped with a clip according to the present invention.
  • FIG. 2 is a cross-sectional view of a carrier boat equipped with a clip according to the present invention.
  • FIG. 3A and 3B are photographs of boats applicable to the process of the present invention.
  • FIGS. 4 through 1 1 are cross-sectional schematic representations of various alternative embodiments of the mechanical pressure device of the invention.
  • the present invention is directed to the packaging of a semiconductor integrated circuit device, i.e., a singulated die or a wafer as in wafer level packaging.
  • the present invention is directed to a method of packaging a semiconductor integrated circuit device inside a package substrate or support structure, (e.g., a ceramic chip carrier package or a leadframe) which is then electrically interconnected with a board in second level interconnect.
  • a package substrate or support structure e.g., a ceramic chip carrier package or a leadframe
  • the present invention is particularly suitable for manufacturing flip chip assemblies.
  • a pressure mechanism is applied to an inactive surface of a semiconductor integrated circuit die after it has been placed in the package substrate or support structure and prior to solder reflow.
  • the pressure mechanism holds the IC die having a solder bump on a die pad on its active side in place in the package; applies pressure to the inactive side of the 1C die to enhance interconnection between the die pad, solder bump, and a substrate pad on the surface of the package substrate; maintains alignment between the solder bumps or copper posts and the pads on the substrate; and enhances collapse of the solder bump during reflow thus forming an electrical interconnection between the die pad and the substrate pad.
  • a pressure mechanism is applied to an inactive surface of a semiconductor integrated circuit wafer after it has been placed in the package substrate or support structure and prior to solder reflow.
  • the pressure mechanism holds the wafer having a solder bump on a die pad on its active side in place in the package, applies pressure to the inactive side of the wafer to enhance interconnection between the die pad, solder bump, and a substrate pad on the surface of the package substrate; to maintain alignment; and to enhance collapse of the solder bump during reflow thus forming an electrical interconnection between the die pad and the substrate pad.
  • the pressure applied by the pressure mechanism in accordance with this invention is typically on the order of between about 0.2 and about 20 psi.
  • a package substrate or support structure may be loaded into a pocket in a carrier boat, which shuttles the substrate from one operation to the next.
  • the boat may comprise from two to twelve pockets, more typically from ten to twelve pockets.
  • the pockets may be arranged in a single row or in two or more rows, for example, two rows of five or six pockets.
  • the packaging process of the present invention provides a simple, cheap, efficient solution to the problem of ensuring adequate electrical interconnection between the at least one solder bump on the active side of the semiconductor integrated circuit device and the substrate pad of the package substrate.
  • the pressure mechanism is a spring-loaded clip on the boat positioned adjacent to a pocket which holds a package substrate. After the semiconductor integrated circuit device is positioned on a surface of a package substrate, the spring-loaded clip is inserted on a surface of the semiconductor integrated circuit device to hold the semiconductor integrated circuit device in place on the package substrate.
  • the assembly is a flip chip assembly in which the active surface faces toward the package substrate, and the clip is inserted over the inactive surface of the semiconductor integrated circuit device.
  • the clip may be equipped with a central protrusion which contacts the center of the inactive side of the semiconductor integrated circuit device.
  • the clip applies adequate pressure to hold the semiconductor integrated circuit device and package substrate together while only minimally contacting the surface of the semiconductor integrated circuit device.
  • the spring-loaded clip applies pressure which enhances collapse of the solder bump onto the substrate pad of the package substrate.
  • the method is suited for packaging integrated circuit devices, which are microelectronic devices manufactured in the surface of a thin substrate of semiconductor material, most often silicon. Although germanium and gallium-arsenide devices are applicable, these are less common than devices manufactured in silicon.
  • the integrated circuit device may be a wafer (as in wafer-level packaging, WLP) prior to singulation or a die which has been singulated from a semiconductor wafer.
  • Integrated circuit devices comprise semiconductor devices (diodes and transistors) and passive components (resistors, capacitors, and inductors).
  • Preparation of a wafer or die for inserting into a package, such as a flip chip assembly is known in the art.
  • the preparation of an integrated circuit die for packaging includes the following steps:
  • solder for joining the integrated circuit device, i.e., wafer or singulated die, and an electronic device substrate such as a package substrate or support structure depends upon several factors.
  • the solder should be compatible with the metal or metals used to form the die pads of the integrated circuit device and the substrate pads of the package substrate (i.e., upon removal of oxides from said metals by the fluxing agent, the solder wets the pads during reflow to form an electrically conductive bond).
  • the selection of the solder may depend upon environmental and/or worker safety concerns. For example, there is an ever increasing demand for lead-free solders.
  • the solder alloy preferably melts at a sufficiently low temperature so that there is no degradation of the integrated circuit device or the package substrate during reflow.
  • the solder preferably melts at a temperature at which the underfill does not degrade.
  • the solder melts at a temperature between about 180 0 C and about 260°C. More preferably, the solder melts at a temperature between about 22O 0 C and about 260 0 C.
  • the solder alloy is preferably stable (i.e., it does not evaporate) at a temperature that is between about 1O 0 C and about 40 0 C above the melt temperature because typical reflow operations result in the solder alloy attaining such temperatures.
  • a relatively high melting temperature such as between about 21O 0 C and about 24O 0 C
  • the reflow temperature is typically between about 220 0 C and about 28O 0 C.
  • a relatively low reflow temperature that is between about 17O 0 C and about 23O 0 C is typical.
  • any conventional leaded solders e.g., Sn63Pb37 and Sn 62 Pb 36 Ag 2
  • Particularly useful solder alloys are substantially free of lead, which are commonly referred to as Pb-free solder alloys and typically contain less than about 0.3 wt% of lead. Pb-free solder alloys tend to have higher liquidus temperatures and/or require longer reflow durations than lead-containing solder alloys.
  • Exemplary Pb-free solder alloys include: Au 80 Sn 2 O, Sn 9 62Ag 2 5Cu 08 Sb 0 5, Sn 6 SAg 25 SbI 0 , Sn 96 5Ag 3 5, Sn 95 5 Ag 3 sCuo 7, Sn 96 5Ag 3 Cu 0 5, Sn 95 5Ag 4 Cu 0 5, Sn 93 6 Ag 4 7 Cui 7, Sn 42 Bi 58 , Sn 90 Bi 9 5 C ⁇ io 5, Sn 99 3Cu 0 7, Sn 99 CUi, Sn ⁇ Cu 3 , Sn 8 7 ilnio 5Ag 2 Sb 04 , Sn 77 2 In 20 Ag 2 8 , Sn 63 6 Ins 8 Zn 2 76, Sn 97 Sb 3 and Sn 95 Sb 5 .
  • the interconnect structure is equipped with a compression stop, which is a spacer-type structure to prevent the die from being pressed completely against the package substrate during solder liquidus.
  • a copper pillar or a post on the die in combination with solder on pad may be utilized to maintain standoff height between the die and the substrate.
  • a standoff is maintained by including a compression stop in the form of spacer beads or spacer technology into the no- flow underfill formulation.
  • solder alloy is typically applied as a solder paste, which is a mixture of powdered solder metal alloy suspended or dispersed in a liquid vehicle.
  • solder paste is compliant enough so that it can be made to conform to virtually any shape. At the same time, it is tacky enough that it tends to adhere to any surface it is placed into contact with.
  • solder paste is deposited by stenciling or screen printing. In one embodiment the solder paste is deposited onto the die pads of the integrated circuit device. Alternatively, in another embodiment the solder paste is deposited onto the substrate pads of the package substrate. In yet another embodiment solder paste is deposited on both the die pads of the integrated circuit device and the substrate pads of the package substrate. The solder can also be applied to the area array device in the shape of preformed solder spheres.
  • the invention is applicable to any electronic device substrate in which integrated circuit devices (i.e., individual die or wafer level packages) are packaged.
  • the electronic device substrates include package substrates and support structures such as a ceramic chip carrier package or a leadframe as are known in the art.
  • the package substrate may be any of those conventionally known, such as organic laminate or ceramic based interposers, flip chip in package, or BGA on board.
  • Applicable substrates are available from Ibiden Circuits of America (Elgin, IL) and Shenko.
  • the substrate is a material selected from the group consisting of ceramic, semiconductor, organic material, polymeric material, and glass.
  • Preferred ceramic substrates are selected from the group consisting of LTCC, A12O3, High CTE Ceramic, and glass ceramic blends.
  • Preferred semiconductor materials are selected from the group consisting of silicon, gallium arsenide, and silicon carbide.
  • Preferred organic or polymer substrate materials are selected from the group consisting of epoxy / BT / glass laminate, polyimide flex, epoxy / glass laminate, liquid crystal polymer, and Teflon.
  • Preferred glass substrates are selected from the group consisting of soda lime glass, borosilicate glass, and fritted glass.
  • the bonding surface of the substrate has a coating selected from among protective, stress relief, dielectric, and mask coatings typically found in microelectronic devices.
  • a coating selected from among protective, stress relief, dielectric, and mask coatings typically found in microelectronic devices.
  • one or both of the bondin surfaces may have a polyimide, BCB, or silicon nitride passivation, or solder mask coating.
  • a carrier boat is used to hold the electronic device substrates and the integrated circuit devices during the flip chip assembly process.
  • the boat serves several purposes including confining the substrate, acting as a shuttle from one operation to the next, and inventory control.
  • the carrier boat is equipped with a clamp which presses two workpieces together.
  • the clamp is a spring-loaded clip positioned adjacent to each pocket. The clamp contacts a surface of the integrated circuit device to hold the device in place during reflow and apply pressure to the device to enhance electrical connection between a solder bump on a pad on the active surface of the device and a substrate pad on the surface of the package substrate. The clamp also enhances collapse of the solder bump onto the pad on the package substrate during reflow.
  • FIGS. 1 and 2 a carrier boat 1 is shown from top down view (FIG. 1) and from cross-section view (FIG. 2).
  • the carrier boat 1 comprises typically between about two and about twelve pockets 3, more typically ten to twelve pockets which may be arranged in a single line or as an array, for example two lines of five or six pockets.
  • Each pocket 3 is equipped with a spring-loaded clip 5.
  • FIGS. 1 and 2 show only two clips 5 on the boat 1 for clarity. It should be understood that all pockets may be equipped with a spring-loaded clip. For illustration purposes only the respective pockets are shown in various states of assembly. In Fig. 1, the top five pockets and bottom left pocket are empty, the second-from-left bottom pocket has its accompanying clamp, the third-from-left bottom pocket is carrying an electronic device substrate, the next pocket has an IC device resting on the substrate, and the next pocket, as shown at 13, is fully assembled with all these aspects. '
  • electronic device substrate 9 is placed in a pocket 3.
  • the IC device 1 1 is placed active side down on the surface of the package substrate 9.
  • the spring-loaded clip 5 is then inserted over the IC device 1 1 in a closed position 13 such that the spring-loaded clip 5 is in contact with and applies pressure to the IC device 1 1.
  • the spring-loaded clip 5 may comprise a central protrusion 7, which contacts the center of the inactive surface of the IC device 1 1 , rather than the entire surface.
  • FIGs. 3A and 3B are photographs of boats for use in the method of the present invention.
  • the boat or tray is comprised of a metal base with pockets to receive the substrate.
  • the spring is attached to the top of the tray over the assembly area after die placement.
  • the clip then applies pressure to the top of the die during reflow.
  • FIG. 3A depicts an embodiment that employs bridge clamps to hold the IC die or wafer in place.
  • FIG. 3B depicts an Auer Boat with ceramic interposers.
  • FIGS. 4 through 1 1 schematically depict various alternative embodiments of the mechanical pressure device of the invention.
  • the substrate may be a substrate for a flip chip device, such as a semiconductor package substrate, or a PCB substrate.
  • Figure 4 depicts a leaf spring 28 and clamp 30 configuration for applying pressure to the top of the IC device.
  • Figure 5 schematically depicts a cantilever spring 32 and clamp configuration for applying pressure to the top of the IC device.
  • Figure 6 shows a coil spring 34 and clamp configuration.
  • Figure 7 shows a compressible polymer or foam 36 which performs a spring function.
  • Figure 8 shows a volute spring 38 and clamp configuration.
  • the spring is a configuration such as a leaf spring, cantilever spring, coil spring, or volute spring, it is preferably constructed of polymer, metal, fiberglass, carbon-fiber composite, glass-fiber composite, or polymer coated metal. The selected material is capable of withstanding repeated reflow cycles between 200 and 350 C, such as between 220 and 265 C.
  • Figure 9 depicts an alternative clamp configuration 40, in combination with a leaf spring.
  • the mechanical pressure device is a weight 46
  • Fig. 1 1 depicts an optional protective pad 50 between a weight and IC device.
  • the material of the weight is capable of withstanding repeated reflow cycles between 200 and 350 C, such as between 220 and 265 C, for example a non-flowable metal, ceramic, stone, glass, filled polymer, or combinations thereof.
  • the weight may be coated with a polymer coating, or a protective polymer sheet of foam as in Fig. 1 1 is used between the weight and the device.
  • an underfill composition is dispensed on the substrate pads on the surface of the electronic device substrate 9.
  • the no-flow underfill may be pre-applied to a chip and/or substrate (e.g., for up to several months, such as at least six months) prior to the solder reflow operation without any decrease in the flow, adhesion, and/or reworkability.
  • the thermoplastic fluxing underfill may be used with lead- containing and lead-free solders.
  • the underfill composition may be one known in the art.
  • the underfill composition comprises an epoxy component and a fluxing curative, as disclosed in U.S. Pub.
  • the no-flow underfill is a conventional no-flow underfill.
  • the no flow underfill is a material that can be solidified or contains the ability to change to a solid state after dispense, printing, or after die placement.
  • the semiconductor integrated circuit device is placed on the surface of the electronic device substrate. If necessary, the material (substrate) or the dies can be heated to melt the solidified no flow underfill so that interconnects can penetrate into the no flow underfill material.
  • the IC device die pad having a solder bump thereon is aligned with the electronic device substrate pad.
  • the no-flow underfill is solidified, holding the die in place.
  • Pressure can then be applied to the device. Pressure can be applied as described herein, e.g., in the form of a weight, clamp, spring, or clamp/spring combination.
  • the clamp e.g., a spring-loaded clip located adjacent to a pocket in the carrier boat
  • contacts the inactive surface of the IC device to hold the IC device in place over the electronic device substrate.
  • a partial polymerization, solidification, or drying can be achieved by any of several different technologies including partial polymerization through heating, B-stage solvent evolution, dual cure, or UV/thermal cure system.
  • conversion of the no flow underfill to solid state prior to application of pressure can be achieved by solvent evaporation, cooling, heating, UV exposure, electron beam exposure, microwave energy, etc. according to known polymerization and solidification technologies.
  • the material and conditions are selected to balance interconnectability with the competing aspects of strength and stability. That is, conditions must be selected so as not to inhibit interconnect formation during subsequent reflow, while providing sufficient strength and dimensional stability to prevent die movement when pressure is applied.
  • the carrier boat holding the electronic device substrate and semiconductor integrated circuit device are then shuttled into a reflow oven. Heat is applied to reflow the solder bump and form an electrical interconnection between the substrate pad of the electronic device substrate and the active surface of the semiconductor integrated circuit device.
  • the temperature of reflow is based primarily on the type of solder used, as is known in the art.
  • the flip chip assembly can be subjected to a conventional post cure (if needed) of the underfill composition, with or without pressure.
  • f [0063]
  • the nature of the no flow underfill itself is not narrowly critical to the operation of the invention. It is a polymer-based no flow underfill having an organic component and a fluxing component. It also optionally has a curing agent, a filler, and other additives as are conventional in the field. In one embodiment, it is a reworkable underfill.
  • the organic component can be a thermoset or thermoplastic resin comprising a monomer, polymer or prepolymer or blends thereof.
  • the fluxing component be comprised of organic acids including, mono-, di-, and multifunctional organic carboxylic acids, organic acid complexes (salts), phenols, anhydrides, mineral acids, fluorinated organic, and sulphonic acids.
  • the fluxing component in the no flow formulation can react with the base polymers via the acid or other functional group within the fluxing component.
  • the curing agent can be comprised of latent amines, anhydrides, phenols, acid-imidazole complexes, imidazoles, free radical initiators, and amines.
  • the filler can be comprised of silica, alumina, aluminum nitride, boron nitride, silica coated aluminum nitride, and ceria, and in one preferred embodiment has a particle size ranging from 5nm - lOOum.
  • candidate additives are catalysts, accelerators, adhesion promoters, wetting or flow aids, rheology modifiers, or and toughening agents.
  • a compression stop is incorporated into the underfill as stated above.
  • the compression stop is solid at the reflow temperature and inhibits collapse of the interconnection.
  • the compression stop functions as a spacer between the device and substrate, and in certain preferred embodiments can be comprised of solid glass spheres, hollow glass spheres, polymer spacer particles, or ceramic spacer particles.
  • the spacer may be non-reflowable polymer particles or insulating dielectric particles such as glass or ceramic.
  • the compression stop in this context preferably comprises a plurality of compression stop units in the underfill, such as particles distribute throughout the underfill.
  • compression stop units are spherical; but other shapes may be suitable.
  • the "compression stop" comprises spheres having a diameter between about 20 urn and about 150 um.

Abstract

A method for forming an electrical interconnection between an active surface of a semiconductor integrated circuit device and a surface of an electronic device substrate involving applying mechanical pressure between the device and the substrate during heating to enhance collapse of the reflowed solder. A reflow carrier having a mechanical pressure device for applying mechanical pressure between an electronic device and an electronic device substrate. A polymer-based no flow underfill comprising an organic component, a fluxing component, and a compression stop.

Description

NO FLOW UNDERFILL PROCESS, COMPOSITION, AND REFLOW CARRIER
FIELD OF THE INVENTION
[ 0001 ] The present invention generally relates to the packaging of semiconductor integrated circuit devices, and more specifically to a no-flow underfill process and apparatus for preparing packaged area array and flip chip assemblies.
BACKGROUND OF THE INVENTION
[0002] Several techniques are known in the art for mounting a semiconductor integrated circuit device (i.e., a microchip, silicon chip, or simply chip) in the die pad or die cavity of a package substrate or support structure. The package is then mounted onto a printed circuit board (PCB) in a manner which achieves electrical interconnection between the integrated circuit device and the PCB. The original configuration comprised an IC die in a package substrate with the active side facing away from the substrate. Wires were then bonded to pads on the IC die to make the first level connection to the package substrate. This technology is generally referred to as "wire bonded interconnect." The die is typically encapsulated with mold compound, typically a plastic, ceramic, or epoxy. Wire bonded interconnect can also be utilized for second level interconnect connecting the package to the PCB.
[0003] In the 1970s, IBM developed flip chip assembly. In this method, solder is reflowed on an integrated circuit device pad forming a solder bump. The package substrate has a matching pad corresponding to the bump on the die. The die is placed with the active side facing toward the package substrate, the bump and pad are aligned, and the assembly is reflowed again so that the solder-pad interconnect is formed on the package substrate side. This technology is generally referred to as "flip chip" because the active side faces the substrate. During device assembly, the solder bump self-aligns with the pad or substrate metallization and during liquidus, and gravity assists in the "collapse" of the solder bump to form the interconnect.
[0004] Several levels of interconnect exist. Interconnection from the integrated circuit device to the package substrate is the first level interconnect, typically flip chip or WLCSP. Second level interconnect describes interconnection from the package substrate to a board. The standoff height and pitch in second level interconnect is generally larger allowing solder balls to be used. Devices that are grouped into this category include BGA and CSP packages. [0005] The process for attaching area array devices may vary depending on configuration and reliability requirements. A conventional flip chip assembly process employing capillary underfill may have the following steps:
[0006] Apply solder to a die pad on a wafer
[ 0007 ] Heat to reflow solder and form a solder bump on the die pad on the wafer
[0008] Singulate the wafer into individual dice
[0009] Apply solder paste or flux to package substrate, which has a substrate pad thereon
[0010] Place a die having the solder bump on the die pad onto the package substrate
[0011] Align die pad, solder bump, and substrate pad
[0012 ] Heat assembly to reflow solder, collapsing the solder bump and forming an electrical interconnection between the die pad and the substrate pad
[0013] Deflux (optional)
[0014 ] Dessicate assembly
[0015] Dispense underfill composition, typically by capillary action
[0016] Cure underfill.
[ 0017 ] Throughout the assembly process, the substrate passes from one operation to the next in a carrier or "boat." The boat serves several purposes including confining the substrate, acting as a shuttle from one operation to the next, and inventory control.
[0018] Underfill of area array devices is required to enable sufficient reliability performance of the chip package. Ideally, no underfill would be needed to meet reliability targets, which is the case for some BGA devices. However, the smaller pitch, smaller gap height, and large CTE mismatch between the device and the package substrate in flip chip assemblies necessitate use of an underfill. Additionally, underfill of area array devices is utilized to ensure assemblies meet the reliability requirements of hand held electronics, primarily drop-shock, even for BGA packages. However, the capillary underfill operation adds significant time to the area array assembly process.
[0019] No-flow underfill is an attractive alternative to conventional capillary underfill in that it enables a significant reduction in assembly steps and enables stress reduction after assembly. No- flow underfill combines the functions of the flux and the underfill into one system. A typical no-flow underfill area assembly process may have the following steps:
[0020] Apply solder to a die pad on a wafer
[0021] Heat to reflow solder and form a solder bump on the die pad on the wafer
[0022] Singulate wafer into individual dice [0023] Dispense no-flow underfill onto package substrate, which has a substrate pad thereon
[0024] Place die having the solder bump on the die pad onto the package substrate
[0025] Align die pad, solder bump, and substrate pad
[0026] Heat assembly to reflow solder (solder bumps collapse forming electrical interconnection between the die pad and the substrate pad) and cure underfill
[0027 ] Post-cure underfill (if needed).
[0028] To improve the reliability performance of area array devices, inorganic filler is often utilized in underfill formulations to modify the thermomechanical properties, for example, the coefficient of thermal expansion and modulus. Due to the viscosity impact of the filler in the formulation, the yield (or interconnect ability) of high I/O is typically low utilizing standard reflow operations in which solder bumps collapse due to gravity. Incorporation of filler increases the buoyancy of the IC die and reduces flow of the no- flow underfill, preventing complete collapse or wetting of the solder to the pads. A method known in the art which overcomes the bouyancy effect of filler in a no-flow operation is thermocompression bonding (TCB). In TCB, a heated head applies pressure and heat to the die, sometimes with heat from the bottom of the package substrate on the side opposite the IC die to reflow the solder and to provide enough pressure to overcome the buoyancy effect of the no-flow underfill. Several process variations exist for TCB. In one version, the die can be placed and heated to interconnect at time of placement. A second version involves placing the die in one operation then shuttling to a bonding station where heat is employed to interconnect. The disadvantage of thermocompression bonding is primarily due to the complexity of the alignment and bonding operations resulting in yield loss. Yield loss can be attributed to misalignment, incomplete wetting of the solder, or material entrapment at either the placement or the bonding step. In addition, capital equipment is required that is not typically found on conventional area array assembly lines. Due to the complexity of the equipment, it is highly engineered and therefore rather expensive. Manufacturers of TCB equipment include Toray, Panasonic, and Grohmann Engineering. The complexity and cost of the TCB equipment is high, especially in the context of high volume manufacturing (HVM). Accordingly, a need exists for an alternative method to apply pressure during the reflow process.
SUMMARY OF THE INVENTION
[0029] Briefly, the invention is directed to a method for forming an electrical interconnection between an active surface of a semiconductor integrated circuit device and a surface of an electronic device substrate, the method comprising applying pressure between the device and the substrate during reflow to enhance collapse of the reflowed solder bump and form an electrical interconnection between the active surface of the electronic device substrate and the active surface of the semiconductor integrated circuit device.
[0030] In another aspect the invention is directed to a reflow carrier apparatus for carrying an electronic device substrate and an electronic device in a reflow oven during attachment of the device to the substrate, the carrier comprising a carrier surface and a mechanical pressure device for applying pressure between the electronic device and the electronic device substrate.
[0031] Other objects and features will be in part apparent and in part pointed out hereinafter.
BRIEF DESCRIPTION OF THE FIGURES
[0032] FIG. 1 is a top down view of a carrier boat equipped with a clip according to the present invention.
[0033] FIG. 2 is a cross-sectional view of a carrier boat equipped with a clip according to the present invention.
[0034 ] FIG. 3A and 3B are photographs of boats applicable to the process of the present invention.
[0035] FIGS. 4 through 1 1 are cross-sectional schematic representations of various alternative embodiments of the mechanical pressure device of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0036] The present invention is directed to the packaging of a semiconductor integrated circuit device, i.e., a singulated die or a wafer as in wafer level packaging. For example, the present invention is directed to a method of packaging a semiconductor integrated circuit device inside a package substrate or support structure, (e.g., a ceramic chip carrier package or a leadframe) which is then electrically interconnected with a board in second level interconnect. The present invention is particularly suitable for manufacturing flip chip assemblies.
[0037 ] According to one embodiment of the packaging method of the present invention, a pressure mechanism is applied to an inactive surface of a semiconductor integrated circuit die after it has been placed in the package substrate or support structure and prior to solder reflow. The pressure mechanism holds the IC die having a solder bump on a die pad on its active side in place in the package; applies pressure to the inactive side of the 1C die to enhance interconnection between the die pad, solder bump, and a substrate pad on the surface of the package substrate; maintains alignment between the solder bumps or copper posts and the pads on the substrate; and enhances collapse of the solder bump during reflow thus forming an electrical interconnection between the die pad and the substrate pad.
[0038] According to another embodiment directed to wafer level packaging, a pressure mechanism is applied to an inactive surface of a semiconductor integrated circuit wafer after it has been placed in the package substrate or support structure and prior to solder reflow. The pressure mechanism holds the wafer having a solder bump on a die pad on its active side in place in the package, applies pressure to the inactive side of the wafer to enhance interconnection between the die pad, solder bump, and a substrate pad on the surface of the package substrate; to maintain alignment; and to enhance collapse of the solder bump during reflow thus forming an electrical interconnection between the die pad and the substrate pad.
[0039] The pressure applied by the pressure mechanism in accordance with this invention is typically on the order of between about 0.2 and about 20 psi.
[0040] As detailed in the background, during assembly, a package substrate or support structure may be loaded into a pocket in a carrier boat, which shuttles the substrate from one operation to the next. The boat may comprise from two to twelve pockets, more typically from ten to twelve pockets. The pockets may be arranged in a single row or in two or more rows, for example, two rows of five or six pockets.
[0041] The packaging process of the present invention provides a simple, cheap, efficient solution to the problem of ensuring adequate electrical interconnection between the at least one solder bump on the active side of the semiconductor integrated circuit device and the substrate pad of the package substrate. For example, in one embodiment, the pressure mechanism is a spring-loaded clip on the boat positioned adjacent to a pocket which holds a package substrate. After the semiconductor integrated circuit device is positioned on a surface of a package substrate, the spring-loaded clip is inserted on a surface of the semiconductor integrated circuit device to hold the semiconductor integrated circuit device in place on the package substrate. In a preferred embodiment, the assembly is a flip chip assembly in which the active surface faces toward the package substrate, and the clip is inserted over the inactive surface of the semiconductor integrated circuit device. The clip may be equipped with a central protrusion which contacts the center of the inactive side of the semiconductor integrated circuit device. In this embodiment, the clip applies adequate pressure to hold the semiconductor integrated circuit device and package substrate together while only minimally contacting the surface of the semiconductor integrated circuit device. During reflow, the spring-loaded clip applies pressure which enhances collapse of the solder bump onto the substrate pad of the package substrate.
[0042] The method is suited for packaging integrated circuit devices, which are microelectronic devices manufactured in the surface of a thin substrate of semiconductor material, most often silicon. Although germanium and gallium-arsenide devices are applicable, these are less common than devices manufactured in silicon. The integrated circuit device may be a wafer (as in wafer-level packaging, WLP) prior to singulation or a die which has been singulated from a semiconductor wafer. Integrated circuit devices comprise semiconductor devices (diodes and transistors) and passive components (resistors, capacitors, and inductors). Preparation of a wafer or die for inserting into a package, such as a flip chip assembly, is known in the art. The preparation of an integrated circuit die for packaging includes the following steps:
[0043] applying solder to a die pad on the active surface of a semiconductor integrated circuit wafer;
[0044] heating the semiconductor integrated circuit wafer to reflow the solder to form a solder bump on the die pad on the active surface of the semiconductor integrated circuit wafer; and
[0045] singulating the semiconductor integrated circuit wafer having a solder bump on a die pad into a semiconductor integrated circuit die, wherein the semiconductor integrated circuit die has a die pad on its active side having at least one solder bump thereon and an inactive side.
[0046] The selection of the solder for joining the integrated circuit device, i.e., wafer or singulated die, and an electronic device substrate such as a package substrate or support structure depends upon several factors. For example, the solder should be compatible with the metal or metals used to form the die pads of the integrated circuit device and the substrate pads of the package substrate (i.e., upon removal of oxides from said metals by the fluxing agent, the solder wets the pads during reflow to form an electrically conductive bond). Additionally, the selection of the solder may depend upon environmental and/or worker safety concerns. For example, there is an ever increasing demand for lead-free solders. Still further, the solder alloy preferably melts at a sufficiently low temperature so that there is no degradation of the integrated circuit device or the package substrate during reflow. Also, the solder preferably melts at a temperature at which the underfill does not degrade. For example, it is typically desirable for a solder to melt at a temperature that is less than about 3000C. Preferably, the solder melts at a temperature between about 1800C and about 260°C. More preferably, the solder melts at a temperature between about 22O0C and about 2600C. Additionally, the solder alloy is preferably stable (i.e., it does not evaporate) at a temperature that is between about 1O0C and about 400C above the melt temperature because typical reflow operations result in the solder alloy attaining such temperatures. For example, when reflowing a solder alloy having a relatively high melting temperature such as between about 21O0C and about 24O0C, the reflow temperature is typically between about 2200C and about 28O0C. Similarly, when reflowing a solder alloy having a relatively low melting temperature such as between about 1600C and about 1900C, a relatively low reflow temperature that is between about 17O0C and about 23O0C is typical.
[0047] In view of the foregoing, any conventional leaded solders (e.g., Sn63Pb37 and Sn62Pb36Ag2) are applicable. Particularly useful solder alloys are substantially free of lead, which are commonly referred to as Pb-free solder alloys and typically contain less than about 0.3 wt% of lead. Pb-free solder alloys tend to have higher liquidus temperatures and/or require longer reflow durations than lead-containing solder alloys. Exemplary Pb-free solder alloys include: Au80Sn2O, Sn962Ag25Cu08Sb05, Sn6SAg25SbI0, Sn965Ag35, Sn95 5Ag3 sCuo 7, Sn965Ag3Cu05, Sn955Ag4Cu05, Sn93 6Ag4 7Cui 7, Sn42Bi58, Sn90Bi9 5Cιio 5, Sn993Cu07, Sn99CUi, Sn^Cu3, Sn87 ilnio 5Ag2Sb04, Sn77 2In20Ag2 8, Sn63 6Ins 8Zn276, Sn97Sb3 and Sn95Sb5.
[0048] Additionally, in the process of the present invention, the interconnect structure is equipped with a compression stop, which is a spacer-type structure to prevent the die from being pressed completely against the package substrate during solder liquidus. A copper pillar or a post on the die in combination with solder on pad may be utilized to maintain standoff height between the die and the substrate. In another embodiment, a standoff is maintained by including a compression stop in the form of spacer beads or spacer technology into the no- flow underfill formulation.
[0049] The solder alloy is typically applied as a solder paste, which is a mixture of powdered solder metal alloy suspended or dispersed in a liquid vehicle. In general, at room temperature the solder paste is compliant enough so that it can be made to conform to virtually any shape. At the same time, it is tacky enough that it tends to adhere to any surface it is placed into contact with. These qualities make solder paste useful for forming solder bumps on electronic components or electronic device substrates. Typically, the solder paste is deposited by stenciling or screen printing. In one embodiment the solder paste is deposited onto the die pads of the integrated circuit device. Alternatively, in another embodiment the solder paste is deposited onto the substrate pads of the package substrate. In yet another embodiment solder paste is deposited on both the die pads of the integrated circuit device and the substrate pads of the package substrate. The solder can also be applied to the area array device in the shape of preformed solder spheres.
[0050] The invention is applicable to any electronic device substrate in which integrated circuit devices (i.e., individual die or wafer level packages) are packaged. The electronic device substrates include package substrates and support structures such as a ceramic chip carrier package or a leadframe as are known in the art. For example, the package substrate may be any of those conventionally known, such as organic laminate or ceramic based interposers, flip chip in package, or BGA on board. Applicable substrates are available from Ibiden Circuits of America (Elgin, IL) and Shenko. As a general proposition, the substrate is a material selected from the group consisting of ceramic, semiconductor, organic material, polymeric material, and glass. Preferred ceramic substrates are selected from the group consisting of LTCC, A12O3, High CTE Ceramic, and glass ceramic blends. Preferred semiconductor materials are selected from the group consisting of silicon, gallium arsenide, and silicon carbide. Preferred organic or polymer substrate materials are selected from the group consisting of epoxy / BT / glass laminate, polyimide flex, epoxy / glass laminate, liquid crystal polymer, and Teflon. Preferred glass substrates are selected from the group consisting of soda lime glass, borosilicate glass, and fritted glass.
[0051] With further regard to the substrate, it is within the scope of this invention that the bonding surface of the substrate, as well as the bonding surface of the electronic device being attached, has a coating selected from among protective, stress relief, dielectric, and mask coatings typically found in microelectronic devices. For example, one or both of the bondin surfaces may have a polyimide, BCB, or silicon nitride passivation, or solder mask coating.
[0052 ] A carrier boat is used to hold the electronic device substrates and the integrated circuit devices during the flip chip assembly process. The boat serves several purposes including confining the substrate, acting as a shuttle from one operation to the next, and inventory control.
[0053] In the process of the present invention, the carrier boat is equipped with a clamp which presses two workpieces together. In one embodiment, the clamp is a spring-loaded clip positioned adjacent to each pocket. The clamp contacts a surface of the integrated circuit device to hold the device in place during reflow and apply pressure to the device to enhance electrical connection between a solder bump on a pad on the active surface of the device and a substrate pad on the surface of the package substrate. The clamp also enhances collapse of the solder bump onto the pad on the package substrate during reflow. [0054] Referring now to FIGS. 1 and 2, a carrier boat 1 is shown from top down view (FIG. 1) and from cross-section view (FIG. 2). The carrier boat 1 comprises typically between about two and about twelve pockets 3, more typically ten to twelve pockets which may be arranged in a single line or as an array, for example two lines of five or six pockets. Each pocket 3 is equipped with a spring-loaded clip 5. FIGS. 1 and 2 show only two clips 5 on the boat 1 for clarity. It should be understood that all pockets may be equipped with a spring-loaded clip. For illustration purposes only the respective pockets are shown in various states of assembly. In Fig. 1, the top five pockets and bottom left pocket are empty, the second-from-left bottom pocket has its accompanying clamp, the third-from-left bottom pocket is carrying an electronic device substrate, the next pocket has an IC device resting on the substrate, and the next pocket, as shown at 13, is fully assembled with all these aspects. '
[0055] According to the process of the invention, electronic device substrate 9 is placed in a pocket 3. To achieve electrical interconnection between a substrate pad of the electronic device substrate 9 and a die pad on the active side of the IC device 1 1, the IC device 1 1 is placed active side down on the surface of the package substrate 9. The spring-loaded clip 5 is then inserted over the IC device 1 1 in a closed position 13 such that the spring-loaded clip 5 is in contact with and applies pressure to the IC device 1 1. The spring-loaded clip 5 may comprise a central protrusion 7, which contacts the center of the inactive surface of the IC device 1 1 , rather than the entire surface.
[0056] FIGs. 3A and 3B are photographs of boats for use in the method of the present invention. The boat or tray is comprised of a metal base with pockets to receive the substrate. The spring is attached to the top of the tray over the assembly area after die placement. The clip then applies pressure to the top of the die during reflow. FIG. 3A depicts an embodiment that employs bridge clamps to hold the IC die or wafer in place. FIG. 3B depicts an Auer Boat with ceramic interposers.
[0057 ] Figures 4 through 1 1 schematically depict various alternative embodiments of the mechanical pressure device of the invention. Each of Figs. 4 through 1 1 shows a substrate 20 sitting on a boat 22. The substrate may be a substrate for a flip chip device, such as a semiconductor package substrate, or a PCB substrate. There are solder beads 24 on top of the, e.g., package substrate, and an IC device 26 on top of the solder. Figure 4 depicts a leaf spring 28 and clamp 30 configuration for applying pressure to the top of the IC device. Figure 5 schematically depicts a cantilever spring 32 and clamp configuration for applying pressure to the top of the IC device. Figure 6 shows a coil spring 34 and clamp configuration. Figure 7 shows a compressible polymer or foam 36 which performs a spring function. Figure 8 shows a volute spring 38 and clamp configuration. Where the spring is a configuration such as a leaf spring, cantilever spring, coil spring, or volute spring, it is preferably constructed of polymer, metal, fiberglass, carbon-fiber composite, glass-fiber composite, or polymer coated metal. The selected material is capable of withstanding repeated reflow cycles between 200 and 350 C, such as between 220 and 265 C. Figure 9 depicts an alternative clamp configuration 40, in combination with a leaf spring. In Fig. 10 the mechanical pressure device is a weight 46, and Fig. 1 1 depicts an optional protective pad 50 between a weight and IC device. The material of the weight is capable of withstanding repeated reflow cycles between 200 and 350 C, such as between 220 and 265 C, for example a non-flowable metal, ceramic, stone, glass, filled polymer, or combinations thereof. To protect the IC device, the weight may be coated with a polymer coating, or a protective polymer sheet of foam as in Fig. 1 1 is used between the weight and the device.
[0058] In one embodiment, after placing the electronic device substrate 9 into a pocket 3 or slot in a carrier boat 1, an underfill composition is dispensed on the substrate pads on the surface of the electronic device substrate 9. In this embodiment, the no-flow underfill may be pre-applied to a chip and/or substrate (e.g., for up to several months, such as at least six months) prior to the solder reflow operation without any decrease in the flow, adhesion, and/or reworkability. Additionally, the thermoplastic fluxing underfill may be used with lead- containing and lead-free solders. The underfill composition may be one known in the art. Preferably, the underfill composition comprises an epoxy component and a fluxing curative, as disclosed in U.S. Pub. 2005/0218195, entitled Underfill Fluxing Curative and assigned to Fry's Metals, Inc. Another preferable composition is the low voiding no flow fluxing underfill disclosed in U.S. Pub. 2004/0251561 also assigned to Fry's Metals, Inc. For many embodiments of the invention, therefore, the no-flow underfill is a conventional no-flow underfill.
[0059] In an alternative embodiment, supplemental strength and stability are imparted to the assembly prior to application of the pressure mechanism. To accomplish this, the no flow underfill is a material that can be solidified or contains the ability to change to a solid state after dispense, printing, or after die placement. In this process, after applying the underfill composition to the surface of the electronic device substrate, the semiconductor integrated circuit device is placed on the surface of the electronic device substrate. If necessary, the material (substrate) or the dies can be heated to melt the solidified no flow underfill so that interconnects can penetrate into the no flow underfill material. The IC device die pad having a solder bump thereon is aligned with the electronic device substrate pad. After the die is aligned, the no-flow underfill is solidified, holding the die in place. Pressure can then be applied to the device. Pressure can be applied as described herein, e.g., in the form of a weight, clamp, spring, or clamp/spring combination. When a clamp is preferred, the clamp (e.g., a spring-loaded clip located adjacent to a pocket in the carrier boat) contacts the inactive surface of the IC device to hold the IC device in place over the electronic device substrate.
[0060] In imparting strength and stability via the underfill prior to application of the pressure mechanism, a partial polymerization, solidification, or drying can be achieved by any of several different technologies including partial polymerization through heating, B-stage solvent evolution, dual cure, or UV/thermal cure system. For example, conversion of the no flow underfill to solid state prior to application of pressure can be achieved by solvent evaporation, cooling, heating, UV exposure, electron beam exposure, microwave energy, etc. according to known polymerization and solidification technologies. The material and conditions are selected to balance interconnectability with the competing aspects of strength and stability. That is, conditions must be selected so as not to inhibit interconnect formation during subsequent reflow, while providing sufficient strength and dimensional stability to prevent die movement when pressure is applied.
[0061] The carrier boat holding the electronic device substrate and semiconductor integrated circuit device are then shuttled into a reflow oven. Heat is applied to reflow the solder bump and form an electrical interconnection between the substrate pad of the electronic device substrate and the active surface of the semiconductor integrated circuit device. The temperature of reflow is based primarily on the type of solder used, as is known in the art.
[0062] The flip chip assembly can be subjected to a conventional post cure (if needed) of the underfill composition, with or without pressure. f [0063] The nature of the no flow underfill itself is not narrowly critical to the operation of the invention. It is a polymer-based no flow underfill having an organic component and a fluxing component. It also optionally has a curing agent, a filler, and other additives as are conventional in the field. In one embodiment, it is a reworkable underfill. The organic component can be a thermoset or thermoplastic resin comprising a monomer, polymer or prepolymer or blends thereof. It is preferably from the resin classes epoxy, bismalimide, acrylate, cyanate ester, benzoxazine, polybenzoxazine, phenoxy, polyphenylsulphones, polyphenylenes, polyphenylsulfide, polyetheretherketone, polyimides, polyaryleneethers, urethane, and silicon. The fluxing component be comprised of organic acids including, mono-, di-, and multifunctional organic carboxylic acids, organic acid complexes (salts), phenols, anhydrides, mineral acids, fluorinated organic, and sulphonic acids. Optionally the fluxing component in the no flow formulation can react with the base polymers via the acid or other functional group within the fluxing component. The curing agent can be comprised of latent amines, anhydrides, phenols, acid-imidazole complexes, imidazoles, free radical initiators, and amines. The filler can be comprised of silica, alumina, aluminum nitride, boron nitride, silica coated aluminum nitride, and ceria, and in one preferred embodiment has a particle size ranging from 5nm - lOOum. Among candidate additives are catalysts, accelerators, adhesion promoters, wetting or flow aids, rheology modifiers, or and toughening agents.
[0064] In one embodiment, a compression stop is incorporated into the underfill as stated above. The compression stop is solid at the reflow temperature and inhibits collapse of the interconnection. The compression stop functions as a spacer between the device and substrate, and in certain preferred embodiments can be comprised of solid glass spheres, hollow glass spheres, polymer spacer particles, or ceramic spacer particles. For example, the spacer may be non-reflowable polymer particles or insulating dielectric particles such as glass or ceramic. The compression stop in this context preferably comprises a plurality of compression stop units in the underfill, such as particles distribute throughout the underfill. Preferably, compression stop units are spherical; but other shapes may be suitable. In one embodiment the "compression stop" comprises spheres having a diameter between about 20 urn and about 150 um.
[0065] In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results attained.
[0066] When introducing elements of the present invention or the preferred embodiment(s) thereof, the articles "a", "an", "the" and "said" are intended to mean that there are one or more of the elements. For example, that the foregoing description and following claims refer to "an" interconnect means that there are one or more such interconnects. The terms "comprising", "including" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.
[0067] As various changes could be made in the above without departing from the scope of the invention, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

Claims

WHAT IS CLAIMED IS:
1. A method for forming an electrical interconnection between an active surface of a semiconductor integrated circuit device and a surface of an electronic device substrate, the method comprising: heating the electronic device substrate and semiconductor integrated circuit device to a reflow temperature to reflow solder between the electronic device substrate and the semiconductor integrated circuit device; and applying mechanical pressure between the device and the substrate during said heating to enhance collapse of the reflowed solder and form an electrical interconnection between the active surface of the electronic device substrate and the active surface of the semiconductor integrated circuit device.
2. The method of claim 1 wherein said applying mechanical pressure is accomplished by use of a clamp.
3. The method of claim 2 wherein the clamp is a spring-loaded clip.
4. The method of claim 1 wherein said applying mechanical pressure is accomplished by use of a weight.
5. The method of claim 1 wherein said applying mechanical pressure is accomplished by use of a compressible polymer or foam.
6. The method of claim 1 wherein said applying mechanical pressure is accomplished by use of a spring.
7. The method of any one of claims 1 through 6 further comprising using a compression stop that is solid at the reflow temperature to halt collapse of the interconnection beyond a predetermined point.
8. The method of claim 7 wherein the compression stop is a copper post.
9. The method of any one of claims 1 through 8 wherein the substrate is a material selected from the group consisting of ceramic, semiconductor, organic material, polymeric material, and glass.
10. The method of claim 9 wherein the substrate is the ceramic and is selected from the group consisting of LTCC, AI2O3, High CTE ceramic, and glass ceramic blends.
1 1. The method of claim 9 wherein the substrate is the semiconductor and is selected from the group consisting of silicon, gallium arsenide, and silicon carbide.
12. The method of claim 9 wherein the substrate is the organic or polymer material and is selected from the group consisting of epoxy / BT / glass laminate, polyimide flex, epoxy / glass laminate, liquid crystal polymer, and Teflon.
13. The method of claim 9 wherein the substrate is the glass and is selected from the group consisting of soda lime glass, borosilicate glass, and fritted glass.
14. A method for forming an electrical interconnection between an active surface of a semiconductor integrated circuit device and a surface of an electronic device substrate, the method comprising: applying a no flow underfill between the integrated circuit device and electronic device substrate; converting the no flow underfill to a solid state; heating the electronic device substrate and semiconductor integrated circuit device to a reflow temperature to reflow solder between the electronic device substrate and the semiconductor integrated circuit device; and applying mechanical pressure between the device and the substrate after said converting the no flow underfill to the solid state and during said heating to enhance collapse of the reflowed solder and form an electrical interconnection between the active surface of the electronic device substrate and the active surface of the semiconductor integrated circuit device.
15. A reflow carrier for carrying an electronic device substrate and an electronic device in a reflow oven, the carrier comprising a carrier surface and a mechanical pressure device for applying mechanical pressure between the electronic device and the electronic device substrate.
16. The reflow carrier of claim 15 wherein the mechanical pressure device is a clamp.
17. The reflow carrier of claim 16 wherein the clamp is a spring-loaded clip.
18. The reflow carrier of claim 15 wherein the mechanical pressure device is a compressible polymer or foam.
19. The reflow carrier of claim 15 wherein the mechanical pressure device is a spring.
20. The reflow carrier of claim 15 wherein the mechanical pressure device is a weight.
21. A polymer-based no flow underfill comprising an organic component, a fluxing component, and a compression stop.
22. The polymer-based no flow underfill of claim 21 wherein the organic component is either a thermoset or thermoplastic resin comprising a monomer, polymer or prepolymer or blends of and from the resin classes: epoxy, bismalimide, acrylate, cyanate ester, benzoxazine, polybenzoxazine, phenoxy, polyphenylsulphones, polyphenylenes, polyphenylsulfide, polyetheretherketone, polyimides, polyaryleneethers, urethane, silicon.
23. The polymer-based no flow underfill of claim 21 or 22 wherein the fluxing component is selected from the group consisting of organic acids including, mono, di, multifunctional organic carboxylic acids, organic acid complexes (salts), phenols, anhydrides, mineral acids, fluorinated organic and sulphonic acids.
24. The polymer-based no flow underfill of claim 21, 22, or 23 wherein the fluxing component reacts with the base polymers via the acid or other functional group within the fluxing component.
25. The polymer-based no flow underfill of claim 21, 22, 23, or 24 wherein the compression stop is selected from the group consisting of solid glass spheres, hollow glass spheres, polymer spacer particles, and ceramic spacer particles.
PCT/US2007/025337 2006-12-11 2007-12-11 No flow underfill process, composition, and reflow carrier WO2008073432A2 (en)

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