JP5169171B2 - 電子部品の接合方法 - Google Patents
電子部品の接合方法 Download PDFInfo
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- JP5169171B2 JP5169171B2 JP2007304065A JP2007304065A JP5169171B2 JP 5169171 B2 JP5169171 B2 JP 5169171B2 JP 2007304065 A JP2007304065 A JP 2007304065A JP 2007304065 A JP2007304065 A JP 2007304065A JP 5169171 B2 JP5169171 B2 JP 5169171B2
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- JP
- Japan
- Prior art keywords
- bonding
- electronic component
- electrode
- resin
- electrodes
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/06102—Disposition the bonding areas being at different heights
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/8184—Sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
図1(a)と図1(b)を用いて本発明の第1実施形態にかかる接合構造体18の構成を説明する。図1(a)は、断面図を示し、図1(b)は、そのBB´面での断面図である。
次に、本発明の実施形態を適用した具体例について、LED素子の実装を一例に挙げて説明する。ここでは、図6(a)と図6(b)を参照しながら説明する。
2 電極
3 電子部品
4 電極
5 金属ナノペースト材料
6 金属ナノ粒子
7 分散剤
8 溶剤
9 接合材料積層体
10 ボイド(空隙)
11 樹脂
12 インクジェット装置
13 セラミック基板
14 電極
15 LED素子
16 P電極
17 N電極
18 接合構造体
Claims (3)
- 複数の電極を有する回路形成体と、
前記回路形成体の複数の電極に各々対向して配置された複数の電極を有する電子部品と、
前記回路形成体と前記電子部品とを接続する接合材料と、
を備えた電子部品の接合構造体の接合方法において、
複数の電極を有する前記回路形成体を準備し、
前記回路形成体の1つの電極上に、平均直径が100nm以下の金属からなる超微粒子を含有した金属ナノペースト材料を用いて接合材料部としての積層体をドットで複数形成し、
前記回路形成体の1つの電極に接続される、前記電子部品上の1つの電極に、接合補強用の樹脂を前記接合材料部の高さよりも低く形成し、前記積層体が流れ出ないように、前記回路形成体に前記電子部品を向かい合わせ、加熱、加圧或いはそれらの組み合わせにより前記積層体を硬化する際に、金属ナノペースト材料中に含まれる分散剤が揮発した際に発生する前記積層体の空隙部に、溶融された前記接合補強用樹脂を浸透させつつ硬化させて、電子部品の実装を一括して行うことを特徴とする接合構造体の接合方法。 - 複数の電極を有する回路形成体と、
前記回路形成体の複数の電極に各々対向して配置された複数の電極を有する電子部品と、前記回路形成体と前記電子部品とを接続する接合材料と、
を備えた電子部品の接合構造体の接合方法において、
複数の電極を有する前記回路形成体を準備し、
前記回路形成体の1つの電極上に、平均直径が100nm以下の金属からなる超微粒子を含有した金属ナノペースト材料を用いて接合材料部としての積層体をドット形状で複数形成し、
前記回路形成体の1つの電極に接続される、前記電子部品上の1つの電極に、接合補強用の樹脂を前記接合材料部の高さよりも低く形成し、前記積層体が流れ出ないように、前記回路形成体に前記電子部品を向かい合わせ、加熱、加圧或いはそれらの組み合わせにより前記積層体を硬化すると共に、溶融された前記接合補強用樹脂を、接合部の隙間部に浸透させつつ硬化させて電子部品の実装を一括して行うことを特徴とする接合構造体の接合方法。 - 前記回路形成体に前記電子部品を向かい合わせる時、前記積層体と前記接合補強用の樹脂とが干渉しないようにする請求項1または2記載の接合構造体の接合方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007304065A JP5169171B2 (ja) | 2007-11-26 | 2007-11-26 | 電子部品の接合方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007304065A JP5169171B2 (ja) | 2007-11-26 | 2007-11-26 | 電子部品の接合方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009130162A JP2009130162A (ja) | 2009-06-11 |
JP2009130162A5 JP2009130162A5 (ja) | 2010-09-16 |
JP5169171B2 true JP5169171B2 (ja) | 2013-03-27 |
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ID=40820777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007304065A Expired - Fee Related JP5169171B2 (ja) | 2007-11-26 | 2007-11-26 | 電子部品の接合方法 |
Country Status (1)
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JP (1) | JP5169171B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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EP4167274A4 (en) * | 2020-06-15 | 2024-01-03 | Sony Semiconductor Solutions Corporation | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1056041A (ja) * | 1996-06-04 | 1998-02-24 | Citizen Watch Co Ltd | 半導体装置の実装構造および実装方法 |
JP3998536B2 (ja) * | 2002-08-22 | 2007-10-31 | 松下電器産業株式会社 | 接合材料およびその製造方法、接合材料の供給方法ならびに電子回路基板 |
US6774497B1 (en) * | 2003-03-28 | 2004-08-10 | Freescale Semiconductor, Inc. | Flip-chip assembly with thin underfill and thick solder mask |
JP4238671B2 (ja) * | 2003-05-23 | 2009-03-18 | 株式会社デンソー | 電子部品の実装構造 |
JP4246134B2 (ja) * | 2003-10-07 | 2009-04-02 | パナソニック株式会社 | 半導体素子の実装方法、及び半導体素子実装基板 |
JP4510649B2 (ja) * | 2005-01-20 | 2010-07-28 | パナソニック株式会社 | 配線基板、多層基板および電子部品実装体の製造方法 |
EP2012352A4 (en) * | 2006-04-24 | 2012-07-25 | Murata Manufacturing Co | ELECTRONIC COMPONENT, ELECTRONIC COMPONENT DEVICE THEREFOR AND METHOD OF MANUFACTURING THEREOF |
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- 2007-11-26 JP JP2007304065A patent/JP5169171B2/ja not_active Expired - Fee Related
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