KR100846089B1 - 설계 블록들 사이에 다수의 글루 로직 엘리먼트들을 분배하는 방법 및 글루 로직 분배 효율을 증가시키는 방법 - Google Patents
설계 블록들 사이에 다수의 글루 로직 엘리먼트들을 분배하는 방법 및 글루 로직 분배 효율을 증가시키는 방법 Download PDFInfo
- Publication number
- KR100846089B1 KR100846089B1 KR1020017004099A KR20017004099A KR100846089B1 KR 100846089 B1 KR100846089 B1 KR 100846089B1 KR 1020017004099 A KR1020017004099 A KR 1020017004099A KR 20017004099 A KR20017004099 A KR 20017004099A KR 100846089 B1 KR100846089 B1 KR 100846089B1
- Authority
- KR
- South Korea
- Prior art keywords
- delete delete
- design
- test
- block
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10256698P | 1998-09-30 | 1998-09-30 | |
| US60/102,566 | 1998-09-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010085867A KR20010085867A (ko) | 2001-09-07 |
| KR100846089B1 true KR100846089B1 (ko) | 2008-07-14 |
Family
ID=22290503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020017004099A Expired - Fee Related KR100846089B1 (ko) | 1998-09-30 | 1999-09-30 | 설계 블록들 사이에 다수의 글루 로직 엘리먼트들을 분배하는 방법 및 글루 로직 분배 효율을 증가시키는 방법 |
Country Status (13)
| Country | Link |
|---|---|
| US (10) | US6269467B1 (enExample) |
| EP (1) | EP1145159A3 (enExample) |
| JP (1) | JP2002526908A (enExample) |
| KR (1) | KR100846089B1 (enExample) |
| CN (1) | CN1331079C (enExample) |
| AU (1) | AU1100500A (enExample) |
| BR (1) | BR9914200A (enExample) |
| CA (1) | CA2345648A1 (enExample) |
| EE (1) | EE200100189A (enExample) |
| HU (1) | HUP0301274A2 (enExample) |
| IL (1) | IL142279A0 (enExample) |
| PL (1) | PL350155A1 (enExample) |
| WO (1) | WO2000019343A2 (enExample) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9690896B2 (en) | 2015-04-09 | 2017-06-27 | Samsung Electronics Co., Ltd. | Method for manufacturing a semiconductor device and semiconductor device manufactured by the same |
| US9698056B2 (en) | 2015-04-09 | 2017-07-04 | Samsung Electronics., Ltd. | Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same |
| US9773772B2 (en) | 2015-04-09 | 2017-09-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US10204920B2 (en) | 2015-04-09 | 2019-02-12 | Samsung Electronics Co., Ltd. | Semiconductor device including polygon-shaped standard cell |
| US11043428B2 (en) | 2015-04-09 | 2021-06-22 | Samsung Electronics Co., Ltd. | Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same |
Families Citing this family (354)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6138266A (en) | 1997-06-16 | 2000-10-24 | Tharas Systems Inc. | Functional verification of integrated circuit designs |
| US6961690B1 (en) * | 1998-05-19 | 2005-11-01 | Altera Corporation | Behaviorial digital simulation using hybrid control and data flow representations |
| US6697773B1 (en) | 1998-05-19 | 2004-02-24 | Altera Corporation | Using assignment decision diagrams with control nodes for sequential review during behavioral simulation |
| US6862563B1 (en) * | 1998-10-14 | 2005-03-01 | Arc International | Method and apparatus for managing the configuration and functionality of a semiconductor design |
| US6519636B2 (en) * | 1998-10-28 | 2003-02-11 | International Business Machines Corporation | Efficient classification, manipulation, and control of network transmissions by associating network flows with rule based functions |
| US7076415B1 (en) * | 1998-12-17 | 2006-07-11 | Cadence Design Systems, Inc. | System for mixed signal synthesis |
| US6446243B1 (en) * | 1999-04-23 | 2002-09-03 | Novas Software, Inc. | Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores |
| US6560754B1 (en) * | 1999-05-13 | 2003-05-06 | Arc International Plc | Method and apparatus for jump control in a pipelined processor |
| US6519754B1 (en) * | 1999-05-17 | 2003-02-11 | Synplicity, Inc. | Methods and apparatuses for designing integrated circuits |
| US6446251B1 (en) * | 1999-06-14 | 2002-09-03 | David Neal Gardner | Method and apparatus for socket-based design with reusable-IP |
| US6634008B1 (en) * | 1999-06-20 | 2003-10-14 | Fujitsu Limited | Methodology server based integrated circuit design |
| US6507808B1 (en) * | 1999-06-23 | 2003-01-14 | International Business Machines Corporation | Hardware logic verification data transfer checking apparatus and method therefor |
| US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
| US6637018B1 (en) * | 1999-10-29 | 2003-10-21 | Cadence Design Systems, Inc. | Mixed signal synthesis behavioral models and use in circuit design optimization |
| US6704908B1 (en) * | 1999-11-17 | 2004-03-09 | Amadala Limited | Method and apparatus for automatically generating a phase lock loop (PLL) |
| US7031900B1 (en) * | 2000-01-07 | 2006-04-18 | Sun Microsystems, Inc. | Static scheduling of test cases |
| US6886121B2 (en) * | 2000-01-18 | 2005-04-26 | Cadence Design Systems, Inc. | Hierarchical test circuit structure for chips with multiple circuit blocks |
| US6631504B2 (en) * | 2000-01-18 | 2003-10-07 | Cadence Design Systems, Inc | Hierarchical test circuit structure for chips with multiple circuit blocks |
| US6901562B2 (en) * | 2000-01-18 | 2005-05-31 | Cadence Design Systems, Inc. | Adaptable circuit blocks for use in multi-block chip design |
| US7181705B2 (en) * | 2000-01-18 | 2007-02-20 | Cadence Design Systems, Inc. | Hierarchical test circuit structure for chips with multiple circuit blocks |
| US6427224B1 (en) * | 2000-01-31 | 2002-07-30 | International Business Machines Corporation | Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor |
| US6615167B1 (en) * | 2000-01-31 | 2003-09-02 | International Business Machines Corporation | Processor-independent system-on-chip verification for embedded processor systems |
| US6571373B1 (en) * | 2000-01-31 | 2003-05-27 | International Business Machines Corporation | Simulator-independent system-on-chip verification methodology |
| US6658508B1 (en) * | 2000-01-31 | 2003-12-02 | Koninklijke Philips Electronics N.V. | Expansion module with external bus for personal digital assistant and design method therefor |
| US6487699B1 (en) * | 2000-01-31 | 2002-11-26 | International Business Machines Corporation | Method of controlling external models in system-on-chip verification |
| US6904397B1 (en) * | 2000-02-22 | 2005-06-07 | Xilinx, Inc. | System and method for assisting in the development and integration of reusable circuit designs |
| US6851094B1 (en) * | 2000-02-28 | 2005-02-01 | Cadence Design Systems, Inc. | Automated method and system for selecting and procuring electronic components used in circuit and chip designs |
| US6594799B1 (en) | 2000-02-28 | 2003-07-15 | Cadence Design Systems, Inc. | Method and system for facilitating electronic circuit and chip design using remotely located resources |
| US6625780B1 (en) * | 2000-02-28 | 2003-09-23 | Cadence Design Systems, Inc. | Watermarking based protection of virtual component blocks |
| US6988154B2 (en) * | 2000-03-10 | 2006-01-17 | Arc International | Memory interface and method of interfacing between functional entities |
| US6970814B1 (en) * | 2000-03-30 | 2005-11-29 | International Business Machines Corporation | Remote IP simulation modeling |
| US6993740B1 (en) * | 2000-04-03 | 2006-01-31 | International Business Machines Corporation | Methods and arrangements for automatically interconnecting cores in systems-on-chip |
| JP3583054B2 (ja) * | 2000-04-19 | 2004-10-27 | Necインフロンティア株式会社 | ネットワークを用いた設計業務システム及び設計方法 |
| WO2001088766A2 (en) * | 2000-05-12 | 2001-11-22 | Simplex Solutions, Inc. | High accuracy timing model for integrated circuit verification |
| JP2001326151A (ja) * | 2000-05-16 | 2001-11-22 | Nec Corp | 半導体集積回路製作システム |
| JP2001338010A (ja) * | 2000-05-25 | 2001-12-07 | Matsushita Electric Ind Co Ltd | 集積回路の設計方法 |
| WO2001095161A2 (en) * | 2000-06-02 | 2001-12-13 | Virtio Corporation | Method and system for virtual prototyping |
| JP2001344287A (ja) * | 2000-06-02 | 2001-12-14 | Nec Microsystems Ltd | アルゴリズム記述におけるバスの性能評価方法 |
| JP3759860B2 (ja) * | 2000-06-08 | 2006-03-29 | シャープ株式会社 | 自己同期型のパイプライン制御を採用したデータ駆動型情報処理装置の設計方法 |
| US7100133B1 (en) * | 2000-06-23 | 2006-08-29 | Koninklijke Philips Electronics N.V | Computer system and method to dynamically generate system on a chip description files and verification information |
| EP1307835A2 (en) * | 2000-06-30 | 2003-05-07 | Infineon Technologies North America Corp. | Method for design and layout of integrated circuits |
| EP1299826A1 (en) * | 2000-07-03 | 2003-04-09 | Cadence Design Systems, Inc. | Circuit component interface |
| US6829731B1 (en) * | 2000-08-14 | 2004-12-07 | International Business Machines Corporation | Method and system for generating a design-specific test case from a generalized set of bus transactions |
| US7020589B1 (en) * | 2000-09-29 | 2006-03-28 | Lsi Logic Corporation | Method and apparatus for adaptive timing optimization of an integrated circuit design |
| JP3852741B2 (ja) * | 2000-10-31 | 2006-12-06 | シャープ株式会社 | 高位合成方法および高位合成装置 |
| GB2406416A (en) * | 2000-10-31 | 2005-03-30 | Advanced Risc Mach Ltd | Describing an integrated circuit configuration |
| US6671843B1 (en) * | 2000-11-13 | 2003-12-30 | Omar Kebichi | Method for providing user definable algorithms in memory BIST |
| JP4118501B2 (ja) * | 2000-11-15 | 2008-07-16 | 株式会社ルネサステクノロジ | システム検証装置 |
| US6704917B1 (en) * | 2000-11-21 | 2004-03-09 | Micro Industries Corporation | Table driven design system and method |
| JP2002184948A (ja) * | 2000-12-12 | 2002-06-28 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| US6691287B2 (en) | 2000-12-14 | 2004-02-10 | Tharas Systems Inc. | Functional verification system |
| US6625786B2 (en) * | 2000-12-14 | 2003-09-23 | Tharas Systems, Inc. | Run-time controller in a functional verification system |
| US6629297B2 (en) | 2000-12-14 | 2003-09-30 | Tharas Systems Inc. | Tracing the change of state of a signal in a functional verification system |
| US7165231B2 (en) * | 2000-12-18 | 2007-01-16 | Yardstick Research, Llc | Method and system for incremental behavioral validation of digital design expressed in hardware description language |
| US7430543B1 (en) * | 2001-02-09 | 2008-09-30 | Synopsys, Inc. | Method of enforcing a contract for a CAD tool |
| US6694494B2 (en) * | 2001-03-16 | 2004-02-17 | Daro Semiconductors Ltd. | Method of designing a multi-module single-chip circuit system |
| DE60204556D1 (de) * | 2001-03-20 | 2005-07-14 | Nptest Inc | Taktsignalgenerator mit niedrigem jitter für ein test-system |
| US6816997B2 (en) * | 2001-03-20 | 2004-11-09 | Cheehoe Teh | System and method for performing design rule check |
| JP2002288255A (ja) * | 2001-03-26 | 2002-10-04 | Toshiba Corp | ハードウェア記述言語で記述されたシステムlsiの回路部品、及びその検証方法、検証支援回路、システムlsiの製造方法 |
| JP4529063B2 (ja) * | 2001-03-30 | 2010-08-25 | ルネサスエレクトロニクス株式会社 | システムシミュレータ、シミュレーション方法及びシミュレーションプログラム |
| US6567959B2 (en) * | 2001-03-30 | 2003-05-20 | Intel Corporation | Method and device for verification of VLSI designs |
| US6957403B2 (en) | 2001-03-30 | 2005-10-18 | Syntest Technologies, Inc. | Computer-aided design system to automate scan synthesis at register-transfer level |
| DE10118470A1 (de) * | 2001-04-12 | 2002-10-24 | Siemens Ag | Objektbearbeitungssystem mit einem Objektmodell |
| US6453443B1 (en) * | 2001-04-16 | 2002-09-17 | Taiwan Semiconductor Manufacturing Company | Method for cell modeling and timing verification of chip designs with voltage drop |
| CN1293503C (zh) * | 2001-04-27 | 2007-01-03 | 株式会社鼎新 | 系统芯片的设计校验方法和装置 |
| US20030004699A1 (en) * | 2001-06-04 | 2003-01-02 | Choi Charles Y. | Method and apparatus for evaluating an integrated circuit model |
| US6578174B2 (en) | 2001-06-08 | 2003-06-10 | Cadence Design Systems, Inc. | Method and system for chip design using remotely located resources |
| US6985843B2 (en) * | 2001-06-11 | 2006-01-10 | Nec Electronics America, Inc. | Cell modeling in the design of an integrated circuit |
| US20030005396A1 (en) * | 2001-06-16 | 2003-01-02 | Chen Michael Y. | Phase and generator based SOC design and/or verification |
| US6757882B2 (en) * | 2001-06-16 | 2004-06-29 | Michael Y. Chen | Self-describing IP package for enhanced platform based SOC design |
| US20030009730A1 (en) * | 2001-06-16 | 2003-01-09 | Chen Michael Y. | Enhanced platform based SOC design including exended peripheral selection and automated IP customization facilitation |
| US6502232B1 (en) * | 2001-06-18 | 2002-12-31 | Verisity Design, Inc. | Electronic circuit design environmentally constrained test generation system |
| JP4035354B2 (ja) * | 2001-07-11 | 2008-01-23 | 富士通株式会社 | 電子回路設計方法及び装置、コンピュータプログラム及び記憶媒体 |
| US6480999B1 (en) * | 2001-07-26 | 2002-11-12 | Xilinx, Inc. | Signal routing in programmable logic devices |
| US20030050967A1 (en) * | 2001-09-11 | 2003-03-13 | Bentley William F. | Apparatus and method for optimal selection of IP modules for design integration |
| US20030061013A1 (en) * | 2001-09-11 | 2003-03-27 | Bentley William F. | Optimal selection of IP modules for design integration |
| US6764869B2 (en) * | 2001-09-12 | 2004-07-20 | Formfactor, Inc. | Method of assembling and testing an electronics module |
| JP3891813B2 (ja) * | 2001-10-09 | 2007-03-14 | 富士通株式会社 | 集積論理回路の階層設計方法 |
| CA2360291A1 (en) * | 2001-10-30 | 2003-04-30 | Benoit Nadeau-Dostie | Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby |
| US6654946B1 (en) * | 2001-10-30 | 2003-11-25 | Lsi Logic Corporation | Interscalable interconnect |
| US6999910B2 (en) * | 2001-11-20 | 2006-02-14 | Lsi Logic Corporation | Method and apparatus for implementing a metamethodology |
| US6775798B2 (en) * | 2001-11-28 | 2004-08-10 | Lsi Logic Corporation | Fast sampling test bench |
| US6543034B1 (en) | 2001-11-30 | 2003-04-01 | Koninklijke Philips Electronics N.V. | Multi-environment testing with a responder |
| US7493470B1 (en) | 2001-12-07 | 2009-02-17 | Arc International, Plc | Processor apparatus and methods optimized for control applications |
| US7103860B2 (en) * | 2002-01-25 | 2006-09-05 | Logicvision, Inc. | Verification of embedded test structures in circuit designs |
| US20030145290A1 (en) * | 2002-01-30 | 2003-07-31 | International Business Machines Corporation | System for controlling external models used for verification of system on a chip (SOC) interfaces |
| US7003743B2 (en) * | 2002-02-01 | 2006-02-21 | Freescale Semiconductor, Inc. | Method and system of data processor design by sensitizing logical difference |
| WO2003067478A1 (en) * | 2002-02-05 | 2003-08-14 | Logicvision, Inc. | Verification of embedded test structures in circuit designs |
| US6732338B2 (en) * | 2002-03-20 | 2004-05-04 | International Business Machines Corporation | Method for comprehensively verifying design rule checking runsets |
| US6735749B2 (en) | 2002-03-21 | 2004-05-11 | Sun Microsystems, Inc. | (Design rule check)/(electrical rule check) algorithms using a system resolution |
| US6760891B2 (en) * | 2002-04-01 | 2004-07-06 | Sun Microsystems, Inc. | Simulator of dynamic circuit for silicon critical path debug |
| US6934897B2 (en) * | 2002-04-05 | 2005-08-23 | Nilanjan Mukherjee | Scheduling the concurrent testing of multiple cores embedded in an integrated circuit |
| US6993733B2 (en) * | 2002-04-09 | 2006-01-31 | Atrenta, Inc. | Apparatus and method for handling of multi-level circuit design data |
| DE10392497T5 (de) * | 2002-04-11 | 2005-02-17 | Advantest Corp. | Herstellungsverfahren und Herstellungsvorrichtung zum Vermeiden eines Prototypen-Aufschubs bei der ASIC/SOC-Herstellung |
| KR100745959B1 (ko) | 2002-04-17 | 2007-08-02 | 후지쯔 가부시끼가이샤 | 집적 회로의 개발 방법 및 집적 회로의 개발 방법을 기록한 프로그램 기록 매체 |
| US20030204386A1 (en) * | 2002-04-24 | 2003-10-30 | Glenn Colon-Bonet | Class-based system for circuit modeling |
| KR100818826B1 (ko) * | 2002-04-25 | 2008-04-01 | 에이알씨 인터내셔널 | 집적회로의 설계를 발생하기 위한 컴퓨터처리되는 장치 및 복수의 성분을 갖는 집적회로 설계 내에 계층을 발생하기 위한 방법 |
| US6952810B2 (en) * | 2002-05-01 | 2005-10-04 | Sun Microsystems, Inc. | Coding speed and correctness of hardware description language (HDL) descriptions of hardware |
| US6711730B2 (en) * | 2002-05-13 | 2004-03-23 | Hewlett-Packard Development Company, L.P. | Synthesizing signal net information from multiple integrated circuit package models |
| US20030217338A1 (en) * | 2002-05-17 | 2003-11-20 | International Business Machines Corporation | Congestion mitigation with logic order preservation |
| US6775811B2 (en) * | 2002-05-22 | 2004-08-10 | Lsi Logic Corporation | Chip design method for designing integrated circuit chips with embedded memories |
| US7567892B2 (en) * | 2002-05-29 | 2009-07-28 | Broadcom Corporation | Method and system for realizing a logic model design |
| US7149991B2 (en) * | 2002-05-30 | 2006-12-12 | Nec Electronics America, Inc. | Calibrating a wire load model for an integrated circuit |
| US6925621B2 (en) * | 2002-06-24 | 2005-08-02 | Agilent Technologies, Inc. | System and method for applying timing models in a static-timing analysis of a hierarchical integrated circuit design |
| US7127692B2 (en) * | 2002-06-27 | 2006-10-24 | Lsi Logic Corporation | Timing abstraction and partitioning strategy |
| US6922822B2 (en) * | 2002-07-19 | 2005-07-26 | Hewlett-Packard Development Company, L.P. | Verifying proximity of ground vias to signal vias in an integrated circuit |
| US6769102B2 (en) * | 2002-07-19 | 2004-07-27 | Hewlett-Packard Development Company | Verifying proximity of ground metal to signal traces in an integrated circuit |
| US6910194B2 (en) * | 2002-07-19 | 2005-06-21 | Agilent Technologies, Inc. | Systems and methods for timing a linear data path element during signal-timing verification of an integrated circuit design |
| US6807657B2 (en) | 2002-07-19 | 2004-10-19 | Hewlett-Packard Development Company, L.P. | Inter-signal proximity verification in an integrated circuit |
| US6871332B2 (en) * | 2002-07-23 | 2005-03-22 | Sun Microsystems, Inc. | Structure and method for separating geometries in a design layout into multi-wide object classes |
| US7392255B1 (en) | 2002-07-31 | 2008-06-24 | Cadence Design Systems, Inc. | Federated system and methods and mechanisms of implementing and using such a system |
| US7702636B1 (en) | 2002-07-31 | 2010-04-20 | Cadence Design Systems, Inc. | Federated system and methods and mechanisms of implementing and using such a system |
| US6954915B2 (en) * | 2002-07-31 | 2005-10-11 | Agilent Technologies, Inc. | System and methods for pre-artwork signal-timing verification of an integrated circuit design |
| US7398445B2 (en) * | 2002-08-09 | 2008-07-08 | Synplicity, Inc. | Method and system for debug and test using replicated logic |
| US6904576B2 (en) * | 2002-08-09 | 2005-06-07 | Synplicity, Inc. | Method and system for debugging using replicated logic |
| US7213216B2 (en) * | 2002-08-09 | 2007-05-01 | Synplicity, Inc. | Method and system for debugging using replicated logic and trigger logic |
| US6842884B2 (en) * | 2002-08-28 | 2005-01-11 | Verplex Systems, Inc. | Combinational equivalence checking methods and systems with internal don't cares |
| WO2004023248A2 (en) * | 2002-09-04 | 2004-03-18 | Mentor Graphics (Holdings) Ltd. | Polymorphic computational system and method in signals intelligence analysis |
| US20040059704A1 (en) * | 2002-09-20 | 2004-03-25 | International Business Machines Corporation | Self-managing computing system |
| US7194445B2 (en) * | 2002-09-20 | 2007-03-20 | Lenovo (Singapore) Pte. Ltd. | Adaptive problem determination and recovery in a computer system |
| US7043419B2 (en) * | 2002-09-20 | 2006-05-09 | International Business Machines Corporation | Method and apparatus for publishing and monitoring entities providing services in a distributed data processing system |
| US20040060054A1 (en) * | 2002-09-20 | 2004-03-25 | International Business Machines Corporation | Composition service for autonomic computing |
| US7216343B2 (en) * | 2002-09-20 | 2007-05-08 | International Business Machines Corporation | Method and apparatus for automatic updating and testing of software |
| US7131097B1 (en) * | 2002-09-24 | 2006-10-31 | Altera Corporation | Logic generation for multiple memory functions |
| US7729898B1 (en) * | 2002-10-17 | 2010-06-01 | Altera Corporation | Methods and apparatus for implementing logic functions on a heterogeneous programmable device |
| US7336268B1 (en) * | 2002-10-30 | 2008-02-26 | National Semiconductor Corporation | Point-to-point display system having configurable connections |
| US6792581B2 (en) * | 2002-11-07 | 2004-09-14 | Intel Corporation | Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification |
| US7424417B2 (en) * | 2002-11-19 | 2008-09-09 | Broadcom Corporation | System and method for clock domain grouping using data path relationships |
| US7024636B2 (en) * | 2002-11-20 | 2006-04-04 | Lsi Logic Corporation | Chip management system |
| FI5706U1 (fi) * | 2002-11-21 | 2003-02-26 | Patria New Technologies Oy | JTAG-testilaitteisto ja -testausjärjestelmä |
| AU2002357880A1 (en) * | 2002-12-17 | 2004-07-29 | International Business Machines Corporation | Asic clock floor planning method and structure |
| US6968406B2 (en) * | 2003-02-20 | 2005-11-22 | Dell Products L.P. | System and method for arbitrating access between common access requests on a bus |
| US7898047B2 (en) * | 2003-03-03 | 2011-03-01 | Samsung Electronics Co., Ltd. | Integrated nitride and silicon carbide-based devices and methods of fabricating integrated nitride-based devices |
| US7143369B1 (en) * | 2003-03-14 | 2006-11-28 | Xilinx, Inc. | Design partitioning for co-stimulation |
| US8639487B1 (en) * | 2003-03-25 | 2014-01-28 | Cadence Design Systems, Inc. | Method for multiple processor system-on-a-chip hardware and software cogeneration |
| US20040199366A1 (en) * | 2003-04-01 | 2004-10-07 | Timothy Holm | Mixed signal analog connectivity check system |
| JP4428110B2 (ja) * | 2003-04-14 | 2010-03-10 | 富士ゼロックス株式会社 | 経験知識情報処理装置 |
| US7587690B1 (en) * | 2003-04-29 | 2009-09-08 | Cadence Design Systems, Inc. | Method and system for global coverage analysis |
| US7216318B1 (en) | 2003-04-29 | 2007-05-08 | Cadence Design Systems, Inc. | Method and system for false path analysis |
| US6728936B1 (en) * | 2003-04-29 | 2004-04-27 | Lsi Logic Corporation | Datapath bitslice technology |
| JP4248925B2 (ja) * | 2003-05-08 | 2009-04-02 | 株式会社ルネサステクノロジ | 自動フロアプラン決定方法 |
| US7000205B2 (en) * | 2003-05-29 | 2006-02-14 | International Business Machines Corporation | Method, apparatus, and program for block-based static timing analysis with uncertainty |
| US7178118B2 (en) * | 2003-05-30 | 2007-02-13 | Synplicity, Inc. | Method and apparatus for automated circuit design |
| US7627842B1 (en) | 2003-06-03 | 2009-12-01 | Cadence Design Systems, Inc. | Method and system for verification of circuits with encoded signals |
| US7043708B2 (en) * | 2003-06-09 | 2006-05-09 | Lsi Logic Corporation | Intelligent crosstalk delay estimator for integrated circuit design flow |
| US7184946B2 (en) * | 2003-06-19 | 2007-02-27 | Xilinx, Inc. | Co-simulation via boundary scan interface |
| US7216326B2 (en) * | 2003-06-20 | 2007-05-08 | Interuniversitar Microelektronica Centrum (Imec) | Resource activity aware system for determining a resource interconnection pattern within an essentially digital device and devices created therewith |
| IL156634A0 (en) * | 2003-06-25 | 2004-01-04 | Shmuel Livne | Method to evaluate and improve the testability of electronic products |
| US7231335B2 (en) * | 2003-06-26 | 2007-06-12 | International Business Machines Corporation | Method and apparatus for performing input/output floor planning on an integrated circuit design |
| JP2005037995A (ja) * | 2003-07-15 | 2005-02-10 | Toshiba Corp | 半導体集積回路の検証システム |
| US20050048348A1 (en) * | 2003-08-26 | 2005-03-03 | Hydrogenics Corporation | Fuel cell system and bracket therefor |
| US20050049843A1 (en) * | 2003-08-29 | 2005-03-03 | Lee Hewitt | Computerized extension apparatus and methods |
| US20050055194A1 (en) * | 2003-09-08 | 2005-03-10 | Krause Luanne Marie | Migration model |
| KR100546886B1 (ko) * | 2003-10-08 | 2006-01-26 | 삼성전자주식회사 | 시스템온칩 성능 측정장치 및 그 성능 측정방법 |
| US7111264B2 (en) * | 2003-10-17 | 2006-09-19 | Lsi Logic Corporation | Process and apparatus for fast assignment of objects to a rectangle |
| US8065128B1 (en) * | 2003-10-23 | 2011-11-22 | Altera Corporation | Methods and apparatus for automated testbench generation |
| US7036102B2 (en) * | 2003-10-27 | 2006-04-25 | Lsi Logic Corporation | Process and apparatus for placement of cells in an IC during floorplan creation |
| NZ547492A (en) * | 2003-10-28 | 2009-12-24 | Bioarray Solutions Ltd | Optimization of gene expression analysis using immobilized capture probes of different lengths and densities |
| US7103865B2 (en) * | 2003-11-21 | 2006-09-05 | Lsi Logic Corporation | Process and apparatus for placement of megacells in ICs design |
| WO2005055341A1 (en) * | 2003-12-01 | 2005-06-16 | Hydrogenics Corporation | Fuel cell system and bracket therefor |
| US7003749B2 (en) * | 2004-01-12 | 2006-02-21 | Cadence Design Systems, Inc. | Constraint data management for electronic design automation |
| US7305332B1 (en) * | 2004-01-14 | 2007-12-04 | Adaptec, Inc. | System and method for automatic extraction of testing information from a functional specification |
| US7093218B2 (en) * | 2004-02-19 | 2006-08-15 | International Business Machines Corporation | Incremental, assertion-based design verification |
| US7788078B1 (en) | 2004-02-27 | 2010-08-31 | Synopsys, Inc. | Processor/memory co-exploration at multiple abstraction levels |
| US7055118B1 (en) | 2004-03-01 | 2006-05-30 | Sun Microsystems, Inc. | Scan chain verification using symbolic simulation |
| US7149993B1 (en) * | 2004-03-29 | 2006-12-12 | Xilinx, Inc. | Method, system, and apparatus for incremental design in programmable logic devices using floorplanning |
| US7620743B2 (en) * | 2004-04-01 | 2009-11-17 | Lsi Corporation | System and method for implementing multiple instantiated configurable peripherals in a circuit design |
| US20050229143A1 (en) * | 2004-04-01 | 2005-10-13 | Lsi Logic Corporation | System and method for implementing multiple instantiated configurable peripherals in a circuit design |
| US7275224B2 (en) * | 2004-04-02 | 2007-09-25 | International Business Machines Corporation | Method for providing an area optimized binary orthogonality checker |
| US7103858B2 (en) * | 2004-04-14 | 2006-09-05 | Lsi Logic Corporation | Process and apparatus for characterizing intellectual property for integration into an IC platform environment |
| US7606692B2 (en) * | 2004-04-26 | 2009-10-20 | Lsi Corporation | Gate-level netlist reduction for simulating target modules of a design |
| JP2005321861A (ja) * | 2004-05-06 | 2005-11-17 | Nec Electronics Corp | 機能検証方法 |
| US20050251767A1 (en) * | 2004-05-07 | 2005-11-10 | Shah Gaurav R | Processing of circuit design data |
| US7243311B2 (en) * | 2004-05-28 | 2007-07-10 | Rohm Co., Ltd. | Method and apparatus for supporting development of integrated circuit and a transactional business method involving contracting and licensing |
| WO2005119531A2 (en) * | 2004-06-01 | 2005-12-15 | Tera Systems, Inc. | Rule-based design consultant and method for integrated circuit design |
| US7409658B2 (en) * | 2004-06-01 | 2008-08-05 | Magma Design Automation, Inc. | Methods and systems for mixed-mode physical synthesis in electronic design automation |
| US20050273683A1 (en) * | 2004-06-07 | 2005-12-08 | Logicvision, Inc. | Insertion of embedded test in RTL to GDSII flow |
| US7310792B2 (en) * | 2004-06-15 | 2007-12-18 | Cadence Design Systems, Inc. | Method and system for modeling variation of circuit parameters in delay calculation for timing analysis |
| US7278122B2 (en) * | 2004-06-24 | 2007-10-02 | Ftl Systems, Inc. | Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization |
| TWI286216B (en) * | 2004-06-29 | 2007-09-01 | Pixart Imaging Inc | Single chip test method, component and its test system |
| US7516423B2 (en) * | 2004-07-13 | 2009-04-07 | Kimotion Technologies | Method and apparatus for designing electronic circuits using optimization |
| US7360177B1 (en) | 2004-08-06 | 2008-04-15 | Xilinx, Inc. | Method and arrangement providing for implementation granularity using implementation sets |
| US7181704B1 (en) * | 2004-08-06 | 2007-02-20 | Xilinx, Inc. | Method and system for designing integrated circuits using implementation directives |
| US7146583B1 (en) | 2004-08-06 | 2006-12-05 | Xilinx, Inc. | Method and system for implementing a circuit design in a tree representation |
| US7171644B1 (en) | 2004-08-06 | 2007-01-30 | Xilinx, Inc. | Implementation set-based guide engine and method of implementing a circuit design |
| US7290241B1 (en) | 2004-08-06 | 2007-10-30 | Xilinx, Inc. | Method and system for managing behavior of algorithms |
| US7913206B1 (en) * | 2004-09-16 | 2011-03-22 | Cadence Design Systems, Inc. | Method and mechanism for performing partitioning of DRC operations |
| US20060080632A1 (en) * | 2004-09-30 | 2006-04-13 | Mathstar, Inc. | Integrated circuit layout having rectilinear structure of objects |
| US7500165B2 (en) | 2004-10-06 | 2009-03-03 | Broadcom Corporation | Systems and methods for controlling clock signals during scan testing integrated circuits |
| US7730437B1 (en) * | 2004-10-27 | 2010-06-01 | Cypress Semiconductor Corporation | Method of full semiconductor chip timing closure |
| US7526745B2 (en) * | 2004-12-08 | 2009-04-28 | Telefonaktiebolaget L M Ericsson (Publ) | Method for specification and integration of reusable IP constraints |
| US20060136188A1 (en) * | 2004-12-22 | 2006-06-22 | Lacey David J | Capturing curation data |
| US20070247189A1 (en) * | 2005-01-25 | 2007-10-25 | Mathstar | Field programmable semiconductor object array integrated circuit |
| US7856611B2 (en) * | 2005-02-17 | 2010-12-21 | Samsung Electronics Co., Ltd. | Reconfigurable interconnect for use in software-defined radio systems |
| US7325210B2 (en) * | 2005-03-10 | 2008-01-29 | International Business Machines Corporation | Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect |
| US20060235657A1 (en) * | 2005-03-18 | 2006-10-19 | Inventec Corporation | System of accumulating component design experience and method thereof |
| US20060225015A1 (en) * | 2005-03-31 | 2006-10-05 | Kamil Synek | Various methods and apparatuses for flexible hierarchy grouping |
| US7178075B2 (en) * | 2005-04-25 | 2007-02-13 | International Business Machines Corporation | High-speed level sensitive scan design test scheme with pipelined test clocks |
| US7506281B1 (en) * | 2005-05-18 | 2009-03-17 | Xilinx, Inc. | Two-pass method for implementing a flexible testbench |
| JP4427002B2 (ja) * | 2005-05-20 | 2010-03-03 | 株式会社アドバンテスト | 半導体試験用プログラムデバッグ装置 |
| US7539957B1 (en) * | 2005-05-26 | 2009-05-26 | Altera Corporation | Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks |
| US7657416B1 (en) * | 2005-06-10 | 2010-02-02 | Cadence Design Systems, Inc | Hierarchical system design |
| US7483823B2 (en) | 2005-06-21 | 2009-01-27 | Nvidia Corporation | Building integrated circuits using logical units |
| US7363610B2 (en) * | 2005-06-21 | 2008-04-22 | Nvidia Corporation | Building integrated circuits using a common database |
| EP1736905A3 (en) * | 2005-06-21 | 2007-09-05 | Nvidia Corporation | Building integrated circuits using logical units |
| US7451426B2 (en) * | 2005-07-07 | 2008-11-11 | Lsi Corporation | Application specific configurable logic IP |
| US7464345B2 (en) * | 2005-08-01 | 2008-12-09 | Lsi Corporation | Resource estimation for design planning |
| US20070033557A1 (en) * | 2005-08-08 | 2007-02-08 | Byrn Jonathan W | Method for creating constraints for integrated circuit design closure |
| US7904852B1 (en) | 2005-09-12 | 2011-03-08 | Cadence Design Systems, Inc. | Method and system for implementing parallel processing of electronic design automation tools |
| US7409656B1 (en) | 2005-09-12 | 2008-08-05 | Cadence Design Systems, Inc. | Method and system for parallelizing computing operations |
| JP2007103662A (ja) * | 2005-10-04 | 2007-04-19 | Matsushita Electric Ind Co Ltd | 半導体集積回路およびその製造方法 |
| JP4366353B2 (ja) | 2005-10-25 | 2009-11-18 | パナソニック株式会社 | 半導体集積回路及びその設計方法 |
| US20070150627A1 (en) * | 2005-11-22 | 2007-06-28 | Lsi Logic Corporation | Endian mapping engine, method of endian mapping and a processing system employing the engine and the method |
| US7627847B1 (en) * | 2005-12-01 | 2009-12-01 | Cadence Design Systems, Inc. | Method and system for representing manufacturing and lithography information for IC routing |
| US20070162268A1 (en) * | 2006-01-12 | 2007-07-12 | Bhaskar Kota | Algorithmic electronic system level design platform |
| US20070162531A1 (en) * | 2006-01-12 | 2007-07-12 | Bhaskar Kota | Flow transform for integrated circuit design and simulation having combined data flow, control flow, and memory flow views |
| JP4652242B2 (ja) * | 2006-01-20 | 2011-03-16 | 株式会社日立製作所 | 半導体集積回路のセル配置方法 |
| US7526742B1 (en) | 2006-01-31 | 2009-04-28 | Xilinx, Inc. | One-pass method for implementing a flexible testbench |
| JP2007213269A (ja) * | 2006-02-08 | 2007-08-23 | Toshiba Corp | 応力解析方法、配線構造設計方法、プログラム及び半導体装置の製造方法 |
| US7469401B2 (en) * | 2006-02-22 | 2008-12-23 | International Business Machines Corporation | Method for using partitioned masks to build a chip |
| WO2007112406A2 (en) | 2006-03-27 | 2007-10-04 | Coherent Logix Incorporated | Programming a multi-processor system |
| US7567947B2 (en) * | 2006-04-04 | 2009-07-28 | Optimaltest Ltd. | Methods and systems for semiconductor testing using a testing scenario language |
| US7543265B1 (en) * | 2006-04-26 | 2009-06-02 | Altera Corporation | Method for early logic mapping during FPGA synthesis |
| US7865694B2 (en) * | 2006-05-12 | 2011-01-04 | International Business Machines Corporation | Three-dimensional networking structure |
| US7571414B2 (en) * | 2006-06-15 | 2009-08-04 | National Chip Implementation Center, National Applied Research Laboratories | Multi-project system-on-chip and its method |
| US8448096B1 (en) | 2006-06-30 | 2013-05-21 | Cadence Design Systems, Inc. | Method and system for parallel processing of IC design layouts |
| US8463589B2 (en) | 2006-07-28 | 2013-06-11 | Synopsys, Inc. | Modifying a virtual processor model for hardware/software simulation |
| KR100831271B1 (ko) | 2006-08-16 | 2008-05-22 | 동부일렉트로닉스 주식회사 | 물리적 레이어의 프로그램적 생성을 통한 물리적 레이아웃 데이터를 변경하는 방법 |
| US7657856B1 (en) | 2006-09-12 | 2010-02-02 | Cadence Design Systems, Inc. | Method and system for parallel processing of IC design layouts |
| JP4805779B2 (ja) * | 2006-10-04 | 2011-11-02 | 富士通株式会社 | 集積回路設計方法、集積回路設計装置及び集積回路設計プログラム |
| US7694251B2 (en) * | 2006-10-30 | 2010-04-06 | Cadence Design Systems, Inc. | Method and system for verifying power specifications of a low power design |
| US8332452B2 (en) * | 2006-10-31 | 2012-12-11 | International Business Machines Corporation | Single precision vector dot product with “word” vector write mask |
| US20080100628A1 (en) * | 2006-10-31 | 2008-05-01 | International Business Machines Corporation | Single Precision Vector Permute Immediate with "Word" Vector Write Mask |
| US9495724B2 (en) * | 2006-10-31 | 2016-11-15 | International Business Machines Corporation | Single precision vector permute immediate with “word” vector write mask |
| US8868397B2 (en) * | 2006-11-20 | 2014-10-21 | Sonics, Inc. | Transaction co-validation across abstraction layers |
| US8020124B2 (en) * | 2006-11-20 | 2011-09-13 | Sonics, Inc. | Various methods and apparatuses for cycle accurate C-models of components |
| US8127113B1 (en) | 2006-12-01 | 2012-02-28 | Synopsys, Inc. | Generating hardware accelerators and processor offloads |
| US8365113B1 (en) * | 2007-01-10 | 2013-01-29 | Cadence Design Systems, Inc. | Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs |
| WO2008091575A2 (en) * | 2007-01-22 | 2008-07-31 | Vast Systems Technology Corporation | Method and system for modeling a bus for a system design incorporating one or more programmable processors |
| KR100893743B1 (ko) * | 2007-01-23 | 2009-04-17 | (주)에스엠티코리아 | 인쇄회로기판의 설계 시스템 및 기록매체 |
| US7603643B2 (en) * | 2007-01-30 | 2009-10-13 | Cadence Design Systems, Inc. | Method and system for conducting design explorations of an integrated circuit |
| US7530036B2 (en) * | 2007-02-08 | 2009-05-05 | International Business Machines Corporation | Random test generation using an optimization solver |
| US20090067343A1 (en) * | 2007-06-04 | 2009-03-12 | David Fritz | Method for the synthesis of optimal asynchronous on-chip communication networks from system-level constraints |
| US7814454B2 (en) * | 2007-06-28 | 2010-10-12 | International Business Machines Corporation | Selectable device options for characterizing semiconductor devices |
| US7895029B2 (en) * | 2007-10-30 | 2011-02-22 | International Business Machines Corporation | System and method of automating the addition of RTL based critical timing path counters to verify critical path coverage of post-silicon software validation tools |
| US8271252B2 (en) * | 2007-11-08 | 2012-09-18 | Nvidia Corporation | Automatic verification of device models |
| US7904289B2 (en) * | 2007-11-12 | 2011-03-08 | International Business Machines Corporation | Method and system for testing functionality of a chip checker |
| US8019970B2 (en) * | 2007-11-28 | 2011-09-13 | International Business Machines Corporation | Three-dimensional networking design structure |
| US20090144595A1 (en) * | 2007-11-30 | 2009-06-04 | Mathstar, Inc. | Built-in self-testing (bist) of field programmable object arrays |
| US8239182B2 (en) * | 2007-12-04 | 2012-08-07 | Spansion Llc | Data transmission system-on-chip memory model based validation |
| US7941299B1 (en) | 2008-01-08 | 2011-05-10 | The Mathworks, Inc. | Verification and validation system for a graphical model |
| US7694266B1 (en) * | 2008-01-22 | 2010-04-06 | Cadence Design Systems, Inc. | Method and apparatus for dynamic frequency voltage switching circuit synthesis |
| US8117579B2 (en) * | 2008-01-31 | 2012-02-14 | International Business Machines Corporation | LSSD compatibility for GSD unified global clock buffers |
| US8510616B2 (en) * | 2008-02-14 | 2013-08-13 | Nvidia Corporation | Scalable scan-based test architecture with reduced test time and test power |
| US8745200B2 (en) * | 2008-05-06 | 2014-06-03 | Nvidia Corporation | Testing operation of processors setup to operate in different modes |
| JP2009294744A (ja) * | 2008-06-03 | 2009-12-17 | Nec Electronics Corp | バスインターフェース設計装置、バスインターフェース設計方法、及びプログラム |
| US8032338B2 (en) * | 2008-06-13 | 2011-10-04 | Power Integrations, Inc. | Method and apparatus for design of a power supply |
| US8219944B2 (en) * | 2008-06-24 | 2012-07-10 | Cadence Design Systems, Inc. | Method and system performing block-level RC extraction |
| US8584073B2 (en) * | 2008-07-21 | 2013-11-12 | Synopsys, Inc. | Test design optimizer for configurable scan architectures |
| JP5138040B2 (ja) * | 2008-07-30 | 2013-02-06 | パナソニック株式会社 | 集積回路 |
| US7949980B1 (en) | 2008-07-31 | 2011-05-24 | Altera Corporation | Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities |
| US8095902B2 (en) * | 2008-08-18 | 2012-01-10 | International Business Machines Corporation | Design structure for couple noise characterization using a single oscillator |
| WO2010023499A1 (en) * | 2008-08-25 | 2010-03-04 | David Fritz | Method for the synthesis of optimal asynchronous on-chip communication networks from system-level constraints |
| US8046726B2 (en) * | 2008-09-16 | 2011-10-25 | Lsi Corporation | Waiver mechanism for physical verification of system designs |
| US8156453B1 (en) | 2008-10-16 | 2012-04-10 | Cadence Design Systems, Inc. | Method and system identifying and locating IP blocks and block suppliers for an electronic design |
| AU2009315179B2 (en) | 2008-11-14 | 2013-11-14 | Sun Patent Trust | Wireless communication terminal apparatus, wireless communication base station apparatus, and cluster constellation setting method |
| US8943457B2 (en) * | 2008-11-24 | 2015-01-27 | Nvidia Corporation | Simulating scan tests with reduced resources |
| US8261215B2 (en) * | 2008-12-22 | 2012-09-04 | Cadence Design Systems, Inc. | Method and system for performing cell modeling and selection |
| US8065638B2 (en) * | 2009-01-30 | 2011-11-22 | Synopsys, Inc. | Incremental concurrent processing for efficient computation of high-volume layout data |
| US8893061B2 (en) * | 2009-01-30 | 2014-11-18 | Synopsys, Inc. | Incremental concurrent processing for efficient computation of high-volume layout data |
| JP5236533B2 (ja) * | 2009-03-05 | 2013-07-17 | 株式会社トヨタIt開発センター | ネットワークの設計を支援するための方法および装置 |
| JP5262909B2 (ja) * | 2009-03-27 | 2013-08-14 | 富士通株式会社 | 検証支援プログラム、検証支援装置および検証支援方法 |
| US8966414B2 (en) * | 2009-05-29 | 2015-02-24 | Cypress Semiconductor Corporation | Implementing a circuit using an integrated circuit including parametric analog elements |
| US20100305933A1 (en) * | 2009-06-01 | 2010-12-02 | Chang Chioumin M | Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution |
| US9477802B1 (en) | 2009-06-09 | 2016-10-25 | Cadence Design Systems, Inc. | Isolating differences between revisions of a circuit design |
| US9858367B1 (en) | 2009-08-31 | 2018-01-02 | Cypress Semiconductor Corporation | Integrated circuit including parametric analog elements |
| US8324924B2 (en) * | 2009-10-20 | 2012-12-04 | David Scott Landoll | Post-programming functional verification for programable integrated circuits |
| US8219228B2 (en) * | 2009-10-23 | 2012-07-10 | Certusoft, Inc. | Parametric configurator for product design: system and method |
| US8214069B2 (en) * | 2009-10-23 | 2012-07-03 | Certusoft, Inc. | Automated hierarchical configuration of custom products with complex geometries: method and apparatus |
| CN101692655B (zh) * | 2009-10-23 | 2012-05-30 | 烽火通信科技股份有限公司 | 一种数据帧存储管理装置 |
| JP5068300B2 (ja) * | 2009-11-24 | 2012-11-07 | インターナショナル・ビジネス・マシーンズ・コーポレーション | データフロー及びプロセッサのメモリ共有化ための装置、方法及びプログラム |
| CN101833491B (zh) * | 2010-04-26 | 2012-10-24 | 浪潮电子信息产业股份有限公司 | 一种节点互连系统链路检测电路的设计与fpga实现方法 |
| US9230047B1 (en) * | 2010-06-11 | 2016-01-05 | Altera Corporation | Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement |
| US20120005643A1 (en) * | 2010-06-30 | 2012-01-05 | International Business Machines Corporation | System and Method for Placing Integrated Circuit Functional Blocks According to Dataflow Width |
| CN101916305A (zh) * | 2010-07-19 | 2010-12-15 | 无锡汉咏微电子有限公司 | 一种复杂管脚芯片的验证方法 |
| CN102096619A (zh) * | 2010-12-17 | 2011-06-15 | 天津曙光计算机产业有限公司 | 一种基于tcp流的验证方法 |
| CN102012957A (zh) * | 2010-12-17 | 2011-04-13 | 天津曙光计算机产业有限公司 | 一种基于五元组的包分类逻辑代码验证方法 |
| JP5565340B2 (ja) * | 2011-02-24 | 2014-08-06 | 富士通株式会社 | 試験方法,試験プログラム,及び試験装置 |
| US8683282B2 (en) * | 2011-03-01 | 2014-03-25 | International Business Machines Corporation | Automatic identification of information useful for generation-based functional verification |
| US8661305B2 (en) * | 2011-07-10 | 2014-02-25 | Ravishankar Rajarao | Method and system for test vector generation |
| US8572527B1 (en) | 2011-09-13 | 2013-10-29 | Jasper Design Automation, Inc. | Generating properties for circuit designs |
| US8788988B2 (en) | 2011-10-31 | 2014-07-22 | Apple Inc. | Managing consistency of multiple-source fabrication data in an electronic design environment |
| US9336107B2 (en) | 2011-11-18 | 2016-05-10 | Mentor Graphics Corporation | Dynamic design partitioning for diagnosis |
| US8516421B1 (en) * | 2012-01-10 | 2013-08-20 | Jasper Design Automation, Inc. | Generating circuit design properties from signal traces |
| US8434052B1 (en) | 2012-02-21 | 2013-04-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for ensuring partitioned block physical compatibility between revisions of an integrated circuit design |
| US8739092B1 (en) | 2012-04-25 | 2014-05-27 | Jasper Design Automation, Inc. | Functional property ranking |
| US8365109B1 (en) * | 2012-06-27 | 2013-01-29 | Xilinx, Inc. | Determining efficient buffering for multi-dimensional datastream applications |
| US8533647B1 (en) * | 2012-10-05 | 2013-09-10 | Atrenta, Inc. | Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design |
| US8635567B1 (en) * | 2012-10-11 | 2014-01-21 | Xilinx, Inc. | Electronic design automation tool for guided connection assistance |
| US9069919B1 (en) * | 2012-10-17 | 2015-06-30 | Qlogic, Corporation | Method and system for arbitration verification |
| US8904256B1 (en) * | 2012-11-09 | 2014-12-02 | Cadence Design Systems, Inc. | Method and apparatus for low-pin count testing of integrated circuits |
| US20140149817A1 (en) * | 2012-11-27 | 2014-05-29 | International Business Machines Corporation | Diagnostic testing for a double-pumped memory array |
| US9251554B2 (en) | 2012-12-26 | 2016-02-02 | Analog Devices, Inc. | Block-based signal processing |
| US8645897B1 (en) * | 2013-01-07 | 2014-02-04 | Freescale Semiconductor, Inc. | Integrated circuit design verification system |
| US8769449B1 (en) * | 2013-02-08 | 2014-07-01 | Xilinx, Inc. | System level circuit design |
| US8826201B1 (en) * | 2013-03-14 | 2014-09-02 | Jasper Design Automation, Inc. | Formal verification coverage metrics for circuit design properties |
| US8745567B1 (en) * | 2013-03-14 | 2014-06-03 | Atrenta, Inc. | Efficient apparatus and method for analysis of RTL structures that cause physical congestion |
| US8826215B1 (en) | 2013-05-24 | 2014-09-02 | International Business Machines Corporation | Routing centric design closure |
| US9507883B2 (en) | 2013-06-24 | 2016-11-29 | Altera Corporation | Method and apparatus for implementing a system-level design tool for design planning and architecture exploration |
| CN103439904A (zh) * | 2013-08-27 | 2013-12-11 | 国家电网公司 | 一种用于配网系统的智能控制通讯装置 |
| US9081927B2 (en) | 2013-10-04 | 2015-07-14 | Jasper Design Automation, Inc. | Manipulation of traces for debugging a circuit design |
| US9158874B1 (en) | 2013-11-06 | 2015-10-13 | Cadence Design Systems, Inc. | Formal verification coverage metrics of covered events for circuit design properties |
| US8875073B1 (en) * | 2014-02-20 | 2014-10-28 | Xilinx, Inc. | Generation of internal interfaces for a block-based design |
| US9653184B2 (en) | 2014-06-16 | 2017-05-16 | Sandisk Technologies Llc | Non-volatile memory module with physical-to-physical address remapping |
| US8976609B1 (en) * | 2014-06-16 | 2015-03-10 | Sandisk Enterprise Ip Llc | Low-test memory stack for non-volatile storage |
| US9613715B2 (en) | 2014-06-16 | 2017-04-04 | Sandisk Technologies Llc | Low-test memory stack for non-volatile storage |
| US9606882B2 (en) | 2014-07-17 | 2017-03-28 | Sandisk Technologies Llc | Methods and systems for die failure testing |
| US9934347B2 (en) | 2014-10-01 | 2018-04-03 | Samsung Electronics Co., Ltd. | Integrated circuit and method of designing layout of integrated circuit |
| US9355211B2 (en) * | 2014-10-10 | 2016-05-31 | Oracle International Corporation | Unified tool for automatic design constraints generation and verification |
| CN104616557B (zh) * | 2015-01-30 | 2017-05-17 | 南车株洲电力机车有限公司 | 一种轨道车辆模拟电路生成方法、系统及控制方法、系统 |
| US9405882B1 (en) * | 2015-06-26 | 2016-08-02 | Cadence Design Systems, Inc. | High performance static timing analysis system and method for input/output interfaces |
| US10395001B2 (en) * | 2015-11-25 | 2019-08-27 | Synopsys, Inc. | Multiple patterning layout decomposition considering complex coloring rules |
| US10289788B1 (en) * | 2015-11-30 | 2019-05-14 | Cadence Design Systems, Inc. | System and method for suggesting components associated with an electronic design |
| US10347024B2 (en) * | 2016-03-18 | 2019-07-09 | Mitsubishi Electric Corporation | Control logic diagram creation support apparatus |
| US10380292B1 (en) * | 2016-04-08 | 2019-08-13 | Cadence Design Systems, Inc. | Systems and methods for finite difference time domain simulation of an electronic design |
| US10235485B1 (en) * | 2016-09-27 | 2019-03-19 | Altera Corporation | Partial reconfiguration debugging using hybrid models |
| JP6780576B2 (ja) * | 2017-04-27 | 2020-11-04 | トヨタ自動車株式会社 | 解析手法提示システム、方法及びプログラム |
| US11361124B1 (en) * | 2017-08-10 | 2022-06-14 | Ansys, Inc. | Generating a power profile by node sampling an IP block |
| US10762262B1 (en) * | 2017-11-03 | 2020-09-01 | Synopsys, Inc. | Multi-dimensional constraint solver using modified relaxation process |
| CN108009339A (zh) * | 2017-11-28 | 2018-05-08 | 深圳市瑞尔时代科技有限公司 | 一种监控主机端口设计方法 |
| CN108596415B (zh) | 2017-12-15 | 2023-11-24 | 创新先进技术有限公司 | 一种模型整合方法及装置 |
| CN108520128B (zh) * | 2018-03-29 | 2022-04-15 | 北京集创北方科技股份有限公司 | 集成电路设计方法和计算机可读存储介质 |
| US10614190B2 (en) | 2018-06-29 | 2020-04-07 | International Business Machines Corporation | Deep trench floorplan distribution design methodology for semiconductor manufacturing |
| FR3085759A1 (fr) * | 2018-09-12 | 2020-03-13 | Stmicroelectronics (Grenoble 2) Sas | Puce electronique a entrees/sorties analogiques comprenant des moyens d'auto-diagnostic |
| US20200410153A1 (en) * | 2019-05-30 | 2020-12-31 | Celera, Inc. | Automated circuit generation |
| US10831965B1 (en) * | 2019-07-23 | 2020-11-10 | International Business Machines Corporation | Placement of vectorized latches in hierarchical integrated circuit development |
| US11467851B1 (en) * | 2019-11-21 | 2022-10-11 | Synopsys, Inc. | Machine learning (ML)-based static verification for derived hardware-design elements |
| ES2752086B2 (es) * | 2019-12-18 | 2020-08-07 | Univ Politècnica De València | Dispositivo fotonico integrado de matriz cuantica de puertas fotonicas programables en campo, dispositivo quantico y circuitos programables |
| GB2592947B (en) * | 2020-03-11 | 2022-08-31 | Agile Analog Ltd | Analogue circuit design |
| TWI749724B (zh) * | 2020-08-21 | 2021-12-11 | 和碩聯合科技股份有限公司 | 電子電路系統 |
| US20220164510A1 (en) * | 2020-11-24 | 2022-05-26 | Raytheon Company | Automated design of field programmable gate array or other logic device based on artificial intelligence and vectorization of behavioral source code |
| US12190152B2 (en) | 2020-11-24 | 2025-01-07 | Raytheon Company | Run-time schedulers for field programmable gate arrays or other logic devices |
| US12248415B2 (en) | 2020-11-24 | 2025-03-11 | Raytheon Company | Automated design of behavioral-based data movers for field programmable gate arrays or other logic devices |
| KR102384978B1 (ko) * | 2020-12-08 | 2022-04-07 | 현대오토에버 주식회사 | 가치 기반 마이크로 컨트롤러 유닛의 포트 자동 설계 장치 및 방법 |
| CN112763890B (zh) * | 2020-12-15 | 2022-09-16 | 成都海光微电子技术有限公司 | 用于芯片的自适应电压与频率调节的测试电路的实现方法 |
| US11188702B1 (en) * | 2020-12-31 | 2021-11-30 | Cadence Design Systems, Inc. | Dynamic weighting scheme for local cluster refinement |
| US11704461B1 (en) * | 2022-01-04 | 2023-07-18 | International Business Machines Corporation | Dynamic control of coverage by a verification testbench |
| TWI789198B (zh) * | 2022-01-04 | 2023-01-01 | 瑞昱半導體股份有限公司 | 掃描鏈設計與電路測試方法 |
| US12135351B2 (en) | 2022-02-03 | 2024-11-05 | Stmicroelectronics S.R.L. | DFT architecture for analog circuits |
| CN114330184B (zh) * | 2022-03-15 | 2022-07-15 | 上海国微思尔芯技术股份有限公司 | 一种多层次分组方法及装置 |
| US12188983B1 (en) * | 2023-06-14 | 2025-01-07 | HCL America Inc. | Method and system for controlling actions of testbench components within a test environment |
| US20250217219A1 (en) * | 2023-12-28 | 2025-07-03 | Advanced Micro Devices, Inc. | Transactional timeouts for managing critical domains |
| CN119026534A (zh) * | 2024-08-12 | 2024-11-26 | 深圳奥维领芯科技有限公司 | SoC的测试用例生成方法、装置、主机及程序 |
| CN119180259B (zh) * | 2024-11-14 | 2025-06-24 | 西安简矽技术有限公司 | 生成可测试性设计架构的方法、装置、设备及存储介质 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4858175A (en) * | 1984-09-29 | 1989-08-15 | Kabushiki Kaisha Toshiba | Monolithic semi-custom IC having standard LSI sections and coupling gate array sections |
| US5519633A (en) * | 1993-03-08 | 1996-05-21 | International Business Machines Corporation | Method and apparatus for the cross-sectional design of multi-layer printed circuit boards |
| US5663076A (en) * | 1995-08-08 | 1997-09-02 | Lsi Logic Corporation | Automating photolithography in the fabrication of integrated circuits |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5544066A (en) * | 1990-04-06 | 1996-08-06 | Lsi Logic Corporation | Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints |
| US5222030A (en) * | 1990-04-06 | 1993-06-22 | Lsi Logic Corporation | Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof |
| US5553002A (en) * | 1990-04-06 | 1996-09-03 | Lsi Logic Corporation | Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface |
| US5623684A (en) * | 1994-05-17 | 1997-04-22 | Commquest Technologies, Inc. | Application specific processor architecture comprising pre-designed reconfigurable application elements interconnected via a bus with high-level statements controlling configuration and data routing |
| US5953519A (en) * | 1995-06-12 | 1999-09-14 | Fura; David A. | Method and system for generating electronic hardware simulation models |
| US6118302A (en) * | 1996-05-28 | 2000-09-12 | Altera Corporation | Interface for low-voltage semiconductor devices |
| US6058263A (en) * | 1996-06-03 | 2000-05-02 | Microsoft Corporation | Interface hardware design using internal and external interfaces |
| US5802518A (en) * | 1996-06-04 | 1998-09-01 | Multex Systems, Inc. | Information delivery system and method |
| US5812416A (en) * | 1996-07-18 | 1998-09-22 | Lsi Logic Corporation | Integrated circuit design decomposition |
| US5812561A (en) * | 1996-09-03 | 1998-09-22 | Motorola, Inc. | Scan based testing of an integrated circuit for compliance with timing specifications |
| US5930762A (en) * | 1996-09-24 | 1999-07-27 | Rco Software Limited | Computer aided risk management in multiple-parameter physical systems |
| JPH10303308A (ja) * | 1996-11-19 | 1998-11-13 | Lsi Logic Corp | 複数のコアおよびシェルを有する集積回路および対応する階層ファームウェア |
| US6058253A (en) * | 1996-12-05 | 2000-05-02 | Advanced Micro Devices, Inc. | Method and apparatus for intrusive testing of a microprocessor feature |
| US6182258B1 (en) * | 1997-06-03 | 2001-01-30 | Verisity Ltd. | Method and apparatus for test generation during circuit design |
| US5974241A (en) * | 1997-06-17 | 1999-10-26 | Lsi Logic Corporation | Test bench interface generator for tester compatible simulations |
| US6141630A (en) * | 1997-08-07 | 2000-10-31 | Verisity Design, Inc. | System and method for automated design verification |
| DE59813158D1 (de) * | 1997-09-18 | 2005-12-08 | Infineon Technologies Ag | Verfahren zum Testen einer elektronischen Schaltung |
| US6237123B1 (en) * | 1997-10-07 | 2001-05-22 | Lucent Technologies Inc. | Built-in self-test controlled by a token network and method |
| US6173435B1 (en) * | 1998-02-20 | 2001-01-09 | Lsi Logic Corporation | Internal clock handling in synthesis script |
| JP2002517042A (ja) * | 1998-05-29 | 2002-06-11 | カデンス デザイン システムズ, インコーポレイテッド | Ipブロックを選択する方法および装置 |
-
1999
- 1999-09-30 JP JP2000572780A patent/JP2002526908A/ja active Pending
- 1999-09-30 EE EEP200100189A patent/EE200100189A/xx unknown
- 1999-09-30 EP EP99954722A patent/EP1145159A3/en not_active Ceased
- 1999-09-30 HU HU0301274A patent/HUP0301274A2/hu unknown
- 1999-09-30 US US09/410,356 patent/US6269467B1/en not_active Expired - Lifetime
- 1999-09-30 KR KR1020017004099A patent/KR100846089B1/ko not_active Expired - Fee Related
- 1999-09-30 PL PL99350155A patent/PL350155A1/xx unknown
- 1999-09-30 AU AU11005/00A patent/AU1100500A/en not_active Abandoned
- 1999-09-30 CN CNB998137790A patent/CN1331079C/zh not_active Expired - Fee Related
- 1999-09-30 CA CA002345648A patent/CA2345648A1/en not_active Abandoned
- 1999-09-30 WO PCT/US1999/022984 patent/WO2000019343A2/en not_active Ceased
- 1999-09-30 BR BR9914200-7A patent/BR9914200A/pt not_active Application Discontinuation
- 1999-09-30 IL IL14227999A patent/IL142279A0/xx unknown
-
2001
- 2001-01-04 US US09/754,559 patent/US6594800B2/en not_active Expired - Lifetime
- 2001-01-04 US US09/754,550 patent/US6567957B1/en not_active Expired - Lifetime
- 2001-01-04 US US09/754,725 patent/US6574778B2/en not_active Expired - Fee Related
- 2001-01-04 US US09/754,734 patent/US6694501B2/en not_active Expired - Lifetime
- 2001-01-04 US US09/754,653 patent/US6701504B2/en not_active Expired - Lifetime
- 2001-02-23 US US09/754,466 patent/US6629293B2/en not_active Expired - Lifetime
- 2001-03-23 US US09/754,642 patent/US6631470B2/en not_active Expired - Lifetime
- 2001-03-23 US US09/754,640 patent/US6698002B2/en not_active Expired - Lifetime
- 2001-03-23 US US09/754,724 patent/US6725432B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4858175A (en) * | 1984-09-29 | 1989-08-15 | Kabushiki Kaisha Toshiba | Monolithic semi-custom IC having standard LSI sections and coupling gate array sections |
| US5519633A (en) * | 1993-03-08 | 1996-05-21 | International Business Machines Corporation | Method and apparatus for the cross-sectional design of multi-layer printed circuit boards |
| US5663076A (en) * | 1995-08-08 | 1997-09-02 | Lsi Logic Corporation | Automating photolithography in the fabrication of integrated circuits |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9690896B2 (en) | 2015-04-09 | 2017-06-27 | Samsung Electronics Co., Ltd. | Method for manufacturing a semiconductor device and semiconductor device manufactured by the same |
| US9698056B2 (en) | 2015-04-09 | 2017-07-04 | Samsung Electronics., Ltd. | Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same |
| US9773772B2 (en) | 2015-04-09 | 2017-09-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US10026688B2 (en) | 2015-04-09 | 2018-07-17 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US10204920B2 (en) | 2015-04-09 | 2019-02-12 | Samsung Electronics Co., Ltd. | Semiconductor device including polygon-shaped standard cell |
| US10332798B2 (en) | 2015-04-09 | 2019-06-25 | Samsung Electronics Co., Ltd. | Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same |
| US11043428B2 (en) | 2015-04-09 | 2021-06-22 | Samsung Electronics Co., Ltd. | Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same |
| USRE49545E1 (en) | 2015-04-09 | 2023-06-06 | Samsung Electronics Co., Ltd. | Semiconductor device including polygon-shaped standard cell |
Also Published As
| Publication number | Publication date |
|---|---|
| US6594800B2 (en) | 2003-07-15 |
| US20010018756A1 (en) | 2001-08-30 |
| US6725432B2 (en) | 2004-04-20 |
| US6701504B2 (en) | 2004-03-02 |
| EP1145159A2 (en) | 2001-10-17 |
| US6631470B2 (en) | 2003-10-07 |
| US6629293B2 (en) | 2003-09-30 |
| US6574778B2 (en) | 2003-06-03 |
| HUP0301274A2 (en) | 2003-08-28 |
| US6269467B1 (en) | 2001-07-31 |
| IL142279A0 (en) | 2002-03-10 |
| US20030115564A1 (en) | 2003-06-19 |
| EP1145159A3 (en) | 2002-07-10 |
| CA2345648A1 (en) | 2000-04-06 |
| KR20010085867A (ko) | 2001-09-07 |
| JP2002526908A (ja) | 2002-08-20 |
| CN1376283A (zh) | 2002-10-23 |
| US20010025369A1 (en) | 2001-09-27 |
| US6698002B2 (en) | 2004-02-24 |
| BR9914200A (pt) | 2002-01-22 |
| US20020166098A1 (en) | 2002-11-07 |
| PL350155A1 (en) | 2002-11-18 |
| EE200100189A (et) | 2002-08-15 |
| US20010042237A1 (en) | 2001-11-15 |
| WO2000019343A3 (en) | 2002-04-25 |
| US6694501B2 (en) | 2004-02-17 |
| US20020016952A1 (en) | 2002-02-07 |
| WO2000019343A2 (en) | 2000-04-06 |
| CN1331079C (zh) | 2007-08-08 |
| US20010039641A1 (en) | 2001-11-08 |
| US20010016933A1 (en) | 2001-08-23 |
| AU1100500A (en) | 2000-04-17 |
| US6567957B1 (en) | 2003-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100846089B1 (ko) | 설계 블록들 사이에 다수의 글루 로직 엘리먼트들을 분배하는 방법 및 글루 로직 분배 효율을 증가시키는 방법 | |
| CN100507923C (zh) | 带有可编程组件的基于块的设计方法 | |
| US8020124B2 (en) | Various methods and apparatuses for cycle accurate C-models of components | |
| US5870308A (en) | Method and system for creating and validating low-level description of electronic design | |
| Bergamaschi et al. | Designing systems-on-chip using cores | |
| US20070276645A1 (en) | Power modelling in circuit designs | |
| US20130179142A1 (en) | Distributed parallel simulation method and recording medium for storing the method | |
| EP1129483A1 (de) | Dram-zellenanordnung und verfahren zu deren herstellung | |
| Engel et al. | Design methodology for IBM ASIC products | |
| US7979262B1 (en) | Method for verifying connectivity of electrical circuit components | |
| Egolf | Virtual prototyping of embedded digital systems: hardware/software codesign, integration, and test | |
| Sweeney | Hardware Design Methodologies Hardware Design Methodologies | |
| Daga et al. | Interface timing verification drives system design | |
| Proctor | by JJ Engel TS Guzowski A. Hunt LD Pickup | |
| Coverage-Driven | verificationavenue |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| A201 | Request for examination | ||
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U12-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-5-5-R10-R18-oth-X000 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20120625 Year of fee payment: 5 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
|
| FPAY | Annual fee payment |
Payment date: 20130625 Year of fee payment: 6 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20140709 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20140709 |