IL156634A0 - Method to evaluate and improve the testability of electronic products - Google Patents
Method to evaluate and improve the testability of electronic productsInfo
- Publication number
- IL156634A0 IL156634A0 IL15663403A IL15663403A IL156634A0 IL 156634 A0 IL156634 A0 IL 156634A0 IL 15663403 A IL15663403 A IL 15663403A IL 15663403 A IL15663403 A IL 15663403A IL 156634 A0 IL156634 A0 IL 156634A0
- Authority
- IL
- Israel
- Prior art keywords
- testability
- evaluate
- improve
- electronic products
- products
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31707—Test strategies
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IL15663403A IL156634A0 (en) | 2003-06-25 | 2003-06-25 | Method to evaluate and improve the testability of electronic products |
PCT/IL2004/000560 WO2004114050A2 (en) | 2003-06-25 | 2004-06-23 | Method to evaluate and improve the testability of electronic products |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IL15663403A IL156634A0 (en) | 2003-06-25 | 2003-06-25 | Method to evaluate and improve the testability of electronic products |
Publications (1)
Publication Number | Publication Date |
---|---|
IL156634A0 true IL156634A0 (en) | 2004-01-04 |
Family
ID=32587672
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL15663403A IL156634A0 (en) | 2003-06-25 | 2003-06-25 | Method to evaluate and improve the testability of electronic products |
Country Status (2)
Country | Link |
---|---|
IL (1) | IL156634A0 (en) |
WO (1) | WO2004114050A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104504386B (en) * | 2014-12-08 | 2017-12-01 | 深圳市浦洛电子科技有限公司 | A kind of modularization AOI localization methods, system and burning IC equipment |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US544391A (en) * | 1895-08-13 | Electric-railway conduit system | ||
US4779273A (en) * | 1984-06-14 | 1988-10-18 | Data General Corporation | Apparatus for self-testing a digital logic circuit |
US5027355A (en) * | 1989-04-14 | 1991-06-25 | Control Data Corporation | Logic circuit and design method for improved testability |
BR9914200A (en) * | 1998-09-30 | 2002-01-22 | Cadence Design Systems Inc | Methods for designing a circuit system, for expanding an existing methodology for assessing the feasibility of a circuit design, for performing a feasibility assessment for a circuit design, for refining a first decision rule for a circuit design, to form a second decision rule for a circuit design, for organizing a designer's experience data for a plurality of pre-designed circuit blocks, for increasing glue logic distribution efficiency and for distributing a plurality of logic elements of glue between design blocks and distribute glue logic for execution in an integrated circuit device design scheme, to convert a circuit block-specific interface, to select a circuit collector, to design a device that incorporates the enable a device test to verify the correct operation of a and to develop a behavioral test bench, collar interface and interface system |
US6532571B1 (en) * | 2000-01-21 | 2003-03-11 | International Business Machines Corporation | Method to improve a testability analysis of a hierarchical design |
-
2003
- 2003-06-25 IL IL15663403A patent/IL156634A0/en unknown
-
2004
- 2004-06-23 WO PCT/IL2004/000560 patent/WO2004114050A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2004114050A3 (en) | 2005-11-03 |
WO2004114050A2 (en) | 2004-12-29 |
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