DE60204556D1 - Taktsignalgenerator mit niedrigem jitter für ein test-system - Google Patents

Taktsignalgenerator mit niedrigem jitter für ein test-system

Info

Publication number
DE60204556D1
DE60204556D1 DE60204556T DE60204556T DE60204556D1 DE 60204556 D1 DE60204556 D1 DE 60204556D1 DE 60204556 T DE60204556 T DE 60204556T DE 60204556 T DE60204556 T DE 60204556T DE 60204556 D1 DE60204556 D1 DE 60204556D1
Authority
DE
Germany
Prior art keywords
test
data
test system
light generator
associating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60204556T
Other languages
English (en)
Inventor
Ricca Paolo Dalla
G West
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NPTest Inc
Original Assignee
NPTest Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NPTest Inc filed Critical NPTest Inc
Application granted granted Critical
Publication of DE60204556D1 publication Critical patent/DE60204556D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31708Analysis of signal quality
    • G01R31/31709Jitter measurements; Jitter generators
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922Timing generation or clock distribution
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/3193Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937Timing aspects, e.g. measuring propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0401Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
DE60204556T 2001-03-20 2002-03-19 Taktsignalgenerator mit niedrigem jitter für ein test-system Expired - Lifetime DE60204556D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US27767501P 2001-03-20 2001-03-20
US27779501P 2001-03-21 2001-03-21
PCT/US2002/008627 WO2002075337A2 (en) 2001-03-20 2002-03-19 Low-jitter clock for test system

Publications (1)

Publication Number Publication Date
DE60204556D1 true DE60204556D1 (de) 2005-07-14

Family

ID=26958642

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60204556T Expired - Lifetime DE60204556D1 (de) 2001-03-20 2002-03-19 Taktsignalgenerator mit niedrigem jitter für ein test-system

Country Status (7)

Country Link
US (2) US7143326B2 (de)
EP (2) EP1377841B1 (de)
CN (1) CN1527948A (de)
AU (2) AU2002245706A1 (de)
DE (1) DE60204556D1 (de)
TW (2) TWI234001B (de)
WO (2) WO2002075336A2 (de)

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US7313739B2 (en) * 2002-12-31 2007-12-25 Analog Devices, Inc. Method and apparatus for testing embedded cores
US7392442B2 (en) 2003-03-20 2008-06-24 Qualcomm Incorporated Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol
US7184915B2 (en) * 2003-03-20 2007-02-27 Qualcomm, Incorporated Tiered built-in self-test (BIST) architecture for testing distributed memory modules
JP4332392B2 (ja) * 2003-09-12 2009-09-16 株式会社アドバンテスト 試験装置
US7117415B2 (en) * 2004-01-15 2006-10-03 International Business Machines Corporation Automated BIST test pattern sequence generator software system and method
US7246025B2 (en) * 2004-01-28 2007-07-17 Texas Instruments Incorporated Method and apparatus for synchronizing signals in a testing system
KR100594240B1 (ko) * 2004-01-29 2006-06-30 삼성전자주식회사 패널 테스트 패턴을 발생하는 패널 구동 드라이버 및 패널테스트 방법
US6991161B2 (en) * 2004-06-23 2006-01-31 Paul Pazniokas Electronic voting apparatus, system and method
DE602004015646D1 (de) * 2004-06-24 2008-09-18 Verigy Pte Ltd Singapore Taktsynthese pro Stift
US7664166B2 (en) * 2004-12-17 2010-02-16 Rambus Inc. Pleisiochronous repeater system and components thereof
US7337335B2 (en) * 2004-12-21 2008-02-26 Packet Digital Method and apparatus for on-demand power management
US7228446B2 (en) * 2004-12-21 2007-06-05 Packet Digital Method and apparatus for on-demand power management
US7375569B2 (en) * 2005-09-21 2008-05-20 Leco Corporation Last stage synchronizer system
US20070080697A1 (en) * 2005-09-27 2007-04-12 Sony Corporation Semiconductor device tester pin contact resistance measurement
US8542050B2 (en) * 2005-10-28 2013-09-24 Sony Corporation Minimized line skew generator
KR100735920B1 (ko) * 2005-12-28 2007-07-06 삼성전자주식회사 디바이스 테스트 장치 및 방법과, 그 인터페이스 장치
US7516385B2 (en) * 2006-04-28 2009-04-07 Sony Corporation Test semiconductor device in full frequency with half frequency tester
US7449876B2 (en) * 2006-05-03 2008-11-11 Agilent Technologies, Inc. Swept-frequency measurements with improved speed using synthetic instruments
US7809052B2 (en) * 2006-07-27 2010-10-05 Cypress Semiconductor Corporation Test circuit, system, and method for testing one or more circuit components arranged upon a common printed circuit board
US7889824B2 (en) * 2006-09-28 2011-02-15 Intel Corporation System and method for alignment of clock to data
US7577231B2 (en) * 2007-03-16 2009-08-18 International Business Machines Corporation Clock multiplier structure for fixed speed testing of integrated circuits
US7788564B2 (en) * 2007-10-12 2010-08-31 Teradyne, Inc. Adjustable test pattern results latency
US8312299B2 (en) 2008-03-28 2012-11-13 Packet Digital Method and apparatus for dynamic power management control using serial bus management protocols
US7882406B2 (en) * 2008-05-09 2011-02-01 Lsi Corporation Built in test controller with a downloadable testing program
US8156391B2 (en) * 2008-05-27 2012-04-10 Lsi Corporation Data controlling in the MBIST chain architecture
US8046643B2 (en) * 2008-06-09 2011-10-25 Lsi Corporation Transport subsystem for an MBIST chain architecture
JPWO2010026765A1 (ja) * 2008-09-05 2012-02-02 株式会社アドバンテスト 試験装置、及び試験方法
US20110099407A1 (en) * 2009-10-28 2011-04-28 Ati Technologies Ulc Apparatus for High Speed Data Multiplexing in a Processor
CN103116124B (zh) * 2011-11-17 2016-05-18 国民技术股份有限公司 可自校准内部晶振的芯片、晶振校准测试系统及校准方法
WO2015081980A1 (en) * 2013-12-02 2015-06-11 Advantest Corporation Instruction provider and method for providing a sequence of instructions, test processor and method for providing a device under test
GB2506825B (en) 2014-02-12 2014-10-15 Ultrasoc Technologies Ltd Functional testing of an integrated circuit chip
US9268597B2 (en) * 2014-04-01 2016-02-23 Google Inc. Incremental parallel processing of data
CN106855608B (zh) * 2015-12-09 2023-11-14 深圳市盛德金科技有限公司 双时钟测试电路

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US5270643A (en) * 1990-11-28 1993-12-14 Schlumberger Technologies Pulsed laser photoemission electron-beam probe
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US5491673A (en) * 1994-06-02 1996-02-13 Advantest Corporation Timing signal generation circuit
US5471176A (en) * 1994-06-07 1995-11-28 Quantum Corporation Glitchless frequency-adjustable ring oscillator
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US6266750B1 (en) * 1999-01-15 2001-07-24 Advanced Memory International, Inc. Variable length pipeline with parallel functional units

Also Published As

Publication number Publication date
WO2002075336A9 (en) 2004-02-12
US20030005360A1 (en) 2003-01-02
TWI234001B (en) 2005-06-11
CN1527948A (zh) 2004-09-08
US7143326B2 (en) 2006-11-28
TWI243247B (en) 2005-11-11
WO2002075337A3 (en) 2003-10-23
AU2002255849A1 (en) 2002-10-03
EP1377840A2 (de) 2004-01-07
US20020188902A1 (en) 2002-12-12
WO2002075336A3 (en) 2003-11-06
WO2002075337A2 (en) 2002-09-26
WO2002075336A2 (en) 2002-09-26
US7093177B2 (en) 2006-08-15
EP1377841A2 (de) 2004-01-07
EP1377841B1 (de) 2005-06-08
AU2002245706A1 (en) 2002-10-03

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Legal Events

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