DE602004015646D1 - Taktsynthese pro Stift - Google Patents

Taktsynthese pro Stift

Info

Publication number
DE602004015646D1
DE602004015646D1 DE602004015646T DE602004015646T DE602004015646D1 DE 602004015646 D1 DE602004015646 D1 DE 602004015646D1 DE 602004015646 T DE602004015646 T DE 602004015646T DE 602004015646 T DE602004015646 T DE 602004015646T DE 602004015646 D1 DE602004015646 D1 DE 602004015646D1
Authority
DE
Germany
Prior art keywords
per pin
clock synthesis
synthesis per
clock
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004015646T
Other languages
English (en)
Inventor
Jochen Rivoir
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verigy Singapore Pte Ltd
Original Assignee
Verigy Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verigy Singapore Pte Ltd filed Critical Verigy Singapore Pte Ltd
Publication of DE602004015646D1 publication Critical patent/DE602004015646D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/31709—Jitter measurements; Jitter generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE602004015646T 2004-06-24 2004-06-24 Taktsynthese pro Stift Active DE602004015646D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04102924A EP1610137B1 (de) 2004-06-24 2004-06-24 Taktsynthese pro Stift

Publications (1)

Publication Number Publication Date
DE602004015646D1 true DE602004015646D1 (de) 2008-09-18

Family

ID=34929240

Family Applications (2)

Application Number Title Priority Date Filing Date
DE602004015646T Active DE602004015646D1 (de) 2004-06-24 2004-06-24 Taktsynthese pro Stift
DE602004021178T Active DE602004021178D1 (de) 2004-06-24 2004-06-24 Taktsynthese pro Stift

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE602004021178T Active DE602004021178D1 (de) 2004-06-24 2004-06-24 Taktsynthese pro Stift

Country Status (6)

Country Link
US (2) US7512858B2 (de)
EP (3) EP1610137B1 (de)
JP (2) JP2008503735A (de)
CN (1) CN1977178A (de)
DE (2) DE602004015646D1 (de)
WO (1) WO2006000252A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7454681B2 (en) * 2004-11-22 2008-11-18 Teradyne, Inc. Automatic test system with synchronized instruments
US7319936B2 (en) * 2004-11-22 2008-01-15 Teradyne, Inc. Instrument with interface for synchronization in automatic test equipment
US7584395B2 (en) * 2006-04-07 2009-09-01 Verigy (Singapore) Pte. Ltd. Systems, methods and apparatus for synthesizing state events for a test data stream
US7449876B2 (en) * 2006-05-03 2008-11-11 Agilent Technologies, Inc. Swept-frequency measurements with improved speed using synthetic instruments
US7623984B2 (en) * 2007-03-23 2009-11-24 Advantest Corporation Test apparatus and electronic device
JP4856007B2 (ja) 2007-05-29 2012-01-18 株式会社アドバンテスト 波形発生装置、設定周期補正方法及び半導体試験装置
CN101471816B (zh) * 2007-12-24 2012-12-12 瑞昱半导体股份有限公司 用来产生抖动时钟信号的抖动产生器
US9274911B2 (en) * 2013-02-21 2016-03-01 Advantest Corporation Using shared pins in a concurrent test execution environment
US9898565B2 (en) 2015-11-25 2018-02-20 Synopsys, Inc. Clock jitter emulation
JP6683515B2 (ja) * 2016-03-23 2020-04-22 株式会社メガチップス 信号生成装置及びレギュレータの出力電圧の変動抑制方法
US10989758B2 (en) * 2018-09-21 2021-04-27 Aem Singapore Pte. Ltd. System and method for temporal signal measurement of device under test (DUT) and method of forming system
US11237587B1 (en) * 2020-12-14 2022-02-01 Qualcomm Incorporated On-chip clock controller (OCC) manager based turbo capture clocking

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2146205B (en) * 1983-09-03 1987-06-24 Marconi Instruments Ltd Jitter circuits assessing jitter performance
JP2609284B2 (ja) * 1988-05-10 1997-05-14 株式会社日立製作所 分散形タイミング信号発生装置
EP0541839B1 (de) * 1991-11-11 1993-07-28 Hewlett-Packard GmbH Einrichtung zur Erzeugung von Testsignalen
DE4305442C2 (de) * 1993-02-23 1999-08-05 Hewlett Packard Gmbh Verfahren und Vorrichtung zum Erzeugen eines Testvektors
GB9313020D0 (en) * 1993-06-24 1993-08-11 Madge Networks Ltd Jitter monitoring
JP3866781B2 (ja) * 1994-05-26 2007-01-10 セイコーエプソン株式会社 消費電力を効率化した情報処理装置
US6469493B1 (en) * 1995-08-01 2002-10-22 Teradyne, Inc. Low cost CMOS tester with edge rate compensation
FI105511B (fi) * 1996-10-29 2000-08-31 Nokia Networks Oy Menetelmä usean signaalin yhdistämiseksi ja tukiasema
DE19650839C2 (de) * 1996-11-29 2000-06-08 Tektronix Inc Durchgangsmodulator zum Verjittern von Signalen
DE69700149T2 (de) 1997-05-22 1999-07-01 Hewlett Packard Co Dekompressionsschaltkreis
EP0886214B1 (de) 1997-05-30 1999-10-20 Hewlett-Packard Company Mehrkanalanordnung mit einem unabhängigen Taktsignal pro Kanal
US5898325A (en) * 1997-07-17 1999-04-27 Analog Devices, Inc. Dual tunable direct digital synthesizer with a frequency programmable clock and method of tuning
JPH1138100A (ja) * 1997-07-18 1999-02-12 Advantest Corp 半導体試験装置
DE69700328T2 (de) 1997-09-13 1999-11-04 Hewlett Packard Co Ausgleich von Latenzzeit in einem Speicher
DE69700327T2 (de) 1997-09-13 1999-11-04 Hewlett Packard Co Optimierte Speicherorganisation in einer Mehrkanalcomputerarchitektur
US6188253B1 (en) * 1998-10-07 2001-02-13 Robert Bruce Gage Analog clock module
US6175939B1 (en) * 1999-03-30 2001-01-16 Credence Systems Corporation Integrated circuit testing device with dual purpose analog and digital channels
US6560296B1 (en) * 1999-05-04 2003-05-06 Lucent Technologies Inc. Method and apparatus for modulating digital data
US6204694B1 (en) * 1999-05-21 2001-03-20 Logicvision, Inc. Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals
US6553529B1 (en) * 1999-07-23 2003-04-22 Teradyne, Inc. Low cost timing system for highly accurate multi-modal semiconductor testing
JP3364206B2 (ja) * 1999-12-13 2003-01-08 松下電器産業株式会社 周波数シンセサイザ装置、通信装置、周波数変調装置及び周波数変調方法
US6445208B1 (en) * 2000-04-06 2002-09-03 Advantest Corp. Power source current measurement unit for semiconductor test system
DE60001254T2 (de) 2000-06-16 2003-07-10 Agilent Technologies Inc Testgerät für integrierte Schaltungen mit Multiportprüffunktionalität
AU2002255849A1 (en) * 2001-03-20 2002-10-03 Nptest, Inc. Low-jitter clock for test system
JP2003057318A (ja) * 2001-08-10 2003-02-26 Advantest Corp 半導体試験装置
US6836852B2 (en) * 2001-10-29 2004-12-28 Agilent Technologies, Inc. Method for synchronizing multiple serial data streams using a plurality of clock signals
US6976183B2 (en) * 2001-11-09 2005-12-13 Teradyne, Inc. Clock architecture for a frequency-based tester
JP2003156543A (ja) * 2001-11-20 2003-05-30 Advantest Corp 半導体試験装置
JP4567974B2 (ja) * 2002-01-18 2010-10-27 株式会社アドバンテスト 試験装置
US7823128B2 (en) * 2004-04-19 2010-10-26 Verigy (Singapore) Pte. Ltd. Apparatus, system and/or method for combining multiple tests to a single test in a multiple independent port test environment
US7315574B2 (en) * 2004-05-03 2008-01-01 Dft Microsystems, Inc. System and method for generating a jittered test signal

Also Published As

Publication number Publication date
JP2006010695A (ja) 2006-01-12
EP1610137B1 (de) 2009-05-20
US20070126414A1 (en) 2007-06-07
WO2006000252A1 (en) 2006-01-05
DE602004021178D1 (de) 2009-07-02
EP1752779A2 (de) 2007-02-14
JP2008503735A (ja) 2008-02-07
CN1977178A (zh) 2007-06-06
US7512858B2 (en) 2009-03-31
EP1759220A1 (de) 2007-03-07
EP1752779B1 (de) 2008-08-06
EP1752779A3 (de) 2007-02-21
EP1610137A1 (de) 2005-12-28
US20050289427A1 (en) 2005-12-29

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