DE69700328T2 - Ausgleich von Latenzzeit in einem Speicher - Google Patents
Ausgleich von Latenzzeit in einem SpeicherInfo
- Publication number
- DE69700328T2 DE69700328T2 DE69700328T DE69700328T DE69700328T2 DE 69700328 T2 DE69700328 T2 DE 69700328T2 DE 69700328 T DE69700328 T DE 69700328T DE 69700328 T DE69700328 T DE 69700328T DE 69700328 T2 DE69700328 T2 DE 69700328T2
- Authority
- DE
- Germany
- Prior art keywords
- latency
- compensate
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
- G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97115982A EP0864977B1 (de) | 1997-09-13 | 1997-09-13 | Ausgleich von Latenzzeit in einem Speicher |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69700328D1 DE69700328D1 (de) | 1999-08-19 |
DE69700328T2 true DE69700328T2 (de) | 1999-11-04 |
Family
ID=8227349
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69700328T Expired - Fee Related DE69700328T2 (de) | 1997-09-13 | 1997-09-13 | Ausgleich von Latenzzeit in einem Speicher |
Country Status (4)
Country | Link |
---|---|
US (1) | US6351793B2 (de) |
EP (1) | EP0864977B1 (de) |
JP (1) | JPH11134242A (de) |
DE (1) | DE69700328T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2829253A1 (fr) * | 2001-08-31 | 2003-03-07 | Koninkl Philips Electronics Nv | Controle d'acces dynamique d'une fonction a ressource collective |
DE10159165B4 (de) | 2001-12-03 | 2007-02-08 | Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto | Vorrichtung zum Messen und/oder Kalibrieren eines Testkopfes |
EP1255386B1 (de) | 2001-12-05 | 2007-10-24 | Agilent Technologies, Inc. | Leitungsentzerrer zur Kompensation von Droop-Effekten |
DE60300141T2 (de) | 2003-02-25 | 2005-11-03 | Agilent Technologies, Inc., Palo Alto | Aufspüren eines Signalübergangs |
US7104346B2 (en) * | 2003-03-25 | 2006-09-12 | Schaffner Walter E | Power wheelchair |
DE60308844T2 (de) | 2003-06-17 | 2007-03-01 | Agilent Technologies, Inc., Palo Alto | Sigma-Delta-Modulator mit Pulsbreitenmodulations-Ausgang |
EP1600784A1 (de) | 2004-05-03 | 2005-11-30 | Agilent Technologies, Inc. | Serielle/parallele Schnittstelle für einen Tester für integrierte Schaltkreise |
DE602004015646D1 (de) | 2004-06-24 | 2008-09-18 | Verigy Pte Ltd Singapore | Taktsynthese pro Stift |
DE602004017440D1 (de) | 2004-06-24 | 2008-12-11 | Verigy Pte Ltd Singapore | Schnelle Synchronisierung einem Anzahl von digitale Takten |
DE602004022878D1 (de) | 2004-07-07 | 2009-10-08 | Verigy Pte Ltd Singapore | Auswertung eines ausgangssignals eines gerade geprüften bausteins |
DE602004015276D1 (de) | 2004-08-06 | 2008-09-04 | Verigy Pte Ltd Singapore | Verbesserte Analogsignalerzeugung mittels eines Delta-Sigma Modulators |
WO2006092173A1 (en) | 2005-03-02 | 2006-09-08 | Agilent Technologies, Inc. | Analog signal test using a-priori information |
ATE405846T1 (de) | 2005-03-11 | 2008-09-15 | Verigy Pte Ltd Singapore | Fehlererkennung in komprimierten daten |
US8068537B2 (en) | 2005-04-29 | 2011-11-29 | Verigy (Singapore) Pte. Ltd. | Communication circuit for a bi-directional data transmission |
US8838406B2 (en) | 2008-11-11 | 2014-09-16 | Advantest (Singapore) Pte Ltd | Re-configurable test circuit, method for operating an automated test equipment, apparatus, method and computer program for setting up an automated test equipment |
JP5873275B2 (ja) * | 2011-09-12 | 2016-03-01 | キヤノン株式会社 | 描画装置及び物品の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5847741B2 (ja) * | 1978-03-29 | 1983-10-24 | 日本電信電話株式会社 | パタ−ン発生器 |
CA1251575A (en) * | 1985-12-18 | 1989-03-21 | A. Keith Jeffrey | Automatic test system having a "true tester-per-pin" architecture |
US5317718A (en) * | 1990-03-27 | 1994-05-31 | Digital Equipment Corporation | Data processing system and method with prefetch buffers |
JPH07253922A (ja) * | 1994-03-14 | 1995-10-03 | Texas Instr Japan Ltd | アドレス生成回路 |
US5890219A (en) * | 1996-11-27 | 1999-03-30 | Emc Corporation | Redundant writing of data to cached storage system |
US5890207A (en) * | 1996-11-27 | 1999-03-30 | Emc Corporation | High performance integrated cached storage device |
US6112266A (en) * | 1998-01-22 | 2000-08-29 | Pc-Tel, Inc. | Host signal processing modem using a software circular buffer in system memory and direct transfers of samples to maintain a communication signal |
-
1997
- 1997-09-13 DE DE69700328T patent/DE69700328T2/de not_active Expired - Fee Related
- 1997-09-13 EP EP97115982A patent/EP0864977B1/de not_active Expired - Lifetime
-
1998
- 1998-08-20 US US09/137,439 patent/US6351793B2/en not_active Expired - Lifetime
- 1998-09-02 JP JP10248261A patent/JPH11134242A/ja not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
JPH11134242A (ja) | 1999-05-21 |
EP0864977A1 (de) | 1998-09-16 |
US6351793B2 (en) | 2002-02-26 |
US20010013092A1 (en) | 2001-08-09 |
EP0864977B1 (de) | 1999-07-14 |
DE69700328D1 (de) | 1999-08-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: SCHOPPE, ZIMMERMANN, STOECKELER & ZINKLER, 82049 PU |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: VERIGY (SINGAPORE) PTE. LTD., SINGAPORE, SG |
|
8339 | Ceased/non-payment of the annual fee |