DE69811421T2 - Fehlertolerante Speicher - Google Patents

Fehlertolerante Speicher

Info

Publication number
DE69811421T2
DE69811421T2 DE69811421T DE69811421T DE69811421T2 DE 69811421 T2 DE69811421 T2 DE 69811421T2 DE 69811421 T DE69811421 T DE 69811421T DE 69811421 T DE69811421 T DE 69811421T DE 69811421 T2 DE69811421 T2 DE 69811421T2
Authority
DE
Germany
Prior art keywords
fault
tolerant memory
tolerant
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69811421T
Other languages
English (en)
Other versions
DE69811421D1 (de
Inventor
Toshiaki Kirihata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/825,949 external-priority patent/US5831914A/en
Priority claimed from US08/825,948 external-priority patent/US5831913A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69811421D1 publication Critical patent/DE69811421D1/de
Application granted granted Critical
Publication of DE69811421T2 publication Critical patent/DE69811421T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/804—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout to prevent clustered faults
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69811421T 1997-03-31 1998-03-23 Fehlertolerante Speicher Expired - Fee Related DE69811421T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/825,949 US5831914A (en) 1997-03-31 1997-03-31 Variable size redundancy replacement architecture to make a memory fault-tolerant
US08/825,948 US5831913A (en) 1997-03-31 1997-03-31 Method of making a memory fault-tolerant using a variable size redundancy replacement configuration

Publications (2)

Publication Number Publication Date
DE69811421D1 DE69811421D1 (de) 2003-03-27
DE69811421T2 true DE69811421T2 (de) 2003-10-23

Family

ID=27124960

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69811421T Expired - Fee Related DE69811421T2 (de) 1997-03-31 1998-03-23 Fehlertolerante Speicher

Country Status (4)

Country Link
EP (1) EP0869440B1 (de)
KR (1) KR100295928B1 (de)
DE (1) DE69811421T2 (de)
TW (1) TW360822B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009505171A (ja) * 2005-06-27 2009-02-05 イコア コーポレイション ステートフルなトランザクション指向のシステムを指定する方法、及び半導体デバイスの構造的に構成可能なイン・メモリ処理へ柔軟にマッピングする装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4639897A (en) * 1983-08-31 1987-01-27 Rca Corporation Priority encoded spare element decoder
DE69129882T2 (de) * 1990-06-19 1999-03-04 Texas Instruments Inc Assoziatives DRAM-Redundanzschema mit variabler Satzgrösse
EP0529330A3 (en) * 1991-07-31 1993-09-29 Texas Instruments Incorporated System with laser link decoder for dram redundancy scheme

Also Published As

Publication number Publication date
KR19980079738A (ko) 1998-11-25
EP0869440A1 (de) 1998-10-07
EP0869440B1 (de) 2003-02-19
DE69811421D1 (de) 2003-03-27
KR100295928B1 (ko) 2001-08-07
TW360822B (en) 1999-06-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee