DE69521656T2 - Dynamischer Speicher - Google Patents

Dynamischer Speicher

Info

Publication number
DE69521656T2
DE69521656T2 DE69521656T DE69521656T DE69521656T2 DE 69521656 T2 DE69521656 T2 DE 69521656T2 DE 69521656 T DE69521656 T DE 69521656T DE 69521656 T DE69521656 T DE 69521656T DE 69521656 T2 DE69521656 T2 DE 69521656T2
Authority
DE
Germany
Prior art keywords
dynamic memory
dynamic
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69521656T
Other languages
English (en)
Other versions
DE69521656D1 (de
Inventor
Kiyofumi Sakurai
Satoru Takase
Masaki Ogihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69521656D1 publication Critical patent/DE69521656D1/de
Publication of DE69521656T2 publication Critical patent/DE69521656T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69521656T 1994-09-29 1995-09-27 Dynamischer Speicher Expired - Lifetime DE69521656T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6234743A JPH08102187A (ja) 1994-09-29 1994-09-29 ダイナミック型メモリ

Publications (2)

Publication Number Publication Date
DE69521656D1 DE69521656D1 (de) 2001-08-16
DE69521656T2 true DE69521656T2 (de) 2002-05-08

Family

ID=16975667

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69521656T Expired - Lifetime DE69521656T2 (de) 1994-09-29 1995-09-27 Dynamischer Speicher

Country Status (7)

Country Link
US (1) US5642326A (de)
EP (1) EP0704850B1 (de)
JP (1) JPH08102187A (de)
KR (1) KR0184092B1 (de)
CN (1) CN1087472C (de)
DE (1) DE69521656T2 (de)
TW (1) TW303051U (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6122710A (en) * 1998-02-17 2000-09-19 International Business Machines Corporation Dynamic word line driver for cache
JP3786521B2 (ja) * 1998-07-01 2006-06-14 株式会社日立製作所 半導体集積回路及びデータ処理システム
JP3298536B2 (ja) * 1999-01-29 2002-07-02 日本電気株式会社 半導体記憶装置
KR20010010053A (ko) * 1999-07-15 2001-02-05 김영환 화면 소거시 화면 흔들림 방지 회로
KR100869870B1 (ko) 2000-07-07 2008-11-24 모사이드 테크놀로지스, 인코포레이티드 메모리 소자에서의 읽기 명령 수행 방법 및 ｄｒａｍ액세스 방법
US6414898B1 (en) * 2001-01-16 2002-07-02 Taiwan Semiconductor Manufacturing Company Method to reduce peak current for RAS cycle sensing in DRAM using non-multiplexed row and column addresses to avoid damage to battery
JP4544808B2 (ja) * 2002-04-09 2010-09-15 富士通セミコンダクター株式会社 半導体記憶装置の制御方法、および半導体記憶装置
US7200050B2 (en) * 2003-05-26 2007-04-03 Semiconductor Energy Laboratory Co., Ltd. Memory unit and semiconductor device
KR100535131B1 (ko) * 2003-05-30 2005-12-07 주식회사 하이닉스반도체 페이지 모드에서의 메모리 소자 리드 방법 및 이를 이용한로우 디코더 제어회로
JP4769548B2 (ja) 2005-11-04 2011-09-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置
KR100780947B1 (ko) * 2006-02-24 2007-12-03 삼성전자주식회사 Ｄｒａｍ 구조의 메모리를 구비하는 디스플레이용 구동집적회로 및 디스플레이 구동방법
JP2008135116A (ja) * 2006-11-28 2008-06-12 Toshiba Corp 半導体記憶装置
JP4675362B2 (ja) * 2007-08-10 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置
JP6287043B2 (ja) 2013-10-17 2018-03-07 富士通セミコンダクター株式会社 半導体記憶装置
WO2022246644A1 (en) * 2021-05-25 2022-12-01 Citrix Systems, Inc. Data transfer across storage tiers

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969706A (en) * 1974-10-08 1976-07-13 Mostek Corporation Dynamic random access memory misfet integrated circuit
JPS5250867A (en) * 1975-10-23 1977-04-23 Iony Kk Wind wheel device for grain selector
JPS6052679A (ja) * 1983-08-26 1985-03-25 Kanegafuchi Chem Ind Co Ltd 耐候性のすぐれた艶消壁装材用シ−ト
JPS6124091A (ja) * 1984-07-12 1986-02-01 Nec Corp メモリ回路
US5031150A (en) * 1988-08-26 1991-07-09 Kabushiki Kaisha Toshiba Control circuit for a semiconductor memory device and semiconductor memory system
JP2962080B2 (ja) * 1991-12-27 1999-10-12 日本電気株式会社 ランダムアクセスメモリ
JP2833359B2 (ja) * 1992-07-29 1998-12-09 日本電気株式会社 Ｄｒａｍ回路

Also Published As

Publication number Publication date
CN1087472C (zh) 2002-07-10
JPH08102187A (ja) 1996-04-16
KR0184092B1 (ko) 1999-04-15
KR960012009A (ko) 1996-04-20
TW303051U (en) 1997-04-11
US5642326A (en) 1997-06-24
EP0704850A2 (de) 1996-04-03
EP0704850B1 (de) 2001-07-11
DE69521656D1 (de) 2001-08-16
CN1142672A (zh) 1997-02-12
EP0704850A3 (de) 1999-07-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition