DE69840995D1 - Speicher mit mehreren Banken - Google Patents

Speicher mit mehreren Banken

Info

Publication number
DE69840995D1
DE69840995D1 DE69840995T DE69840995T DE69840995D1 DE 69840995 D1 DE69840995 D1 DE 69840995D1 DE 69840995 T DE69840995 T DE 69840995T DE 69840995 T DE69840995 T DE 69840995T DE 69840995 D1 DE69840995 D1 DE 69840995D1
Authority
DE
Germany
Prior art keywords
memory
several banks
banks
several
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69840995T
Other languages
English (en)
Inventor
Patrick J Kawamura
Harvey A Vargas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69840995D1 publication Critical patent/DE69840995D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69840995T 1997-12-24 1998-12-23 Speicher mit mehreren Banken Expired - Lifetime DE69840995D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/998,338 US5896310A (en) 1997-12-24 1997-12-24 Multiple bank memory with over-the-array conductors programmable for providing either column factor or y-decoder power connectivity

Publications (1)

Publication Number Publication Date
DE69840995D1 true DE69840995D1 (de) 2009-09-03

Family

ID=25545074

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69840995T Expired - Lifetime DE69840995D1 (de) 1997-12-24 1998-12-23 Speicher mit mehreren Banken

Country Status (5)

Country Link
US (1) US5896310A (de)
EP (1) EP0926682B1 (de)
JP (1) JPH11283366A (de)
DE (1) DE69840995D1 (de)
TW (1) TW430810B (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630249B (zh) 2017-03-24 2022-03-04 铠侠股份有限公司 半导体存储装置
JP2018163729A (ja) * 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体記憶装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4739475A (en) * 1983-09-20 1988-04-19 Mensch Jr William D Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability
JP2758504B2 (ja) * 1990-07-06 1998-05-28 松下電器産業株式会社 半導体記憶装置
JPH0562461A (ja) * 1991-04-09 1993-03-12 Mitsubishi Electric Corp 半導体記憶装置
US5155302A (en) * 1991-06-24 1992-10-13 At&T Bell Laboratories Electronic device interconnection techniques
JP2647023B2 (ja) * 1994-10-27 1997-08-27 日本電気株式会社 半導体記憶装置
JP3160480B2 (ja) * 1994-11-10 2001-04-25 株式会社東芝 半導体記憶装置
US5668389A (en) * 1994-12-02 1997-09-16 Intel Corporation Optimized power bus structure
JPH09162305A (ja) * 1995-12-08 1997-06-20 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
US5896310A (en) 1999-04-20
EP0926682A2 (de) 1999-06-30
TW430810B (en) 2001-04-21
EP0926682B1 (de) 2009-07-22
EP0926682A3 (de) 1999-07-21
JPH11283366A (ja) 1999-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition