KR100803643B1 - 집적 회로 패키지의 제조 방법 - Google Patents

집적 회로 패키지의 제조 방법 Download PDF

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Publication number
KR100803643B1
KR100803643B1 KR20010043828A KR20010043828A KR100803643B1 KR 100803643 B1 KR100803643 B1 KR 100803643B1 KR 20010043828 A KR20010043828 A KR 20010043828A KR 20010043828 A KR20010043828 A KR 20010043828A KR 100803643 B1 KR100803643 B1 KR 100803643B1
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KR
South Korea
Prior art keywords
integrated circuit
substrate
conductive layer
dielectric layer
region
Prior art date
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Expired - Lifetime
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KR20010043828A
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English (en)
Korean (ko)
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KR20020009445A (ko
Inventor
콘찰레스
호크주니어도널드어리
Original Assignee
에이저 시스템즈 가디언 코포레이션
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Publication of KR20020009445A publication Critical patent/KR20020009445A/ko
Application granted granted Critical
Publication of KR100803643B1 publication Critical patent/KR100803643B1/ko
Assigned to 에이저 시스템즈 엘엘시 reassignment 에이저 시스템즈 엘엘시 권리의 전부이전등록 Assignors: 에이저 시스템즈 가디언 코포레이션
Assigned to 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 reassignment 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 권리의 전부이전등록 Assignors: 에이저 시스템즈 엘엘시
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/206—Wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
KR20010043828A 2000-07-21 2001-07-20 집적 회로 패키지의 제조 방법 Expired - Lifetime KR100803643B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/621110 2000-07-21
US09/621,110 US6790760B1 (en) 2000-07-21 2000-07-21 Method of manufacturing an integrated circuit package

Publications (2)

Publication Number Publication Date
KR20020009445A KR20020009445A (ko) 2002-02-01
KR100803643B1 true KR100803643B1 (ko) 2008-02-19

Family

ID=24488766

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20010043828A Expired - Lifetime KR100803643B1 (ko) 2000-07-21 2001-07-20 집적 회로 패키지의 제조 방법

Country Status (5)

Country Link
US (1) US6790760B1 (https=)
JP (1) JP2002043458A (https=)
KR (1) KR100803643B1 (https=)
GB (1) GB2370414B (https=)
TW (1) TW546767B (https=)

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US6790760B1 (en) * 2000-07-21 2004-09-14 Agere Systems Inc. Method of manufacturing an integrated circuit package
US6770963B1 (en) * 2001-01-04 2004-08-03 Broadcom Corporation Multi-power ring chip scale package for system level integration
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
US20040145874A1 (en) * 2003-01-23 2004-07-29 Stephane Pinel Method, system, and apparatus for embedding circuits
US7183786B2 (en) * 2003-03-04 2007-02-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Modifying a semiconductor device to provide electrical parameter monitoring
US20040183167A1 (en) * 2003-03-21 2004-09-23 Texas Instruments Incorporated Recessed-bond semiconductor package substrate
US7219242B2 (en) * 2003-03-31 2007-05-15 Intel Corporation Direct plane access power delivery
US6956286B2 (en) * 2003-08-05 2005-10-18 International Business Machines Corporation Integrated circuit package with overlapping bond fingers
JP4703300B2 (ja) * 2005-07-20 2011-06-15 富士通セミコンダクター株式会社 中継基板及び当該中継基板を備えた半導体装置
JP4474431B2 (ja) * 2007-03-26 2010-06-02 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージおよび該製造方法
US8415785B1 (en) 2010-01-27 2013-04-09 Marvell International Ltd. Metal ring techniques and configurations
US9204561B2 (en) * 2012-04-17 2015-12-01 Advanced Flexible Circuits Co., Ltd. Method of manufacturing a structure of via hole of electrical circuit board
US9814142B1 (en) * 2015-06-24 2017-11-07 Automated Assembly Corporation Electronic devices wire bonded to substrate through an adhesive layer and method of making the same
CN111443440B (zh) * 2020-05-09 2025-03-04 菲尼萨光电通讯(上海)有限公司 光器件结构及其制作方法

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JPH06342853A (ja) * 1993-04-06 1994-12-13 Tokuyama Soda Co Ltd 半導体素子用パッケージ
JPH10163635A (ja) * 1996-11-28 1998-06-19 Sony Corp プリント配線板
JPH11176976A (ja) * 1997-12-08 1999-07-02 Sumitomo Metal Smi Electron Devices Inc 電子部品用パッケージの製造方法
JPH11354566A (ja) * 1998-06-08 1999-12-24 Hitachi Ltd 半導体装置およびその製造方法
JP2002043458A (ja) * 2000-07-21 2002-02-08 Agere Systems Guardian Corp 集積回路パッケージの製造方法

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US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
KR950702068A (ko) * 1993-04-06 1995-05-17 쓰지 가오루 반도체 소자용 패키지(package for semiconductor chip)
US5490324A (en) 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
JP2931741B2 (ja) 1993-09-24 1999-08-09 株式会社東芝 半導体装置
JP3094069B2 (ja) * 1993-12-24 2000-10-03 日本特殊陶業株式会社 セラミックパッケージ本体の製造方法
EP1213754A3 (en) * 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
JPH07288385A (ja) 1994-04-19 1995-10-31 Hitachi Chem Co Ltd 多層配線板及びその製造法
US5622588A (en) 1995-02-02 1997-04-22 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
FR2736206B1 (fr) * 1995-06-30 1997-08-08 Commissariat Energie Atomique Procede de realisation d'un substrat d'interconnexion permettant de connecter une puce sur un substrat de reception
JP3292798B2 (ja) * 1995-10-04 2002-06-17 三菱電機株式会社 半導体装置
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US5729047A (en) * 1996-03-25 1998-03-17 Micron Technology, Inc. Method and structure for providing signal isolation and decoupling in an integrated circuit device
US6043559A (en) * 1996-09-09 2000-03-28 Intel Corporation Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
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US6027999A (en) * 1998-09-10 2000-02-22 Chartered Semiconductor Manufacturing, Ltd. Pad definition to achieve highly reflective plate without affecting bondability
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JPH06342853A (ja) * 1993-04-06 1994-12-13 Tokuyama Soda Co Ltd 半導体素子用パッケージ
JPH10163635A (ja) * 1996-11-28 1998-06-19 Sony Corp プリント配線板
JPH11176976A (ja) * 1997-12-08 1999-07-02 Sumitomo Metal Smi Electron Devices Inc 電子部品用パッケージの製造方法
JPH11354566A (ja) * 1998-06-08 1999-12-24 Hitachi Ltd 半導体装置およびその製造方法
JP2002043458A (ja) * 2000-07-21 2002-02-08 Agere Systems Guardian Corp 集積回路パッケージの製造方法
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US6790760B1 (en) * 2000-07-21 2004-09-14 Agere Systems Inc. Method of manufacturing an integrated circuit package

Also Published As

Publication number Publication date
US6790760B1 (en) 2004-09-14
KR20020009445A (ko) 2002-02-01
GB2370414B (en) 2004-10-20
JP2002043458A (ja) 2002-02-08
GB2370414A (en) 2002-06-26
GB0117316D0 (en) 2001-09-05
TW546767B (en) 2003-08-11

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