TW546767B - Methods of manufacturing an integrated circuit package and a substrate adapted to receive an integrated circuit chip - Google Patents

Methods of manufacturing an integrated circuit package and a substrate adapted to receive an integrated circuit chip Download PDF

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Publication number
TW546767B
TW546767B TW90117314A TW90117314A TW546767B TW 546767 B TW546767 B TW 546767B TW 90117314 A TW90117314 A TW 90117314A TW 90117314 A TW90117314 A TW 90117314A TW 546767 B TW546767 B TW 546767B
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TW
Taiwan
Prior art keywords
integrated circuit
dielectric layer
conductive layer
substrate
layer
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Application number
TW90117314A
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English (en)
Inventor
Charles Cohn
Donald Earl Hawk Jr
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Agere Syst Guardian Corp
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Publication of TW546767B publication Critical patent/TW546767B/zh

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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Description

546767
發明領域 本發明一般性地涉及積體電路，更特定言之，本發明涉 及製造積體電路封裝之方法以及製造那些封裝之方法。 由於球柵陣列（BGA)積體電路封裝（此後稱之爲bga封裝: 具有#午多較其他封裝技術爲優的特性，所以積體電路晶片 廣泛地使用此種封裝技術。BGA封裝可在有限的面積中安 裝多引腳的結構。另外，由於BGA封裝的外部端子既粗卫 短，所以較不易受到衝擊損害。除此之外，BGA封裝的接 合銲墊到錫球的跡線長度亦相對較短，此可增進電效能。 圖8是一般的BGA封裝。該BGA封裝包含基板丨及積體電 路晶片3，此基板爲雙面或多層結構，積體電路晶片則是以 黏著劑2黏著於基板1之上表面。金屬導線4使多個形成於 積體電路上表面上之接合銲#3a，與形成於基…上之接 口銲塾7在私氣上互連。基板i的上表面上亦提供出一塑封 仏將該積體電路晶片3及金屬導電4加以膠封。錫球6黏 者於基板1的下表面。；f在人如iv — ^ τ 、 接口却塾7利用形成於基板1中之鍍 通孔8 ’與锡球6連接。 封裝的製造包含以下幾個製程：黏晶製程，以黏著 f’將積體電路晶片3黏著於基板i的上中央部。接著， 銲線製程，以金屬導線4， w 將形成於孩積體電路3上表面上 接A整3a，與形成於基板1上之接合銲塾7予以互連。 m…a 體電路3、金屬導線4以及基板 上表面的-邵份加以膠封’形成塑封區5。錫球6的植球
裝 訂
k -4- 546767 A7 B7 五、發明説明（2 ) 製程，將錫球黏著於基板1的下表面。 雖然BGA封裝有許多優點，但亦有其缺陷。舉個例子， 該多金屬層結構之基板1中將會有大量的通孔，廣佈於電源 環及接地環之間以及各個内平面之間。此造成該等内部的 電源平面及接地平面之導電路徑減少，使電效能退化。於 是，欲發展一種可降低此問題程度之BGA封裝。 發明摘要 本發明係關於積體電路晶片所使用之積體電路封裝（像是 BGA封裝）之製程。本發明所形成之積體電路封裝之基板具 有一個腔洞，曝露出基板内部的導電層，如此，積體電路 可與該内部的導電層直接連接，減少了以鍍通孔從一個導 電層連接至另一個導電層的需要。内部電源平面及接地平 面中因鍍通孔的存在而必須切斷的導電路徑將因此減少， 先前技術所受之電效能退化之苦得以避免或減輕。本發明 可更進一步地容納更多的信號，以及/或者縮減積體電路的 尺寸，以增進電效能。另外，此多接合層之積體電路封裝 可令導線間的距離加寬，此有利於銲線及後續的封膠製程。 舉個例證：該積體電路封裝之基板包含一形成於第一介 電層之上之導電層，以及一形成於該第一導電層之上之第 二介電層。該第二介電層具有一腔洞，曝露出一邵份的第 一導電層。積體電路則位在該第二介電層之上，與該第 一導電層之曝露部份連接。 應了解，以上之一般性敘述以及以下詳細地敘述均止於 示範，本發明不限於此。 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 546767
配合著附圖閱讀以下的詳細說明，將會對本發明有所了 解。必須強調料，根據半導體工業的慣例，目示之各部 份毋須按比例緣製。相反地，各部份的尺寸可依説明之所 需，自由地放大縮小。本說明之圖示包含·· 圖1乃一流程圖，示範説明本發明球栅陣列封裝之程製； 圖2 6乃本發明圖丨製程所製造之球柵陣列基板其於各製 作階段時的簡圖； 圖7是圖5之球柵陣列基板的頂視圖；以及 圖8疋傳統球栅陣列封裝之簡圖。 發明之詳細説明 現參考圖式，其中相同的參考數字代表相同的元件。圖i 之流程圖説明本發明積體電路封裝製程之示範用具體實施 例。以下參照著圖2 - 6，對圖1所示之製程加以説明。 步驟100,提供出一多層基板10(圖2)。製造多層基板1〇 的程序眾所周知。該基板包含絕緣層2〇，22，24及導電層 30, 32, 34, 36。導電層30, 32, 34, 36可以使用標準 的技術予以圖案化。將這些金屬層圖案化以形成從多層基 材10之頂12至底14之互連態勢。導電層30，32，34，36 可以是像銅這樣的金屬，或是其他合適的導電物質。 步驟110，使用標準的方法，於該多層基板1〇中形成像 4 0及4 2 (圖3 )這樣的通孔。該等通孔可以使用譬如，機械 或雷射鑽孔該多層基材10的方式形成。雖然圖中所示僅兩 個通孔40及4*2 ’但該多層基板1〇中之通孔數可以不止於此。 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 546767 A7
接著’步驟1 1 2，將通孔4 〇、4 2以及外導雷屉a 。外導m “ 久卜等電層加以電鍍 卜導弘層包括導電層32及36。電鍍的程序爲：先於 面(包括通孔)上形成一種子層，接著再施以無電極電鍍： 電極電鍍。電鍍材料包括，譬如，銅。步驟114，使用^所 周知之方法，將導電層32及36圖案化。然後，步驟， 對導電層32及36施以銲錫遮罩46及48，決定出導電層” 及3 6的曝露部份及絕緣層2 2的圖案。 接著，步驟120，於絕緣層22中形成一腔洞50(圖5)，曝 露出導電層3 0。使用成型、雷射銑削、電漿蝕刻或其他的 腔洞成形技術均可形成腔洞5 〇。導電層3 〇的曝露使積體電 路的接合導線得以直接地銲至多層基板1 0中至少兩個不同 的接合層上。 一或多個的導電層3 0曝露部份可以形成不同的電源平面 、電源環或電源區。若是做成如此，則積體電路可有多個 接合銲墊互連至該等曝露平面、環或區域。導電層3〇的曝 露部份除了可作電源平面之外，亦可將之形成爲接地平面 。使用此法將可縮減該用以連接電源或接地之通孔的需求 量或甚至不需使用。亦可將部份的曝露導電層3 〇做成包含 一或多個接地平面、電源平面或用以連接信號之組合區域。 步驟130,將導電的導線可接合材料形成於導電層3〇， 32及36所曝露出之導電區域上。該導電材料可包含形成於 鎳上之金。若欲使用此種材料，則應先於導電層30，32及 3 6的曝露部份之上鍍鎳，然後再於鎳上鍍金。 步驟140，裝置完成（圖6)。此包含使用黏著劑70，將積 本紙張尺度適用中國國家標準(CNS) A4规格(210χ 297公釐)
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線 546767 A7 •--------B7 五、發明説明^ ) --- 體電路晶片75連接至多層基板1〇。接合導線8〇形成於積體 電路上之接合銲墊（未顯示）及多層基板1〇上之連接區域及/ 或接合銲塾30a，30b，3 2a，32b之間。該連接區域所指 的是像接合銲塾這樣的導線可藉此直接連至導電層3 〇及3 2 的區域。最後’使用環氧樹脂將該積體電路晶片及接合導 線予以覆塑’並使用傳統的技術將錫球6 5連接至連接銲墊 6〇(形成於導電層36)上。 在此不範具體實施例中，積體電路晶片75乃是形成於遮 罩70區段上（圖6及7)。雖然圖中僅有一條接合導線連接至 接地平面，但接地平面3 2 a及積體電路7 5之間的互連其實 疋可以使用多條接合導線的。因此，該等用以將積體電路 75予以接地之多個通孔就毋須在多層基板1〇中形成。 另外’導電層30之區段30a可以形成一電源平面，電連 接至積體電路晶片7 5。雖然圖中僅有一條接合導線連接至 该電源環3 0 a，但電源環3 〇 a及積體電路7 5之間的互連其 疋可以使用多條接合導線的。該等用以將積體電路7 5與 電源平面30a予以互連之多個通孔就毋須在多層基板1〇>中 形成。或者，區段3 Ob可以形成電源平面。電源平面、接 地平面或其他的導電層區段可以沿著積體電路的一、二、 三或更多側或甚至環繞著整個積體電路，共同形成一連續 的區域。 雖然本發明已以示範具體實施例爲代表加以説明，但本 發明不限於此些具體實施例。舉個例子，雖然上述示範用 之具體實施例包含有四個導電層，不過本發明仍可應用於
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k -8 ·
546767 A7 B7 五、 發明説明（6 ) 三或更多導電層（以及用以分離這些導電層之相關絕緣層） 之基板。除此之外，腔洞的大小範圍可不僅止於一個介電 層，曝露基板的一或多個導電層。另外，信號線、電源或 接地的連結，或這些組合們連結，均可提供於基板的腔洞 之中。於是，所附之專利應建構成包含由習於此藝人士在 不脱離本發明之眞實精神及範圍的情況下所完成之本發明 的其他變化及具體實施例。 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)

Claims (1)

  1. 5 時曝 中文, -利申請案 丨替換本(92年4月) 8 8 8 8 A B c D 々、申請專利範圍 1. 一種製造一積體電路封裝之方法，包含： (a) 形成一基板，該基板具有一第一介電層，具有與 一第二區域隔離之一第一區域並位於該第一介電層之上 之一導電層，以及於該導電層之上之一第二介電層，該 第二介電層具有一腔洞，其中該第一與第二區域曝露於 該腔洞中，且該第一區域以一第三介電層與該第二區域 隔離；以及 (b) 將積體電路之一第一引線互連至該曝露之第一區 域，並將積體電路之一第二引線互連至該曝露之第二區 域。 2. 如申請專利範圍第1項之方法，其中步騾（b)包含： 將一導體連接至形成於該積體電路上之接合銲墊；以 及 將該導體直接地連接至該導電層。 3 .如申請專利範圍第1項之方法，另包含，於該導體層之 曝露部份中，提供出接地平面及電源平面二者之一。 4. 如申請專利範圍第3項之方法，另包含，於該導體層之 曝露部份中，提供至少一個信號線所用的連接。 5. 如申請專利範圍第1項之方法，另包含，於該導體層之 曝露部份中，提供至少一個信號線所用的連接。 6. 如申請專利範圍第1項之方法，另包含，於該積體電路 晶片及該導電層之間，形成多條互連。 7. 一種製造適於承接一積體電路晶片之基板之方法，包含 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 546767 A8 B8 C8 D8 六、申請專利範圍 (a) 於一基板上形成一第一介電層； (b) 於該第一介電層上形成具有與一第二區域絕緣之 一第一區域之一導電層； (c) 於該導電層上形成一第二介電層； (d) 於該第二介電層中形成一腔洞，以曝露該導體層 之第一與第二區域，並將該積體電路晶片之第一引線耦 合至曝露之第一區域，且將該積體電路晶片之第二引線 耦合至曝露之第二區域，該第一區域以一第三介電層與 該第二區域隔離。 8. 如申請專利範圍第7項之方法，其中步騾（a)，（b)及（c )於步騾（d)之前發生。 9. 如申請專利範圍第7項之方法，另包含： 藉由曝露該部份的導電層，為接地平面提供出接觸區 〇 1 0 .如申請專利範圍第7項之方法，另包含： (e) 於基板中形成鍍通孔。 1 1 .如申請專利範圍第10項之方法，其中步騾（e)執行於步 騾（d)之前。 12. —種製造一積體電路封裝之方法，包含： 提供該基板，其中該基板包含： (a) 位於一基板上之一第一介電層； (b) 位於該第一介電層上具有與一第二區域絕緣之一 第一區域之一導電層； (〇位於該導電層上之一第二介電層； -2- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 8 8 8 8 A B c D 546767 々、申請專利範圍 (d) 於該第二介電中曝露該導電層之第一與第二區域 之一腔洞；以及 將一積體電路晶片耦合至該基板，包含： (e) 將該積體電路晶片之一第一引線耦合至該曝露之 第一區域； (f) 將該積體電路晶片之一第二引線耦合至該曝露之 第二區域，該第一區域以一第三介電層與該第二區域隔 離。 1 3 . —種製造適以接受積體電路晶片之基板之方法，包含： (a) 提供一第一介電層； (b) 於該介電層之上提供一第一導電層； (c) 於該第一導電層之上提供一第二介電層； (d) 於該第二介電層之上提供一第二導電層； (e) 於該第二介電層之第一區域中形成一腔洞，曝 露出該第一導電層的一部份。 1 4 .如申請專利範圍第1 3項之方法，其中步騾（d)另包含， 於非該第一區域之區域上，提供該第二導電層。 1 5 .如申請專利範圍第1 3項之方法，其中步騾（d)另包含， 將形成於該第一區域之上之導電層的一部份予以移除。 16. —種製造一積體電路封裝之方法，包含： 提供一基板，其中該基板包含： (a) —第一介電層； (b) 位於該第一介電層上之一第一導電層； (〇位於該第一導電層上之一第二介電層； -3- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 546767 8 8 8 8 A B CD 、申請專利範圍 (d) 位於該第二介電層上之一第二導電層； (e) 於該第二介電中曝露該第一導電層之一部分之 腔洞；以及 將一積體電路晶片耦合至該基板。 17. —種製造積體電路封裝之方法，包含： 於該第一 (a)容納一基板，其具有一第一介電層 介電層之上之導電層，以及一於該導電層之上之第二介 電層，該第二介電層具有一腔洞，曝露出部份的導電層 :以及 (b)將積體電路直接地互連至該腔洞所曝露出之部份 導電層。 4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100803643B1 (ko) * 2000-07-21 2008-02-19 에이저 시스템즈 가디언 코포레이션 집적 회로 패키지의 제조 방법

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770963B1 (en) * 2001-01-04 2004-08-03 Broadcom Corporation Multi-power ring chip scale package for system level integration
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
US20040145874A1 (en) * 2003-01-23 2004-07-29 Stephane Pinel Method, system, and apparatus for embedding circuits
US7183786B2 (en) * 2003-03-04 2007-02-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Modifying a semiconductor device to provide electrical parameter monitoring
US20040183167A1 (en) * 2003-03-21 2004-09-23 Texas Instruments Incorporated Recessed-bond semiconductor package substrate
US7219242B2 (en) * 2003-03-31 2007-05-15 Intel Corporation Direct plane access power delivery
US6956286B2 (en) * 2003-08-05 2005-10-18 International Business Machines Corporation Integrated circuit package with overlapping bond fingers
JP4703300B2 (ja) * 2005-07-20 2011-06-15 富士通セミコンダクター株式会社 中継基板及び当該中継基板を備えた半導体装置
JP4474431B2 (ja) * 2007-03-26 2010-06-02 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージおよび該製造方法
US8415785B1 (en) 2010-01-27 2013-04-09 Marvell International Ltd. Metal ring techniques and configurations
US9204561B2 (en) * 2012-04-17 2015-12-01 Advanced Flexible Circuits Co., Ltd. Method of manufacturing a structure of via hole of electrical circuit board
US9814142B1 (en) * 2015-06-24 2017-11-07 Automated Assembly Corporation Electronic devices wire bonded to substrate through an adhesive layer and method of making the same

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320438A (en) 1980-05-15 1982-03-16 Cts Corporation Multi-layer ceramic package
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
JPH06342853A (ja) * 1993-04-06 1994-12-13 Tokuyama Soda Co Ltd 半導体素子用パッケージ
KR950702068A (ko) * 1993-04-06 1995-05-17 쓰지 가오루 반도체 소자용 패키지(package for semiconductor chip)
US5490324A (en) 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
JP2931741B2 (ja) 1993-09-24 1999-08-09 株式会社東芝 半導体装置
JP3094069B2 (ja) * 1993-12-24 2000-10-03 日本特殊陶業株式会社 セラミックパッケージ本体の製造方法
WO1995026047A1 (en) * 1994-03-18 1995-09-28 Hitachi Chemical Company, Ltd. Semiconductor package manufacturing method and semiconductor package
JPH07288385A (ja) 1994-04-19 1995-10-31 Hitachi Chem Co Ltd 多層配線板及びその製造法
US5622588A (en) 1995-02-02 1997-04-22 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
FR2736206B1 (fr) * 1995-06-30 1997-08-08 Commissariat Energie Atomique Procede de realisation d'un substrat d'interconnexion permettant de connecter une puce sur un substrat de reception
JP3292798B2 (ja) * 1995-10-04 2002-06-17 三菱電機株式会社 半導体装置
US6060378A (en) * 1995-11-03 2000-05-09 Micron Technology, Inc. Semiconductor bonding pad for better reliability
US5796170A (en) * 1996-02-15 1998-08-18 Northern Telecom Limited Ball grid array (BGA) integrated circuit packages
US5729047A (en) * 1996-03-25 1998-03-17 Micron Technology, Inc. Method and structure for providing signal isolation and decoupling in an integrated circuit device
US6043559A (en) * 1996-09-09 2000-03-28 Intel Corporation Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5854512A (en) * 1996-09-20 1998-12-29 Vlsi Technology, Inc. High density leaded ball-grid array package
JPH10163635A (ja) * 1996-11-28 1998-06-19 Sony Corp プリント配線板
US6054758A (en) 1996-12-18 2000-04-25 Texas Instruments Incorporated Differential pair geometry for integrated circuit chip packages
JPH1174651A (ja) 1997-03-13 1999-03-16 Ibiden Co Ltd プリント配線板及びその製造方法
JPH11176976A (ja) * 1997-12-08 1999-07-02 Sumitomo Metal Smi Electron Devices Inc 電子部品用パッケージの製造方法
US6140707A (en) * 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package
JPH11354566A (ja) * 1998-06-08 1999-12-24 Hitachi Ltd 半導体装置およびその製造方法
JP3420703B2 (ja) * 1998-07-16 2003-06-30 株式会社東芝 半導体装置の製造方法
US6027999A (en) * 1998-09-10 2000-02-22 Chartered Semiconductor Manufacturing, Ltd. Pad definition to achieve highly reflective plate without affecting bondability
TW399309B (en) * 1998-09-30 2000-07-21 World Wiser Electronics Inc Cavity-down package structure with thermal via
US6329228B1 (en) * 1999-04-28 2001-12-11 Citizen Watch Co., Ltd. Semiconductor device and method of fabricating the same
TW439147B (en) * 1999-12-20 2001-06-07 United Microelectronics Corp Manufacturing method to form air gap using hardmask to improve isolation effect
US6465882B1 (en) * 2000-07-21 2002-10-15 Agere Systems Guardian Corp. Integrated circuit package having partially exposed conductive layer
US6790760B1 (en) * 2000-07-21 2004-09-14 Agere Systems Inc. Method of manufacturing an integrated circuit package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100803643B1 (ko) * 2000-07-21 2008-02-19 에이저 시스템즈 가디언 코포레이션 집적 회로 패키지의 제조 방법

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GB2370414A (en) 2002-06-26
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