GB2370414B - A method of manufacturing an integrated circuit package with a cavity to expose a lower conductive level - Google Patents

A method of manufacturing an integrated circuit package with a cavity to expose a lower conductive level

Info

Publication number
GB2370414B
GB2370414B GB0117316A GB0117316A GB2370414B GB 2370414 B GB2370414 B GB 2370414B GB 0117316 A GB0117316 A GB 0117316A GB 0117316 A GB0117316 A GB 0117316A GB 2370414 B GB2370414 B GB 2370414B
Authority
GB
United Kingdom
Prior art keywords
expose
cavity
manufacturing
integrated circuit
circuit package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0117316A
Other languages
English (en)
Other versions
GB2370414A (en
GB0117316D0 (en
Inventor
Charles Cohn
Junior Donald Earl Hawk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Guardian Corp filed Critical Agere Systems Guardian Corp
Publication of GB0117316D0 publication Critical patent/GB0117316D0/en
Publication of GB2370414A publication Critical patent/GB2370414A/en
Application granted granted Critical
Publication of GB2370414B publication Critical patent/GB2370414B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/206—Wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
GB0117316A 2000-07-21 2001-07-16 A method of manufacturing an integrated circuit package with a cavity to expose a lower conductive level Expired - Fee Related GB2370414B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/621,110 US6790760B1 (en) 2000-07-21 2000-07-21 Method of manufacturing an integrated circuit package

Publications (3)

Publication Number Publication Date
GB0117316D0 GB0117316D0 (en) 2001-09-05
GB2370414A GB2370414A (en) 2002-06-26
GB2370414B true GB2370414B (en) 2004-10-20

Family

ID=24488766

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0117316A Expired - Fee Related GB2370414B (en) 2000-07-21 2001-07-16 A method of manufacturing an integrated circuit package with a cavity to expose a lower conductive level

Country Status (5)

Country Link
US (1) US6790760B1 (https=)
JP (1) JP2002043458A (https=)
KR (1) KR100803643B1 (https=)
GB (1) GB2370414B (https=)
TW (1) TW546767B (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6790760B1 (en) * 2000-07-21 2004-09-14 Agere Systems Inc. Method of manufacturing an integrated circuit package
US6770963B1 (en) * 2001-01-04 2004-08-03 Broadcom Corporation Multi-power ring chip scale package for system level integration
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
US20040145874A1 (en) * 2003-01-23 2004-07-29 Stephane Pinel Method, system, and apparatus for embedding circuits
US7183786B2 (en) * 2003-03-04 2007-02-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Modifying a semiconductor device to provide electrical parameter monitoring
US20040183167A1 (en) * 2003-03-21 2004-09-23 Texas Instruments Incorporated Recessed-bond semiconductor package substrate
US7219242B2 (en) * 2003-03-31 2007-05-15 Intel Corporation Direct plane access power delivery
US6956286B2 (en) * 2003-08-05 2005-10-18 International Business Machines Corporation Integrated circuit package with overlapping bond fingers
JP4703300B2 (ja) * 2005-07-20 2011-06-15 富士通セミコンダクター株式会社 中継基板及び当該中継基板を備えた半導体装置
JP4474431B2 (ja) * 2007-03-26 2010-06-02 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージおよび該製造方法
US8415785B1 (en) 2010-01-27 2013-04-09 Marvell International Ltd. Metal ring techniques and configurations
US9204561B2 (en) * 2012-04-17 2015-12-01 Advanced Flexible Circuits Co., Ltd. Method of manufacturing a structure of via hole of electrical circuit board
US9814142B1 (en) * 2015-06-24 2017-11-07 Automated Assembly Corporation Electronic devices wire bonded to substrate through an adhesive layer and method of making the same
CN111443440B (zh) * 2020-05-09 2025-03-04 菲尼萨光电通讯(上海)有限公司 光器件结构及其制作方法

Citations (8)

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Publication number Priority date Publication date Assignee Title
GB2077036A (en) * 1980-05-15 1981-12-09 Cts Corp Multi-layer ceramic package for semiconductor chip
EP0645811A2 (en) * 1993-09-24 1995-03-29 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chip with backside electrode
EP0678918A2 (en) * 1994-04-19 1995-10-25 Hitachi Chemical Company, Ltd. Multilayer printed wiring board
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
WO1996023612A1 (en) * 1995-02-02 1996-08-08 Hestia Technologies, Inc. Methods of making multi-layer laminate substrates for electronic device packaging
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
EP0849793A2 (en) * 1996-12-18 1998-06-24 Texas Instruments Incorporated Improvements in or relating to integrated circuit device packages
EP1011139A1 (en) * 1997-03-13 2000-06-21 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same

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US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
JPH06342853A (ja) * 1993-04-06 1994-12-13 Tokuyama Soda Co Ltd 半導体素子用パッケージ
WO1994023448A1 (fr) * 1993-04-06 1994-10-13 Tokuyama Corporation Boitier pour puce de semiconducteur
JP3094069B2 (ja) * 1993-12-24 2000-10-03 日本特殊陶業株式会社 セラミックパッケージ本体の製造方法
EP1213754A3 (en) * 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
FR2736206B1 (fr) * 1995-06-30 1997-08-08 Commissariat Energie Atomique Procede de realisation d'un substrat d'interconnexion permettant de connecter une puce sur un substrat de reception
JP3292798B2 (ja) * 1995-10-04 2002-06-17 三菱電機株式会社 半導体装置
US6060378A (en) * 1995-11-03 2000-05-09 Micron Technology, Inc. Semiconductor bonding pad for better reliability
US5796170A (en) * 1996-02-15 1998-08-18 Northern Telecom Limited Ball grid array (BGA) integrated circuit packages
US5729047A (en) * 1996-03-25 1998-03-17 Micron Technology, Inc. Method and structure for providing signal isolation and decoupling in an integrated circuit device
US6043559A (en) * 1996-09-09 2000-03-28 Intel Corporation Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
US5854512A (en) * 1996-09-20 1998-12-29 Vlsi Technology, Inc. High density leaded ball-grid array package
JPH10163635A (ja) * 1996-11-28 1998-06-19 Sony Corp プリント配線板
JPH11176976A (ja) * 1997-12-08 1999-07-02 Sumitomo Metal Smi Electron Devices Inc 電子部品用パッケージの製造方法
US6140707A (en) * 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package
JPH11354566A (ja) * 1998-06-08 1999-12-24 Hitachi Ltd 半導体装置およびその製造方法
JP3420703B2 (ja) * 1998-07-16 2003-06-30 株式会社東芝 半導体装置の製造方法
US6027999A (en) * 1998-09-10 2000-02-22 Chartered Semiconductor Manufacturing, Ltd. Pad definition to achieve highly reflective plate without affecting bondability
TW399309B (en) * 1998-09-30 2000-07-21 World Wiser Electronics Inc Cavity-down package structure with thermal via
US6329228B1 (en) * 1999-04-28 2001-12-11 Citizen Watch Co., Ltd. Semiconductor device and method of fabricating the same
TW439147B (en) * 1999-12-20 2001-06-07 United Microelectronics Corp Manufacturing method to form air gap using hardmask to improve isolation effect
US6790760B1 (en) * 2000-07-21 2004-09-14 Agere Systems Inc. Method of manufacturing an integrated circuit package
US6465882B1 (en) * 2000-07-21 2002-10-15 Agere Systems Guardian Corp. Integrated circuit package having partially exposed conductive layer

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2077036A (en) * 1980-05-15 1981-12-09 Cts Corp Multi-layer ceramic package for semiconductor chip
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
EP0645811A2 (en) * 1993-09-24 1995-03-29 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chip with backside electrode
EP0678918A2 (en) * 1994-04-19 1995-10-25 Hitachi Chemical Company, Ltd. Multilayer printed wiring board
WO1996023612A1 (en) * 1995-02-02 1996-08-08 Hestia Technologies, Inc. Methods of making multi-layer laminate substrates for electronic device packaging
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
EP0849793A2 (en) * 1996-12-18 1998-06-24 Texas Instruments Incorporated Improvements in or relating to integrated circuit device packages
EP1011139A1 (en) * 1997-03-13 2000-06-21 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same

Also Published As

Publication number Publication date
US6790760B1 (en) 2004-09-14
GB2370414A (en) 2002-06-26
KR20020009445A (ko) 2002-02-01
TW546767B (en) 2003-08-11
KR100803643B1 (ko) 2008-02-19
JP2002043458A (ja) 2002-02-08
GB0117316D0 (en) 2001-09-05

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20160716