KR100709689B1 - 에피택셜 공정을 사용한 ｓｏｉ 기판의 표면 마무리 방법 - Google Patents

에피택셜 공정을 사용한 ｓｏｉ 기판의 표면 마무리 방법 Download PDF

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Publication number
KR100709689B1
KR100709689B1 KR1020017013384A KR20017013384A KR100709689B1 KR 100709689 B1 KR100709689 B1 KR 100709689B1 KR 1020017013384 A KR1020017013384 A KR 1020017013384A KR 20017013384 A KR20017013384 A KR 20017013384A KR 100709689 B1 KR100709689 B1 KR 100709689B1
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South Korea
Prior art keywords
substrate
wafer
silicon
hydrogen
soi
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Expired - Fee Related
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Korean (ko)
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KR20020007377A (ko
Inventor
강시엔지.
말릭이고르제이.
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실리콘 제너시스 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/967—Semiconductor on specified insulator

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  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Magnetic Heads (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
KR1020017013384A 1999-04-21 2000-04-20 에피택셜 공정을 사용한 ｓｏｉ 기판의 표면 마무리 방법 Expired - Fee Related KR100709689B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13042399P 1999-04-21 1999-04-21
US09/399,985 US6287941B1 (en) 1999-04-21 1999-09-20 Surface finishing of SOI substrates using an EPI process
US09/399,985 1999-09-20
US60/130,423 1999-09-20
PCT/US2000/010872 WO2000063954A1 (en) 1999-04-21 2000-04-20 Surface finishing of soi substrates using an epi process

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020067024245A Division KR20060126629A (ko) 1999-04-21 2000-04-20 에피택셜 공정을 사용한 ｓｏｉ 기판의 표면 마무리 방법

Publications (2)

Publication Number Publication Date
KR20020007377A KR20020007377A (ko) 2002-01-26
KR100709689B1 true KR100709689B1 (ko) 2007-04-19

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020017013384A Expired - Fee Related KR100709689B1 (ko) 1999-04-21 2000-04-20 에피택셜 공정을 사용한 ｓｏｉ 기판의 표면 마무리 방법
KR1020067024245A Ceased KR20060126629A (ko) 1999-04-21 2000-04-20 에피택셜 공정을 사용한 ｓｏｉ 기판의 표면 마무리 방법

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020067024245A Ceased KR20060126629A (ko) 1999-04-21 2000-04-20 에피택셜 공정을 사용한 ｓｏｉ 기판의 표면 마무리 방법

Country Status (8)

Country Link
US (3) US6287941B1 (https=)
EP (2) EP1887616A3 (https=)
JP (1) JP2002542622A (https=)
KR (2) KR100709689B1 (https=)
AT (1) ATE372590T1 (https=)
AU (1) AU4483300A (https=)
DE (1) DE60036286T2 (https=)
WO (1) WO2000063954A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170117612A (ko) * 2009-12-29 2017-10-23 썬에디슨, 인크. Ｓｏｉ 웨이퍼를 가공 처리하는 방법

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US6287941B1 (en) 2001-09-11
WO2000063954A1 (en) 2000-10-26
EP1194949A1 (en) 2002-04-10
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EP1887616A2 (en) 2008-02-13
US20020022344A1 (en) 2002-02-21
ATE372590T1 (de) 2007-09-15
KR20060126629A (ko) 2006-12-07
JP2002542622A (ja) 2002-12-10
US20070259526A1 (en) 2007-11-08
US7253081B2 (en) 2007-08-07
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