KR100678345B1 - 에폭시 수지 조성물 및 예비성형 반도체 패키지 - Google Patents
에폭시 수지 조성물 및 예비성형 반도체 패키지 Download PDFInfo
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- KR100678345B1 KR100678345B1 KR1020000072696A KR20000072696A KR100678345B1 KR 100678345 B1 KR100678345 B1 KR 100678345B1 KR 1020000072696 A KR1020000072696 A KR 1020000072696A KR 20000072696 A KR20000072696 A KR 20000072696A KR 100678345 B1 KR100678345 B1 KR 100678345B1
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- epoxy resin
- resin composition
- porous silica
- package
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- 230000005484 gravity Effects 0.000 claims description 9
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- 239000007822 coupling agent Substances 0.000 description 6
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- AUOZNINQGUNWOV-UHFFFAOYSA-N triphenyl borate;triphenylphosphane Chemical compound C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C=1C=CC=CC=1OB(OC=1C=CC=CC=1)OC1=CC=CC=C1 AUOZNINQGUNWOV-UHFFFAOYSA-N 0.000 description 1
- IUURMAINMLIZMX-UHFFFAOYSA-N tris(2-nonylphenyl)phosphane Chemical compound CCCCCCCCCC1=CC=CC=C1P(C=1C(=CC=CC=1)CCCCCCCCC)C1=CC=CC=C1CCCCCCCCC IUURMAINMLIZMX-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
- H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
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- C—CHEMISTRY; METALLURGY
- C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
- C08K—Use of inorganic or non-macromolecular organic substances as compounding ingredients
- C08K3/00—Use of inorganic substances as compounding ingredients
- C08K3/34—Silicon-containing compounds
- C08K3/36—Silica
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Abstract
Description
Claims (8)
- 에폭시 수지, 경화제 및 무기질 충전제를 함유하는 에폭시 수지 조성물에 있어서, 무기질 충전제로서 비표면적이 20∼200 ㎡/g이고, 참비중이 2.0∼2.2이며, 평균 입경이 2∼50 ㎛인 다공질 실리카(A)를 함유하고, 또한, 에폭시 수지 조성물을 중공 상자형의 예비성형 패키지로서 리드프레임을 개재시켜서 175℃, 6.9 N/㎟, 성형 시간 120 초의 조건에서 성형한 후, 180℃에서 4 시간 후 경화시키고, 얻어진 패키지에 에폭시 수지 접착체로 투명한 유리 실드를 접착하며, 이 중공 패키지에 대하여(1) 121℃/100%RH/2 기압의 분위기 하에 4 시간 방치,(2) 실온(25℃)에 30 분 방치,(3) 100℃의 핫플레이트에 유리 실드 면을 10 초간 접촉,(4) 실온의 철판으로 옮기고, 유리 실드 면을 7 초간 방치의 (1) 내지 (4)의 사이클을 3 회 반복해도 유리 실드의 내면에 이슬 응결이 없는 경화물을 부여하는 것을 특징으로 하는 예비성형 중공 패키지용 에폭시 수지 조성물.
- 제1항에 있어서, 다공질 실리카가 전체 에폭시 수지 조성물 중 40∼90 중량%의 비율을 차지하는 것을 특징으로 하는 에폭시 수지 조성물.
- 제1항에 있어서, 다공질 실리카가 졸-겔법에 의해 50 ㎛까지의 중량 평균 입경을 갖는 실리카겔을 형성하고, 700∼1200℃의 온도로 실리카겔을 연소함에 의해 제조되는 것을 특징으로 하는 에폭시 수지 조성물.
- 제1항에 있어서, 다공질 실리카가 24 시간 동안 25℃ 및 RH 70%로 유지되는 경우, 최소한 0.3 중량%의 수분 픽업을 가지는 것을 특징으로 하는 에폭시 수지 조성물.
- 제1항에 있어서, 다공질 실리카가 1 ppm까지의 각 알칼리 및 알칼리 토금속을 함유하는 것을 특징으로 하는 에폭시 수지 조성물.
- 삭제
- 에폭시 수지, 경화제 및 무기질 충전제를 함유하는 에폭시 수지 조성물의 경화물에 캡슐화된 예비성형 반도체 장치 소자용 중공 패키지에 있어서, 에폭시 수지 조성물의 경화물에 함유된 무기질 충전제는 비표면적이 20∼200 ㎡/g이고, 참비중이 2.0∼2.2이며, 평균 입경이 2∼50 ㎛인 다공질 실리카(A)를 함유하고, 또한, 에폭시 수지 조성물을 중공 상자형의 예비성형 패키지로서 리드프레임을 개재시켜서 175℃, 6.9 N/㎟, 성형 시간 120 초의 조건에서 성형한 후, 180℃에서 4 시간 후 경화시키고, 얻어진 패키지에 에폭시 수지 접착체로 투명한 유리 실드를 접착하며, 이 중공 패키지에 대하여(1) 121℃/100%RH/2 기압의 분위기 하에 4 시간 방치,(2) 실온(25℃)에 30 분 방치,(3) 100℃의 핫플레이트에 유리 실드 면을 10 초간 접촉,(4) 실온의 철판으로 옮기고, 유리 실드 면을 7 초간 방치의 (1) 내지 (4)의 사이클을 3 회 반복해도 유리 실드의 내면에 이슬 응결이 없는 경화물을 부여하는 것을 특징으로 하는 반도체 장치 소자용 중공 패키지.
- 제7항에 있어서, 다공질 실리카가 전체 에폭시 수지 조성물 중 최소한 55 중량%의 비율을 차지하는 것을 특징으로 하는 예비성형 중공 반도체 패키지.
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JP2000360597A JP4614214B2 (ja) | 1999-12-02 | 2000-11-28 | 半導体装置素子用中空パッケージ |
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KR100678345B1 true KR100678345B1 (ko) | 2007-02-05 |
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JP (1) | JP4614214B2 (ko) |
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JP2000191890A (ja) * | 1998-10-20 | 2000-07-11 | Nitto Denko Corp | 半導体封止用樹脂組成物およびそれを用いた半導体装置 |
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CA1271307A (en) | 1985-06-27 | 1990-07-10 | Iwao Ohshima | Process for manufacturing high purity silica |
JPH04253760A (ja) * | 1991-02-04 | 1992-09-09 | Matsushita Electric Works Ltd | 封止用エポキシ樹脂成形材料 |
JP2750254B2 (ja) | 1993-02-08 | 1998-05-13 | 京セラ株式会社 | 半導体素子収納用パッケージ |
JP3296520B2 (ja) | 1993-09-29 | 2002-07-02 | 東芝テック株式会社 | ダウンロード・ブートストラップ方法 |
US5827908A (en) * | 1994-01-26 | 1998-10-27 | Shin-Etsu Chemical Co., Ltd. | Naphthalene and or biphenyl skeleton containing epoxy resin composition |
JP3471514B2 (ja) * | 1996-02-01 | 2003-12-02 | 水澤化学工業株式会社 | 半導体封止用樹脂組成物及びそれに用いる吸湿性充填剤 |
JP3375835B2 (ja) * | 1996-10-28 | 2003-02-10 | 住友ベークライト株式会社 | 液状封止樹脂組成物及びこの液状封止樹脂組成物を用いた半導体製品 |
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2000
- 2000-11-28 JP JP2000360597A patent/JP4614214B2/ja not_active Expired - Lifetime
- 2000-12-01 TW TW89125643A patent/TW561177B/zh not_active IP Right Cessation
- 2000-12-01 US US09/726,575 patent/US6399677B2/en not_active Expired - Lifetime
- 2000-12-02 KR KR1020000072696A patent/KR100678345B1/ko active IP Right Grant
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2001
- 2001-11-20 US US09/988,752 patent/US6569532B2/en not_active Expired - Lifetime
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JPH01242615A (ja) * | 1988-03-23 | 1989-09-27 | Sumitomo Bakelite Co Ltd | 半導体封止用エポキシ樹脂組成物 |
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JPH01275626A (ja) * | 1988-04-28 | 1989-11-06 | Sumitomo Bakelite Co Ltd | 半導体封止用エポキシ樹脂組成物 |
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KR900009849A (ko) * | 1988-12-08 | 1990-07-05 | 스미또모 배꾸라이또 가부시끼가이샤 | 반도체 밀봉용 에폭시 수지 조성물 |
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KR100240121B1 (ko) * | 1997-08-30 | 2000-01-15 | 성재갑 | 전하 결합 소자 봉지용 에폭시 수지 조성물 |
JP2000191890A (ja) * | 1998-10-20 | 2000-07-11 | Nitto Denko Corp | 半導体封止用樹脂組成物およびそれを用いた半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20010004651A1 (en) | 2001-06-21 |
US6569532B2 (en) | 2003-05-27 |
US6399677B2 (en) | 2002-06-04 |
US20020076558A1 (en) | 2002-06-20 |
JP2001220496A (ja) | 2001-08-14 |
JP4614214B2 (ja) | 2011-01-19 |
TW561177B (en) | 2003-11-11 |
KR20010062093A (ko) | 2001-07-07 |
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