KR100545225B1 - 자체수리회로를 채용한 메모리 동작 테스트 방법 및 메모리 위치를 영구적으로 디스에이블하는 방법 - Google Patents
자체수리회로를 채용한 메모리 동작 테스트 방법 및 메모리 위치를 영구적으로 디스에이블하는 방법 Download PDFInfo
- Publication number
- KR100545225B1 KR100545225B1 KR1019980016166A KR19980016166A KR100545225B1 KR 100545225 B1 KR100545225 B1 KR 100545225B1 KR 1019980016166 A KR1019980016166 A KR 1019980016166A KR 19980016166 A KR19980016166 A KR 19980016166A KR 100545225 B1 KR100545225 B1 KR 100545225B1
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- column
- row
- columns
- rows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/852,692 US5987632A (en) | 1997-05-07 | 1997-05-07 | Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations |
| US8/852,692 | 1997-05-07 | ||
| US08/852,692 | 1997-05-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980086794A KR19980086794A (ko) | 1998-12-05 |
| KR100545225B1 true KR100545225B1 (ko) | 2006-04-10 |
Family
ID=25313994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980016166A Expired - Fee Related KR100545225B1 (ko) | 1997-05-07 | 1998-05-06 | 자체수리회로를 채용한 메모리 동작 테스트 방법 및 메모리 위치를 영구적으로 디스에이블하는 방법 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5987632A (enExample) |
| JP (1) | JP4716530B2 (enExample) |
| KR (1) | KR100545225B1 (enExample) |
| DE (1) | DE19820442A1 (enExample) |
| TW (1) | TW376558B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190102580A (ko) * | 2018-02-26 | 2019-09-04 | 고려대학교 산학협력단 | 결함 정보 저장 테이블을 이용한 리페어 분석 시스템 및 그의 리페어 분석 방법 |
Families Citing this family (80)
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| US6456101B2 (en) * | 1999-04-07 | 2002-09-24 | Agere Systems Guardian Corp. | Chip-on-chip testing using BIST |
| DE19917588A1 (de) * | 1999-04-19 | 2000-11-02 | Siemens Ag | Halbleiterspeicheranordnung mit BIST |
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| KR100317486B1 (ko) * | 1999-12-29 | 2001-12-24 | 박종섭 | 자동복구 기능을 가지는 플래시 메모리 |
| US6493647B1 (en) * | 1999-12-29 | 2002-12-10 | Advanced Micro Devices, Inc. | Method and apparatus for exercising external memory with a memory built-in self-test |
| JP2001195895A (ja) * | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | 半導体記憶装置 |
| KR100354437B1 (ko) * | 2000-01-28 | 2002-09-28 | 삼성전자 주식회사 | 내장 메모리를 위한 자기 복구 회로를 구비하는 집적회로반도체 장치 및 메모리 복구 방법 |
| US6874110B1 (en) * | 2000-05-11 | 2005-03-29 | Stretch, Inc. | Apparatus and method for self testing programmable logic arrays |
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| US6577156B2 (en) * | 2000-12-05 | 2003-06-10 | International Business Machines Corporation | Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox |
| US6496432B2 (en) | 2000-12-08 | 2002-12-17 | International Business Machines Corporation | Method and apparatus for testing a write function of a dual-port static memory cell |
| US6691264B2 (en) * | 2001-01-22 | 2004-02-10 | Lsi Logic Corporation | Built-in self-repair wrapper methodology, design flow and design architecture |
| DE10109335C2 (de) | 2001-02-27 | 2002-12-19 | Infineon Technologies Ag | Integriertes Halbleiterspeicherbauelement |
| US20020194558A1 (en) * | 2001-04-10 | 2002-12-19 | Laung-Terng Wang | Method and system to optimize test cost and disable defects for scan and BIST memories |
| US6766468B2 (en) * | 2001-07-11 | 2004-07-20 | International Business Machines Corporation | Memory BIST and repair |
| US7401271B1 (en) * | 2001-08-20 | 2008-07-15 | Emc Corporation | Testing system and method of using same |
| US7096397B2 (en) * | 2001-09-17 | 2006-08-22 | Intel Corporation | Dft technique for avoiding contention/conflict in logic built-in self-test |
| US7085971B2 (en) * | 2001-10-25 | 2006-08-01 | International Business Machines Corporation | ECC based system and method for repairing failed memory elements |
| US20030084389A1 (en) * | 2001-10-25 | 2003-05-01 | Sailesh Kottapalli | Method and apparatus for flexible memory for defect tolerance |
| KR100464953B1 (ko) * | 2002-04-02 | 2005-01-06 | 매그나칩 반도체 유한회사 | 의사 랜덤 오류 데이터 복구용 읽기 전용 메모리 장치 및데이터 복구 방법 |
| US6865694B2 (en) * | 2002-04-30 | 2005-03-08 | Texas Instruments Incorporated | CPU-based system and method for testing embedded memory |
| US20040123181A1 (en) * | 2002-12-20 | 2004-06-24 | Moon Nathan I. | Self-repair of memory arrays using preallocated redundancy (PAR) architecture |
| US6856569B2 (en) * | 2003-01-10 | 2005-02-15 | International Business Machines Corporation | Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability |
| KR100512176B1 (ko) * | 2003-03-19 | 2005-09-02 | 삼성전자주식회사 | 대기 전류 불량의 판별 기능을 갖는 반도체 메모리 장치 |
| DE60336047D1 (de) * | 2003-05-22 | 2011-03-31 | Infineon Technologies Ag | Verfahren und Schaltung zur verzögerungsfreien Speicherung von Fehlern zur Selbstreparatur von eingebetteten RAM-Speichern |
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| US20050144525A1 (en) * | 2003-12-05 | 2005-06-30 | Keerthinarayan Heragu | Method to test memories that operate at twice their nominal bandwidth |
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| US7565585B2 (en) * | 2004-01-13 | 2009-07-21 | International Business Machines Corporation | Integrated redundancy architecture and method for providing redundancy allocation to an embedded memory system |
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| KR100702300B1 (ko) * | 2005-05-30 | 2007-03-30 | 주식회사 하이닉스반도체 | 테스트 제어 회로를 갖는 반도체 메모리 장치 |
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| US11887685B2 (en) | 2020-08-18 | 2024-01-30 | Changxin Memory Technologies, Inc. | Fail Bit repair method and device |
| US11791010B2 (en) | 2020-08-18 | 2023-10-17 | Changxin Memory Technologies, Inc. | Method and device for fail bit repairing |
| EP3985675B1 (en) | 2020-08-18 | 2024-01-31 | Changxin Memory Technologies, Inc. | Method and device for repairing fail bits |
| US11797371B2 (en) | 2020-08-18 | 2023-10-24 | Changxin Memory Technologies, Inc. | Method and device for determining fail bit repair scheme |
| US11783884B2 (en) * | 2020-12-10 | 2023-10-10 | SK Hynix Inc. | Semiconductor memory device and memory system including the same |
| KR102883537B1 (ko) | 2020-12-14 | 2025-11-11 | 에스케이하이닉스 주식회사 | 타겟 리프레쉬 동작을 수행하는 메모리 장치를 포함하는 메모리 시스템 |
| US11749371B2 (en) | 2020-12-14 | 2023-09-05 | SK Hynix Inc. | Memory system including memory device performing target refresh |
| US11984179B2 (en) | 2021-03-26 | 2024-05-14 | Changxin Memory Technologies, Inc. | Redundant circuit assigning method and device, and medium |
| CN112908402B (zh) * | 2021-03-31 | 2022-05-10 | 长鑫存储技术有限公司 | 备用电路分派方法、装置、设备及介质 |
| US11881278B2 (en) | 2021-03-31 | 2024-01-23 | Changxin Memory Technologies, Inc. | Redundant circuit assigning method and device, apparatus and medium |
| US11791012B2 (en) | 2021-03-31 | 2023-10-17 | Changxin Memory Technologies, Inc. | Standby circuit dispatch method, apparatus, device and medium |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4543594A (en) * | 1982-09-07 | 1985-09-24 | Intel Corporation | Fusible link employing capacitor structure |
| JPS6020397A (ja) * | 1983-07-15 | 1985-02-01 | Toshiba Corp | 半導体メモリ |
| JPH0223592A (ja) * | 1988-07-12 | 1990-01-25 | Mitsubishi Electric Corp | 半導体装置 |
| JPH04228196A (ja) * | 1990-04-18 | 1992-08-18 | Hitachi Ltd | 半導体集積回路 |
| JPH04245100A (ja) * | 1991-01-31 | 1992-09-01 | Hitachi Ltd | 半導体メモリic |
| JP3371971B2 (ja) * | 1992-05-01 | 2003-01-27 | 株式会社日立製作所 | 半導体集積回路装置 |
| JP3282253B2 (ja) * | 1992-01-31 | 2002-05-13 | 松下電器産業株式会社 | ダイナミック・ランダム・アクセス・メモリ装置とその検査方法 |
| US5577050A (en) * | 1994-12-28 | 1996-11-19 | Lsi Logic Corporation | Method and apparatus for configurable build-in self-repairing of ASIC memories design |
| US5841709A (en) * | 1995-12-29 | 1998-11-24 | Stmicroelectronics, Inc. | Memory having and method for testing redundant memory cells |
| US5764878A (en) * | 1996-02-07 | 1998-06-09 | Lsi Logic Corporation | Built-in self repair system for embedded memories |
| US5668818A (en) * | 1996-08-06 | 1997-09-16 | Hewlett-Packard Co. | System and method for scan control of a programmable fuse circuit in an integrated circuit |
-
1997
- 1997-05-07 US US08/852,692 patent/US5987632A/en not_active Expired - Lifetime
-
1998
- 1998-05-04 TW TW087106864A patent/TW376558B/zh active
- 1998-05-06 KR KR1019980016166A patent/KR100545225B1/ko not_active Expired - Fee Related
- 1998-05-07 DE DE19820442A patent/DE19820442A1/de not_active Withdrawn
- 1998-05-07 JP JP14057198A patent/JP4716530B2/ja not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190102580A (ko) * | 2018-02-26 | 2019-09-04 | 고려대학교 산학협력단 | 결함 정보 저장 테이블을 이용한 리페어 분석 시스템 및 그의 리페어 분석 방법 |
| KR102122821B1 (ko) | 2018-02-26 | 2020-06-15 | 고려대학교 산학협력단 | 결함 정보 저장 테이블을 이용한 리페어 분석 시스템 및 그의 리페어 분석 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11120787A (ja) | 1999-04-30 |
| TW376558B (en) | 1999-12-11 |
| DE19820442A1 (de) | 1998-11-12 |
| KR19980086794A (ko) | 1998-12-05 |
| US5987632A (en) | 1999-11-16 |
| JP4716530B2 (ja) | 2011-07-06 |
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