TW376558B - Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations - Google Patents

Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

Info

Publication number
TW376558B
TW376558B TW087106864A TW87106864A TW376558B TW 376558 B TW376558 B TW 376558B TW 087106864 A TW087106864 A TW 087106864A TW 87106864 A TW87106864 A TW 87106864A TW 376558 B TW376558 B TW 376558B
Authority
TW
Taiwan
Prior art keywords
rows
test
memory
self
locations
Prior art date
Application number
TW087106864A
Other languages
Chinese (zh)
Inventor
V Swamy Irrinki
Thomas R Wik
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Application granted granted Critical
Publication of TW376558B publication Critical patent/TW376558B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A test method for a memory device wherein failures that may only occur under specified worst-case conditions are converted to hard functional failures. These locations are subsequently detected and remapped by built-in self test (BIST) and built-in self-repair (BISR) circuitry. First, a test suite is performed on a memory array which includes redundant row and column locations. Typically, this test suite is performed under conditions which are most likely to induce failure. Row and column locations that are determined to be malfunctioning are scanned out of the memory device, along with the number of available redundant rows and columns. If there are sufficient redundant locations, the failing rows and columns are permanently disabled by blowing each of the corresponding fuse links. When power is subsequently applied to the memory device, BIST will detect rows and columns, including those permanently disabled, with hard functional failures. Accesses to these locations may then be redirected by BISR circuitry. The test suite may then be re-executed, and the device deemed defective if additional errors are found. Rows and columns in the memory array that are prone to failure are thus never enabled. Additionally, the BIST and BISR circuitry provides the ability to verify basic memory functionality and remap failing addresses on each applications of power to the device. Test coverage of the memory array is advantageously increased. A method of testing a memory device, said memory device including a memory array including a plurality of rows, comprising: performing a given test on said plurality of rows under a particular set of operating conditions; determining that a particular row within said plurality of rows is malfunctioning in response to results from said given test; permanently disabling memory accesses to said particular row; performing a self-test operation upon said memory array in response to an application of power to said memory device during normal operating conditions, wherein said self-test operation identifies any malfunctioning rows within said memory array including said particular row, and wherein said self-test operation is performed subsequently to said permanently disabling memory accesses to said particular row; and enabling a redundant row for each of said malfunctioning rows.
TW087106864A 1997-05-07 1998-05-04 Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations TW376558B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/852,692 US5987632A (en) 1997-05-07 1997-05-07 Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

Publications (1)

Publication Number Publication Date
TW376558B true TW376558B (en) 1999-12-11

Family

ID=25313994

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087106864A TW376558B (en) 1997-05-07 1998-05-04 Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

Country Status (5)

Country Link
US (1) US5987632A (en)
JP (1) JP4716530B2 (en)
KR (1) KR100545225B1 (en)
DE (1) DE19820442A1 (en)
TW (1) TW376558B (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112908402A (en) * 2021-03-31 2021-06-04 长鑫存储技术有限公司 Spare circuit allocation method, device, equipment and medium
US11791012B2 (en) 2021-03-31 2023-10-17 Changxin Memory Technologies, Inc. Standby circuit dispatch method, apparatus, device and medium
US11791010B2 (en) 2020-08-18 2023-10-17 Changxin Memory Technologies, Inc. Method and device for fail bit repairing
US11797371B2 (en) 2020-08-18 2023-10-24 Changxin Memory Technologies, Inc. Method and device for determining fail bit repair scheme
US11853152B2 (en) 2020-08-18 2023-12-26 Changxin Memory Technologies, Inc. Fail bit repair method and device
US11881278B2 (en) 2021-03-31 2024-01-23 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, apparatus and medium
US11887685B2 (en) 2020-08-18 2024-01-30 Changxin Memory Technologies, Inc. Fail Bit repair method and device
US11984179B2 (en) 2021-03-26 2024-05-14 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, and medium

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2212089C (en) * 1997-07-31 2006-10-24 Mosaid Technologies Incorporated Bist memory test system
US6085334A (en) * 1998-04-17 2000-07-04 Motorola, Inc. Method and apparatus for testing an integrated memory device
US6351789B1 (en) * 1998-05-29 2002-02-26 Via-Cyrix, Inc. Built-in self-test circuit and method for validating an associative data array
JP2000030483A (en) * 1998-07-15 2000-01-28 Mitsubishi Electric Corp Bist circuit for large-scale memory
JP3866436B2 (en) * 1999-03-18 2007-01-10 株式会社東芝 Semiconductor device and semiconductor system provided with the same
KR100309464B1 (en) * 1999-03-27 2001-09-26 김영환 Semiconductor memory device having refresh test circuit
US6456101B2 (en) * 1999-04-07 2002-09-24 Agere Systems Guardian Corp. Chip-on-chip testing using BIST
DE19917588A1 (en) 1999-04-19 2000-11-02 Siemens Ag Semiconductor memory device with BIST
DE19924153B4 (en) * 1999-05-26 2006-02-09 Infineon Technologies Ag Circuit arrangement for repair of a semiconductor memory
US6304989B1 (en) * 1999-07-21 2001-10-16 Credence Systems Corporation Built-in spare row and column replacement analysis system for embedded memories
US6553510B1 (en) * 1999-09-02 2003-04-22 Micron Technology, Inc. Memory device including redundancy routine for correcting random errors
KR100532408B1 (en) * 1999-09-15 2005-11-30 삼성전자주식회사 Memory test and faulty cell(s) repair method for semiconductor device having memory
JP2001155980A (en) * 1999-11-25 2001-06-08 Nec Corp Test and repair system, product fabrication system, component test system, data processing system, component repair system, and information storage medium
US6505313B1 (en) * 1999-12-17 2003-01-07 Lsi Logic Corporation Multi-condition BISR test mode for memories with redundancy
US6493647B1 (en) * 1999-12-29 2002-12-10 Advanced Micro Devices, Inc. Method and apparatus for exercising external memory with a memory built-in self-test
KR100317486B1 (en) * 1999-12-29 2001-12-24 박종섭 A flash memory including auto repair function
JP2001195895A (en) * 2000-01-13 2001-07-19 Mitsubishi Electric Corp Semiconductor memory
KR100354437B1 (en) * 2000-01-28 2002-09-28 삼성전자 주식회사 An integrated circuit semiconductor device having built-in self-repair circuit for embedded memory and a method for repairing the memory
US6874110B1 (en) * 2000-05-11 2005-03-29 Stretch, Inc. Apparatus and method for self testing programmable logic arrays
US6510398B1 (en) * 2000-06-22 2003-01-21 Intel Corporation Constrained signature-based test
US6629281B1 (en) 2000-09-26 2003-09-30 International Business Machines Corporation Method and system for at speed diagnostics and bit fail mapping
US6577156B2 (en) * 2000-12-05 2003-06-10 International Business Machines Corporation Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox
US6496432B2 (en) 2000-12-08 2002-12-17 International Business Machines Corporation Method and apparatus for testing a write function of a dual-port static memory cell
US6691264B2 (en) * 2001-01-22 2004-02-10 Lsi Logic Corporation Built-in self-repair wrapper methodology, design flow and design architecture
DE10109335C2 (en) * 2001-02-27 2002-12-19 Infineon Technologies Ag Integrated semiconductor memory device
US20020194558A1 (en) * 2001-04-10 2002-12-19 Laung-Terng Wang Method and system to optimize test cost and disable defects for scan and BIST memories
US6766468B2 (en) * 2001-07-11 2004-07-20 International Business Machines Corporation Memory BIST and repair
US7401271B1 (en) * 2001-08-20 2008-07-15 Emc Corporation Testing system and method of using same
US7096397B2 (en) * 2001-09-17 2006-08-22 Intel Corporation Dft technique for avoiding contention/conflict in logic built-in self-test
US20030084389A1 (en) * 2001-10-25 2003-05-01 Sailesh Kottapalli Method and apparatus for flexible memory for defect tolerance
US7085971B2 (en) * 2001-10-25 2006-08-01 International Business Machines Corporation ECC based system and method for repairing failed memory elements
KR100464953B1 (en) * 2002-04-02 2005-01-06 매그나칩 반도체 유한회사 Read only memory for pseudo random error data recovery and method thereof
US6865694B2 (en) * 2002-04-30 2005-03-08 Texas Instruments Incorporated CPU-based system and method for testing embedded memory
US20040123181A1 (en) * 2002-12-20 2004-06-24 Moon Nathan I. Self-repair of memory arrays using preallocated redundancy (PAR) architecture
US6856569B2 (en) * 2003-01-10 2005-02-15 International Business Machines Corporation Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability
KR100512176B1 (en) * 2003-03-19 2005-09-02 삼성전자주식회사 Semiconductor memory device with function of judging standby current failure
EP1480228B9 (en) * 2003-05-22 2011-06-29 Infineon Technologies AG Method and device for at-speed storage of faults for built-in self-repair (BISR) of embedded-RAMs
KR100555532B1 (en) * 2003-11-27 2006-03-03 삼성전자주식회사 Memory test circuit and test system
US7210085B2 (en) * 2003-12-02 2007-04-24 International Business Machines Corporation Method and apparatus for test and repair of marginally functional SRAM cells
US20050144525A1 (en) * 2003-12-05 2005-06-30 Keerthinarayan Heragu Method to test memories that operate at twice their nominal bandwidth
KR100582357B1 (en) * 2003-12-29 2006-05-22 주식회사 하이닉스반도체 Semiconductor memory device with tag block for decoding row address efficiently
US7565585B2 (en) * 2004-01-13 2009-07-21 International Business Machines Corporation Integrated redundancy architecture and method for providing redundancy allocation to an embedded memory system
US7417813B2 (en) * 2004-05-26 2008-08-26 Seagate Technology Llc Overlapping data track access
US7272758B2 (en) * 2004-08-31 2007-09-18 Micron Technology, Inc. Defective memory block identification in a memory device
US7257745B2 (en) * 2005-01-31 2007-08-14 International Business Machines Corporation Array self repair using built-in self test techniques
JP2006302464A (en) * 2005-04-25 2006-11-02 Nec Electronics Corp Semiconductor memory device
US7221603B2 (en) * 2005-05-12 2007-05-22 Micron Technology, Inc. Defective block handling in a flash memory device
KR100702300B1 (en) * 2005-05-30 2007-03-30 주식회사 하이닉스반도체 Semiconductor memory device having a test control circuit
US20070118778A1 (en) * 2005-11-10 2007-05-24 Via Telecom Co., Ltd. Method and/or apparatus to detect and handle defects in a memory
US7536614B1 (en) * 2006-06-28 2009-05-19 Integrated Device Technology, Inc Built-in-redundancy analysis using RAM
CN101101795B (en) * 2006-07-07 2010-05-12 慧荣科技股份有限公司 Non-volatile memory array
US7895482B2 (en) * 2007-04-26 2011-02-22 Agere Systems Inc. Embedded memory repair
US7779312B2 (en) * 2007-08-13 2010-08-17 Faraday Technology Corp. Built-in redundancy analyzer and method for redundancy analysis
US8850277B2 (en) * 2011-07-15 2014-09-30 Synopsys, Inc. Detecting random telegraph noise induced failures in an electronic memory
US9953725B2 (en) * 2012-02-29 2018-04-24 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of operating the same
US9087613B2 (en) * 2012-02-29 2015-07-21 Samsung Electronics Co., Ltd. Device and method for repairing memory cell and memory system including the device
KR20130135658A (en) 2012-06-01 2013-12-11 삼성전자주식회사 Memory device capable of rescuing fail cell after packaging
US8495436B1 (en) 2012-06-17 2013-07-23 Freescale Semiconductor, Inc. System and method for memory testing in electronic circuits
KR102021898B1 (en) * 2012-12-28 2019-11-04 에스케이하이닉스 주식회사 Test mediation device, test system of memory device and method for testing memory device
KR102054272B1 (en) * 2013-06-18 2019-12-10 에스케이하이닉스 주식회사 Chip tester, test system including the same, and test method thereof
US9490033B2 (en) * 2013-09-27 2016-11-08 Cavium, Inc. Auto-blow memory repair
US9564245B2 (en) * 2013-12-26 2017-02-07 Intel Corporation Integrated circuit defect detection and repair
US9548137B2 (en) * 2013-12-26 2017-01-17 Intel Corporation Integrated circuit defect detection and repair
US9496052B2 (en) 2014-12-11 2016-11-15 Freescale Semiconductor, Inc. System and method for handling memory repair data
US9659666B2 (en) * 2015-08-31 2017-05-23 Sandisk Technologies Llc Dynamic memory recovery at the sub-block level
US9653183B1 (en) * 2016-09-01 2017-05-16 Qualcomm Incorporated Shared built-in self-analysis of memory systems employing a memory array tile architecture
KR20180104455A (en) * 2017-03-13 2018-09-21 에스케이하이닉스 주식회사 Repair device and semiconductor including the same
KR102122821B1 (en) * 2018-02-26 2020-06-15 고려대학교 산학협력단 Repair analyzing system based on fault information storage table and repair analyzing method thereof
US11862271B2 (en) * 2018-12-17 2024-01-02 Arm Limited Memory testing techniques
US11112455B2 (en) * 2019-02-26 2021-09-07 Texas Instruments Incorporated Built-in self-test circuits and related methods
US11783884B2 (en) * 2020-12-10 2023-10-10 SK Hynix Inc. Semiconductor memory device and memory system including the same
US11749371B2 (en) 2020-12-14 2023-09-05 SK Hynix Inc. Memory system including memory device performing target refresh

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4543594A (en) * 1982-09-07 1985-09-24 Intel Corporation Fusible link employing capacitor structure
JPS6020397A (en) * 1983-07-15 1985-02-01 Toshiba Corp Semiconductor memory
JPH0223592A (en) * 1988-07-12 1990-01-25 Mitsubishi Electric Corp Semiconductor device
JPH04228196A (en) * 1990-04-18 1992-08-18 Hitachi Ltd Semiconductor integrated circuit
JPH04245100A (en) * 1991-01-31 1992-09-01 Hitachi Ltd Semiconductor memory ic
JP3371971B2 (en) * 1992-05-01 2003-01-27 株式会社日立製作所 Semiconductor integrated circuit device
JP3282253B2 (en) * 1992-01-31 2002-05-13 松下電器産業株式会社 Dynamic random access memory device and inspection method thereof
US5577050A (en) * 1994-12-28 1996-11-19 Lsi Logic Corporation Method and apparatus for configurable build-in self-repairing of ASIC memories design
US5841709A (en) * 1995-12-29 1998-11-24 Stmicroelectronics, Inc. Memory having and method for testing redundant memory cells
US5764878A (en) * 1996-02-07 1998-06-09 Lsi Logic Corporation Built-in self repair system for embedded memories
US5668818A (en) * 1996-08-06 1997-09-16 Hewlett-Packard Co. System and method for scan control of a programmable fuse circuit in an integrated circuit

Cited By (9)

* Cited by examiner, † Cited by third party
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US11791010B2 (en) 2020-08-18 2023-10-17 Changxin Memory Technologies, Inc. Method and device for fail bit repairing
US11797371B2 (en) 2020-08-18 2023-10-24 Changxin Memory Technologies, Inc. Method and device for determining fail bit repair scheme
US11853152B2 (en) 2020-08-18 2023-12-26 Changxin Memory Technologies, Inc. Fail bit repair method and device
US11887685B2 (en) 2020-08-18 2024-01-30 Changxin Memory Technologies, Inc. Fail Bit repair method and device
US11984179B2 (en) 2021-03-26 2024-05-14 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, and medium
CN112908402A (en) * 2021-03-31 2021-06-04 长鑫存储技术有限公司 Spare circuit allocation method, device, equipment and medium
CN112908402B (en) * 2021-03-31 2022-05-10 长鑫存储技术有限公司 Spare circuit allocation method, device, equipment and medium
US11791012B2 (en) 2021-03-31 2023-10-17 Changxin Memory Technologies, Inc. Standby circuit dispatch method, apparatus, device and medium
US11881278B2 (en) 2021-03-31 2024-01-23 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, apparatus and medium

Also Published As

Publication number Publication date
KR100545225B1 (en) 2006-04-10
JPH11120787A (en) 1999-04-30
US5987632A (en) 1999-11-16
DE19820442A1 (en) 1998-11-12
KR19980086794A (en) 1998-12-05
JP4716530B2 (en) 2011-07-06

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