TW376558B - Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations - Google Patents

Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

Info

Publication number
TW376558B
TW376558B TW087106864A TW87106864A TW376558B TW 376558 B TW376558 B TW 376558B TW 087106864 A TW087106864 A TW 087106864A TW 87106864 A TW87106864 A TW 87106864A TW 376558 B TW376558 B TW 376558B
Authority
TW
Taiwan
Prior art keywords
rows
test
memory
self
locations
Prior art date
Application number
TW087106864A
Other languages
English (en)
Inventor
V Swamy Irrinki
Thomas R Wik
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Application granted granted Critical
Publication of TW376558B publication Critical patent/TW376558B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
TW087106864A 1997-05-07 1998-05-04 Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations TW376558B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/852,692 US5987632A (en) 1997-05-07 1997-05-07 Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

Publications (1)

Publication Number Publication Date
TW376558B true TW376558B (en) 1999-12-11

Family

ID=25313994

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087106864A TW376558B (en) 1997-05-07 1998-05-04 Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

Country Status (5)

Country Link
US (1) US5987632A (zh)
JP (1) JP4716530B2 (zh)
KR (1) KR100545225B1 (zh)
DE (1) DE19820442A1 (zh)
TW (1) TW376558B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112908402A (zh) * 2021-03-31 2021-06-04 长鑫存储技术有限公司 备用电路分派方法、装置、设备及介质
US11791010B2 (en) 2020-08-18 2023-10-17 Changxin Memory Technologies, Inc. Method and device for fail bit repairing
US11791012B2 (en) 2021-03-31 2023-10-17 Changxin Memory Technologies, Inc. Standby circuit dispatch method, apparatus, device and medium
US11797371B2 (en) 2020-08-18 2023-10-24 Changxin Memory Technologies, Inc. Method and device for determining fail bit repair scheme
US11853152B2 (en) 2020-08-18 2023-12-26 Changxin Memory Technologies, Inc. Fail bit repair method and device
US11881278B2 (en) 2021-03-31 2024-01-23 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, apparatus and medium
US11887685B2 (en) 2020-08-18 2024-01-30 Changxin Memory Technologies, Inc. Fail Bit repair method and device
US11984179B2 (en) 2021-03-26 2024-05-14 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, and medium

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Cited By (9)

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Publication number Priority date Publication date Assignee Title
US11791010B2 (en) 2020-08-18 2023-10-17 Changxin Memory Technologies, Inc. Method and device for fail bit repairing
US11797371B2 (en) 2020-08-18 2023-10-24 Changxin Memory Technologies, Inc. Method and device for determining fail bit repair scheme
US11853152B2 (en) 2020-08-18 2023-12-26 Changxin Memory Technologies, Inc. Fail bit repair method and device
US11887685B2 (en) 2020-08-18 2024-01-30 Changxin Memory Technologies, Inc. Fail Bit repair method and device
US11984179B2 (en) 2021-03-26 2024-05-14 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, and medium
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CN112908402B (zh) * 2021-03-31 2022-05-10 长鑫存储技术有限公司 备用电路分派方法、装置、设备及介质
US11791012B2 (en) 2021-03-31 2023-10-17 Changxin Memory Technologies, Inc. Standby circuit dispatch method, apparatus, device and medium
US11881278B2 (en) 2021-03-31 2024-01-23 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, apparatus and medium

Also Published As

Publication number Publication date
JPH11120787A (ja) 1999-04-30
DE19820442A1 (de) 1998-11-12
JP4716530B2 (ja) 2011-07-06
KR100545225B1 (ko) 2006-04-10
US5987632A (en) 1999-11-16
KR19980086794A (ko) 1998-12-05

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