JPH04228196A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide the semiconductor integrated circuit which can make self-relieving of the defect generated after the circuit is built into a system. CONSTITUTION:The timing for relieving the defective address in a memory cell array 1 is generated by a timer 10 and the presence or absence of the memory cell selected in accordance with the output address signal of an address counter circuit 15 operated in accordance with this timing is decided by an error deciding circuit 18. The address of the memory cell, the detect of which is detected by the result of this decision, is stored into a defective address memory circuit 21. The address held in the defective address memory circuit 21 and the address from the outside are compared in the event of the access from the outside. The memory cell array 1 is accessed in the case of incoincidence and the redundancy memory cell array 2 is accessed in the case of coincidence.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits such as memory LSIs, logic LSIs, or microcomputers, which are equipped with a memory cell array and a circuit for selecting desired memory cells included therein, and further to such semiconductor integrated circuits. The present invention relates to a technology for relieving defects in memory cells in integrated circuits, and relates to a technology that is effective when applied to large storage capacity memory LSIs such as DRAMs (dynamic random access memories).

0002

2. Description of the Related Art As the degree of integration and the miniaturization of circuit elements continue to advance, some semiconductor integrated circuits have a redundant structure in order to improve their yield. When a defect is detected in an inspection process such as a wafer probe test, a fuse program, for example, is performed to select a redundant configuration that can repair the defect.

[0003] A self-check/self-repair function takes the conventional redundant configuration one step further and independently determines the presence or absence of a defect within a semiconductor integrated circuit, and if a defect exists, repairs the defect by itself. IEEE, 1989, proposed a semiconductor integrated circuit with
CUSTOM INTEGRATED CIRCU
ITS CONFERENCE, Built-in
Self-Repair Circuit for
r High-Density ASMIC P.
26, 1, 1-P. 26, 1, 4. The technology described in such documents is based on ASMIC
ion Specific Memory IC), it is a technology that performs internal memory checks and self-repairs by applying an external clock, and is intended to shorten test time for defect relief using conventional redundancy and program time for fuses, etc. shall be.

0004

However, defects in memory cells and the like may occur over time in a system, and conventional self-check and self-repair techniques cannot deal with this problem. Furthermore, when dealing with the occurrence of a defect in a system, consideration must be given to the possibility of notifying an external party when the hardware exceeds the limit of defect repair.

An object of the present invention is to provide a semiconductor integrated circuit that can self-repair even from defects that occur after it is incorporated into a system. In addition to this, the present invention aims to provide a semiconductor integrated circuit that can notify the outside of a state in which self-repair is not possible.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, the timing for relieving a defective address in the memory cell array serving as the first storage means is generated by the timing generating means itself, and the timing is selected based on the output address signal of the address generating means operated based on the timing. A determination means determines whether or not there is a defect in a memory cell, and the address of the memory cell in which a defect is detected based on the determination result is stored in a defective address storage means, and when accessing the memory cell array, the address held in the defective address storage means is stored. and an access address supplied from the outside, and if they do not match, the memory cell array is accessed, and if they match, the redundant memory cell array serving as the second storage means is accessed.

When a state in which self-repair is impossible due to the limit of hardware storage capacity for rescue is reached, in order to notify the outside, a redundant memory cell array capable of replacing defective memory cells in the memory cell array is provided. a control signal that manages the presence or absence of a free address in the address space, and when the determination means detects a defect in a state where there is no free address, in response to this, notifies that defect relief is impossible;
Alternatively, the same control signal and the address signal at that time are outputted to the outside.

The self-relief timing by the timing generating means may be generated periodically or may be generated at any time in accordance with an external instruction.

[0011] When a configuration is also provided in which a redundant relief address is programmed using a fuse or the like as a non-volatile memory element, when accessing from the outside, the address programmed in the non-volatile memory element and the defective address storage means are The held address and the access address supplied from the outside are compared, and if they do not match, the memory cell array is accessed, and if they match, the redundant memory cell array is accessed.

[0012] In order to deal with the case where a redundant memory cell that replaces an address programmed in advance in a nonvolatile memory element becomes defective over time, a defective address stored in the defective address program circuit is replaced. The address of a redundant memory cell is recognized, and when a defect occurs at the address, another redundant memory cell is allocated for relief.

[0013]

[Operation] According to the above-mentioned means, self-generating the timing for self-repairing defective addresses in the memory cell array has the effect that it can also self-repair defects that occur after it is incorporated into the system. do.

[0014]Furthermore, when a defect detected during a self-repair operation reaches the limit of repairing an unrepairable hardware defect, the management means reports this to the outside together with the defect address. , the host processor or the like that receives the notification can autonomously prohibit access to the defective memory cell in subsequent accesses. As a result, accesses to defective memory cells that occur over time can be suppressed, and the reliability of the system is improved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a semiconductor integrated circuit 31 according to an embodiment of the present invention, and FIG. 2 shows a microcomputer system to which the semiconductor integrated circuit 31 is applied. This microcomputer system consists of three semiconductor integrated circuits.
In addition to 1, a central processing unit (hereinafter also simply referred to as CPU)
33, an interrupt controller 32, etc., which are connected to an address bus AB1, a data bus DB, and a control bus CB. Semiconductor integrated circuit 3 shown in the figure
Although not particularly limited, 1 is configured as a memory LSI, and is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique.

In the figure, reference numeral 1 denotes a memory cell array in which a large number of static or dynamic type memory cells are arranged in a matrix, the selection terminals of which are connected to word lines (not shown), and the data input/output terminals connected to bits (not shown). connected to a line.

Reference numeral 2 denotes a redundant memory cell array including memory cells (spare cells) for replacing defective memory cells included in the memory cell array 1. For example, a plurality of static type memory cell arrays are arranged in a matrix. ing. Although not particularly limited, in this embodiment, word lines and bit lines are separated from each other in each of the memory cell array 1 and the redundant memory cell array 2.

Addressing of the memory cells of the memory cell array 1 is performed by an output selection signal 4 of an address decoder 3. Further, addressing of the memory cells included in the redundant memory cell array 2 is performed by the output selection signal 6 of the address decoder 5. Reading and writing data to addressed memory cells is
This is done via the input/output circuit 7 and data terminal DT1, which are interfaced to the data bus DB.

In the semiconductor integrated circuit 31 of this embodiment,
A timing controller 8 performs timing control based on external access. For example, a chip select signal CS, a read/write signal R/W, etc. are supplied to this timing controller 8 from the CPU 33 via a control bus CB and control signal terminals C1 and C2, and when the chip select signal CS is asserted, CPU33
The data input/output direction at this time is determined by the read/write signal R/
Directed by W.

The semiconductor integrated circuit 31 of this embodiment self-determines whether or not there is a defect in the memory cell of the memory cell array 1, and if there is a defect, it self-remedies the defect, and if self-repair is not possible. When a situation arises, this will be communicated to the outside world. The configuration for this purpose will be explained below.

A timer 10 periodically generates an operation timing for self-relief. This timer 10 generates a check clock 11 at periodically occurring self-repair operation timings. This check clock 11 is a timing signal that defines an operation cycle for defect determination and repair, and is changed by a predetermined number of clocks corresponding to the number of operations. In this example, the action for self-help is as follows:
The check clock 12 applied from the control bus CB via the control terminal C3 allows the operation to be performed at any desired timing, and the internal operation timing is controlled by the output clock 14 of the OR gate 13 which receives two inputs of the check clocks 11 and 12. is controlled. It should be noted that the configuration that allows the check clock 12 to be input from the control terminal C3 at any time is not essential to the present invention.

The timing clock 14 is supplied to an address counter 15, a multiplexer 16, a test data generation circuit 17, and an error determination circuit 18.

The address counter 15 generates an internal address signal for sequentially addressing the memory cell array for defect determination. The update timing of the output address by the counter 15 or the timing of the address increment operation is determined by the timing clock 1.
This is done in synchronization with the 4th cycle. Note that the timer 10
Further, the operation of the address counter 15 is enabled only after the check enable signal ES supplied from the control terminal C4 is once asserted. those timers 10
The input stage of the check enable signal ES in the address counter 15 is configured by a master-slave type flip-flop, although it is not particularly limited. It is placed in a state where judgment and relief operations are possible.

The multiplexer 16 selectively selects the internal address signal output from the address counter 15 and the address signal supplied via the address bus AB1 and the address input dedicated terminal AT1. For example, the internal address signal is selected during the low level period of the timing clock 14, and the external address signal is selected at other times. Incidentally, the timing clock 14 takes a high level when its change is stopped.

Although the output address signal of the multiplexer 16 is not particularly limited, the address signal of the address decoder 3,
The signal is supplied to the input/output circuit 7, the defective address determination circuit 20, and the defective address storage circuit 21. Note that each circuit is provided with an address latch circuit at its address input stage.

The test data generation circuit 17 generates test data for determining the presence or absence of a defect by using the timing clock 14.
Output in sync with.

The error determination circuit 18 reads stored data from a memory cell specified by the output address of the address counter 15, writes test data to the memory cell, reads written test data, and performs read/write operations. Compare test data. Through this comparison, it is determined whether or not the memory cell at the address is defective. The judgment result is sent to the error flag generation circuit 22.
given to. Incidentally, since such a judgment operation is performed periodically on the system, the data that is first read from the memory cell to the error judgment circuit 18 is not judged so that the original data used in the system is not destroyed by the test. The data is held until the data is completed, and then written back to the memory cell at the same address.

When the error flag generation circuit 22 is notified by the signal 23 outputted from the error determination circuit 18 that the determination result is defective, it generates an error flag EF, and, together with the error flag EF, The access address (the address of the defective memory cell and the address signal output from the multiplexer 16) is stored in pairs in the defective address storage circuit 21. Here, the error flag EF is code information such as an address for selecting a memory cell included in the redundant memory cell array 2, although it is not particularly limited.
It has a logic that manages the error flag EF and prevents the same error flag EF from being output twice.

The defective address storage circuit 21 is constituted by a storage element such as a static flip-flop, although it is not particularly limited. Therefore, if the device itself is not backed up by a battery, for example, when the power is turned on and the power-on reset is performed, the check clock 1
2 and execute the self-judgment relief operation first to initialize the defective address storage circuit 21 by itself. In this way, there will be no problem even if the once stored defective address and error flag EF are lost when the power is turned off. The initial storage setting at power-on may be configured to be automatically performed upon detection of power-on. Note that if this defective address storage circuit 21 is constituted by an electrically writable nonvolatile storage element, there is little need for initial storage settings during battery backup or power-on reset. However, in this case as well, a configuration may be adopted in which a self-automatic check is performed at power-on.

Reference numeral 24 denotes a defective address program circuit in which an address to be repaired is programmed using a fuse or the like as a non-volatile memory element. Programming of defective addresses to the defective address program circuit 24 is performed for defective addresses detected by testing at the wafer stage. Code information corresponding to the error flag EF specifying the address of the redundant memory cell array 2 to be replaced is also added to the defective address in the memory cell array 1 programmed here, and the fuse is programmed.

The defective address program circuit 24 outputs an error flag corresponding to the defective address set therein to the error flag generating circuit 22 via a path 26.

When the error flag generation circuit 22 manages the error flags EF output by itself, it regards the error flags given from the defective address program circuit 24 as already output error flags. Therefore, the memory cell addresses of the redundant memory cell array assigned by the defective address program circuit 24 are not stored in the defective address storage circuit 21 overlappingly.

A full state detection circuit 27 receives error flag management information from the error flag generation circuit 22 and detects a state in which all error flags have been output. Therefore, this full state detection circuit 27 manages the presence or absence of an empty address in the redundant memory cell array 2 that can replace a defective memory cell in the memory cell array 1. When the error determination circuit 18 detects a defect in a state where there is no free address, the full state detection circuit 27 responds to this by using a control signal 28 to input/output a signal indicating that the defect cannot be repaired. The interrupt controller 32 is notified via the circuit 7 and the control terminal C5. As a result, the input/output circuit 7 receives the control signal 28 indicating that the defect cannot be repaired, and sends the address signal corresponding to the defective address outputted from the multiplexer 16 from the path 29 to the address terminal AT2 and the address bus. It is output to the interrupt controller 32 via AB2.

20 is a defective address program circuit 24
The defective address programmed in the memory cell and the address held in the defective address storage circuit 21 are compared with the access address output from the multiplexer 16, and if they do not match, the memory cell array 1 is selected, and if they match, the memory cell array 2 is selected. This is a defective address determination circuit that accesses the address. If the judgment results do not match, control signal 2
5 is set to a low level, thereby activating address decoder 3, while redundant address decoder 5 assumes an inactive state, and memory cell array 1 is addressed via address decoder 3. If the judgment result is a match, the control signal 25 is set to a high level, thereby activating the redundant address decoder 5, while the address decoder 3 assumes an inactive state and performs the matching defective address. The paired error flags are supplied to the redundant address decoder 5 as address information. As a result, the redundant memory cell array 2 that replaces the defective address in the memory cell array 1 is addressed via the redundant address decoder 5.

It should be noted that an ECC (error checking and correcting) circuit 30 is added to the input/output circuit 7 for data input/output to/from the outside, so as to prevent data errors of several bits. You can try to help yourself.

Next, the operation for relieving a defective address in the semiconductor integrated circuit of this embodiment will be explained.

[1] Relief at wafer stage

[0038]
For defects in the memory cell array 1 detected at the wafer stage, the defective bits are replaced with predetermined bits of the redundant memory cell array 2 by programming in the defective address program circuit 24. The bit address of the redundant memory cell array 2 replaced here is given to the error flag generation circuit 22 as an error flag.

[2] Self-repair (memory cell array defect)

When the self-relief judgment timing comes periodically due to the action of the timer 10, the timing clock 14
The output address signal of address counter 15 is selected by multiplexer 16 in synchronization with . At this time, the defective address determination circuit 20 compares the address signal with the output of the defective address storage circuit 21 and the output of the defective address program circuit 24 to determine coincidence/mismatch.

If the determination result is a mismatch, the address decoder 3 is activated by the control signal 25, and the memory cell array 1 is addressed by the output address signal of the multiplexer 16. At this time, the error determination circuit 18 reads data from the addressed memory cell, writes test data to the memory cell, reads the written test data, compares the read and written test data, and reads the first read data. Write back data. If the comparison results of the read and written test data do not match, that is, if the memory cell in question is defective, the control signal 23 notifies the error flag generation circuit 22 of this fact. Thereby, the error flag generation circuit 22 causes the defective address storage circuit 21 to store the address at that time and also stores a predetermined error flag. As a result, the defective memory cell is replaced with a redundant memory cell specified by the error flag.

[3] Self-repair (defective redundant memory cell array)

When the self-relief judgment timing comes periodically due to the action of the timer 10, the timing clock 14
The output address signal of address counter 15 is selected by multiplexer 16 in synchronization with . At this time, the defective address determination circuit 20 compares the address signal with the output of the defective address storage circuit 21 and the output of the defective address program circuit 24 to determine coincidence/mismatch.

If the judgment result is a match, the redundant address decoder 5 is activated by the control signal 25, and an error flag paired with the matched address is given to the redundant address decoder 5, thereby decoding the redundant memory cell array. 2 is addressed. At this time, the error determination circuit 18 reads data from a memory cell in the addressed redundant memory cell array, writes test data to the memory cell, reads the written test data, compares the read and written test data, and Writes back the data that was originally read. If the comparison results of read and written test data do not match, that is, if the memory cell concerned has a defect, the control signal 23
Then, the error flag generation circuit 22 is notified of this fact. As a result, the error flag generation circuit 22 causes the defective address storage circuit 21 to store the address at that time, and
A predetermined error flag is stored. The error flag at this time is different from the one assigned by the defective address program circuit 24 due to the flag management function of the error flag generation circuit 22. As a result, the defective redundant memory cell in the redundant memory cell array 2 is replaced with another redundant memory cell specified by its error flag.

[4] Self-help impossible state

When the self-relief operation described in items [2] and [3] is performed periodically, the full state detection circuit 27 receives error flag management information from the error flag generation circuit 22.
In response to the defect detection by the error determination circuit 18, the controller determines that all error flags have been outputted, in other words, it is no longer possible to self-repair the defect. Then, the control signal 28 notifies the input/output circuit 7 and the interrupt controller 32 that defect relief is impossible. At this time, the input/output circuit 7 outputs an unrepairable address signal corresponding to the defective address outputted from the multiplexer 16 from the path 29 to the interrupt controller 32 via the address terminal AT2 and the address bus AB2. When the interrupt controller 32 receives the control signal 28 from the control terminal C3,
A non-repairable address signal supplied from the input/output circuit 7 is taken in from the address terminal AT3. Then, the interrupt controller 32 sends a signal indicating that an irreparable address signal has been generated to the CPU 3 from the control terminal C7.
It is output to the control terminal (interrupt terminal) C9 of No. 3. Based on this signal, the CPU 33 recognizes the occurrence of an interrupt,
The processing in progress is temporarily stopped, and in order to know the unrepairable address signal, a control signal is outputted to the interrupt controller 32 via the control bus CB to cause the interrupt controller 32 to output the unrepairable address signal. The interrupt controller 32 transfers the irreparable address signal taken in from the address terminal AT3 from the data terminal DT2 to the data bus DB in response to the control signal from the CPU 33.
It is output to the CPU 33 via. The CPU 33 receives the unrepairable address signal and executes the interrupt program. For example, by executing this interrupt program, the main program is changed so that the unrepairable address signal is no longer output to the semiconductor integrated circuit 31.

Furthermore, as another embodiment, the ECC circuit 30
A configuration may be adopted in which data stored in an unrecoverable address is corrected by using the . E
When the CC circuit 30 receives a control signal 28 indicating that defect relief is impossible from the full state detection circuit 27, the CC circuit 30 detects several bit errors in the data read from the memory cell array 1 to the input/output circuit 7. Make sure to make corrections. The corrected data is then supplied to the CPU 33 from, for example, the data terminal DT1 via the data bus DB. Therefore, when using the ECC circuit 30 in this way, there is no need to impose restrictions on the main program so that unrepairable addresses are not output to the semiconductor integrated circuit 31. You can get away without it. Further, in this case, when the control signal 28 indicating that the defect cannot be repaired is not supplied to the ECC circuit 30, the ECC circuit 30 may not be operated. As a result, when the control signal 28 is not supplied, the memory operating speed of the semiconductor integrated circuit is reduced to ECC.
It is possible to avoid being limited by the operating speed of the circuit 30.

The semiconductor integrated circuit of the above embodiment can be formed as a MOS type semiconductor integrated circuit, but it can also be formed by a process in which bipolar transistors such as Bi-CMOS and complementary MOS (CMOS) are mixed. be able to. In particular, if a bipolar transistor can be included, the fuse in the defective address program circuit 24 can be replaced with a bipolar PROM (programmable read only memory).

FIG. 3 shows an example of a memory circuit for one bit of address in the defective address program circuit 24 using a bipolar PROM. In the figure, a bipolar PROM 40 is composed of a P-channel MOSFET 41 and an N-channel MOSFET 41 constituting a CMOS inverter.
Inverters 43, 44, and 45 are interposed between the OSFETs 42 and connected in series to a coupling node between the drain electrode of the MOSFET 42 and the emitter of the bipolar PEROM 40. Note that the N-channel MOSFET 46 has a function of fixing the low level input of the inverter 43. The bipolar PROM 40 is, for example, a junction short type, and is brought into a write state by shorting the emitter-base junction by applying a reverse voltage to the emitter and causing an avalanche breakdown current to flow. The write state corresponds to the fuse 47 not being blown in FIG. 4, and the non-writing state corresponds to the fuse 47 being blown. In the circuit of FIG. 3, the control signal 48 is set to a low level when redundancy is required. Therefore, the level of signal 49 is determined depending on the program state of bipolar PROM 40. Such bipolar PR
OM40 is a fuse 46 made of polysilicon etc.
The layout size can be reduced compared to .

According to the above embodiment, the following effects can be obtained.

(1) The timing for self-repairing a defective address in the memory cell array 1 is determined by the timer 1.
The error determination circuit 18 determines whether or not there is a defect in the memory cell selected based on the output address signal of the address counter 15 which is generated at 0 and is operated based on this. The address of the cell is stored in the defective address storage circuit 21, and when accessing the memory cell array 1, the address held in the defective address storage circuit 21 is compared with the access address supplied from the outside, and if they do not match, the memory cell array 1 is If they match, the redundant memory cell array 2 is accessed, so it is possible to self-repair defects that occur after being incorporated into the system.

(2) When a state in which self-repair is impossible due to the limit of hardware storage capacity for rescue is reached, in order to notify the outside, the defective memory cell in the memory cell array 1 can be replaced. The presence or absence of a free address in the redundant memory cell array 2 is managed, and when the error determination circuit 18 detects a defect in a state where there is no free address, in response, a notification is sent that the defect cannot be repaired. Since the control signal 28 and the management means 22 and 27 for outputting the address signal at that time to the outside are provided, it is possible to reach the limit of hardware-based defect repair which cannot be repaired for defects detected during self-repair operation. This state is notified to the outside by the management means along with the defective address, and as a result, the host processor or the like that receives the notification can autonomously prohibit subsequent accesses to the defective memory cell. can.

(3) By making the self-relief timing by the timer 10 occur not only periodically but also according to instructions from outside, the idle time of the semiconductor integrated circuit on the system can be made effective. be able to use it. For example, the system reset period at power-on is used to easily initialize the defective address storage circuit 21 as a volatile memory (a self-check/self-repair operation for the entire memory cell array 1). be able to.

(4) When the configuration is such that a redundant relief address is programmed using a fuse or the like as a non-volatile memory element, a redundant memory cell is used to replace the defective address stored in the defective address program circuit 24. By the action of the management means 22 which recognizes an address and allocates another redundant memory cell for relief when a failure occurs at the address, a redundant memory cell is replaced over time to replace the address programmed in the non-volatile memory element in advance. It is also possible to deal with cases where the product becomes defective.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, in the above embodiment, a case has been described in which a defective address program circuit is provided in which a defective address at the wafer stage is programmed into a nonvolatile memory element, but such a circuit can be omitted, and the defective address memory circuit 21 You can deal with it alone. Furthermore, in the above embodiment, the data in the defective address memory circuit 21 is backed up by a battery, the memory element is configured with an electrically writable non-volatile memory element, and a state in which it is not possible to repair the defect that has occurred is also considered. Although the signal 28 is used to notify the outside, if the semiconductor integrated circuit includes a necessary logic circuit, the internal circuit can be used to handle the situation by itself. Furthermore, the ECC circuit 30 can be omitted. Furthermore, the memory cell array referred to in the present invention is not limited to a configuration in which memory elements are arranged in a matrix and can be randomly accessed, but also a register array such as a set of multiple registers or a shift register such as a parallel-in/parallel-out type. It can be understood as a concept that includes things like this.

In the above description, the invention made by the present inventor was mainly applied to the memory LSI, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and is applicable to microcomputers. The present invention can be widely applied to various semiconductor integrated circuits such as logic LSIs.

[0058]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, by providing the function of self-determining defective bits and at least generating and controlling the repair timing by itself, it is possible to self-repair even defects that occur after being incorporated into the system. be.

[0060] The presence or absence of free addresses in the redundant memory cell array is managed, and when a new defect in the memory cell array is detected in a state where there is no free address, a notification is sent in response to this that the defect cannot be repaired. a control signal;
By providing a means for outputting the address signal at that time to the outside, it is possible to notify the outside when a state in which self-repair is impossible due to the limit of hardware storage capacity for rescue is reached. Therefore, it becomes possible for a host processor or the like that receives the notification to autonomously prohibit access to the defective memory cell in subsequent accesses.

By causing the self-relief timing by the timing generating means to occur not only periodically but also according to external instructions, for example, a defective address can be stored in a non-volatile memory element of a defective address storage circuit. This makes it possible to easily perform the initial setting operation by using the system reset or power-on reset period, and also makes it possible to effectively utilize the idle time of the semiconductor integrated circuit.

[0062] When the configuration is such that a redundant relief address is programmed using a fuse or the like as a non-volatile memory element, the address of a redundant memory cell to replace the defective address stored in the defective address program circuit is programmed. By recognizing this and allocating another redundant memory cell for relief when a defect occurs at that address, if the redundant memory cell that replaces the address programmed in advance in the non-volatile memory element becomes defective over time. It also has the effect of being able to deal with it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a microcomputer system to which the semiconductor integrated circuit of FIG. 1 is applied.

FIG. 3 is a partial circuit diagram of an example of a nonvolatile program circuit using a bipolar PROM as a nonvolatile memory element.

FIG. 4 is a partial circuit diagram of an example of a nonvolatile program circuit using a fuse as a nonvolatile memory element.

[Explanation of symbols]

1 Memory cell array 2 Redundant memory cell array 3 Address decoder 5 Redundant address decoder 10 Timer 15 Address counter 17 Test data generation circuit 18 Error determination circuit 20 Defective address determination circuit 21 Defective address storage circuit 22 Error flag generation circuit 24 Defective address program circuit 27 Full state detection circuit 31 Semiconductor integrated circuit 32 Interrupt controller 33 Central processing unit

Claims (7)

[Claims] 1. A first storage means having an address input terminal, a plurality of memory cells, and a first storage means forming a selection signal for selecting a memory cell included in the first storage means.
a selection means, a second storage means including a memory cell for replacing a defective memory cell included in the first storage means, and a selection signal for selecting a memory cell included in the second storage means. a second selection means forming a second selection means, a timing generation means, an address generation means for generating an address signal based on an instruction of the timing generation means, and a memory cell selected based on the address generated from the address generation means. a determination means for determining the presence or absence of a defect;
A defective address storage means stores the address of the memory cell in which a defect has been detected by the determination means, and compares the address supplied from the address input terminal with the address stored in the address storage means to find a match. / Determine a mismatch; if a mismatch, supply the address supplied from the address input terminal to the first selection means; if a match, an address of a memory cell to replace the defective memory cell designated by the address; The second
1. A semiconductor integrated circuit formed on one semiconductor substrate, including: a determination control means for supplying a signal to a selection means. 2. The second storage means manages the presence or absence of a memory cell that has not yet been allocated as a replacement for a defective memory cell, and responds when the determination means detects a defect when there are no free memory cells. Claim 1 further comprising a control signal for notifying that the defect cannot be repaired and a management means for outputting the address at that time to the outside.
The semiconductor integrated circuit described. 3. The timing generating means operates the address generating means, the determining means, and the defective address storage means periodically or/and at any time according to instructions from the outside to activate a self-repair operation for the defective address. 3. The semiconductor integrated circuit according to claim 1 or 2. 4. The determining means further includes test data generating means for generating test data for determining whether or not the memory cell is defective, and the test data generating means is selected according to the address generated by the address generating means. Writing test data into the memory cell from the test data generating means, reading out the written test data, comparing both data to determine whether or not there is a defect in the memory cell at that address, and outputting the determination result. 4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a semiconductor integrated circuit. 5. The defective address storage means further comprises error flag generation means for specifying an address of a memory cell to replace the defective memory cell based on a defective determination output from the determination means, and the defective address storage means includes: 2. The semiconductor integrated circuit according to claim 1, wherein an error flag is stored together with the address of the defective memory cell. 6. The semiconductor integrated circuit according to claim 5, wherein said defective address storage means includes a nonvolatile storage element in which the address of the defective memory cell in the first storage means and said error flag are stored in advance. 7. The error flag generating means updates an error flag in response to a defective memory cell included in the second storage means, and provides the updated error flag to the defective address storage means. Semiconductor integrated circuit.