KR100253385B1 - 반도체 소자의 배선형성 방법 - Google Patents

반도체 소자의 배선형성 방법 Download PDF

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Publication number
KR100253385B1
KR100253385B1 KR1019970071889A KR19970071889A KR100253385B1 KR 100253385 B1 KR100253385 B1 KR 100253385B1 KR 1019970071889 A KR1019970071889 A KR 1019970071889A KR 19970071889 A KR19970071889 A KR 19970071889A KR 100253385 B1 KR100253385 B1 KR 100253385B1
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KR
South Korea
Prior art keywords
layer
forming
barrier layer
copper
copper wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019970071889A
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English (en)
Korean (ko)
Other versions
KR19990052424A (ko
Inventor
라사균
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR1019970071889A priority Critical patent/KR100253385B1/ko
Priority to TW087106994A priority patent/TW380307B/zh
Priority to US09/129,000 priority patent/US6294462B1/en
Priority to JP36437498A priority patent/JP4829389B2/ja
Publication of KR19990052424A publication Critical patent/KR19990052424A/ko
Application granted granted Critical
Publication of KR100253385B1 publication Critical patent/KR100253385B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
KR1019970071889A 1997-12-22 1997-12-22 반도체 소자의 배선형성 방법 Expired - Fee Related KR100253385B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019970071889A KR100253385B1 (ko) 1997-12-22 1997-12-22 반도체 소자의 배선형성 방법
TW087106994A TW380307B (en) 1997-12-22 1998-05-06 Manufacturing method of interconnection layer for semiconductor
US09/129,000 US6294462B1 (en) 1997-12-22 1998-08-04 Manufacturing method of interconnection layer for semiconductor device
JP36437498A JP4829389B2 (ja) 1997-12-22 1998-12-22 半導体素子の配線形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970071889A KR100253385B1 (ko) 1997-12-22 1997-12-22 반도체 소자의 배선형성 방법

Publications (2)

Publication Number Publication Date
KR19990052424A KR19990052424A (ko) 1999-07-05
KR100253385B1 true KR100253385B1 (ko) 2000-05-01

Family

ID=19528155

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970071889A Expired - Fee Related KR100253385B1 (ko) 1997-12-22 1997-12-22 반도체 소자의 배선형성 방법

Country Status (4)

Country Link
US (1) US6294462B1 (enExample)
JP (1) JP4829389B2 (enExample)
KR (1) KR100253385B1 (enExample)
TW (1) TW380307B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100330163B1 (ko) * 2000-01-06 2002-03-28 윤종용 반도체 장치의 텅스텐 콘택 플러그 형성 방법
KR20040002065A (ko) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 파워 소자 형성 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
JP4666339B2 (ja) * 2004-05-14 2011-04-06 株式会社トリケミカル研究所 導電性バリア膜形成材料、導電性バリア膜形成方法、及び配線膜形成方法
KR100711920B1 (ko) * 2005-12-28 2007-04-27 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 및 그의 형성 방법
JP5170589B2 (ja) * 2010-12-08 2013-03-27 株式会社トリケミカル研究所 導電性バリア膜形成材料、導電性バリア膜形成方法、及び配線膜形成方法
CN103500728B (zh) * 2013-09-29 2016-03-02 武汉新芯集成电路制造有限公司 一种铜阻挡层和铜晶籽层的形成方法
CN110085569B (zh) * 2018-01-25 2020-12-22 联华电子股份有限公司 半导体结构及其制作方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5219788A (en) * 1991-02-25 1993-06-15 Ibm Corporation Bilayer metallization cap for photolithography
JPH0555167A (ja) * 1991-08-28 1993-03-05 Nec Corp 半導体装置の製造方法
JPH05198525A (ja) * 1992-01-21 1993-08-06 Sony Corp 配線構造及び配線の形成方法
JPH05235174A (ja) * 1992-02-20 1993-09-10 Toshiba Corp 半導体装置の製造方法
JPH05347269A (ja) * 1992-06-16 1993-12-27 Sony Corp 半導体装置の製造方法
US5654245A (en) * 1993-03-23 1997-08-05 Sharp Microelectronics Technology, Inc. Implantation of nucleating species for selective metallization and products thereof
US5506449A (en) 1993-03-24 1996-04-09 Kawasaki Steel Corporation Interconnection structure for semiconductor integrated circuit and manufacture of the same
JPH06291194A (ja) * 1993-04-05 1994-10-18 Nec Corp 半導体装置の製造方法
KR0147682B1 (ko) * 1994-05-24 1998-11-02 구본준 반도체 소자의 금속배선 제조방법
KR0132490B1 (ko) * 1994-07-21 1998-04-16 문정환 박막트랜지스터 제조방법
US5635423A (en) 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5529953A (en) * 1994-10-14 1996-06-25 Toshiba America Electronic Components, Inc. Method of forming studs and interconnects in a multi-layered semiconductor device
KR0144913B1 (ko) * 1995-03-03 1998-08-17 김광호 반도체장치의 금속배선층 형성방법
US5484747A (en) * 1995-05-25 1996-01-16 United Microelectronics Corporation Selective metal wiring and plug process
US5891804A (en) * 1996-04-18 1999-04-06 Texas Instruments Incorporated Process for conductors with selective deposition
KR100193897B1 (ko) * 1996-06-28 1999-06-15 김영환 반도체 소자의 플러그 형성 방법
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US5893752A (en) * 1997-12-22 1999-04-13 Motorola, Inc. Process for forming a semiconductor device
US6077780A (en) * 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
US5968333A (en) * 1998-04-07 1999-10-19 Advanced Micro Devices, Inc. Method of electroplating a copper or copper alloy interconnect

Also Published As

Publication number Publication date
JPH11260920A (ja) 1999-09-24
JP4829389B2 (ja) 2011-12-07
KR19990052424A (ko) 1999-07-05
TW380307B (en) 2000-01-21
US6294462B1 (en) 2001-09-25

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